Symposium Organizers
Vasudeva P. Atluri Intel Corporation
Sujit Sharan Intel Corporation
Ching-Ping Wong Georgia Institute of Technology
Darrel Frear Freescale Semiconductor
V1/W2: Joint Session: System in Package
Session Chairs
Monday PM, November 27, 2006
Room 206 (Hynes)
2:30 PM - **V1.1/W2.1
Silicon Based System-in-Package : Breakthroughs in Miniaturization and ”nano”-integration Supported by Very High Quality Passives and System Level Design Tools.
Franck Murray 1 , François LeCornec 1 , Serge Bardy 1 , Catherine Bunel 1 , Jan Verhoeven 2 , Erik van der Heuvel 2 , Johan Klootwijk 2 , Fred Roozeboom 2
1 , NXP Research, Caen France, 2 , Philips Research, Eindhoven Netherlands
Show Abstract3:00 PM - **V1.2/W2.2
Process and Material Requirements for Successful Heterogonous Passive Component Integration in RF System.
Eric Beyne 1 , Walter De Raedt 1 , Geert Carchon 1 , Philippe Soussan 1
1 , IMEC, Leuven Belgium
Show AbstractAs wireless communication devices become more abundant in numbers and variety, high-density system integration is becoming an increasingly important requirement. High-density integration of RF radio devices not only requires integration of active devices (RF system-on-a-chip [RF-SoC]), it also requires the integration of a large number of passive devices, such as transmission lines, resistors, capacitors and inductors, as well as functional blocks, such as filters and baluns. To reduce system size and cost, a higher degree of miniaturization is required. These components do not scale as well as active IC technology, making it difficult to integrate all these devices on chip. Such technologies may be integrated on the die or in the package using heterogeneous integration technologies. (rf-System-in-a-Package, rf-SIP)This paper will present the system-level requirements for integrated passives integration for rf systems. Requirements for material characteristics and device process tolerances will be discussed.As a key enabling technology for the realization of the passive component integration, the multilayer thin-film technology will be presented. A key feature of this technology is the use of photolithographic technology for the definition of the various passive circuit components, resulting in a high degree in miniaturization and high patterning accuracy, with tolerances in the micron and submicron ranges. This results in excellent circuit repeatability and predictability, key ingredients for the realization of first-time-right and high-manufacturing-yield devices. This technology may be applied to passive substrates or active device wafers. Examples of both will be presented.
4:30 PM - **V1.3/W2.3
Through Wafer Interconnects – a Technology not only for Medical Applications.
Gereon Vogtmeier 1 , Christian Drabe 3 , Ralf Dorscheid 2 , Roger Steadman 1 , Alexander Wolter 3
1 X-ray Imaging Systems, Philips Research Europe, Aachen Germany, 3 , Fraunhofer Institute Photonic Microsystems, Dresden Germany, 2 Engineering and Technology, Philips Research Europe, Aachen Germany
Show AbstractThe foremost driver for the development of fully CMOS compatible Through Wafer Interconnects (TWIs) is the need of very large photodiode arrays for detectors, e.g. computed tomography application. Only the front to back-side contact allows the four-side buttable chip placement of the already large chips (20 mm x 22 mm). The TWI technology allows an interconnection for chips up to 280µm thickness and it also enables a metal signal routing on the active side, on top of the interconnection. The application specific optical sensitive front-side of the chip is fully accessible. This is very important, as the imager process with the optical interface to an x-ray converting scintillator material on top of the imager is not limited by the TWI-process. The whole process has been thought to be fully CMOS-fabrication compatible.In more detail the production process is separated into three main steps. The first step is the implementation of the special TWI geometry into the raw wafer. Depending on the electrical and geometrical requirements of the circuit different TWI structures are available – also within one wafer or chip design. All geometries are built with deep trenches (up to 280µm), which are passivated and filled with doped poly-silicon. The used technologies like DRIE-etching, oxidation and low pressure CVD are standard CMOS compatible processes. Low leakage current and shielded conductive structures, e.g. coaxial double ring structures, have been selected as most valuable for our application.After this first step the conductive structure is already located at the correct position in the wafer before proceeding with the standard CMOS process. The CMOS process runs normally on the front-side as if a polished raw wafer was being used. The use of poly-silicon limits the conductive interconnection to a certain resistance but allows the use of all CMOS process steps for an imager production (no temperature limitation – compared to other TWI process flows).The third step is a low temperature back-side process starting with wafer thinning down to 280 µm or less (depending on the final wafer thickness) to open the implemented TWI structure from the back-side. The thickness may be selected depending on the application. For Computed Tomography a thick wafer is desired to ensure proper mechanical stability.A modified under ball metallization (UBM) process, which could include also re-routing of signals on the back-side, concludes the process flow until the ball placement or similar bond connections are done.The special process flow opens a variety of applications, which benefit from the full CMOS compatible processing and the accessible front-side.
5:00 PM - V1.4/W2.4
FsCSP Packaging Technology: Case Studies on Package Processability and Reliability Performance and its Dependence on Material Properties
Rahul Manepalli 1 , Chris Matayabas 1 , Eduardo Gacho 1
1 Assembly Technology Development, Intel Corporation, Chandler, Arizona, United States
Show Abstract5:15 PM - V1.5/W2.5
The Flexible Physiological Monitor of Patch Type Package Based on Non-weave Material.
Wen-Yang Chang 1 2 , Hung-Hsin Tsai 1 , Ying-Chiang Hu 1
1 , Industrial Technology Research Institute, Tainan Taiwan, 2 Microsystems Technology Center, Industrial Technology Research Institute, Tainan Taiwan
Show Abstract5:30 PM - V1.6/W2.6
An Approach for Characterizing Residual Mechanical Stress by Packaging Processes.
Soeren Hirsch 1
1 FEIT-IMOS, University of Magdeburg, Magdeburg Germany
Show Abstract5:45 PM - V1.7/W2.7
Laser Printing Method for Manufacturing of Flexible Copper Electrodes and Interconnects
Nurdan Demirci Sankir 1 , Andrea Hill 1 , Jennifer Lalli 1 , Brad Davis 1 , Hang Ruan 1 , Richard Goff 2 , Richard Claus 3 4
1 , NanoSonic Inc., Blacksburg, Virginia, United States, 2 Department of Engineering Education, Virginia Tech, Blacksburg, Virginia, United States, 3 Department of Materials Science and Engineering, Virginia Tech, Blacksburg, Virginia, United States, 4 Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, Virginia, United States
Show Abstract
Symposium Organizers
Vasudeva P. Atluri Intel Corporation
Sujit Sharan Intel Corporation
Ching-Ping Wong Georgia Institute of Technology
Darrel Frear Freescale Semiconductor
V2: Advanced Packaging
Session Chairs
C. Robert Kao
King-Ning Tu
Tuesday AM, November 28, 2006
Room 301 (Hynes)
9:30 AM - **V2.1
Packaging and Packaging Materials in the 2006 ITRS Roadmap.
William Chen 1 , Bill Bottoms 1
1 , ASE, Santa Clara, California, United States
Show AbstractThis talk will present the Assembly & Packaging aspects in the current International Technology Roadmap for Semiconductors (ITRS) Roadmap. Materials and materials processing has always been the key enabling elements in innovation and challenges in semiconductor packaging. Starting with a brief introduction of the history & purpose of ITRS, the talk will focus on the directions, challenges and potential solutions as seen from ITRS. The speaker will address the near-term assembly & packaging roadmap requirements and discuss new requirements and potential solutions to meet market needs in the longer term. Today assembly and packaging is a limiting factor in both cost and performance for electronic systems. This has resulted in acceleration of innovation. Design concepts, packaging architectures, materials, materials and manufacturing processes and systems integration technologies are all changing rapidly. As traditional Moore's-law scaling becomes more difficult, assembly and packaging innovation allowing scaling in the third dimension, is taking up the slack. With consumers driving the more than half of the electronic end product market, innovative technologies such as wafer packaging, stacked packages, system in package (SiP), 3D packaging, novel interconnects, will require significant materials and materials process knowledge, data and innovations for product realization in the global market place.
10:00 AM - **V2.2
Trends and Challenges in Advanced Packaging.
Debendra Mallik 1
1 , Intel, Chandler, Arizona, United States
Show Abstract10:30 AM - **V2.3
Challenges in High Density Interconnect Packaging.
Ravi Mahajan 1
1 , Intel, Chandler, Arizona, United States
Show Abstract11:15 AM - **V2.4
Optoelectronics is Again Vibrant and Penetrating Many New MarketS.
Michael Lebby 1
1 , Optoelectronics Industry Development Association, Washington, District of Columbia, United States
Show Abstract11:45 AM - **V2.5
Methodologies for Next Generation Semiconductor Packaging.
Tarun Verma 1
1 , Altera Corporation, San Jose, California, United States
Show Abstract12:15 PM - V2.6
Reactive Multilayer Foils for Wafer Level Packaging.
Xiaotun Qiu 1 , Jiaping Wang 1
1 ME, Louisiana State University, Baton Rouge, Louisiana, United States
Show AbstractSeveral bonding methods, such as anodic bonding, direct bonding, and intermediate layer bonding, have been reported for the Si wafer-to-wafer bonding processes. One important area of application for the wafer bonding technique is in wafer level packaging. However, most of the existing bonding techniques are conducted at high temperatures and thus may cause thermal damage to the microstructures. In addition to thermal considerations, it is difficult to achieve a hermetic seal for non-planarized surface. The reflow of organic photoresist has been employed to solve this problem, but an out-gassing effect has occurred. Solder reflow bonding is another solution; however the devices could be damaged by the global heating process.In this paper, we describe a novel room temperature joining technique that uses reactive multilayer Al/Ni foils as local heat sources to melt solder layers and thus bond components. The reactive multilayer foils contain hundreds of nanoscale Al and Ni bilayers. When a small spark is applied to one end of such a free-standing foil, the nanoscale layers begin to mix and release heat to the surrounding foil. This leads to more chemical mixing in adjoining areas and a chemical reaction which can self-propagate across the full length of the foil. By inserting a free-standing foil between two solder layers and two components, heat generated by the reaction of the foil will melt the solder or braze and consequently bond the components. With localized heating, temperature sensitive components such as microelectronic devices can be joined without thermal damage. Such bonding can be performed in many environments, and can be completed in a second or less.In the bonding experiments, silicon wafers were metallized with Cr and Au to ensure better wetting and bonding. Two solder layers and one reactive Al/Ni foil were stacked between two wafer specimens, with an applied pressure. The foil was then ignited with a spark and heat released from the self-propagating reaction of the foil enabled the melting of the solder layers and then the bonding of the wafer specimens. Multilayer Al/Ni foils with different thicknesses and reaction heats were used in the bonding experiments. The bond strength was measured by tensile test, showing that strong bonding can be achieved in reactive multilayer foil joining. Temperature distributions on wafer specimens during the bonding process were monitored by an infrared camera. The bonding leakage test was also performed on the bonded wafers.
12:30 PM - **V2.7
The Increasing Importance of Materials in Electronic Packaging.
Ken Brown 1
1 , Intel, Chandler, Arizona, United States
Show AbstractV3: Physical Behavior in Packaging
Session Chairs
Nikhilesh Chawla
Ravi Mahajan
Tuesday PM, November 28, 2006
Room 301 (Hynes)
2:30 PM - **V3.1
Massive Spalling of Intermetallic Compound in Lead-Free Solder Joints.
Cheng En Ho 1 , Su Yang 1 , C Robert Kao 1
1 Dept. of Chemical & Materials Eng., National Central University, Jhungli City Taiwan
Show AbstractThe massive spalling phenomenon refers to the detachment of intermetallic compound from the interface in large scale. This problem had been observed in SnAgCu soldered over Ni surface. In solder joints subjected to massive spalling, a continuous layer of intermetallic compound detached itself entirely from the interface after soldering. The gap between this detached compound and the substrate was filled with the solder. The massive spalling can weaken the solder joints and cause serious reliability problems. The massive spalling occurs in reacting systems that exhibit strong concentration dependency to a component in limited supply. The reaction between SnAgCu solder and Ni substrate meets these two conditions: a strong concentration dependency on Cu and the limited supply of Cu. The reactions between SnAgCu solders and Ni substrate depend strongly on the Cu concentration. As the Cu concentration decreases from 1.0 wt.% to 0.2 wt.%, the reaction products change from (Cu,Ni)6Sn5 to (Ni,Cu)3Sn4. In addition, the supply of Cu in SnAgCu is limited because the Cu concentration in SnAgCu is usually very low, seldom higher than 1 wt. %. During soldering, the intermetallic at the interface gradually grows thicker. As the intermetallic grows, more Cu atoms are incorporated into the intermetallic compound, and the Cu concentration in solder decreases. As the Cu concentration decreases, the type of the equilibrium intermetallic at the interface may change from (Cu,Ni)6Sn5 to (Ni,Cu)3Sn4. When this occurs, (Cu,Ni)6Sn5 spalls massively from the interface into the solder. The above explanation is only the simply version of the complex story. Our preliminary study shows that several other factors also favor the occurrence of the massive spalling. For example, smaller joint size, longer soldering time, and the presence of Au all tend to favor the massive spalling. More recently, we observed that massive spalling also occurred in the reaction between SnZn solders and Cu substrate. In this presentation, we will present what we know about this rather interesting problem, and offer potential solutions to overcome it.
3:00 PM - **V3.2
Phase Separation in Eutectic Solder Joints Driven by External Forces.
King-Ning Tu 1
1 Materials Science and Engineering, UCLA, Los Angeles, California, United States
Show AbstractDue to the trend in miniaturization and the increase in functionality, reliability of solder joint in microelectronic devices is of concern, even for wireless and handheld consumer electronic products. The reliability problems due to phase change or microstructure instability in a solder joint are caused by externally applied forces. Examples are electromigration, thermomigration, and stress-migration (creep). Since we cannot use the constant temperature and constant pressure condition, the phase change is not governed by minimizing Gibbs free energy. Typically, solder has a eutectic two-phase microstructure, so phase separation in the two-phase microstructure can occur readily without the resistance from up-hill diffusion. Failure tends to occur at the interfaces of the solder joints and to be affected by the phase separation. The failure mode will be discussed for flip chip solder joints.
3:30 PM - **V3.3
Effect of Zn Addition on the Interfacial Reactions between Cu and Lead-Free Solders.
Su-Chun Yang 1 , C. Robert Kao 1 2 , Cheng-En Ho 1 , Chien-Wei Chang 1
1 National Central University, Department of Chemical & Materials Engineering, Jhongli City Taiwan, 2 National Central University, Institute of Materials Science & Engineering, Jhongli Taiwan
Show AbstractRecently, it was reported that adding Zn to solder was an effective way for reducing the formation of both Cu3Sn and Cu6Sn5 and inhibiting Kirkendall voids formation. The objective of this study is to investigate this Zn effect in detail. Three Sn-xZn solders (x = 0.5, 0.7, and 2 wt. %) were reacted with Cu substrates at 250 C for 2-10 mins. A slight variation in the Zn concentration changed the reaction product formed at the interface. When the Zn concentration was low (x = 0.5 wt. %), the reaction product was Cu6Sn5. At high Zn concentration (x = 2 wt. %), the reaction product became Cu5Zn8. When Zn concentration was in-between (x = 0.7 wt. %), Cu6Sn5 and CuZn co-existed. The above findings are explained using the Cu–Sn–Zn phase diagram. The implication is that the type of compound forms at the interface can be controlled by adjusting the Zn concentration of the Sn-based solders.
4:45 PM - V3.5
Controlled Study of Effect of Stress on Growth of Interfacial Intermetallic Compounds in Pb-free Solder Interconnects
Wei Zhou 1 , Shwu Lan Ngoh 1 , John Pang 1
1 School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore Singapore
Show AbstractReliability of solder joint interconnects is a most critical issue in electronic packaging. There is the urgent need to understand reliability of lead-free solder joints because lead-free solders are replacing the conventional Sn-Pb solders due to legislation to ban Pb usage in electronic products. In soldering process, formation of thin intermetallic compounds due to reaction between the solder and substrate is helpful to achieve a good metallurgical bond. However, excessive intermetallic growth in service would lead to premature failure of the joint. Stress is known to influence growth of intermetallic compounds, but no existing method is available to study effect of stress on the intermetallic growth in a controlled manner. Therefore, we developed a technique to make it easy to carry out quantitative study of the stress effect at various stress levels or temperatures. We machined copper substrate into an open ring in the shape of letter C, drilled two holes in the lower and upper ends of the C-ring and used a bolt to tighten the C-ring. When the C-ring is tightened, its diameter is reduced, so the tensile stress on the outer surface and compressive stress on the inner surface can be calculated quantitatively from the amount of reduction in diameter. We coated the copper C-ring with 95.5Sn-3.8Ag-0.7Cu lead-free solder, tightened the ring to apply stress to the solder-substrate interface, and used the stressed C-rings for isothermal annealing at various temperatures. To study effect of surface finishes on the growth of intermetallic compounds, we also used copper C-rings coated either with immersion Sn or with electroless Ni/Pd plating and immersion Au (EPIG). We demonstrate that the specially designed specimens provide consistent and reliable results for studying effect of in-plane stress on intermetallic formation at the interfaces. It is interesting to find that compressive stress results in significantly faster interfacial intermetallic growth than tensile stress at the same annealing temperature and applied stress level. The technique developed can be applied to study interfacial intermetallic growth for any types of substrates, surface finishes or solders.
5:00 PM - V3.6
Bonding Interface Analysis of Au-Ag Bonding Wire.
Eun Kyu Her 1 , Hee-Suk Chung 1 , Suk Hoon Kang 1 , Kyu Hwan Oh 1 , Jong Soo Cho 2 , Jeong Tak Moon 2
1 school of materials science and engineering, Seoul National University, Seoul Korea (the Republic of), 2 , MK electron, Yongin-si, Gyeonggi-do, Korea (the Republic of)
Show Abstract5:15 PM - V3.7
Thermodynamics and Kinetics of Oxidation of Pure Indium Solders.
Harry Schoeller 1 , Junghyun Cho 1
1 Mechanical Engineering, SUNY Binghamton, Binghamton, New York, United States
Show AbstractMicroElectroMechanical System (MEMS) optical devices often require low-temperature, fluxless soldering techniques due to their high temperature sensitivity and performance requirements of the components. While seeking the development of a soldering technology using pure indium, the major focus of this study is to assess thermodynamics and kinetics of indium oxidation at various solder reflow environments that will ultimately provide an acceptable processing window for solder reflow and surface oxide cleaning. With a glove box employed to generate reducing environments, oxygen, moisture, and hydrogen contents are varied to examine their effects on oxidation and reduction behavior of indium. We also explore oxidation mechanisms at different stages of oxide growths, as well as at different regimes of temperature and time. In particular, electron transport from indium to indium oxide and diffusive transport through oxide layers are compared to determine the rate controlling mechanism under specific oxidizing conditions. For accurate thickness measurements of the oxide layers, a spectroscopic ellipsometer is employed. In addition, nanoindentation is utilized to complement the thickness measurements via ellipsometry.
5:30 PM - V3.8
A Novel PPF Technique— Sn-PPF: Effects of in-situ Formation Cu-Sn-Ni Intermetallic Nano-layer on Electronic Packaging Performances.
Lilin Liu 1 , Tongyi Zhang 1 , Ran Fu 2 , Deming Liu 2
1 Department of Mechanical Engineering, Hongkong University of Science and Technology, Hong Kong China, 2 , ASM Assembly Automation Ltd, Hong Kong China
Show AbstractA novel technique for impeding Cu out-diffusion in Cu alloy based pre-plated leadframes follows electroplating a 3-4 nm thick Sn layer on a Cu alloy base prior to electroplating a Ni layer. A 10-14 nm thick epitaxy-like and dense (Cu,Ni)3Sn intermetallic compound (IMC) layer was automatically formed en route of diffuse reaction, resulting in a drastic reduction of Cu out-diffusion and hence significantly improved protection of the leadframes against oxidation and corrosion attack. The Cu diffusion coefficient in the IMC interlayer was estimated from EDX measurements to be about 1.6×10-22m2/s at 250οC. Results from the porosity test indicate that 1nm thick Sn layer is super to a 200nm thick Ni layer in functioning as a diffusion barrier, thereby indicating the possibility to reduce the Ni layer thickness from current 1µm to 200nm. Corrosion behaviors of the Sn-PPFs and prevalent PPFs in a 3.5wt%NaCl solution were also evaluated, which gave the corrosion current densities and corrosion rates. In addition, the wire pull test, the solderability test and the bending test were performed to ensure the Sn-PPF’s compatibility with basic packaging requirements.Note: This work was supported by the donated research grant, ASMML04/05.EG01, from ASM Assembly Automation Ltd., Hong Kong, and ASM Semiconductor Materials (Shenzhen) Ltd., China, and has been applied for US Patent. The patent application number is 11/293,711, titled “Leadframe comprising tin plating or an intermetallic layer formed therefrom”, which was filed on 1 December, 2005.
5:45 PM - V3.9
Challenges for large form factor Land Grid Array Sockets: Surface Mount Technology and Beyond.
Subhadarshi Nayak 1 , Gregorio Murtagian 1 , Brent Stone 1 , Pramod Malatkar 1 , Donald Tran 1 , Jagdish Umaretiya 1
1 , Intel, Chandler, Arizona, United States
Show Abstract
Symposium Organizers
Vasudeva P. Atluri Intel Corporation
Sujit Sharan Intel Corporation
Ching-Ping Wong Georgia Institute of Technology
Darrel Frear Freescale Semiconductor
V4: Mechanical Behavior in Packaging
Session Chairs
Ken Brown
Indranath Dutta
Wednesday AM, November 29, 2006
Room 301 (Hynes)
9:30 AM - **V4.1
Technology Development and Integration Challenges with Pb-Free Solder Interconnects.
Nasser Grayeli 1
1 , Intel Corporation, Chandler, Arizona, United States
Show AbstractThe conversion to lead free materials and process technologies is a significant undertaking for the electronic packaging industry, with many challenges having been overcome during the initial transition. The move to less ductile, higher melting point Sn-Ag based solder alloys has impacted the development and integration of silicon-to-package and package-to-board interconnects, and has driven the need to optimize materials and process for the new metallurgy. The goal of this work has been to provide the best possible performance across multiple package and product architectures as the wide range of market segments into which Pb-free products are being applied is driving a divergence in use conditions and field performance requirements. For example, solder joint thermal fatigue is a concern for high end, high power applications while exceptional shock resistance is expected in applications where small form factor, fine pitch interconnect devices are typically used. The approach has been to optimize both the bulk alloy mechanical properties and the interfacial properties of the solder-printed circuit board surface finish system.
10:00 AM - **V4.2
Compression Creep Behavior of the 95.5Sn-(4.3, 3.9, 3.8)Ag-(0.2, 0.6, 0.7)Cu Solders.
Paul Vianco 1 , Jerome Rejent 1 , Alice Kilgo 1 , Joseph Martin 2
1 , Sandia National Laboratories, Albuquerque, New Mexico, United States, 2 , Orion International, Inc., Albuquerque, New Mexico, United States
Show AbstractA matter of discussion has been the effect had by minor alloy differences on the long-term reliability of electronic interconnections made with one of the various Sn-Ag-Cu solder compositions. A direct determination could be made of any such differences by means of accelerated aging protocols and printed wiring assembly (PWA) test vehicles assembled with each of the candidate Pb-free solders. However, such a study would be daunting. Rather, an investigation was undertaken to compile the stress-strain and creep properties of the three Pb-free compositions within the Sn-Ag-Cu alloy family. The objective was to determine the sensitivity of the stress-strain (time-independent) and creep (time-dependent) mechanical properties to Cu concentration in the candidate solders. Those solder compositions were 95.5Sn-(4.3, 3.9, 3.8)Ag-(0.2, 0.6, 0.7)Cu (wt.%). The samples were tested in the as-fabricated condition as well as following a 125°C, 24 hour annealing treatment. The initial tests, which examined the stress-strain properties, identified significant differences between their time-independent deformation properties. The yield stress increased with Cu content; the effect became less dramatic with increasing test temperature. Thus, it was deemed essential to perform the follow-on creep study in order to determine the composition sensitivity of the time-dependent deformation. Creep tests were performed at temperatures of -25°C to 160°C and stresses of 1 MPa to 45 MPa. The steady-state or minimum creep rate was analyzed for the creep rate kinetics, using the “sinh law” representation. The effect of the solder composition on the steady-state creep rate kinetics and creep strain magnitude will be discussed in terms of a mechanism controlling the deformation. The effect by the annealing treatment provided an indication of the sensitivity of creep to the likely range of solder microstructures expected in actual interconnections. Also, the evolution of the creep-tested microstructures were examined with respect to their sensitivity to the applied stress and temperature conditions. Several samples were tested well into the tertiary creep stage to determine the mechanism responsible for time-dependent deformation/damage that culminated into the eventual creep rupture of the material.
10:30 AM - **V4.3
Thermomechanical Behavior and Reliability of Pb-Free Solders
Nik Chawla 1
1 School of Materials, Arizona State University, Tempe, Arizona, United States
Show AbstractThe creep, thermal fatigue behavior, and microstructure of bulk solder and solder spheres will be reviewed in this talk. Results on Sn-Cu, Sn-Ag, Sn-Ag-Cu, and pure Sn, will be presented. It will be shown that the thermomechanical behavior of Sn-rich solders is very much dependent on: (a) size spacing of Ag3Sn particles in the Sn-matrix, (b) Sn matrix microstructure, and (c) temperature. Changes in the creep stress exponent with increasing stress were observed and will be explained in terms of a threshold stress for creep. The activation energy for creep was also found to be temperature dependent. Scanning and transmission electron microcopy were used to characterize the as-reflowed microstructure, as well as to understand deformation mechanisms in the solder. Creep and thermal fatigue mechanisms will be presented and discussed in terms of the solder microstructure.
11:30 AM - V4.4
Factors Affecting the Mechanical Properties of Cu/electroless Ni-P/Sn-3.5Ag Solder Joint.
Aditya Kumar 1 2 , Zhong Chen 1 , Chee Cheong Wong 1 , Subodh Gautam Mhaisalkar 1 , Kripesh Vaidyanathan 2
1 School of Materials Science and Engineering, Nanyang Technological University, Singapore Singapore, 2 , Institute of Microelectronics, Singapore Singapore
Show AbstractThis work investigates the factors that affect the mechanical properties of Cu/electroless Ni-P/Sn-3.5Ag solder joint. For the investigation, solder joints having three different electroless Ni-P thicknesses have been tensile tested after solid-state aging at different temperatures for various durations. Several factors such as Ni3Sn4 morphology, accumulation of spalled Ni3Sn4 intermetallic particles at the solder/Ni3Sn4 interface, growth of interfacial compounds (IFCs), and formation of Kirkendall voids at the Ni3P/Cu interface, are found to deteriorate the mechanical properties of solder joint. Although all these factors, either alone or combined, reduce the tensile strength of solder joint and increase the brittleness of failure, the most severe decrease in tensile strength with a brittle fracture at the Cu/Ni3P interface is observed after the formation of a layer of Kirkendall voids at the Ni3P/Cu interface due to out diffusion of Cu from the substrate. The layer of Kirkendall voids remains the main cause of brittle failure even after transformation of Ni3P layer into a ternary Ni-Sn-P compound layer and formation of Cu-Sn intermetallics at the Ni-Sn-P/Cu interface. Based on the understanding of the factors that affect the mechanical properties of solder joints, possible solutions are suggested.
12:00 PM - V4.6
Time-Lapse Measurements of Creep in Au-Sn Die Bonds.
Ryan Marinis 2 , Adam Klempner 2 , Ryszard Pryputniewicz 2 , Peter Hefti 2 , Thomas Marinis 1 , Joseph Soucy 1
2 Mechanical Engineering, Worcester Polytechnic Institute, Worcester, Massachusetts, United States, 1 , Draper Laboratory, Cambridge, Massachusetts, United States
Show AbstractGold-tin braze is the preferred material for attaching high-precision MEMS inertial sensors within hermetic ceramic packages. The bonds can be made at relatively low temperatures, are mechanically robust, and outgas at very low rates in vacuum sealed packages. There is one significant limitation to Au-Sn bonds, however. The thermal expansion coefficients of MEMS die and ceramic packages are not perfectly matched and temperature gradients occur when the assembly is cooled after brazing. As a result, there is considerable residual stress in the bonded assembly, which is accommodated to some extent by distortion of the sensor die. Over time, as these stresses relax, the distortion of the die changes, which causes the spacing between elements of the integral MEMS sensor to change as well. An important element of sensor-package design is insuring that stress relaxation effects do not cause the instrument to drift beyond its performance specification limits over a typical lifetime of 20 years. Even though Au-Sn has been used for decades to attach silicon chips to ceramic substrates, there is little data available, particularly at low temperatures. An oven, with a specially designed window, allowed in-situ measurements to be made as a function of temperature, joint thickness and load stress. Additionally, a MEMS device brazed to a package with Au-Sn has been measured interferometrically over time to quantify die distortion in a packaged application.
12:15 PM - V4.7
Mechanical Property Measurement of Interconnect Materials by Magnetostrictive Sensors
Cai Liang 1 , Bart Prorok 1 , Leslie Mathison 1 , Charles Ellis 2
1 Materials Engineering, Auburn University, Auburn, Alabama, United States, 2 Electrical and Computer Engineering, Auburn University, Auburn, Alabama, United States
Show AbstractThis paper reports on the measurement of elastic modulus for some electronic thin film materials used in electronic interconnects by a magnetostrictive sensor. Thin film materials of Au, Sn, In and lead free solder (AuSn) were sputter deposited onto well defined strips of MetglasTM. This material possesses magnetostrictive properties whereby it deforms when subjected by a magnetic field and generates a magnetic field when deformed. The MetglasTM is driven to resonance via application of a modulated magnetic field generated by a Helmholtz coil. The elastic modulus of the above materials was determined by measuring the resonant frequency of the sensors before and after film deposition and using the frequency shift, two analytical approaches were employed to extract values. The as sputtered films were examined by X-ray Diffraction (XRD) and Scanning Election Microscope (SEM) to characterize their microstructures. The elastic modulus of Au films was determined by employing two mathematical methodologies that resulted in values of 71.2GPa and 75.9GPa, which exhibit less than 5% divergence. Errors in the different measuring methodologies are discussed. Moreover, elastic modulus values of solder materials of AuSn (80/20 at%), tin and indium films, which were also measured in their as deposited forms, will be discussed. This method represents a potentially new, non-destructive method to determine critical material properties of as deposited materials.
12:30 PM - V4.8
Mixed-Mode Testing of Wafer Bonded Interfaces
Rajappa Tadepalli 1 , Kevin Turner 2
1 Materials Science and Engineering, M.I.T., Cambridge, Massachusetts, United States, 2 Mechanical Engineering, University of Wisconsin-Madison, Madison, Wisconsin, United States
Show AbstractAccurate characterization of interfacial adhesion is essential for the development of robust bonding processes that yield reliable bonds. In most packaging applications, the bonded interface experiences a combination of shear as well as normal loading (i.e. mixed-mode loading). As such, when characterizing the fracture properties of a bond, it is important to measure the interface toughness under similar mixed-mode conditions. Unfortunately, there are relatively few effective techniques for characterizing the mixed-mode interface toughness of bonded wafers and die. In the current work, a chevron specimen with layers of different thickness that provides a mixed-mode loading at the interface is analyzed. The specimen is well-suited for the measurement of bonds between typical semiconductor substrates that range in thickness from 0.1 to 1 mm.The specimen, which has a nominal geometry of 10 x 10 mm by 0.5-2 mm thick, was analyzed using a 3-D finite element (FE) model in combination with the virtual crack closure technique. The results of the analysis show that the phase angle (i.e. the degree of mode-mixity) at the interface can be varied from 0° to 35° by changing the layer thickness ratio from 1 to 0.1. The FE analysis also provides expressions that allow for the calculation of interface toughness from experimental data. The results have been fitted to appropriate expressions so that the simulation results are accessible. Typical experimental results from bonded silicon wafers will be presented with the modeling results to illustrate the use of the specimen and the FE analysis.In addition to the results above, this work will also discuss common situations in packaging in which mixed-mode loading arises in order to provide a guide as to when using the chevron specimen with different layer thicknesses is appropriate.
12:45 PM - V4.9
Fracture of Organosilicate Glass Coatings at Low Temperature.
Youbo Lin 1 , Joost Vlassak 1
1 DEAS, Harvard University, Cambridge, Massachusetts, United States
Show AbstractV5: Electromigration and Thermal Behavior in Packaging
Session Chairs
Paul Vianco
Vijay Wakharkar
Wednesday PM, November 29, 2006
Room 301 (Hynes)
2:30 PM - V5.1
Electromigration Driving Force and Threshold Product of Current Density and Line Length for Sn-based Alloy Solders
Bit-Na Kim 1 , Min-Seung Yoon 1 , Byoung-Joon Kim 1 , Young-Bae Park 2 , Young-Chang Joo 1
1 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 School of Materials Science and Engineering, Andong National University, Andong Korea (the Republic of)
Show AbstractWith the higher packaging density of the modern electronic devices, the applied current density of the solder bumps has been increased. Because of such increase in current density, there has been an increasing reliability concern about electromigration of solder. To minimize electromigration failure, the Blech product, i.e. the threshold product of the current density and the line length, is a very important parameter. It is because no line will fail due to electromigration if the product of its length and current density is smaller than the Blech product. For the interconnects of pure material such as Al or Cu, it is well established that the threshold current density is inversely proportional to line length, or equivalently, the Blech product is constant. [1] On the contrary, solders are made up of binary, ternary, or multinary, alloy materials. This makes the electromigration characteristics, including the Blech product, of solder complicated to understand. In fact, there have been few reports available on the Blech products of alloy solders. Using the edge-drift structure, we have investigated the Blech products for solders of various alloys: SnAg3.0Cu0.5, eutectic SnPb, and Sn5Pb95. The reflowed-solder lines with thickness of 4 to 5 µm on Ni or Cu underlayer were fabricated. These lines, of which length varied from 100 to 1000 µm, were stressed under the various current densities of 2 to 6 x104 A/cm2 at temperature either of 100 or 140 oC. Drift velocity of a line under electromigration as a function of applied current density was analyzed from interruptive observations for the whole line using a scanning electron microscope (SEM). The threshold current density was estimated from the current density extrapolated to zero drift velocity. The threshold current densities of Pure Sn and SnAg3.0Cu0.5 solder lines were inversely proportional to their line lengths. However, even though the lines of a ternary alloy solder as well as that of pure Sn had a constant Blech product, the lines of eutectic SnPb solder did not. This suggests that the back-flux force, induced by chemical potential due to a compositional gradient built up by migration of Pb prior to that of Sn as well as stress-gradient, may play a significant role in electromigration of eutectic SnPb. With comparison of the measured Blech products for the lines of pure Sn, SnAg3.0Cu0.5, eutectic SnPb ,Sn5Pb95 and pure Pb, the differences in the characteristics of the back-flux in electromigration of various Sn-based alloy solders will be discussed in more detail. [1] I.A. Blech, J. Appl. Phys., 47, 1203 (1976)
2:45 PM - V5.2
Morphology of the Electromigration Damage of Lead-free Solders on Electroless NiP/Cu Metallization.
Jin-Wook Jang 1 , Lakshmi Ramanathan 1 , Jong-Kai Lin 1 , Darrel Frear 1
1 , Freescale Semiconductor, Inc., Tempe, Arizona, United States
Show Abstract3:00 PM - V5.3
In-situ Investigation of Electromigration Characteristics of Eutectic SnPb and SnAgCu Interconnects.
Young-Bae Park 1 , Oh-Han Kim 2 , Min-Seung Yoon 3 , Yong-Duk Lee 1 , Young-Chang Joo 3
1 School of Materials Science and Engineering, Andong National University, Andong Korea (the Republic of), 2 , STATSchipPAC R&D Center, Icheon Korea (the Republic of), 3 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Show Abstract3:15 PM - V5.4
Geometrical Effect of Bump Resistance for Flip-Chip Solder Joints during Electromigration Test measured by Kelvin Probes.
Shih-Wei Liang 1 , Yun-Wei Chang 1 , Chih Chen 1
1 Materials Science & Engineering, National Chiao Tung University, Hsinchu Taiwan
Show AbstractDue to the line-to-bump structure, the bump resistance of flip-chip solder joints was difficult to be measured by daisy-chain structures. In this study, the Kelvin structure for flip-chip solder joints were designed and fabricated to measure the bump resistance. The bump resistance of flip-chip solder joints was measured experimentally and analyzed by finite element method. The measured value was only about 0.9 mohm at room temperature, which was much lower than the expected. Three-dimensional modeling was performed to examine the current and voltage distribution in the joint. The simulated value was 7.7 mohm, which was about 9 times larger than the experimental value. The current crowding effect was found to be responsible for the difference in bump resistance. Therefore, the measured bump resistance strongly depended on the layout of the Kelvin structure. Various layouts were simulated to investigate the geometrical effect of bump resistance, and significant geometrical effect was found. A proper layout was proposed to measure the bump resistance correctly. The Kelvin structure would play an important role in monitoring void formation and microstructure changes during electromigration of flip-chip solder joints. Effect of void formation on the bump resistance will be discussed.
3:30 PM - V5.5
Kinetic Study of Grain Rotation of Tin Under Electromigration.
Albert TzuChia Wu 1 , Ming-Hsung Chen 1 , Cheng-Ping Huang 1 , C. Robert Kao 2
1 Materials and Mineral Resources Engineering, National Taipei University of Technology, Taipei City Taiwan, 2 Chemical and Materials Engineering, National Central University, Chungli City Taiwan
Show Abstract4:15 PM - V5.6
Electric Current Induced Brittle Failure of Lead and Lead-free Solder Joints with Electroless Ni-P Metallization.
Aditya Kumar 1 2 , Zhong Chen 1 , Chee Cheong Wong 1 , Subodh Gautam Mhaisalkar 1 , Kripesh Vaidhyanathan 2
1 School of Materials Science and Engineering, Nanyang Technological University, Singapore Singapore, 2 , Institute of Microelectronics, Singapore Singapore
Show AbstractThe mechanical properties of thermally-aged and electrical current-stressed lead (Sn-37Pb) and lead-free (Sn-3.5Ag) solder joints with electroless Ni-P metallization were investigated using tensile testing and nano-indentation. Multi-layered test samples Cu/Ni-P/solder/Ni-P/Cu having two electroless Ni-P/solder interfaces were prepared. Tensile testing results of the solder joints showed that irrespective of the type of solder, electric current causes the brittle failure of solder joint and the tendency of brittle failure increases with the current density. The lead solder joint was found to be more prone to current induced brittle failure as compared to the lead-free solder joint. In lead solder joint, brittle failure always occurred at cathode side Ni-P/Sn-37Pb interface (where electrons flow from Ni-P to solder), whereas, no such polarity effect was observed in the case of lead-free solder joint. Nano-indentation test revealed that current increases the hardness and reduced modulus of solder, thus causing the failure to occur at the brittle solder/interfacial compounds (IFCs) interface rather than inside the ductile solder. Microstructure analysis of solder joint revealed that electric current also causes grain coarsening in the lead solder. However, no significant effect of electric current was observed on the growth of Ni3Sn4 compound. Detailed explanations of these mechanical and micro-structural observations have been provided.
4:30 PM - V5.7
Evaluation of Void Formation Mechanism in Cu Thin Films; Separation of The Effect of Electron Wind Force and Stress
Yousuke Fujii 1 , Masanori Tsutsumi 2 , Junya Inoue 1 , Toshihiko Koseki 1
1 Materials Engneering, The University of Tokyo, Tokyo Japan, 2 , FUJITSU Co. Ltd. , Tokyo Japan
Show AbstractMost of studies on electromigration (EM) and stress-induced voiding (SIV) in Cu Dual-Damascene Interconnects (Cu-DDI) have been conducted on the multilevel interconnects structure and focused only on estimating the MTTF (Mean Time To Failure) of EM and SIV. However, the atomic flux produced during EM can be the mixed product of EM and SIV. In addition, it is very difficult to deal with the stress distribution in Cu-DDI due to its complicated structure. To clarify the mechanisms of EM and SIV, they have to be separately analyzed in a simpler way. In this work, the EM and SIV behaviors in Cu and Cu alloys thin films are studied separately. We evaluated the characterization of EM in a newly developed interconnect structure where the effect of current density can be observed by the absence of stress disturbance. SIV, on the other hand, is examined in detail by applying a uniform stress to Cu films without electric current. For an investigation of the EM behavior under high current density without stress disturbance, a modified Standard Wafer-level Electromigration Acceleration Test (SWEAT) structure was employed. Cu or Cu alloy thin film (100nm) was deposited on a Si substrate by electron beam physical deposition (EB-PVD) using a SWEAT patterned mask. In some test samples, 10nm-thick Ta film was deposited on the Cu film as a capping layer in order to suppress vacancy sinks and sources on the free surface of Cu films. The average current densities in the narrow regions of the test structure were controlled to be constant on the order of 1 MA/cm2. For the case of SIV test, Cu and Ta thin films were deposited on heat-resistant polyimide substrates by EB-PVD. In this case, the Ta layer serves as a barrier to suppress surface diffusion of Cu. To apply uniform tensile stress to the film, a uniform curvature was applied to the substrate. The samples were kept at a variety of elevated temperature to clarify the mechanism dominating SIV.As a result of EM tests, it was clearly demonstrated that void and hillock formations are concentrated mainly in the region with high current density gradient without stress disturbance. By observing the location of voids, the gradient of current density as well as high current density is considered to be the dominant cause of EM void formation. After the SIV test performed under the high stress of 1GPa, voids are observed to form at grain boundaries and grain boundary triple junctions. Under the high stress, SIV is shown to be generated in the absence of stress gradient. The detailed effects of alloying elements in Cu on EM and SIV will also be presented in the presentation.
4:45 PM - V5.8
Thermal Management in High-Density, Stacked-Die, Multi-chip Modules.
Thomas Marinis 1 , Darek Pryputniewicz 1 , Caroline Kondoleon 1 , Jason Haley 1
1 , Draper Laboratory, Cambridge, Massachusetts, United States
Show AbstractVery high density multi-chip modules are being manufactured by tiling an alumina substrate with IC chips and passive components, laminating a film of Kapton over them, laser drilling vias to their I/O pads, and interconnecting them with photo patterned, copper metallization. Additional layers of chips and interconnect are bonded on top of this first interconnect layer as required. Two layers of chips and seven layers of interconnect are typically used in current products. As higher power applications have emerged and the power density of IC chips has increased, thermal management has become a significant element of module design. We have been conducting a thermal modeling effort to map the design space for this technology. Our principal objective is to determine the lowest thermal impedance configuration for a given chip set and method of heat removal. A second objective is to determine what gains in module performance might be realized by improvements in material properties or changes in the relative thicknesses of dielectric and metal layers.One question in particular that we are addressing is, what is the optimal number of interconnect layers from a thermal impedance perspective? A significant portion of the heat flux is conducted between dielectric layers, by the electrical vias. When wiring density is doubled, so as to eliminate an interconnect layer, the size and number of vias is reduced proportionately, which decreases the effective thermal conductivity of the dielectric layer. The thermal impedance to heat spreading within an interconnect layer is also increased, because metallization thickness has to be reduced to facilitate high density photolithography. Design is further constrained, by several practical limitations on how thin the dielectric layers can be made. Optimal thermal performance is obtained by correctly sizing interconnect wiring density to the thermal impedance of the dielectric layer. Doubling the thermal conductivity of the dielectric is a challenging problem in materials engineering. Success, however, would significantly improve module thermal performance.
5:00 PM - V5.9
Thermal Resistance of the Solder Joint in High Brightness Light Emitting Diode (HB LED) Packages.
Jin-Woo Park 1 , Young-Bok Yoon 1 , Sang-Hyun Shin 2 , Sang-Hyun Choi 2
1 Fundamental Technology Center, Samsung Electro-Mechanics, Suwon, Gyunggi-Do, Korea (the Republic of), 2 Packaging Technology Team, Samsung Electro-Mechanics, Suwon, Gyunggi-Do, Korea (the Republic of)
Show AbstractHigh brightness (HB) LED, which is the LED of high light output (10~100 lm* per LED), is a strong candidate for the next-generation general illuminations. Also, the applications of HB LED in automotive lighting, signs and displays, and mobile phones have been extensively grown for last decade. The optical power and reliability of the HB LED depend strongly on the successful heat management of packages because the conversion efficiency from electrical to optical power decreases with increasing junction temperature. To decrease junction temperature below a certain limit during operation, using highly conductive materials for the package, particularly for heat sink, is essential. However, in terms of cost and reliability, selections of the materials are very limited. It has been known that thermal resistance (Rth) of the solder joint between the HB LED chip and heat sink constitutes a large portion of total Rth of the HB LED package while the reduction in Rth of the packages by varying materials within the limited selections is insignificant. Rth of the solder joint becomes larger than the original solder in general as the thermal properties of the solder are altered with formation of defects and/or intermetallic compounds (IMC) during joining and operations. However, quantitative prediction of Rth of the joint is difficult since the structure of the joint is highly dependent on processing conditions. In addition, the measurement technique of Rth of each part in the package has not been standardized yet. In this study, efforts have been made on developing theoretical understanding of the important factors affecting the Rth of the joint. Rth was calculated by finite element method (FEM) simulations and transient thermal analysis using structure function and transient temperature changes measured in the packages on cooling. Commercial HB LEDs were epi-down flip-chip, die bonded to Si heat sinks using Au-Sn eutectic solder and the joint structure was analyzed using transmission electron microscopy (TEM). Based on the theoretical understanding and the calculation results, the effects of various joint microstructures on the increased Rth of the joint could be investigated. The guidelines for reducing Rth of the joint were also proposed.
5:15 PM - V5.10
Advanced Thermal Interface Materials
Yimin Zhang 1 , Daniel Duffy 1 , Jeff McVey 1 , Allison Xiao 1
1 Corporate Research, National Starch & Chemical, Bridgewater, New Jersey, United States
Show AbstractHeat buildup in electronic devices should be dissipated efficiently to assure performance and reliability. Thermal interface materials (TIMs) are used to joint a heat source and a heat sink to improve the heat transfer. Current TIMs have limitations and cannot accommodate the growing powder density of these devices. We will illustrate the methodology, such as using nano-structured materials and combination of different particles, to develop TIMs for various applications. The methodology can lead to significant improvement in thermal conductivity. Advanced characterization tools will also be presented.
Symposium Organizers
Vasudeva P. Atluri Intel Corporation
Sujit Sharan Intel Corporation
Ching-Ping Wong Georgia Institute of Technology
Darrel Frear Freescale Semiconductor
V6: Nanotechnology in Packaging
Session Chairs
Jin-Wook Jang
Ching-Ping Wong
Thursday AM, November 30, 2006
Room 301 (Hynes)
9:30 AM - **V6.1
Nanomaterials for Advanced Interconnection and Packaging.
Sungho Jin 1
1 Materials Science & Engineering, University of California, San Diego, La Jolla, California, United States
Show AbstractEver-decreasing feature size of electronic circuits and devices for higher-density assembly requires innovative nanoscale materials and technologies to enable nano-interconnections and nano-packaging with significantly reduced conductor diameter and length. Nanomaterials such as nanowires and nanoparticles offer exciting possibilities for ultra-high-density interconnection and packaging. Alignable nanowires such as carbon nanotubes can provide interconnection with extremely large current carrying capability in excess of 10{8} A/cm2 with the conductor diameter as small as ~1 nanometer, and vertically- or spring-configured nanowire array can produce elastically compliant interconnections that can accommodate large thermal expansion mismatch between connected devices. High-density, periodic array of metallic nanoparticles suitably coated with solderable surface can allow convenient areal array packaging. As the two-dimensional circuit interconnection and packing get more crowded, a development of new, three-dimensional nano interconnection and packaging methodology becomes highly desirable. In this talk, various possible interconnection configurations and the use of nanowires or nanoparticles for ultra-high-density circuit interconnection and packaging will be discussed, and some synthesis and geometry control of the nanomaterials for enhanced physical properties will also be described.
10:00 AM - **V6.2
Shape Controlled Nanoparticles for Nanoelectronics.
Zhong Wang 1
1 School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractCeria nanoparticles are a widely used nanomaterial for applications in catalysts, fuel cell, and microelectronics. An important factor that influences the performance of CeO2 is the particle shape. A systematic study has been carried out to determine the shapes of CeO2 nanoparticles. For particles in the size range of 3-10 nm, the particle shape is dominated by truncated octahedral that is defined by the {100} and {111} facets, thus, the large size CeO2 particles are dominated by the octahedral shape with flat surfaces [1]. For chemical-mechanical planarization of advanced integrated circuits, the polyhedral shaped nanoparticles scratch the silicon wafers and increase defect concentrations. We present here an innovative approach for large-scale synthesis of single-crystal ceria nanospheres [2], which can reduce the polishing defects by 80% and increase the silica removal rate by 50%, facilitating precise and reliable mass-manufacturing of chips for nanoelectronics. The principle demonstrated here could be applied to other oxide systems.[1] Z.L. Wang and X.D. Feng, J. Phys. Chem. B, 107, 13563 (2003).[2] X.D. Feng, D.C. Sayle, Z.L. Wang et al., Science, 312, 1504 (2006).[3] The work presented here was also contributed by Xiangdong Feng, Dean C. Sayle, M. Sharon Paras, Brian Santora, Anthony C. Sutorik, Thi X. T. Sayle, Yi Yang, Yong Ding, Xudong Wang, and Yie-Shein Her.
10:30 AM - **V6.3
Opportunities and Challenges in the use of Nanotechnology & Nano-Materials.
Vijay Wakharkar 1 , Chris Matayabas 1
1 , Intel, Chandler, Arizona, United States
Show Abstract11:30 AM - **V6.4
Development of Smart Lead-free Solders via Shape-Memory Alloy Reinforcement.
Indranath Dutta 1 , Bhaskar Majumdar 2 , Tiandan Chen 1 , Koh Choon Chung 1
1 Mechanical & Astronautical Engineering, Naval Postgraduate School, Monterey, California, United States, 2 Dept of Materials Science & Engineering, New Mexico Institute of Mining & Technology, Socorro, New Mexico, United States
Show AbstractMicroelectronic solder joints are exposed to aggressive thermo-mechanical cycling (TMC) during service, resulting in strain localization near solder / bond-pad interfaces, which eventually leads to low-cycle fatigue (LCF) failure of the joint. In order to mitigate these strain concentrations and thereby improve LCF life, a 'smart solder' reinforced with a martensitic NiTi based shape memory alloy (SMA) is being developed. This paper presents an overview of processing, characterization and modeling of these composite solders, and articulates the role of NiTi particles on strain evolution in composite solders. Based on finite element modeling and experiments on model single fiber composites, it is shown that NiTi pariculate reinforcements can reduce inelastic strain levels in the solder via shape recovery associated with the B19'to B2 transformation. In situ TMC studies in the SEM, in conjunction with strain analysis via digital image correlation, show evidence of reverse deformation in the solder commensurate with the NiTi phase transformation, demonstrating the conceptual viability of the smart solder approach. Details of processing and joint formation, and the resultant microstructures of smart solder are discussed. Finally, results of TMC experiments on monolithic solder and NiTi/solder composite joints are reported, highlighting the beneficial effect of shape-memory transformation in reducing inelastic strain range, and hence enhancing the LCF life, of solders.______________________________________________________This research is supported by the U.S. Army Research Office.
12:00 PM - V6.5
Well-Aligned In-situ formed Open-end Carbon Nanotube for Device and Assembly Applications.
Lingbo Zhu 2 1 , ChingPing Wong 1
2 Chemical and Biomolecular Engr, Georgia Institute of Technology, Atlanta, Georgia, United States, 1 Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractThe remarkable properties of carbon nanotubes (CNTs) with ballistic electrical transport and ultra high thermal conductivity have made them very attractive for microelectronic interconnects, thermal management and nanoscale device applications.This paper will discuss our recently developed chemical vapor deposition(CVD) growth of well-aligned in-situ formed open-end CNT films/arrays, their characterizations and applications related to microelectronic applications. However, this CVD process requires a high CNT growth temperature (>600 °C) and resulted poor substrate adhesion which impede the CNT implementation in microelectronics. To circumvent these obstacles for a successful CNT application, we have demonstrated a low-temperature “CNT transfer technology process”. The process is featured with a separation of the CNT growth and CNT to device assembly, which enable by an in-situ formed open-ended CNT structure which we have recently developed. This technique is similar to a flip-chip reflow process and is compatible with current microelectronic device fabrication sequences and surface mount component assembly technology.Field emission testing of the as-assembled CNT devices indicates good field emission characteristics, with a field enhancement factor of 4540. In addition, we will also demonstrate the creation of hierarchic structures (micro and nano-scaled) by controlled growth of CNTs for Lotus Effect(superhydrophobic) surfaces coatings and its geometric design and optimization will be discussed. Aligned CNT prototypes for thermal management and electrical interconnect will also be illustrated. Referneces:1.L. Zhu, Aligned Carbon Nanotube Stacks by Water –assisted Selective Etching,” Nano Letters, Vol.5, No.12, p.2641-2645(2005)2.L. Zhu, Y. Xiu, J. Xu, P. A. Tamirisa, D. W. Hess, and C. P. Wong, "Superhydrophobicity on Two-Tier Rough Surfaces Fabricated by Controlled Growth of Aligned Carbon Nanotube Arrays Coated with Fluorocarbon", Langmuir, Vol. 21, No. 24, p. 11208-11212 (2005).3.L. Zhu, Y. Sun, D. Hess, and C. P. Wong, "Well-Aligned Open-Ended Carbon Nanotube Architecture: an Approach for Device Assembly," Nano Letters, Vol. 6(2), pp.243-247 (2005).4.L. Zhu, J. Xu, Y. Xiu, D. Hess, and C. P. Wong, "A Rapid Growth of Aligned Carbon Nanotube Films and High-Aspect-Ratio Arrays," Journal of Electronic Materials, Vol. 35, No. 2, p.195-201(2006).5.L. Zhu, J. Xu, Y. Xiu, Y. Sun, D. W. Hess, and C. P. Wong, "Growth and Electrical Characterization of High-aspect ratio Carbon Nanotube Arrays", Carbon, Vol. 44,No. 2, p.253-258 (2006)
12:15 PM - V6.6
Effect of Single-walled Carbon Nanotube Purity on the Performance of Nanotube-based Composites for Thermal Management.
Aiping Yu 1 2 , Mikhail Itkis 1 2 , Elena Bekyarova 1 2 , Robert Haddon 1 2
1 , UC-Riverside, Riverside, California, United States, 2 , Center for Nanoscale Science and Engineering, Riverside, California, United States
Show Abstract12:30 PM - V6.7
Examination of the Melting Point of Sn Nano-Particles for Nanosolder Applications
Kevin Grossklaus 1 , Carol Handwerker 1 , Eric Stach 1
1 Materials Science and Engineering, Purdue University, West Lafayette, Indiana, United States
Show AbstractAs the result of legislation in Europe prohibiting the use of lead in consumer electronics, there has been much recent emphasis on developing lead-free solders. One of the primary requirements for a lead-free solder is that its melting point approach that of the tin-lead eutectic solders traditionally used in electronic applications. However, many of the most promising lead-free alloys have melting points 30 to 50 degrees above the 183 °C melting point of the tin-lead eutectic. As a novel approach to this problem nanoparticles are being studied for use in solder materials. By decreasing the particle size of the metals used in soldering to the nanoscale, it is hoped that the melting point can be lowered to close to the 183 °C mark. As part of the process of developing a “nanosolder,” this work examines the melting behavior of nano-particles of Sn produced by an organo-metallic chemical process. The tin nanoparticles were characterized and their melting behavior was examined by transmission electron microscopy (TEM) and differential scanning calorimetry (DSC). The results will be discussed with respect to classical and modern theory regarding the role of surface area and size on the properties of nanoscale materials.
12:45 PM - V6.8
Water Diffusion and Fracture in Nano-porous Organosilicate Glass Coatings.
Youbo Lin 1 , Joost Vlassak 1
1 DEAS, Harvard University, Cambridge, Massachusetts, United States
Show AbstractV7: Thin Films and Adhesives in Packaging
Session Chairs
Thursday PM, November 30, 2006
Room 301 (Hynes)
2:30 PM - V7.1
High Performance Conductive Adhesives for Lead-free Interconnects.
Yi Li 1 , ChingPing Wong 1
1 Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractTin-lead solder alloys are widely used in the electronic industry. They serve as interconnects that provide the conductive path required to achieve connection from one circuit element to another. There are increasing concerns with the use of tin-lead alloy solders in recognition of hazards of using lead. Lead-free solders and electrically conductive adhesives (ECAs) have been considered as one of the most promising alternatives of tin-lead solder. ECAs consist of a polymeric resin (such as, an epoxy, a silicone, or a polyimide) that provides physical and mechanical properties such as adhesion, mechanical strength, impact strength, and a metal filler (such as, silver, gold, nickel or copper) that conducts electricity. ECAs offer numerous advantages over conventional solder technology, such as environmental friendliness, mild processing conditions (enabling the use of heat-sensitive and low-cost components and substrates), fewer processing steps (reducing processing cost), low stress on the substrates, and fine pitch interconnect capability (enabling the miniaturization of electronic devices). Therefore, conductive adhesives have been used in LCD (liquid crystal display) and smart card applications as an interconnect material and in flip-chip assembly, CSP (chip scale package) and BGA (ball grid array) applications in replacement of solder. However, no currently commercialized ECAs can replace tin-lead metal solders in all applications due to some challenging issues such as lower electrical conductivity, conductivity fatigue (decreased conductivity at elevated temperature and humidity aging or normal use condition) in reliability testing, limited current-carrying capability, and poor impact strength. In this presentation, different approaches are applied to enhance the electrical performance of ECA, including the improvement of electrical conductivity, stabilization of contact resistance and electromigration control for long term reliability. High performance electrically conductive adhesives are developed for potential applications as environmental friendly solder replacement in the electronic packaging industry.
2:45 PM - V7.2
Impact of Die Attach Material Properties on Stress Evolution in Stacked Die Packages.
Rahul Manepalli 1 , Prasanna Raghavan 1 , Yi He 1 , Amram Eitan 1
1 Assembly Technology Development, Intel Corporation, Chandler, Arizona, United States
Show Abstract3:00 PM - V7.3
Adhesion Measurement of Polymer-dielectric Interfaces using Laser Spallation.
Soma Kandula 1 , Cheryl Hartfield 2 , Nancy Sottos 3
1 Aerospace Engineering, University of Illinois at Urbana-Champaign, Urbana, Illinois, United States, 2 Semiconductor Packaging Development, Texas Instruments, Dallas, Texas, United States, 3 Theoretical and Applied Mechanics, University of Illinois at Urbana-Champaign, Urbana, Illinois, United States
Show Abstract3:15 PM - V7.4
Rational Design of Highly Filled Polymers and Reactive Resins for Target Properties in Electronic Materials with Multiple Performance Constraints.
Daniel Duffy 1 , Allison Xiao 1
1 Corporate Research, National Starch & Chemical Company, Bridgewater, New Jersey, United States
Show Abstract3:30 PM - V7.5
Orientation Fixing of Conductive NiP Hollow Microrods in Thermosetting Resins Under a Magnetic Field.
Hirokazu Oda 1 , Taichi Nagashima 2 , Shin-ichi Kawasaki 2 , Mitsuaki Yamada 2 , Tomokazu Iyoda 1 , Masaru Nakagawa 1
1 Chemical Resources Laboratory, Tokyo Institute of Technology, Yokohama Japan, 2 , Osaka Gas Co. Ltd., Osaka Japan
Show Abstract4:15 PM - V7.6
Impact of Environment and Mechanical Fatigue Effects on the Reliability of Silane-Modified Polymer/Silicon Interfaces
Bree Sharratt 1 , Reinhold Dauskardt 2
1 Aeronautics and Astronautics, Stanford University, Stanford, California, United States, 2 Materials Science and Engineering, Stanford University, Stanford, California, United States
Show AbstractA fundamental understanding of the mechanisms associated with the growth of interfacial defects at polymer/silicon interfaces is imperative for the design of microelectronic devices and, specifically, device packaging. The impact of environment and mechanical fatigue on interface reliability is of particular concern for the commonly employed model polymer/silicon interface under consideration. This materials system exhibits interesting debond growth characteristics, the most striking of which is the absence of a debond growth rate threshold. An anomalous moisture diffusion mechanism precludes the definition of a threshold debond driving energy, one below which debond growth may be assumed dormant, such as can be defined for most interfaces. This presentation reviews the debonding mechanisms and model associated with this phenomenon in several testing environments under monotonic and cyclic loading. Next, the impact of interface modification is considered. Model polymer/silicon interfaces were modified with organosilane molecules as both additives, 0.2 wt% blended into the polymer film, and as a confined layer occupying a 10 nm thickness between the silicon substrate and the unmodified polymer film. The mechanisms by which the incorporation of organosilane molecules modifies the debond growth rate response to moisture attack and mechanical fatigue are discussed from a fracture mechanics perspective. The blending of organosilanes into the polymer film results in moderation of the anomalous behavior while confinement inhibits the stress-dependent transport mechanism responsible for the anomalous debond growth rates. Implications for design of thin-film polymer/inorganic interfaces from a defect tolerance perspective are discussed.
4:30 PM - V7.7
Parylene-PDMS Bilayer Coatings for Microelectronic and MEMS Packaging.
Hyungsuk Lee 1 , Junghyun Cho 1
1 Mechanical Engineering, SUNY Binghamton, Binghamton, New York, United States
Show AbstractCurrent microelectronic devices and microelectromechanical systems (MEMS) require that packaging costs be reduced with more enhanced device performance. In addition, the packaging materials are often exposed to harsh environments, for which their performance is drastically degraded. Importantly, such devices become lighter and smaller, precluding the use of conventional packaging materials and schemes. Given that, surface coatings can provide an alternative solution for some of the aforementioned issues. Polydimethylsiloxane (PDMS) is a good candidate material in many applications provided that its surface can be effectively protected. In this study, the PDMS surface is coated with the parylene C through vapor-phase deposition. This parylene – PDMS bilayer structure can even have more protective surface with the subsequent harder, stiffer ceramic coatings grown on the former. Proper surface modification of PDMS via plasma treatments, however, seems to be essential to generate desirable interfacial adhesion between the parylene and the PDMS and to maintain transparency of the parylene layer. Mechanical performances of the bilayer coatings are systematically examined via dynamic nanoindentation testing. While performing the nanoindentation, the indentation mechanics of the film-on-substrate is applied to obtain the intrinsic “film-only” properties of the parylene. In addition, extensive surface characterizations are performed with atomic force microscope (AFM), scanning electron microscope (SEM), and optical microscope (OM).
4:45 PM - V7.8
Preparation and Magnetic and Conductive Properties of Magnetic Conductive Au/NiP Hollow Microrods.
Hirokazu Oda 1 , Tomokazu Iyoda 1 , Masaru Nakagawa 1
1 Chemical Resources Laboratory, Tokyo Institute of Technology, Yokohama Japan
Show Abstract5:00 PM - V7.9
Anisotropic Deposition of Electroplated Copper for Resistless Wiring Process
Toshio Haba 1 , Hiroshi Yoshida 1 , Haruo Akahoshi 1 , Akira Chinda 2
1 Department of Electronic Materials and Devices Research, Hitachi, Ltd. Materials Research Laboratory, Hitachi-shi, Ibaraki-ken, Japan, 2 , Hitachi Cable, Ltd., Hitachi-shi, Ibaraki-ken, Japan
Show AbstractCopper plating processes are widely applied to the fabrication of electronic devices and components, e.g. printed wiring boards. Plating processes are generally isotropic process; therefore, photolithographically patterned resist layers are required to fabricate specific structures. However, the photolithography involves many steps, including lamination, exposure and development, which not only increase the processing costs, but also increase use of less environmentally-friendly chemicals. In this work, we report on a novel "anisotropic" electroplating process which we have developed to preferentially deposit copper perpendicular to the surface, and which was successfully applied in fabricating fine copper wirings without using a patterned resist layer. A sputtered copper film that was deposited onto a substrate was used as a cathode electrode. A part of the sputtered copper film had grooves of sub-micrometer depth. Cyanine dye was used as an additive in an electroplating bath. We examined the effects of the cyanine dye concentration and plating current density on the shapes of the deposited copper. "Anisotropic" electro copper deposition was achieved by using substrates with roughened surfaces and cyanine dye in the electroplating bath. We found that copper preferentially deposited on the roughened area of the surface and grew perpendicular to the surface. Under proper conditions, the deposits resulted in quadrangular pyramid-like shapes, which possessed triangular-like cross-sections. By applying this "anisotropic" electro copper deposition, we could fabricate 10 um wide copper wiring with trapezoidal or rectangular cross-sections. We believe that the anisotropy of the plating rate comes from inhomogeneity of the additive enhanced by the roughened surface since the surface roughness and the additive concentration affect the anisotropic deposition of copper.
5:15 PM - V7.10
Surface Flatness and Interface Stability of Ni-P Film using New Electroless Plating Method with the Emulsion of Supercritical CO2
Hiroki Uchiyama 1 , Masato Sone 1 , Chiemi Ishiyama 1 , Yakichi Higo 1
1 Precision and Intelligence Laboratory, Tokyo Institute of Technology, Yokohama Japan
Show AbstractCurrently, electroless Cu, Co, Ni, Ag are used as materials for interconnects and packaging applications for ULSI as well as for MEMS. However, the recent increasing in complexity and decreasing dimensions of devices for microelectronics are placing stringent demands on film technologies that, to date, have not been fully met. These include conformal coverage of complex surfaces, and complete filling of narrow, high-aspect-ratio structures.We have developed a new technique based on the criteria mentioned above. The technique is a new electroless plating method using a supercritical carbon dioxide (sc-CO2) as a solvent. Sc-CO2 has excellent characteristics of intermolecular interaction control due to the changeability of its density and its ability to convey materials to a nano scale area because of its high density and high diffusivity. For example, Chemical Fluid Deposition and Nano-scale Casting with Supercritical Fluid, etc. are proposed as for the technology using those features. However, it has been said that sc-CO2 is not suitable as a medium for plating reactions. Metal salts are generally soluble in water, but water and CO2 are not prone to mix. This problem can be solved by the emulsification of sc-CO2 and a plating solution and then adding a nonionic surfactant.In this research, we experimented with common electroless Ni-P film which is applied to the barrier and capping layer of devices. We made, and compared thin films respectively under the same experiment conditions (substrate, pretreatment process and plating solution) by the new method and a conventional method. Pinholes and pits are formed on surface as for the thin film made by conventional method, and fine nickel particles are formed in the early stages of the reaction. These particles were agglomerated with progress of reaction time. Therefore, the roughness of the deposited nickel increased with reaction time. Moreover, voids are generated by hydrogen by the electroless plating reaction in the interface of the substrate and the plating film, and it influences the adhesion harmfully.However, the new technique has improved these defects. It became much more uniform than conventional method. By the same token, pinholes and pits on surface could be greatly reduced. Moreover, in the interface of the substrate and the plating film, the voids have decreased and the adhesion is improved. It is known that supercritical carbon dioxide mixes easily with hydrogen. This may explain the decrease in defects caused by hydrogen. It could depend on the transport properties of sc-CO2 though this technology as a solution-based technique. The film growth mechanism by a new method from these results might be different from a conventional method.As a result, the thin film made by this electroless plating technique is more excellent than conventional method. And this technique should be a promising way to meet the future requirements of the semiconductor industry and MEMS.
5:30 PM - V7.11
The Effects of the Crystallinity and the Sintering Density of Ca-based Glass-ceramic on Bonding Strength Between Ceramic and Electrode.
Minji Ko 1 , SooHyun Lyoo 1 , EunTae Park 1 , HoSung Choo 1 , Yongseok Choi 1 , BeomJoon Cho 1 , HyoungHo Kim 1
1 , Samsung electro-mechanics, Suwon City, Gyeonggi Province Korea (the Republic of)
Show Abstract5:45 PM - V7.12
Solvent-Less Flux Removal Using Atmospheric Plasma for Advanced Microelectronic Packaging Applications
Donovan Leonard 1 , Peter Yancey 2 , Michael Salmon 2
1 Materials Science and Engineering, North Carolina State University, Raleigh, North Carolina, United States, 2 , Atmospheric Plasma Solutions, Cary, North Carolina, United States
Show Abstract