The peculiar properties of carbon nanotubes (CNTs) make them good alternatives to Cu for future interconnects. However, their adoption is limited by process integration and low CNT area densities as well as unclear electrical contact issues. Integration schemes were developed for vertical interconnects (i.e. vias) with CNT densities approaching the required value of 3.10¹³cm^-2, however the resistance vs. length characteristic shows a much larger advantage over Cu for CNT lengths above 1 micron, i.e. the range relevant for horizontal interconnects. Despite this potential, integration schemes for horizontal CNT interconnects are much less advanced than those for vertical interconnects with CNTs or graphene. Here, we demonstrate the first horizontal lines using CNTs bundles of realistic high density and length. The CNT lines are integrated into test structures designed to evaluate their electrical performances in two different contact geometries.
The process uses dense bundles of vertically grown CNTs in individual vias on an Al bottom layer [1] which are subsequently flipped onto the surface of the chip by alcohol dipping, as is done for MEMS. The latter step which orientates the CNTs also allows increasing their density up to 9.10¹² cm^-2 with our typical 3nm diameter double wall CNT. A versatile process has been developed to metalize the CNTs with two contact configurations: side contact and end-bonded contact. Electrically contacted 20µm-long CNTs lines with diameter between 100nm and 50nm were realized and electrical measurements were performed for both contact configurations. Metal-CNT line contact resistances of 600 Ohms have been obtained, which leads to a specific contact resistance of 4.10^-8 Omega;.cm².i.e. only one order of magnitude higher than the best metal-metal specific contact resistance. The resistivity of the lines (1.1mOmega;cm) is only two orders of magnitudes higher than copper characteristics for tiny geometries. Analysis of the results with different contact configurations leads to the conclusion that not all the tubes are properly contacted in the bundle, probably due to the contact statistics of individual tubes. The relatively high scattering resistance of the bundles also partly comes from this effect but also from the low CNT growth temperature (< 600°C). We are confident that these points can be improved since we now have a versatile tool to investigate and optimize the impact of technology and growth steps on the ultimate performances of CNT lines.
[1] J Dijon, et al. “Ultra-high density Carbon Nanotubes on Al-Cu for advanced Vias”, IEDM (2010) p334

Carbon nanotubes have been proposed as interconnects in future integrated circuits due to their extremely high current carrying capacity. However, this use requires CNTs to be grown in densities of over ~ 3e13 cm-2. In fact, the area densities of most existing ‘high density&’ vertically aligned CNT forests is only ~6e11 cm-2 [1], and uses only 5% of the cross sectional area. Density can only be increased by increasing the density of the original catalyst nanoparticles for the CVD process. We have derive three different methods to increase the catalyst and CNT density to 3e13 cm-2, and confirmed each value by a weight gain method. The weight gain method derives the area density by measuring the weight gain during growth, and dividing this by the weight per unit length of nanotube, as deduced from the CNT diameter and wall number measured by TEM and the forest height measured by SEM or optical photography. The three processing methods that can be used to increase the catalyst density as (1) use a more diffusion resistant underlying support layer by plasma compaction to allow use of thinner catalyst layers and thus growth of smaller diameter SWNTs [2], (2) use a multi-cycle catalyst deposition process that increases the catalyst density cumulatively [3], and (3) use a short time carbon plasma to immobilise the catalyst particles before the growth step, as confirmed by us [4]. We also show how to use ultrathin Al2O3 layers on top of metallic substrates such as TiN, W or CoSi2, and still achieve conductive paths. The optimum Al2O3 nominal thickness of 0.5 - 1 nm is sufficiently thin to be either discontinuous or to allow tunnelling conduction through the oxide, while still providing a low surface energy and a diffusion barrier property to allow the Fe growth catalyst to operate properly and not sinter or diffuse away.

References
1. K Hata, et al, Science 306 1362 (2004); G Zhong, T Iwasaki, H Kawarada, Carbon 44 2009 (2006); D N Futaba, et al, Nature Mat. 5, 987 (2006)
2. S Esconjauregui, et al, ACS Nano 4 7431 (2010)
3. G Zhong, et al ACS Nano 6 2893 (2012)
4. Y Yamazaki, et al, App. Phys. Exp 3 55002 (2010); C Zhang, submitted to Carbon
5. J Robertson, et al, JJAP 51 01AH01 (2012)

In order to fabricate a single-molecule electronic circuit, we have to develop a viable method for wiring each functional molecule. We found before that a stimulation with the probe tip of a scanning tunneling microscope (STM) could initiate a chain polymerization of diacetylene compound. As a result, we could fabricate a single conjugated polydiacetylene chain at designated positions [1,2]. Based on these previous studies, here we report a novel method, chemical soldering, for connecting single polymer chains to single organic molecules [3,4]. We present a demonstration using 10,12-nonacosadiynoic acid as the diacetylene compound and phthalocyanine molecule as the functional molecule. After a small quantity of phthalocyanine is deposited on a self-assembled molecular layer of diacetylene compound, the phthalocyanine molecules form stable nanoclusters on the molecular layer. Then a pulsed bias voltage is applied between the substrate and the STM tip on the molecular row of the diacetylene compound to which the phthalocyanine molecule is adsorbed. As a result, a chain polymerization is initiated by the pulsed voltage. Since the propagating ends of chain polymerization have reactive chemical species, the end of chain spontaneously reacts with the encountered phthalocyanine molecule and forms chemical bonding. This result enables us to connect single conductive polymer chains to single functional molecules, which is an important step in advancing the development of single-molecule electronic circuitry. We will also discuss the properties of the contacts between single polydiacetylene chains and metal nanoclusters. This work was partially supported by JSPS KAKENHI Grant Number 21310078, 24241047. [1] Y. Okawa and M. Aono, Nature 409, 683 (2001). [2] Y. Okawa and M. Aono, J. Chem. Phys. 115, 2317 (2001). [3] Y. Okawa et al., J. Am. Chem. Soc. 133, 8227 (2011). [4] Y. Okawa et al., Nanoscale 4, 3013 (2012).

One of the demonstrators of the FP7 HELIOS project is a 16 channel 10G transceiver based on a separate integrated transmitter incorporating lasers and modulators on silicon and a separate receiver both for 1550nm wavelength range.

Thick modulators (400nm) have been fabricated based on carrier depletion in a PIPIN diode, demonstrating large 40 Gbit/s-extinction ratio simultaneously with low optical loss. The silicon rib waveguide width is 420 nm, the rib height is 390 nm and the etching depth is 290 nm, leading to quasi-TE and quasi-TM single mode propagations at a wavelength of 1.55 µm. Compared to a regular PIN diode, a P-doped slit with a nominal doping concentration of 3.10¹⁷ cm-3 is inserted in the intrinsic region of the lateral PIN diode and acts as a source of holes. Optical loss is then reduced because a large part of the waveguide is not intentionally doped. The optical modulator is fabricated on a 200mm SOI wafer with a 2 µm BOX and a 400 nm silicon film with microelectronic tools Different length silicon PIPIN MZM optical modulators working at 40 Gbit/s were demonstrated: one 0.95 mm long with an ER of 3.2 dB, and an optical loss of 4.5 dB, and one 4.7 mm long with an ER of 6.2 dB, and an optical loss of 6 dB.
An integrated tunable laser and MZM (ITLMZ) chip consists of a single mode hybrid III-V/silicon laser, a silicon Mach-Zehnder (MZ) modulator and an optical output coupler. The single-mode hybrid laser includes an InP waveguide providing light amplification, and a ring resonator allowing to achieve a single mode operation. Two Bragg reflectors etched on silicon waveguides form the laser cavity. The MZ modulator is based on 220nm depletion type and allows to modulate the output light emitted from the hybrid laser. The fabrication process is based on 200mm SOI wafers with 400 nm silicon on a 2µm BOX. DUV 193nm lithography and HBR etching of 180 nm silicon, allow the definition of rib waveguides for the coupling between the bonded III-V and silicon waveguides. Then different ion implantation steps are carried out in order to make p++, p , n and n++ doping for the modulators. An HDP oxide deposition on the wafers and a CMP are used to planarize the wafers. InP samples with the heterostructure are directly bonded to the planarized SOI wafer after the preparation of the surfaces. Then InP lasers are then processed, and metallization steps are performed for contacting the modulators, the heaters (NiCr) above ring resonators and the hybrid III-V/Si lasers. The heaters allow to tune thermally the resonance frequency of the ring resonator.
The laser threshold CW current is around 41 mA at 20°C and the output power coupled to the silicon waveguide is of around 1.8 mW for an injection current of 100 mA. The maximum output power is around 3 mW at 20°C, and the output power is higher than 0.5 mW at 60°C. Single mode operation with SMSR larger than 35 dB is achieved. The transmitter exhibited 10G operation with high BER.
High speed and high responsivity germanium photodetectors exhibited a zero-bias 40Gbit/s operation. A 10µm long silicon recess was etched at the end of the waveguide (220nm thick, 500nm wide) down to a thin silicon layer of about 50nm. Ge was selectively grown by RP-CVD in the Si cavity. The photodetectors were connected to a demux composed of a 2D surface grating coupler and two 16 channels AWG to define a 16 channels receiver.
This research has been funded by the European Community's Seventh Framework Program through the HELIOS project.

Increases in power efficiency per data bit is intended to be achieved by replacing electrical interconnects with their optical counterparts in the near future. This replacement is expected to proliferate next generation&’s data centers and computer systems. A combined RGBV (red, green, blue and violet) wavelength router/switch optical network can increase the connectivity of an optical system in visible range using automatically reconfigurable circuit-switching solutions and reduce the number of signal demultiplexers and wavelength division switches required by the conventional multi-stage switching node architecture. So, in the visible range, the conception of new devices based on new materials for optically switchable multilayer photonic structures is a demand.
In this paper we demonstrate an add/drop filter based on SiC technology. Tailoring of the channel bandwidth and wavelength is experimentally demonstrated. The concept is extended to implement a 1 by 4 wavelength division multiplexer with channel separation in the visible range.
Experimental optoelectronic characterization of the fabricated devices is presented and shows the feasibility of tailoring channel bandwidth and wavelength. The device consists of a p-i'(a-SiC:H)-n/p-i(a-Si:H)-n heterostructure with low conductivity doped layers. Several monochromatic pulsed lights, separately (input channels) or in a polychromatic mixture (multiplexed signal) at bit rates between 500 bps and 12000 bps illuminated the device. Independent tuning of each channel is performed by steady state violet optical bias superimposed either from the front and back sides of the add/drop filter. Results show that, front background enhance the light-to-dark sensitivity of the long and medium wavelength channels and quench strongly the others. Back violet background has the opposite behavior; it enhances channel magnitude in short wavelength range and reduces it in the long ones. This nonlinearity provides the possibility for selective removal or addition of wavelengths. It provides a low-cost solution to many aspects of optical and optoelectronic interconnection technologies and architectures according to their suitability of use in optical cross connections (OXCs), switches and routers.
Results show that the WDM demonstrated here is ideally suited for inter-chip level communications since it is implemented on a SiC platform. The large interference suppression also ensures minimal crosstalk between adjacent WDM channels. An optoeletronic model gives insight on the system physics. A numerical simulation, having as input parameters the experimental data, is presented and explains the light filtering properties of the add/drop filter, under different electrical and optical bias conditions.

Carbon nanotubes have been well studied for its electrical and thermal properties demonstrated through theoretical and experimental approaches. However it was largely put down by its large contact resistances. Nevertheless, its mechanical properties are still well sought after for its strength and damping purposes. With this knowledge, applications of carbon nanotubes should be tuned in the direction of interconnection for integration between heterogeneous assemblies. In next generation sensing architectures, compact systems that could enhance manoeuvrability and at the same time diversify sensing capability has to be carried out through pitch size reduction to incorporate more pixels per unit area. Integration of these sensors to its Si read-out circuits is important and has to be technologically compatible for proper signal digitization. In the case of using metal interconnects, further down-scaling could lead to higher failure rate and mismatch in coefficient of thermal expansion. In this study, optical interconnects between the sensors and the Si read-out circuits using vertically aligned carbon nanotubes arrays were investigated. Due to the low thermal budget of the sensing device and read-out circuits, vertically aligned carbon nanotube arrays were fabricated at low temperatures, using a modified chemical vapour deposition approach that decomposes the gases before it impinge onto the reaction surface. These high dense carbon nanotubes were grown on both the sensing and read-out circuits, and bonded together like in a flip-chip process. As a result of the close proximity of adjacent tubes, the assembly could adhere due to stiction at the microscopic scale. This ‘velcro&’ effect could be achieved due to its dense but fin-like structure. Electro-optical measurements showing its feasibility of using it as optical interconnects for high impedance devices would be evaluated.

Optical waveguides are widely used for on-chip interconnects in a variery of micro/nano-scale optical and photonic devices involving micro-resonators, communication network multiplexers, and optical buffers. To solve the bandwidth challenges, chip-to-chip interconnects using waveguides or fibers have also become necessary. While developing a scalable waveguide fabrication technique is therefore of great need, reducing the propagation loss which is typically proportional to the waveguide length is one of the most important requirements. Waveguide loss is the sum of many factors including material absorption, Rayleigh scattering, substrate leakage and sidewall roughness; among which sidewall roughness is a dominant one in the micro-fabricated waveguides. Nanoimprint Lithography (NIL) provides a solution to produce such waveguide structures from the micro-trench mold at high precision and low cost, but the sidewall roughness (e.g., scallops, jags) inevitably emerging on the original trench mold surface during the fabrication steps (e.g., RIE) is also left on the stamped waveguide structures in conventional NIL.
To address these issues, we utilize our newly developed process, NanoChannel-guided Lithography (NCL), which can continuously create seamless micro/nano-scale grating structures. In NCL, a well-cleaved waveguide mold (i.e., trenches fabricated on Si) typically heated (~80 °C) contacts to a UV-curable liquid resist-coated substrate at a tilted angle (~20°). As the mold slides under conformal two-dimensional (2D) contact with slight pressure, the liquid lines are continuously extruded through the trench openings in a mold. These delineated liquid lines are then instantly solidified by UV illumination before reflowing, to complete the fabrication of gratings that function as rib waveguide array. Currently we use epoxy-silsesquixane (SSQ, index ~1.5) as a waveguide material that is formed on a perfluoroalkoxy (PFA, index ~1.34) substrate that function as undercladding for SSQ waveguide.
Since a tilted cleaved mold make a 2D contact to a substrate, NCL can produce seamless and scalable waveguide structures that have ideally smooth sidewall regardless of the roughness existing on the original trench mold. This can significantly reduce the propagation loss of the fabricated all-polymer SSQ-PFA waveguide system. More detailed results along with simulation analysis will be presented at the conference.

In addition to size miniaturization, flexible electronics is another important trend for the development of next generation microelectronic devices. It is envisioned that all-polymer transistors fabricated by ink-jet printing (IJP) can revolutionize flexible electronic devices, such as organic light emitting diode (OLED) displays and electronic papers. With respect to the metallic interconnects/electrodes on flexible substrates, several issues still need to be addressed. For example, a low processing temperature below 150 °C becomes a necessity for achieving advanced circuits on flexible substrates. The IJPed conductors need to possess similar electrical conductivities as bulk materials. This presentation introduces the approaches to achieve those requirements by tailoring the metallic ink precursors. Polymer/silver nitrate composite inks were adopted and modified to obtain printed silver conductive lines with suitable continuity and low electrical resistivity. The additions of energetic reagents in the solvent provide extra joule heats at the confined area, which dramatically accelerate the thermally-induced reaction and significantly reduce the processing temperature. One more breakthrough is a chemical reduction process was developed to convert the IJPed metallic nanoparticles on PET to conductive films at room temperature. The conductors thus produced exhibited excellent conductivity even under bending deformation.
T.H. Kao,et. al. Applied Physics Letters, 95, 2009, 131905,
T.J. Wu, et. al. J. Phys. Chem. C., 114, 2010, 4659,
T.H. Kao, et. al. Acta Materialia, 59, 2011, 1184,
C.N. Chen, et. al. Acta Materialia, 60, 2012, 5914;

Supported by the National Science Council of Taiwan. NSC 101-2120-M-006 -003

Carbon nanotubes (CNTs) and graphene are both promising nanoscale forms of carbon for electronics applications. While their electrical properties differ—CNTs are 1D and can have a sizable energy band gap while graphene is 2D and has a zero band gap—the interface between metal contacts and the sp2-bonded carbon surface of CNTs or graphene has similarities. Both materials have proven to be sensitive to the scaling of source/drain contact lengths in field-effect transistors, with a transfer length of approximately 100 nm for graphene (IEEE Electron Device Lett., 32:1035, 2011) and 50 nm for CNTs (Nature Nanotechnol., 5:858, 2010). Without a band gap, graphene is not applicable to digital transistors, and thus would not likely be used in applications where extreme scaling is needed; however, information regarding the contact scaling behavior does provide valuable insights into transport mechanisms at the metal-graphene contact. In contrast to graphene, nanotubes continue to show promise for enabling a ‘next switch&’ replacement for silicon digital technology. While recent work has shown that CNT transistors provide excellent performance at sub-10 nm channel lengths (Nano Lett., 12:758, 2012), the true performance limiter is the contacts, which must also be scaled. I will review the limitations posed by nanoscale contacts to CNTs and present some recent advances that have been made to improve the scaling behavior. Ultimately, nanotube devices will be limited by the contacts—the question is: by how much can we reasonably expect to overcome this limitation? I will attempt to provide enough theoretical and experimental background information to begin answering this question.

The performance of graphene electronic devices is often limited by poor metal-graphene contacts. From ab initio quantum mechanical studies, end-contacted metal-graphene contacts have been shown to provide much lower contact resistance compared to that of side-contacted contacts by up to a few orders of magnitude (Matsuda,2010). In addition, an experimental study demonstrated that the current crowding takes place at the edge of the contact metal with graphene (Nagashio,2010). However, the end-contacted configuration is limited by the amount of exposed graphene edges in contact with the metal. Conventional metallization schemes place the metal electrode on top of the graphene channel resulting in a side-contacted configuration, except for a small amount of edge coverage. In this work we incorporated a metal-mediated etching technique (Wang,2012) into the fabrication graphene device fabrication process. This etching technique creates a number of etched edges on graphene surface to allow the extensive formation of end-contacted metal-graphene contacts.
Exfoliated graphene was first patterned into desired geometry followed by deposition of a thin metal film at the source/drain graphene regions. The prepared sample was then annealed in a hydrogen ambience. This causes the metal film to ball up due to surface tension and etches the graphene surface progressively. The etching is found to initiate from the graphene edges and extend along the natural crystallographic orientation of graphene. Most of the etch pits observed are triangular or germinal hexagonal in shape. The sample preparation was followed by forming electrical contacts onto graphene via conventional means such as electron-beam lithography and thermal evaporation.
For comparison purposes, a few-layer graphene was patterned into two equivalent strips. Two small cobalt pads (3nm thick) were deposited at the end of one of the graphene strip. We then annealed the sample in hydrogen and patterned electrical leads to these contacts. Electrical measurements were carried out under ambient conditions. It was found that the two-point resistance of the graphene device with cobalt-etched-graphene contacts is 5 times lower than that of the untreated graphene device.
Since nickel-graphene contact appears to provide the lowest contact resistance (Nagashio,2010), we also fabricated a 4-point single layer graphene(SLG) device with nickel-etched-graphene contacts. The contact resistance measured under ambient conditions is 250Omega;µm2, which to the best of our knowledge, is the lowest reported value for exfoliated SLG devices, with all previous reported ambient values above 700Omega;µm2 (Nagashio,2011;Xia,2011). Using this metal-assisted etching approach, the lowest contact resistance we obtained so far is ~70Omega;µm2 from a bilayer graphene device.
In summary, the findings suggest that the metal-mediated etching technique could be a promising method to obtain low-contact-resistance metal contacts to graphene.

Producing low-resistance contacts to carbon nanotubes in a reproducible manner is a crucial challenge towards the development of efficient nanotube-based electronics. A full understanding of the mechanisms responsible of charge injection through the contacts is necessary to steadily minimize their resistance. While the physics of junctions is very well-understood in the case of bulk materials, the geometry of low-dimensional structures such as nanotubes makes it a very different case, in which it is already known that the transmission of charges differs than the one for planar junctions [1]. Here we present our recent results revealing a better identification of the mechanisms implied in carrier injection at carbon nanotube/metal contacts. We performed a thorough study of the electrical characteristics of individual single-walled nanotubes, arranged in field-effect transistors with Ti/Pd metallic top contacts. Measurements acquired over a wide range of temperature (77-400K) and for various gate and drain-source bias were used to investigate the transmission of carriers through the Schottky barrier formed at the interface between the metal and the nanotube band gap. Careful analysis of the temperature dependence of the electrical characteristics revealed an injection behavior following an Arrhenius activation mechanism, instead of the expected Richardson relation for thermionic emission generalized to 1D semiconductors [2]. We discuss the interpretation underlying this mechanism, such as the contribution of intermediate localized states at the interface. The effective charge injection barrier was also extracted from the data. The height of this barrier was observed to decrease exponentially as a function of drain-source bias, which is consistent with an increasing tunneling component due to barrier thinning. Finally, barrier heights were measured for several individual quasi-metallic and semiconducting nanotubes, with values respectively close to the band gap of both species.
[1] F. Léonard & A. A. Talin. Nature nanotechnology, 6, 773 (2011), and others.
[2] M. F. O&’Dwyer, R. A. Lewis & C. Zhang. Microelectronics Journal 39, 597 (2008)

The quality of electrical contacts to carbon nanotubes is known to be determined by the work function of the contact material, as well as by the wetting interaction of the material on the carbon nanotube. Conventionally, contacts are fabricated using patterning by photo or electron beam lithography and metallization by physical deposition techniques such as evaporation or sputtering. In this work, contacts were patterned using the resist-free direct-write technique of electron beam induced deposition (EBID), and the material was deposited by atomic layer deposition (ALD).
This approach has two advantages over conventional patterning techniques: Firstly, contacts deposited by ALD are anticipated to have a better wetting interaction with the CNT surface due to the chemical nature of the technique. ALD relies on alternating and self-limiting chemical surface reactions, involving the adsorption of an organometalic precursor, and subsequent elimination of the precursor ligands. Secondly, EBID allows for direct patterning without the need for additional lithography steps, and thereby eliminates compatibility issues between CNTs and resist films or lift-off steps. In general, resist films cannot be removed completely from the surface of a CNT without damaging it. Moreover, when no lift-off steps are required, it is not necessary to have a Ti adhesion layer between the CNT and the contact material to facilitate the lift-off.
The approach consists of the patterning of a thin seed layer of less than 0.5 nm Pt-containing material by EBID, followed by area-selective ALD growth. It has been established that this combined approach gives high-quality material (virtually 100% pure Pt, resistivity of 12 µOmega;cm), while it allows for patterning of Pt line deposits of only 10 nm in width.[1] Recent work indicates that similar nanostructures can be fabricated of Pd, which potentially gives a better wetting interaction as compared to Pt. In this contribution, the main characteristics of the direct-write ALD technique will be discussed, and it will be demonstrated that the technique is able to pattern electrical contacts on single-walled and multi-walled carbon nanotubes. The quality of contacts on single-walled carbon nanotubes was evaluated by fabricating carbon nanotube field effect transistors. Moreover, the wetting interaction between the material and the CNT was investigated by transmission electron microscopy.
[1] A.J.M. Mackus, S.A.F. Dielissen, J.J.L. Mulders, W.M.M. Kessels, Nanoscale 4, 4477 (2012).

Vertically aligned carbon nanotubes (CNTs) grown by plasma-enhanced chemical vapor deposition (PECVD) offer a potentially suitable material for via interconnects in next-generation integrated circuits. Key performance-limiting factors include high contact resistance and low CNT packing density, which fall short of meeting the via resistance requirement delineated by the ITRS roadmap for interconnects [1]. Previously, we reported an individual CNT resistance of about 1 kOmega; in a vertically aligned CNT array with an average diameter of ~100 nm and a length of 1.5 µm. Of such resistance, about 800 Omega; is attributed to the contact between the CNT and metal electrodes [2]. High-resolution transmission electron microscopy (HRTEM) images revealed a clean interface between CNT and the underlayer metal, albeit with significant surface asperity and large metal grains. Further, energy-dispersive x-ray spectroscopy (EDS) showed large amounts of oxygen and nitrogen present in the interfacial region, which could negatively impact the contact resistance.
Currently, we have succeeded in reducing the average diameter of the PECVD-grown CNTs to about 15 nm while increasing the packing densities to >1011 cm-2. This result is comparable to recent work reported for CNT vias [3]. We have also made changes in the PECVD process flow to improve the as-grown CNT-metal contact with the primary objective of reducing the contact resistance contribution to the total CNT via resistance. The CNT-metal interface is studied extensively using HRTEM and EDS to gain a better understanding of the physical origin of the contact resistance, and to provide the needed feedback for process improvement. Such understanding is critical to the eventual functionalization of CNT via interconnects.
[1] 2011 International Technology Roadmap for Semiconductors, http://www.itrs.net/Links/2011ITRS/Home2011.htm
[2] P. Wilhite, A. Vyas, J. Tan, P. Wang, J. Park, M. Jackson, and C .Y .Yang, “Nanostructure Characterization of Carbon Nanotube/Metal Interfaces”, MRS Spring Meeting, 2012.
[3] M. Nihei, “CNT/Graphene Technologies for Advanced Interconnects”, IITC Short Course, 2012.

Metal-semiconductor junctions with optimum performance and stability are essential for most semiconductor devices and for this reason continue to be extensively investigated in the electronics industry. Recently, metal-semiconductor diodes have been demonstrated to also be useful for solar to hydrogen conversion using photoelectrochemical water splitting: the Schottky barrier provides the electric field necessary for photocarrier separation, and the metal catalyzes water oxidation and/or reduction reactions. In my talk I will describe how the performance of metal-semiconductor devices can be substantially improved by separating the metal and the semiconductor with a nanometer-thick thermal oxide, which protects the semiconductor from electrolyte induced corrosion, reduces carrier recombination, and allows the Schottky barrier to be optimized by tuning the metal work function. Schottky barriers also form at electrolyte-semiconductor junctions, and certain semiconductors such as hematite can be used directly to split water. In my talk I will discuss the challenges of establishing the role and concentration of dopants in electrolyte-semiconductor junctions. Finally, I will discuss Li-ion batteries where semiconducting cathode-electrolyte junction resistance can substantially degrade performance and how ideas developed for making high performance Ohmic contacts for semiconductor devices can be used to improve battery performance.

Assuming graphene remains structurally intact upon the electron-beam deposition of metal electrodes, this type of metal-graphene contact geometry is termed as “side-contact”. The commonly studied metals can be classified into two categories for side-contact with graphene: weakly and strongly bound. In the weakly bound case, metals such as Al and Cu interact with graphene weakly, and there is a relatively large interface distance (>3Å) with charge transfer between metal and graphene. In the strongly bound case, metals such as Ti and Pd interact more strongly with graphene through a substantial interface orbital hybridization with a relatively small interface distance (<2.5Å). Despite a large amount of research efforts on investigating electronic structures and transport properties of such metal-graphene contacts,1-4 describing this interface only within the “side-contact” configuration is not necessarily realistic .
Investigating the atomic structure and electronic transport properties for a realistic metal-graphene contact is a key issue that is not fully studied yet. Electron-beam deposition of wetting metal electrodes such as Ti and Pd on graphene may react with, and strongly perturb, graphene. In-situ x-ray photoelectron spectroscopy studies of Ti and Pd deposited on as-grown graphene on copper foil are therefore performed to unravel the realistic metal-graphene contact configuration. The predominant titanium carbide signature and the significant presence of Pd-C bond reveal an unambiguous perturbation of the underlying sp2-bonded network of graphene. The experimental data suggest the relevance of the concept of an “end-contact” formed when metals react with the underlying contacted graphene and thus result in metal-carbon bonding to the edge of the graphene channel. First principles methods are employed to investigate the electronic transport across the hybridized metal/graphene/metal (Pd and Ti) end-contact structures. An unusual double-dip transmission as a function of Fermi level is found for Pd end-contact. For the Ti end-contact, a contact-induced transport gap (~0.2 eV) is opened, as the two conductance dips are merged into one. Interface metal-carbon hybridization is shown to introduce a random distribution of π-orbital local density of states at different carbon sites throughout the graphene channel, leading to conductance suppression. The strong electron-hole conduction asymmetry suggests an n-type doping of graphene near the titanium contact. A local density of states profile model is developed for the quantitative analysis of the unique transport behavior through metal-graphene end-contacts.
[1] J. Appl. Phys. 2010, 108, 123711;ACS Nano 2012, 6, 5381.
[2] Phys. Rev. B 2010, 82, 115437; Phys. Rev. Lett. 2008, 101, 026803.
[3] Phys. Rev. Lett. 2010, 104, 076807; Nano Lett. 2012, 12, 3424.
[4] Appl. Phys. Lett. 2010, 97, 142105; Nano Lett. 2011, 11, 151.

Realistic carbon-nanotube metal contact geometries are generated using a combination of classical and quantum molecular dynamics. The substrate, metal cohesive properties and carbon-metal wetting are shown to influence the geometry of the contact. Realistic contact geometries are used to compute electronic structures and study the electrical transport across the interfaces. Factors influencing contact resistance are identified. The carbon-metal distance and metal work function play key roles in establishing Schottky or Ohmic contacts.

One of the biggest obstacles to realizing carbon-based electronics lies in the difficulty of establishing reliable low-resistance contacts between carbon nanomaterials and metal electrodes. Applying a first-principles computational approach to a series of junction models based on pristine or hydrogenated open-ended carbon nanotubes (CNTs) and capped CNTs, we critically examine the correlation between metal-CNT chemical bonding and contact resistance. We first show that, because the decay rate of Schottky barriers (SBs) sensitively depends on the atomistic details of metal-CNT contacts, the true charge injection capacity of different junction models can be determined only by looking into the long-length limit and considering only short junction models can lead to incorrect conclusions [1]. Whereas the comparison of conventional contact models supports the more prevalent viewpoint that regards the strong metal-CNT chemical bonds as a precondition of low-resistance contacts, we next demonstrate that the presence of structural defects that preserve the sp² carbon network endows the contact models based on CNT caps a superior charge injection capacity [2]. Finally, we show that different arrangements of pentagon topological defects induce significant variation in the conductance magnitude and even device type. We thus (1) demonstrate the critical role of atomistic details in metal-CNT contacts and localized CNT edge states for the SB shape and metal-induced gap states, (2) resolve the controversy on the nature of optimal metal-CNT chemical bonding for device applications, and (3) predict that controlled placement of topological defects will be a promising route to achieve high-performance defect-engineered CNT devices.
[1] Y.-H. Kim and H. S. Kim, “Anomalous length scaling of carbon nanotube-metal contact resistance: An ab initio study”, Appl. Phys. Lett. 100 , 213113 (2012).
[2] H. S. Kim, G. I. Lee, H. S. Kim, J. K. Kang, and Y.-H. Kim, “Intrinsically low-resistance carbon nanotube-metal contacts mediated by topological defects”, MRS Commun. 2 , 91 (2012).

The good electrical conductivity, high optical transparency, and mechanical flexibility of graphene make it a promising candidate for transparent, conductive, and flexible electrodes in optoelectronic and photovoltaic devices [1]. Unlike conventional metal electrodes, graphene has the added advantage that its Fermi level and hence its workfunction can be tailored by chemical doping or electrostatic gating. As a result, graphene can be used in traditional as well as novel design structures [2]. For that purpose, integration of graphene into conventional semiconductor technologies, in particular those based on silicon, is of utmost importance.
In this talk, we describe metal-semiconductor-metal (MSM) photodetectors where chemical vapor deposition (CVD)-grown monolayer graphene plays the role of the metal and the semiconductor is p-type silicon (p-Si). Graphene synthesized by CVD enables large-scale and high yield production of such devices [3]. In order to understand the operation of the MSM photodetectors, we first investigate the electronic properties of graphene/p-Si Schottky junctions in a metal-semiconductor (MS) configuration as a function of temperature. We find that thermionic emission is the dominant electronic transport mechanism above 260 K with a zero-bias barrier height of 0.48 eV, whereas at lower temperatures tunneling begins to dominate. Using temperature-dependent I-V measurements, we investigate the reverse-bias dependence of the Schottky barrier height and conclude that the Fermi level change in graphene due to charge transfer from Si dominates this dependence. Furthermore, comparison of the experimental and theoretical reverse saturation currents suggests the presence of an interfacial native oxide layer. This interfacial layer helps to improve the performance of MSM photodetectors by suppressing the dark current.
Finally, we characterize the photoresponse of interdigitated finger MSM photodetectors based on graphene/p-Si Schottky junctions. We extract important parameters, including responsivity and normalized photocurrent-to-dark current ratio, which are found to be higher than those previously obtained for similar detectors based on carbon nanotubes. Our results provide crucial insights into the fundamental electronic and optoelectronic properties of MSM photodetectors based on graphene/p-Si junctions, which are important for the integration of graphene-based materials into existing semiconductor technologies.
[1] C.-C. Chen, et al., Nano Lett. 11, 1863 (2011); S. Tongay, et al., Phys. Rev. X 2, 011002 (2012).
[2] L. Britnell, et al., Science 335, 947 (2012); H. Yan, et al., Science 336, 1140 (2012).
[3] S. Bae, et al., Nat. Nanotechnol. 5, 574 (2010).

As feature sizes shrink and porous low-k dielectrics get broadly adopted to reduce the RC delay in future technology nodes, new metallization processes are required. Traditional PVD barrier/seed metallization is facing a significant challenge in ensuring an acceptable sidewall copper seed coverage as features scale and possibly also cause significant dielectric damage during barrier deposition. Poor copper seed coverage results in voids during subsequent ECP metallization leading to increased resistance and poor reliability. Conformal deposition processes such as ALD and CVD are being actively investigated as replacements for PVD to deposit thin barrier and seed films to enable void free bottom up fill with ECP. In addition, pore sealing prior to barrier seed metallization becomes critical as well for the porous dielectrics to prevent metal from migrating into the porous dielectric during metallization leading to poor reliability.
Here, we discuss an alternate metallization scheme, using a wet conformal deposition process; electroless copper, directly on the dielectric enabled by a post-etch treatment. Etch processes are routinely tailored to enable PVD barrier/seed and ECP copper metallization, resulting in specifications that relate to etch profile control, low-k damage, etch residues and more. In this case, we look to the post-etch treatment to seal the pores and functionalize the dielectric surface to enable wet deposition. We explore the benefits of electroless copper processing to BEOL metallization scaling and review recent results from deposition on porous low-k as well as early results on Copper gap-fill.

The reduction in size and distance between microcomponents makes electronic devices more susceptible to corrosion problem. This work aims to improve the current understanding of the creep corrosion problem in Cu deposit. It contributes to the understanding of nanowhisker growth mechanism which is considered as the representative of the creep corrosion and main cause of the failure in the electronic systems. Thermal stress which is continually exerted on electronics was identified as the main driving force for the nanowhisker growth. In order to optimize material characteristics of the deposit, the work provides a novel insight into the interconnections between deposit crystalline structure and its thermal resistance.
An experimental demonstration of the effects of the electrochemical parameters on the crystallographic structure and surface topography of the Cu microparts has been presented. This demonstration is inspired by the grand influence of morphology and topography on the deposit corrosion resistance. To resolve crystalline structure of the deposit a combination of quantitative characterization techniques and image analysis methods was used. Moreover, scanning electron microscopy and light interferometry were utilized to obtain deposit surface topography. Based on the thermodynamic analysis of the microelectrodeposition process, a model was suggested to explain effects of the electrochemical parameters on the roughness and crystalline grain size of the deposit. The model can be used as a design strategy to predictably deposit microparts with controlled surface and crystallographic structures.

Sun et al. [1] reported a quantitative analysis of both surface and grain boundary scattering in Cu thin films with independent variation of film thickness (28 nm to 158 nm) and grain size (35 nm to 425 nm) in SiO₂ and Ta/SiO₂ encapsulated samples prepared by sub-ambient temperature film deposition followed by annealing. Film resistivities of carefully characterized samples were measured at both room temperature and at 4.2 K and were compared with physical models that included the effects of surface and grain boundary scattering. Grain boundary scattering was found to provide the strongest contribution to the resistivity increase. However, a weaker, but significant, role was observed for surface scattering. It was found that the resistivity data were best fit when the Mayadas-Shatzkes model of grain boundary scattering and the Fuchs-Sondheimer model of surface scattering resistivity contributions were combined using Matthiessen&’s rule (simple summation). Using Matthiessen&’s rule, the data are well described by a specularity coefficient p = 0.52 and a grain boundary reflection coefficient R = 0.43. The work of Sun et al. did not account for twin boundary scattering in the quantitative analysis of the resistivity size effect, both due to limitations in characterizing twin boundaries in nanocrystalline Cu and to the expectation that the contribution of these boundaries to the observed resistivity increase would be negligible. In the current study, a newly developed system that employs precession electron diffraction in the transmission electron microscope and a template matching algorithm to determine crystal orientation was used to map two SiO₂ and six SiO₂/Ta₃₈Si₁₄N₄₈ encapsulated nanocrystalline Cu films. The mapping of crystal orientations allowed us to determine the fraction of twin boundaries in the Cu films that were coherent, and to then perform quantitative analysis of the resistivity size effect to determine the relative contribution of surface and grain boundary scattering, including twin boundaries, to the observed resistivity increase. Although independent variation of the twin boundary fraction was not observed in these samples, inclusion of the twin boundaries in quantitative modeling shows the resistivity data to be best described by the Fuchs-Sondheimer surface scattering model and the Mayadas-Shatzkes grain boundary scattering model, combined using Matthiessen's rule, with a surface specularity coefficient p = 0.55 and a grain boundary reflection coefficient R = 0.26.
1. T. Sun, B. Yao, A. P. Warren, K. Barmak, M. F. Toney, R. E. Peale, K. R. Coffey, Phys. Rev. B 81 (2010).
Financial support of the SRC, Task 1292.008 and 2121.001, and of the MRSEC program of the NSF under DMR-0520425 is gratefully acknowledged. E. Rauch is thanked for helpful discussions.

Gallium arsenide is known as a semiconductor with a high electron mobility, which is suitable for high frequency devices with low power consumption. In order to take advantage of the superior mobility, the development of a low ohmic contact material is essential. Among various ohmic contact materials to n-GaAs, Cu/Ge bilayered films showed a very low contact resistance and a good thermal reliability. In this research, we focused on Cu-Si alloys since Si is a popular dopant in GaAs, but also has a higher diffusion coefficient in GaAs than Ge. The electrical properties and microstructure of Cu-Si alloy electrode were investigated to understand the effects of Si concentration on ohmic contact property.
Alloy films of Cu1-xSix (x=0.05, 0.1, 0.15, and 0.2) with 100nm in thickness were deposited by a multi-target co-sputtering system on n-type GaAs(100) wafers doped with Si to a concentration of 1×1018cm-3. We prepared three types of samples : Cu/Si/GaAs, Si/Cu/GaAs, and co-sputtered Cu-Si alloy on GaAs. The samples were annealed at 300, 400, and 500oC for 30 min in an Ar atmosphere. For the measurement of I-V characteristics and contact resistance, electrode patterns with 20 mu;m intervals were formed on the n-GaAs substrate by photolithography and liftoff processes. The resistance between two electrodes was measured by a Kelvin method in order to minimize the effect of series resistance between the probe and the electrode. Phase identification of the Cu-Si alloy and a reaction layer was carried out by X-ray diffraction (XRD). The microstructure of the reaction layer was observed by transmission electron microscopy (TEM) equipped with energy dispersive X-ray spectroscopy (EDX) for composition analysis. High resolution TEM (HRTEM) images and selected area diffraction (SAD) patterns were observed for further analysis of the microstructure of the reaction layer. Additional composition analysis was performed by secondary ion mass spectrometry (SIMS).
In the Cu/Si/GaAs samples, all sample showed schottky I-V characteristics. No diffusion into GaAs was observed for all Si concentration after annealing at 400 oC. Instead, a thin and flat layer including Si was formed between Cu-Si films and GaAs. On the contrary, all films of Si/Cu/GaAs and co-sputtered Cu-Si alloy formed good ohmic contact with n-GaAs(100) substrates after annealing at 400 oC. A thick reaction layer was observed regardless of the Si concentration in the Si/Cu/GaAs samples. In the case of the co-sputtered Cu-Si alloy films, the reaction layers became thinner as the Si concentration was increased. The interface reaction layer was a hexagonal Cu3As phase, which grew with an orientation relation of Cu3As{0001}//GaAs{111}. It is considered that the formation of Cu3As phase promotes Si diffusion into GaAs, and that the formation of highly Si doped n+layer at the interface is attributed to obtain the ohmic contact formation.

Recently, metallic nanoparticles (NPs) have attracted much interest in a range of applications such as the fabrication of advanced microelectronic, magnetic or optical devices.[1] For instance, they can be used to build continuous and highly conformal metallic coatings.[2] For the metallization of through silicon vias in the 3D integration of interconnects, thin metallic liners are of interest as seed or barrier layers. Recently, alloyed copper films have been investigated as so-called self-formed barriers.[3] In this view, it could be interesting to form bimetallic copper and manganese NPs.
However, the controlled synthesis of metallic NPs in the range of 1 to 10 nm is still an on-going challenge, as is the understanding of their stabilization and agglomeration.[4] In particular, substantial effort has been centered on stabilizing transition-metal nanoparticles, using polymers, ligands and organic or inorganic templates. Unlike traditional solvents, ionic liquids (ILs) can be used to generate metallic NPs and stabilize them in the absence of further additives.[5] Ionic liquids are molten salts, generally liquid at room temperature, composed of an organic cation and an inorganic or organic anion. They are thermally and electrochemically stable, non-volatile and electrically conductive.
Due to these unique properties, ILs are ideal media for the elaboration of metallic NPs. Indeed, our group has recently demonstrated that they can dissolve organometallic (OM) precursors, which precipitate into metallic NPs by decomposition under dihydrogen.[6] Interestingly enough, this novel process provides suspensions of a variety of metallic NPs, with accurate size control and high stability. Even more interestingly, upon mixing two different OM precursors, bimetallic NPs can be obtained. Depending on the decomposition kinetics of the OM precursors, specific structures (such as core-shell) can even be obtained.
Finally, the thermal stability of ILs enables in-situ sintering of NPs by thermal treatment of the suspension. When applied onto a substrate, such a suspension could be converted into a metallic film. Preliminary results of the formation of Cu, Mn and MnCu coatings will be described.
[1] H. Goesmann and C. Feldmann, Angewandte Chemie International Edition 49, 1362-1395 (2010).
[2] C. Barriere, G. Alcaraz, O. Margeat, P. Fau, J.B. Quoirin, C. Anceau, B. Chaudret, J. Mat. Chem. 18, 3084-3086 (2008)
[3] Usui, T. et al., IEEE TRANSACTIONS ON ELECTRON DEVICES 53, 2492-2499 (2006).
[4] H. Bönnemann, K.S. Nagabhushana, R.M. Richards, Colloidal Nanoparticles Stabilized by Surfactants or Organo-Aluminium Derivatives: Perparation and Use as Catalyst Precursors, in: D. Astruc (Ed.) Nanoparticles and Catalysis, Wiley-VCH, Weinheim, 49-92 (2008)
[5] J. Dupont, J.D. Scholten, Chem. Soc. Rev. 39, 1780-1804 (2010)
[6] T. Gutel, C.C. Santini, K. Philippot, A. Padua, K. Pelzer, B. Chaudret, Y. Chauvin, J.-M. Basset, J. Mater. Chem. 19 3624-3631 (2009)

I describe extreme bottom-up copper filling of high aspect ratio annular through silicon vias (TSV) over 50 micrometers tall wherein deposition occurs on the bottom surface of the vias with negligible deposition on their sidewalls or the field around them. The process uses a single deposition suppressing additive. The growth dynamic cannot be accounted for using existing shape change models based on either suppressor consumption induced gradients or area change coupled with adsorbate coverage (the latter known as the Curvature Enhanced Accelerator Coverage mechanism of damascene superfill). Rather, I detail a quantitative model of feature filling in chemical systems exhibiting unstable deposition characterized by S-shaped negative differential resistance (S-NDR) where deposition is limited by the resistivity of the electrolyte. For appropriate conditions, the model predicts rapid, progressive suppression of deposition down filling features followed by stabilization of on-going metal deposition at the bottoms of the features. Through modeling I explore the sensitivity of the feature filling to parameters covering geometry, kinetics, and experimental conditions, capturing the experimental filling evolution both geometrically and temporally.
Specifically, model predictions agree with experiment for concentrations and dimensions for experimental extreme bottom-up filling of Cu TSV and transport and kinetics drawn from the literature.1,2 The model also explains how the history-dependent nature of the S-NDR system provides for sustained deposition on the bottom surface while the initially suppressed regions of the sidewalls remain fully suppressed throughout filling.
I also detail the processing window for suppressor concentrations and applied potential, showing agreement with experimental results exhibiting experimental conditions that generated bottom-up filling, the agreement speaking to the utility of the model. Modeling predicts a range of observed deposition profiles, spanning from extreme filling, with the growth fully localized to the bottom surface, to a more relaxed version of superfilling where significant sidewall deposition attenuates with height in the feature. The former regime is consistent with results for Cu TSV filling. Due to the simplicity of the mechanism, the possibility for broad application to materials and systems beyond TSV is considerable.
1. T.P. Moffat and D. Josell, J. Electrochem. Soc., 159(4), D208 (2012)
2. D. Josell, D. Wheeler and T.P. Moffat, J. Electrochem. Soc., 159(10), D570 (2012).

The rapid downward scaling in silicon integrated circuit technology has accelerated the demand for studies of alternatives to copper as the preeminent interconnect material. Decreased Cu linewidths increase current density that approaches or exceeds its current capacity, causing reliability problems for both horizontal lines and vertical vias [1]. Further, as Cu resistivity rises rapidly with decreasing linewidth in the sub-50 nm regime due to surface scattering, downward scaling increases the line and via resistances, thus degrading the chip performance [1]. It is well known that nanocarbons are materials with potential to replace Cu because of their high current capacity and resistivity approaching that of nanoscale Cu [1]. For vias, in particular, carbon nanotube (CNT) appears to be an ideal candidate. The major challenges in incorporating CNTs as on-chip via interconnects lie in achieving high-density growth (>1012/cm2) and minimizing the contact resistance at the CNT-metal interface to yield an acceptable via resistance [1,2].
In this study we compare the electrical performance of CNT and Cu vias fabricated on a Pt underlayer. To examine the electrical characteristics over a wide range of frequencies and via dimensions, we fabricate a one-port ground-signal-ground test structure with via diameters ranging from 30 nm to 1 µm. A 200 nm Pt underlayer acts as the ground plane to provide a low-resistance path from signal to ground. For Cu vias, a 2 nm barrier layer of TaN is deposited on the via base and sidewalls to prevent Cu diffusion during subsequent electroplating. For CNT vias, a Ni film is electroplated onto the Pt underlayer prior to CNT growth by plasma-enhanced chemical vapor deposition (PECVD), with acetylene as the carbon source and ammonia as a reducing agent [3]. The current capacities and resistances of CNT and Cu vias are measured at dc and their impedances extracted from S-parameter measurements at frequencies up to 50 GHz. The electrical characteristics are correlated with the CNT-Pt interface nanostructures obtained using transmission electron microscopy and energy-dispersive X-ray spectroscopy.
[1] 2011 International Technology Roadmap for Semiconductors, http://www.itrs.net/.
[2] N. Chiodarelli, M.H. van der Veen, B. Vereecke, D.J. Cott, G. Groeseneken, P.M. Vereecken, C. Huyghebaert, and Z. Tokei, "Carbon nanotube interconnects: Electrical characterization of 150 nm CNT contacts with Cu damascene top contact," International Interconnect Technology Conference, pp.1-3 (2011).
[3] H-S. Yoo, S-J. Lee, S-K. Joo, and W-Y. Sung,” Density control of carbon nanofibers on titanium buffer layer using electroplated Ni catalyst,” Journal of Vacuum Science and Technology B, vol. 26, pp. 880 (2008).

GaN has been considered an indispensable material in the realm of high power or optoelectronic applications, thanks to the wide bandgap and the high mobility. [1-2] Its limitation, however, rests in the fact that SiC and sapphire currently are the only compatible substrates in respect to structural defect density and heat transfer. This adds to the cost of fabricating GaN devices, thus confining the use to small-area components. [3] The future lies in the more economical Si process, where there are significant challenges in controlling defect density, lattice mismatches and lattice constants. [4]
In this research, we are proposing a novel method for affixing low-defect, GaN-deposited Si (111) wafer onto Si (100) substrate by wafer bonding. This configuration lends itself well not only to MOSFET and AlGaN/GaN high electron mobility transistor (HEMT) at the moment, but also to heterogeneous integrated circuits combining the two without performance loss in the future. Moreover, bonding strength could be further enhanced with our approach by introducing an intermediate layer, which doubles as a passivation layer for better electrical properties.
During GaN wafer bonding with Si (100) process, wafer bow and surface roughness is hindered whole wafer bonding. For spontaneous and strong bonding process, surface roughness is required less than 1nm, but typical GaN wafers are roughness is over 2nm (5µm×5µm). Also, GaN wafer bow is range of few microns to up to ten of microns which significantly hampered bonding process. To solve these problems, we tried CMP process reduced surface roughness less than 1nm and heat treatment with intermediate layer to diminish wafer bow up to 50% which improve larger area and bonding strength GaN wafer bonding with Si (100) process.
Reference
[1] U. K. Mishra, L. Shen, T. E. Kazior, and Y.-F. Wu, Proc. IEEE, vol. 96, no. 2, pp. 287-305 Feb. 2008.
[2] S. Nakamura, G. Fasol, and S. J. Pearton, Germany: Springer-Verlag, 2000.
[3] Annu Rev Mater. Res 2010. 40:469-500.
[4]A. Dadgar, F. Schulze, M. Wienecke, A. Gadanecz, J. Blasing, P. Veit,T. Hempel, A. Diez, J. Christen, and A. Krost, New J. Phys., vol. 9, no. 10, p. 389, Oct. 2007.

Inkjet printing technology is experiencing an increasingly central role in large consumer electronics manufacturing as selective transfer process. In recent years its use has been broadening also to prototyping of circuits in microwave range like impedance matching [1], antennas [2] and RF sensors [2]. Current and future electronics systems and in particular the radio frequency (RF) ones, demands multiple functionalities of re-configurability and of tunability with guaranteeing at the same time the miniaturization, reliability and temperature stability. At the same time, the progress on carbon materials like Carbon nanotubes (CNTs) and Graphene have demonstrated superior properties, such as exceptional stiffness, remarkable mechanical properties, electrical and thermal conductivity. Here we report the development of resonator fully printed on paper substrate for microwaves application and their thorough microwave characterization (6GHz-40GHz). The RF resonator based on both Ag nanoparticles and double wall carbon nanotubes (DWCNTs) inks was fabricated on paper substrate. To study the electrical performance of Ag nanoparticles with an average particles size of 20-25nm at high frequency, the transmission lines (coplanar waveguide “CPW”) were printed on paper. A conductivity of 1.4.106 S/m for 0.85µm of thickness is obtained and an acceptable -1.3 dB transmission at 10GHz is able to validate the Ag-ink based microwave device feasibility. DWCNTs are fabricated using a catalytic chemical vapor deposition (CCVD) technique. Then, they are dispersed in solvent to form printable ink adapted with ink-jet printing process [3]. Deposited on the specific area gap (g) of 100µm, the DWCNTs films are used as sensitive part of electromagnetics fields and could tune the frequency resonance of the resonator depending on its enviroenment. The RF characterizations revealed a dependence on the number of DWCNTs films (3 to 15 layers of DWCNTs films) printed on gap of RF resonator. The transmission of frequency response is performed from 28.55dB (without DWCNTs) to 25dB (15 layers of DWCNTs films). This first prototype RF resonator confirms that the fabrication device at low cost, low temperature of process and low consumption by using ink-jet process and paper substrate can be integrated on future wireless sensor for sensing application .
[1] De Paolis, R., Pacchini, S., Coccetti, F., Monti, G., Tarricone et al. Circuit model of carbon-nanotube inks for microelectronic and microwave tunable devices. Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International (pp. 1-4).
[2] Lee, H., Shaker, G., Naishadham, K., Member, S., Song, X., Mckinley, et al. (2011). Carbon-Nanotube Loaded Antenna-Based Ammonia Gas Sensor. October, 59(10), 2665-2673.
[3] Sébastien Pacchini, E. Flahaut , N. Fabre, V. Conedera, F. Mesnilgrente et al., International Journal of Microwave and Wireless Technologies, Vol. 2, Iss. 05, pp. 487-495, 2010

Due to the continuous miniaturization of integrated circuits, interconnects with higher electromigration (EM) resistance and acceptable cost of fabrication are highly desired. Without grain boundaries and triple junctions (flux divergence) under current stressing, single crystal interconnects are expected to show better performance and higher reliability. In the present work, we show an effective and microelectronic compatible method capable of producing single crystal-like thin metallic films with the help of ion bombardment. The method started from a seed layer of 50 nm thick Au film, deposited by magnetron sputtering, with strong (111) fiber texture. Single crystal-like Au film with thickness of 500 nm was then achieved by a process consisting of repeated sequence of ion induced selective sputtering and subsequent deposition of the seed layer. In the same way, single crystal-like Cu film was successfully produced from a 50 nm Cu seed layer. Because the fastest diffusion path for Au and Cu is through surface diffusion, the effect of microstructure change is investigated with/without the SiNx passivation layer. Their reliability performance was characterized by accelerated EM test with high current density and high temperature. From the preliminary results in Au, we found that single crystal-like interconnects show longer lifetime than polycrystalline counterparts. Besides, we will, measure the activation energy of EM and propose possible mechanisms of the microstructural effect on EM.

In this paper, a comprehensive model of a micro-switch with both the electrostatic and piezoelectric actuators, which accounts for the shortening effect (the neutral bending axis does not elongate), is presented and formulated to demonstrate the mechanical characteristics of such a micro-system. Dynamic equations of this model have been derived by the Lagrange method and solved by the Galerkian method using five modes. The micro-switch beam has been assumed as an elastic Euler-Bernoulli beam with clamped-free end conditions. Nonlinear terms due to inertia, geometry, electrostatic forces and piezoelectric actuator have been considered in the dynamic equations. The electrostatic actuation results have been compared with other existing experimental and numerical results. Whereas the major drawback of electrostatically actuated micro-switches is the high driving voltage, using the piezoelectric and electrostatic actuators together can lower the driving voltage. We demonstrate that when the ratio of electrostatic actuation distance to length of micro-switch is small, the nonlinear piezoelectric term has a significant effect on the pull-in phenomenon. There are three ways to influence the design and control of the mechanical characteristics of this micro-switch: the softening effect due to electrostatic actuation, the hardening effect due to piezoelectric actuation, and varying the length and thickness of the piezoelectric actuator.

Isotropic conductive adhesives (ICAs) have numerous advantages over traditional Sn/Pb solder as they require fewer processing steps and lower processing temperature, allowing the preparation of heat-sensitive and low-cost chip carriers with fine-pitch capability. However, their high electrical resistivity and poor mechanical properties have hindered development.
A novel method of improving the electrical conductivity of epoxy/silver nanocomposites by adding silica particles was explored experimentally and theoretically. Silica particles significantly decreased both the electrical percolation threshold concentration of silver nanoparticles and the electrical resistivity of the composite. They also enhanced thermomechanical properties, such as CTE. Molecular simulations demonstrated that effective intermolecular interactions between silver nanoparticles become more attractive with increasing the content of silica particles, aiding the formation of electrical percolation networks

I describe processes, and underlying mechanisms, whereby metal deposition can be emphasized at, or entirely limited to, the bottom regions of submicrometer patterned damascene features.
I begin by detailing the interplay of adsorbate coverage and area change within the “Curvature Enhanced Coverage Mechanism” yielding enhanced deposition of metal toward the bottoms of filling features1-2; such “superfill” has been the basis of damascene copper since its introduction by IBM in 1997. I will summarize CEAC-based superfilling processes for noble metals discovered since then3-5. I will note tell-tale characteristics observed in deposition on planar substrates and detail pattern filling signatures of copper, silver and gold superfill by electrodeposition and copper superfill by chemical vapor deposition in submicrometer damascene features; I will also discuss the impact of surface diffusion on superfilling processes, detailing how it explains subtle differences in the filling profiles for the different processes.
I then detail an entirely different, just disclosed mechanism6 that induces deposition entirely localized to the bottoms of filling features, with no deposition on the sides of filling features nor the field above them. I explain how this mechanism underlies previously disclosed superconformal filling of submicrometer damascene features with the elemental and alloyed ferrous metals nickel, cobalt and iron7-9. I discuss the potential of these magnetic material processes for achieving advanced memory, logic and active devices, and, due to the generality of the mechanism, the possibility for broad application to materials and systems.

1. T.P. Moffat, D. Wheeler, W.H. Huber, and D. Josell, Electrochemical and Solid-State Letters 4(4), C26 (2001).
2. T.P. Moffat, D. Wheeler, M. Edelstein and D. Josell, IBM Journal of Research and Development 49(1), 19-36 (2005).
3. B.C. Baker, M. Freeman, B. Melnick. D. Wheeler, D. Josell and T.P. Moffat, Journal of the Electrochemical Society 150(2), C61-C66 (2003).
4. D. Josell, D. Wheeler and T.P. Moffat, Journal of the Electrochemical Society 153(1), C11-C18 (2006).
5. D. Josell, S. Kim, D. Wheeler, T.P. Moffat and S.G. Pyo, Journal of the Electrochemical Society 150(5), C368-C373 (2003).
6. D. Josell, T.P. Moffat and D. Wheeler, J. Electrochem. Soc., 159(10), D570 (2012)
7. S.-K. Kim, J.E. Bonevich, D. Josell and T.P. Moffat, J. Electrochem. Soc., 154, D443 (2007).
8. C.H. Lee, J.E. Bonevich, J.E. Davies, and T.P. Moffat, J. Electrochem. Soc., 155, D499 (2008).
9. C.H. Lee, J.E. Bonevich, J.E. Davies, T.P. Moffat, J. Electrochem. Soc, 156, D301 (2009).

Selection of different types of soldering materials is driven by factors such as packaging conditions and environmental usage. Besides being environmentally toxic, the traditional Pb-Sn soldering material is not reliable for high temperature electronics either. On the other hand, miniaturization and double-sided electronics require more accuracy and higher temperature tolerance of interconnects even in harsh environments. In this work, nano-size Au-Sn alloy powder (AP) has been successfully synthesized by chemical reduction method. This alloy has the potential as a new class of lead-free soldering material for high temperature electronics. It offers superior properties compared to the traditional Pb-Sn solder for applications in aerospace, army, electronics and recently automobile industry. Tetra kis (Hydroxymethyl) Phosphonium Chloride (THPC) was used for controlling the resulting unique low melting temperature. Experiments showed that the melting temperature of this AP decreases significantly (187 °C) by reducing the size of the particles down to 10 nm. The resulting stoichiometry in the AP was found to be a strong function of the precursors&’ ligands and concentration. The Au-Sn AP offers a unique set of advantages as a lead-free soldering material. In nano-size powder state, it flows at lower temperatures leading to less thermal stresses in adjacent electronic components during the manufacturing process. After the completion of solder joint formation, i.e., in the bulk state, the joint reclaims its bulk Au-Sn properties including permanent high melting temperatures (up to 420 °C). This phenomenon manifests the potential superior thermal and mechanical performance of this AP joint. Reliability of this candidate, however, requires further investigations before large scale production for industrial applications.

Recently, there has been extensive research on stretchable electronics implantable to human body such as skin and organs. In particular, high performance stretchable devices including UV, gas, and pressure sensors would have potential applications in bio-organs, industries, and under harsh environments. Up to now, silicon and polymer-based materials have been mostly used as active components in flexible/stretchable devices. However, 1D materials including nanowires (NWs) and nanotubes are expected to be advantageous in future stretchable electronics, exhibiting enhanced performance and better integration due to their superior electronic properties and structural flexibility.
In this study, we report on the fabrication of high performance, stretchable UV sensor arrays based on active matrix (AM) device using SWCNT field effect transistors (FETs) and SnO2 NW FETs together. Through the optimization of fabrication processes for SWCNT and SnO2 NWs devices, ~90 % process yield of AM based UV sensor arrays on stretchable PDMS substrate is obtained. Application of AM device structures provides spatial addressing of individual UV sensors. Compared to the previously reported results from NW- based photo sensors, these devices demonstrate high performance of UV sensor arrays with average photosensitivity of ~10^5 and external quantum efficiency of ~10^6 under very low UV power intensity of 0.02 - 0.04 mWcm-2 . In order to have all the external strain accommodated by the interconnection, very narrow and long metal interconnections encapsulated by polyimide are fabricated. Therefore, the device performance is not deteriorated when the whole devices are radially stretched up to 20 %, consistent with the mechanical analysis demonstrating its high potential application in the fields of wearable sensors or curvilinear devices that is not available with conventional rigid or flexible photo sensors.

Robust electro-migration (EM) reliability becomes more imperative as Cu-line widths are aggressively scaled for successive technology nodes. This causes smaller Cu-grain sizes, more barrier layer dependency, and substantial atomic migration at the Cu-capping interface, which requires process dependent vacancy parameters in TCAD simulations. By understanding the interaction of physical EM failure kinetics with the internal microstructure of Cu-alloy interconnects in early simulations, it is possible to define a set of electrical design rules that simultaneously optimize the density, performance, and reliability of the overall chip.The simulated test layout used Cu-line dimensions typical for a 22nm node dual-damascene structure.
We describe a mass transport TCAD simulation by using Sentaurus S-Interconnect tool that models reported EM behaviors: 3-step EM induced resistance (R) change, line length (L) effect, and temperature dependency on L and current density (j) products. We performed trend and sensitivity analyses for key physical EM model parameters: Cu-void formation, a sudden jump in line R associated with void growth, and Cu-vacancy (Cv) and void (Cvoid) profiles. In this manner, we have a new methodology for accurately determining the EM lifetime.
During EM stress, Cu-vacancies move from anode to cathode in a manner analogous to the movement of holes in an electron sea through diffusion/drift conduction, whereas Cu-atoms migrate toward the anode as pushed by the electron wind. To model Cu-alloy line EM failures, we used the key input parameters: void formation density (VFD), surface energy density (SED) of Cvoid interior, and grain-boundary energy density (GED) of voids. For higher VFD values, the line R jump at the onset of full void formation and the Cu-atom drift velocity tend to decrease which in turn results in a longer EM lifetime (tf). We consider Cv time dependency at the cathode end, located underneath a cylinder-like via hole.
Vacancy transport takes place predominantly at the Cu-void surface and grain boundaries, so mass transport kinetics can be determined by the SED and GED parameters. Gibbs free energy of void formation increases by SED but decreases by GED. When Cvoid reaches the specified VFD level, we&’re able to define tf as a failure criterion corresponding to a ~10% line R change. Our results of via and line depletions, including the short L effect, matched well with EM test results.

The level of details provided by these 3D TCAD simulations allows us to extract new information. Two asymptotical parabolic lines from L-dependent simulations have been derived that define 3 new figure-of-merit regions for determining EM lifetime: safety, aware, and failure. The EM-aware region depends upon the length of Cu-lines, and we observed a non-linearity in the length dependence on the EM failure jL product at ~9000 A/cm under high current stress. This methodology provides fast and practical EM lifetime prediction.

Carbon nanotubes (CNTs) have been considered as promising interconnect materials to replace the solder bump used in the flip chip package because of their special electrical, mechanical and thermal properties, which may promote both the performance and reliability of the flip chip packaging. In this paper, electrophoretic deposition (EPD) of CNTs on substrates has been demonstrated for the interconnect application. EPD is a simple, low cost and high throughput process that is capable to produce densely packed film with good homogeneity at low temperature. By altering the electric fields and deposition time during the EPD process, the thickness of the CNTs film could be controlled. In this study, single- and multi-walled carbon nanotubes (SW- and MW- CNTs) were successfully coated on the various substrates using the EPD method. A highly uniform CNTs microstructure film with controlled thickness was achieved. In addition, the selective depositions of CNTs on the pre-defined bond pads to form CNTs bumps were also accomplished. By employing typical flip-chip bonding technique, high density CNTs bumps were aligned to form a test chip/host substrate interconnects. The electrical conductivity of the CNTs interconnects was carried out using four-point measurement. Reliable electrical contacts with linear relationship in the current-voltage (I-V) characteristic suggesting ohmic behaviour were attained. The overall resistances extracted were also relatively low. These superior electrical properties have demonstrated that the CNTs bumps deposited using EPD method is a viable way to serve as an alternative to current metal solder interconnects material. Hence, it offers a promising interconnect application in the quest for device miniaturization in microelectronic industry.

We have successfully investigated the feasibility of CuNx barrier for Cu metallization as an adhesion promoter and diffusion barrier between Cu and amorphous silicon. To obtain the appropriate diffusion barrier ability of CuNx film, we have optimized the deposition conditions of it. Cu/CuNx bilayer was continuously deposited on substrate by using single Cu target(5N) and N₂ reactive sputtering in the same camber and was defined by a chemical etchant based on H₂O₂. CuNx film&’s properties were influenced by deposition conditions as follows; substrate temperature, Ar/N₂ flow rate ratio, plasma power and working pressure. Particularly, CuNx deposited under high working pressure and low power is very unstable. Consequently, we have to get over poor thermal stability to use CuNx as a glue layer and diffusion barrier for copper. To make the stable CuNx film at high temperature, we have investigated deposition conditions under low pressure and high power.
Finally, the stable CuNx film could effectively suppress Cu diffusion into amorphous silicon until approximately 400°C. We have achieved to characterize a hydrogenated amorphous silicon thin film transistor with Cu/CuNx bilayer as a gate and a source/drain electrode. The subthreshold slope and the on/off current ratio obtained from the transfer curve at the drain voltage, Vd = 10V were 0.93V/dec and approximately 10⁶, respectively. The electron field-effect mobility at the saturation region and threshold voltage, VT at Vd = 10V were 0.32cm²/Vs and 1.63V. The off-state leakage current at Vg = -5V was 10^-12A.

The integration of silicon nanowires (SiNW) into microelectronic devices is an increasing area of research. Due to their high surface to volume ratio coupled with their electrical properties, they offer for instance, the potentiality of new functionalities in interconnection levels. Indeed, it seems potentially interesting to integrate passives, sensing or energy production devices as close as possible of the command and information-processing electronics. Moreover, nanowires provide a unique opportunity to integrate logic functions in interconnects levels as, for example, by introducing vertical transistors in vias. This would constitute an interesting step toward reconfigurable interconnections.
However, the generally applied growth methods for SiNW are not compatible with the requirements imposed by microelectronic fabrication processes. First, SiNW are usually grown in the presence of gold catalyst not compatible with CMOS standards. Moreover, the replacement of gold by other metallic catalysts often implies process growth at temperatures higher than 450°C (a higher limit for interconnects).
In this study, SiNW were grown by Chemical Vapor Deposition (CVD) using a Cu-based catalyst. We have used an original process by applying an oxidation step to a Cu layer prior to the growth. This method allows decreasing the growth temperature down to 400°C (the growth occurring by a Vapor-Solid-Solid growth mode).
Growth mechanisms and SiNW morphology were studied using electronic microscopy and physico-chemical experiments. We highlight the importance of the oxidation conditions and of the surface state. A specific analysis of the first step of the reaction reveals the formation of copper silicide (Cu3Si) which acts as the catalyst of the growth. Finally, a careful understanding of this growth process has allowed to growth Si nanowire on TiN bottom electrode and in patterned structures.
Using this method, the fabrication and the characterization of CVD grown silicon nanowires capacitors were performed. These capacitors were integrated using Back-End-Of-Line compatible processes. We take advantage of the highly developed surface of a nanowire assembly grown on a metal to get high density Metal-Oxide-Semiconductor (MOS) capacitors. The obtained devices with alumina and conformal metallization have a capacitance density of 18 mu;F/cm2 and feature a × 23 gain when compared to the same structure without nanowires. This demonstration prefigures a new generation of energy storage components or ultra-dense decoupling capacitors for integrated circuits and opens the path toward novel technologies using bottom up nanowires.

Electromigration becomes a major reliability issues for Cu interconnects in current driven TFT devices.
Generally, TFT panels using the huge glass substrate so LCD panel interconnect structures are exposed to high mechanical stresses during manufacturing and operation. Electromigration characteristics related with between copper surface and following cap layer. We found that Cu line with SiO2 capping layer has more serious electromigration damage and mechanical stress than Cu line with SiN capping layer. The failure time of electromigration was effected by the adhesion difference between the copper and cap material, and the thermal difference of capping materials between SiO2 and SiN.
In this paper, we investigate the influence of copper grain sizes on the electromigration reliability according to PECVD capping layers. We have applied a Cu alloy to improve the electromigration reliability. Cu alloy enhanced electromigration characteristics induced external stress regardless of passivation materials because the grain size of copper alloy is smaller than pure copper. As a result, the median-time-to failure of electromigration under J=1.8MA/cm2 was significantly improved over than 70%.

Single walled carbon nanotubes (SWCNTs) have shown great potential as channel materials in future nano-electronics due to their excellent electrical and physical performance. Compared to other channel materials, such as silicon, metal oxide nanowire, and organic materials, SWCNTs have much higher tensile strength and robustness. As-grown SWCNTs exhibit intrinsically p-type semiconducting behavior in air ambient due to electron-accepting adsorbates. So, surface treatment with electron donating materials such as β-nicotinamide adenine dinucleotide, reduced dipotassium salt (NADH), can be used for the excellent type conversion of p-type SWCNTs.
Here, we report on the fabrication of wholly stretchable complementary metal oxide semiconductor (CMOS) inverter arrays consisting of p-type and n-type SWCNTs channel regions. SWCNTs were grown at 925 °C by using ferritin solution (by diluted 1:6000 DI-water) as Fe catalyst via chemical vapor deposition technique. SWCNTs were transferred onto a thin polyimide (PI) film coated substrate using the thermal release tape. NADH coating of pristine SWCNTs FET showed n-type semiconducting behavior with on/off current ratio of ~ 1000 and the fabricated SWCNT CMOS inverters showed gain values higher than 5. The PI substrate containing whole inverter array could be successfully attached on a thin PDMS film which had been coated with thin Cr/SiO2 (2/20 nm) layer and subsequently exposed to O2 plasma. Device performance of the fabricated CMOS inverter array was not deteriorated after stretching up to 40 % and 1000 times repetition of stretching and releasing. This work demonstrates that SWCNT technology can be exploited in soft systems, well suited for use in implantable electronics where conventional, planar devices cannot meet requirements.

The dual damascene technological process has some problems. They reveal themselves in the increase of an effective value of copper (Cu) conductor resistivity, and the necessity of decreasing the signal delay necessitates reduction of keff , the film dielectric constant of an intralevel isolation down to ~ 2.0. These problems can be solved by introducing certain changes in the metallization technology. The most important change is the use of a local upwards-directed (“from the bottom upwards”) electrochemical deposition (ECD) when forming Cu horizontal conductors (CuHCs), for example, thru the photoresist mask (HCPRM) atop barrier and seed layers (B/SLs), and then forming Cu vertical conductors (CuVCs) thru the VCPRM, as said in [1]. In such a process no copper CMP is used, the voids formation during the copper deposition is eliminated, no beetling edge during the deposition of metal B/SLs is formed, the electrolyte composition is simplified, the conditions of copper ECD are improved, and during the Cu ECD process itself a textured structure is being formed. After removing the VC/HC photoresist masks the S/B layers are etched off, a porous intralevel ultra-low-k dielectric is formed or the “air gap” isolation is formed. In this case there is no selective etching of the porous intralevel dielectric and no danger of opening an area with the porous dielectric or with the “air gap”. We have also been working out a new flowroute version based on [2], where in the beginning the horizontal conductor is fully manufactured as per [1], then HC photoresist mask, B/S layers are removed. By using the spin-on procedure the porous intralevel ultra-low-k dielectric is applied. It becomes possible to cover all the conductor sidewalls including a boundary between HCs and VCs with an optimal barrier film. After that the porous film is completely etched off from the surface of conductors and to some extent slightly below. Further an interlevel isolation of barrier and dense low-k dielectrics is formed, the surface is planarized by CMP technique, a barrier dielectric is applied and the vias for the vertical conductors are formed. Further the wafer surface and via sidewalls are coated with barrier and seed layers, e.g., Ta and Ni. After that a polymer layer, e.g. photoresist, is applied by spin-on technique and then is removed by back-etching from the wafer surface and the most area of an upper part of the vertical vias. Then by using the wet etching the seed layer is etched from open areas. In this ECD process a copper vertical conductor on such a structure is formed locally because copper is not deposited on the Ta surface, while a larger, upper part of vias is filled mainly “from the bottom upwards”. Finally the metal barrier layer is removed by maskless etching. This method enhances the structure strength and reduces its aspect ratio during the treatments.
Patents of the RF: [1] 2420827, [2] 2230391

Patterned organic thin films with ordered sub-micron features are of great importance in applications such as nanoelectronics and optoelectronics. We present here a new approach for making patterned organic films using area selective molecular layer deposition (MLD). MLD is a technique that allows for conformal deposition of organic thin films with controllable thickness and composition in the nanometer range. Area selective MLD provides for lateral patterning of the film in addition to the excellent vertical thickness and composition control. In this work, polyurea MLD was deposited by alternating pulses of 1,4-phenylene diisocyanate and ethylenediamine in the gas phase at room temperature, achieving a linear growth of 6Å/cycle. Self-assembled monolayers (SAMs) from octadecyltrichlorosilane were patterned on silicon (100) substrates by soft lithography in a well-controlled environment. The quality of the SAMs was monitored by Fourier transform infrared spectroscopy and water contact angle measurement. Auger electron spectroscopy revealed that polyurea films were grown selectively on the ODTS-free regions of the substrate, indicating effective blocking of MLD by the ODTS SAM. The requirements of the SAM to block the MLD process will be described. Potential lithographic applications of the patterned polymeric thin films will also be discussed.

The first high-k/metal gate (MG) was introduced into mass production by Intel in 2007. By using Hf-based dielectric/MG in its product of 45 nm technology nodes, the significant improvement on gate leakage and device performance makes high-k/MG an extremely hot topic in CMOS. Three high-k/MG integration schemes, namely, high-k/MG first, high-k first/MG last and high-k/MG last, are mainly involved in the fabrication of the state-of-the-art transistors. Currently, the high-k/MG last scheme is of great interest due to the ease in choosing suitable metal gate materials. Nevertheless, one possible issue bothering high-k/MG high-k/MG integration process is that the post high-k deposition anneal (PDA) of usually high temperature may break the integrity of NiPtSi films formed on source/drain (S/D) regions. As a consequence, a remarkable increase of parasitic S/D series occurs which leads to poor device performance. In order to circumvent this problem, a silicide-last process was proposed. The term “last” refers that silicides are usually formed in contact holes after high-k/MG integration. The silicide-last process avoids not only degrading NiPtSi films during PDA, but also the abnormal lateral encroachment of Ni-based silicides towards channel during common self-aligned silicidation (SALICIDE) process. Furthermore, as the gate pitch continuously scales, the silicide-last process is getting more and more competent in achieving low parasitic S/D resistance. Profiles of Ni films sputtered in contact holes with different aspect ratios and the as-formed NiSi/Si interface were characterized by SEM. Based on the NiPtSi-last process, the specific contact resistivity of NiPtSi to highly doped N- and P-type substrate using cross-bridge Kelvin Resistor (CBKR) method were investigated. Meanwhile, the cold Ti/Si specific contact resistivity(ρc) utilizing CBKR patterns and NiPt combined with Ti/TiN as contact liner were checked for the first time. It is revealed that as the aspect ratio of contact holes increases, the gap-fill performance of Ni PVD degrades since the adhension between Ni films and Si is weak. As a result, the as-formed NiSi is non-uniform and NiSi/Si interface is rough. Uniform NiSi films and nice NiSi/Si interface is obtained by increasing the Ni thickness. The The ρc of 2.5x10-7#8486;cm2 for NiPtSi/n+-Si and 2.75x10-7#8486;cm2 for NiPtSi/p+-Si were achieved even for the minimum contact area of 0.5um2. In the cold Ti/Si case, the ρc of Ti to n+-Si is 5.85x10-7#8486;cm2 at the contact area of 0.5um2, which can be comparable to that of NiPtSi/n+-Si. Lower ρc for cold Ti/n+-Si would be realized by improving process conditions. Thus, it is proposed to employ cold Ti for contact to microelectronic NMOS devices.

As the needs for electronic devices are increasing, Importance of MIM (metal-insulator-metal) structure is increasing as well. Conventionally, Sol-gel and tape casting method have been used to fabricate these capacitors. However, this type of deposition process requires solution such as paste and slurry type, resulting in quite complex and toxic process. To overcome these problems, eco-friendly fabrication of dielectric layer through Nano Particle Deposition System (NPDS) has been introduced in this study. The mechanism of NPDS is as follows; powders are accelerated through the nozzle with supersonic velocity using air compressor and deposited on the substrate by high kinetic energy. The major advantage of NPDS compared to cold spray or aerosol deposition process is that both metallic and ceramic powders can be deposited at room temperature on various substrates without using solvent. In this study, NPDS was used to deposit dielectric layer film to fabricate eco-friendly MIM structure. BaTiO3 powders which are used as a dielectric layer were deposited with its thickness of 5um and its structural and dielectric properties were analyzed. As a result, Hysteresis loop was successfully formed with its remnant and saturation polarization values measured. Using those fabricated MIM structures, actuator was fabricated. Therefore, the possibility of eco-friendly fabrication of MIM capacitor system via NPDS has been successfully demonstrated.

In recent years, 3D integration has become an alternative solution to the “More Moore” concept for providing circuits with higher performance or increased functionality.
Via-Middle trough silicon via (TSV) is considered a reference integration scheme. This scheme requires void-free copper fill of very high aspect ratio TSVs: typically in the range of 10:1.
Metallization of such structures, in particular barrier and seed layer deposition, becomes a critical process step for two main reasons. First, the barrier material must be robust, preventing copper diffusion into the silicon during subsequent BEOL and backside processes. Second, the barrier/seed stack must cover the internal surfaces of the TSV completely to avoid disruption to the electrical current distribution during ECD via-fill.
Ionized PVD (I-PVD) is known as the reference process for TSV barrier/seed deposition. It does however, have several drawbacks and limitations for 3D applications. The step coverage from I-PVD is below 10% in 10:1 aspect ratio TSVs which means very thick barrier/seed layers for successful integration. This thickness leads to a limitation in the minimum CD of the TSV that can be successfully electroplated and also leads to expensive deposition and further subsequent CMP processes. In addition, because I-PVD Ta(N), today considered as the reference process exhibits highly compressive stress values, the thick layers required for TSV barrier deposition can lead to adhesion problems.
Considering the maturity level of the alternative processes, MOCVD metallization appears to be a very promising option, particularly for the barrier material. MOCVD TiN layers have been widely reported to provide excellent step coverage and diffusion barrier efficiency in BEOL processes.
An MOCVD TiN process was selected for the presented study because of its ability to deposit TiN barrier layers over a wide temperature range (from 175 to 400°C) used for both Via-Middle and Via-Last TSV schemes (Via-Last TSV temperatures should not exceed the degradation temperature of the carrier bonding glue).
The paper will first discuss the process development and characterization of this material under various process conditions with particular focus on key parameters for 3D integration such as deposition rate, uniformity, and crystalline structure at different temperatures. In addition, film integration in Via-Middle TSVs will be described, comparing step coverage performance in high aspect ratio features along with barrier properties against the I-PVD reference process.
Finally, full integration in a 300 mm 3D demonstrator, including both I-PVD and MOCVD barriers for TSV as well as damascene interconnect will be presented. The demonstrator will include front and backside metallization, allowing electrical measurements of daisy chains and interconnect lines, and will show the low temperature MOCVD TiN barrier process to be a very attractive and integratable solution for 3D technology.

Technologies namely SiGe based HBTs are well suited for emerging high-volume applications such as high-speed communication, broadband (60 GHz WLAN), radar (77 GHz automotive), imaging and sensing (160 GHz ICs). The present state-of-the-art devices are operating at RT in frequency of about 500 GHz/1.9 ps (fmax/td) ranges. A higher operating speed can open up new application areas at very high frequencies and also it can be traded-in for lower power dissipation. In addition, it could help to reduce the impact of process, voltage and temperature variations at lower frequencies for better circuit reliability. HBTs have always led the frequency race compared to MOS devices, while offering high power density and better analogue performances. Particularly, SiGe HBT is a key reliable device for applications requiring power greater than few mW (future MOS limitation) and enabling high density, low cost integration compared to III-V compound semiconductors. The reliability of CMOS devices are verified and tested by well-defined industry standards for e.g. JEDEC. However for the BiCMOS devices, there is a lack of industry-wide acceptable guidance. In most cases, either the suppliers simply follow the generalised approach of looking into the well-known hot carrier injection, time dependent dielectric breakdown stress tests or electromigration of the intermetallic connections. But the other degradation mechanism that could impact the HBT reliability is the increase of beta parameter, due to the degradation of base or collector currents. If the transistors have to be operated beyond the emitter-collector breakdown voltage and within their upper limit of collector-base breakdown voltage, then continuous device degradation is very much expected, as it is often the case in RF circuits. Hence the industry needs proper reliability models, which describe the transistor under various operating conditions. The scope and content of this work is to develop such a reliability model and we are working with partners towards this common goal. In our approach, the transistor degradation mechanism under different ambient temperatures (-45°C to 125°C), long operating times, stress modes (base-collector voltage, emitter current) including “mixed-mode” conditions has been studied. Further, the ageing of the devices under enhanced stress conditions will also be discussed. The observed HBT degradation has been used to develop an “ageing function”, which in turn applied to predict the long-time transistor degradation. Until now SiGe HBT reliability investigations in the literature were based on short-term stress tests (only up to 10 hours) which were then extrapolated to the required lifetime limit. Finally, stress-adapted HBT models that are incorporated into appropriate test circuits to simulate the influence of HBT ageing on circuit performance will be presented.

Chemical Vapor Deposition (CVD) methods have been extensively studied for thin film deposition, and are widely used industrially. But CVD processes have some difficulties like poor film quality, high processing temperature, limit of precursors, and patterning necessary. The Laser CVD (LCVD) process at atmospheric pressure has recently emerged to overcome all those problems mentioned earlier. For the deposition of thin films by LCVD, a focused laser beam irradiates on the surface of a substrate placed in a reaction region filled with precursor gas to locally raise its surface temperature. For the advantages like direct writing, mask-less patterning process, high deposition rate and throughput the LCVD process can be widely used in the micro-circuit repairing and mask repairing.
In this research an open-atmosphere LCVD process was used. In this process a third harmonic Nd:YLF laser (355nm) of high repetition rates, up to 4 KHz, as the laser source and W(CO)6 as the precursor, known as easily photo-activable were used. Using on processing imaging system, the tungsten (W) film formation can be observed as well as desired region can be controlled by moving system. To varying a laser energy is a key factor of LCVD process which can control deposition with raising temperature on the surface of substrate and can change concentration of photo-activated precursor.
The growth behavior of LCVD deposited W thin films varying the laser energy from 50 to 300nJ was investigated. Through the analysis of composition, compounds, crystallinity, morphology and resistivity, those films were evaluated.
The growth rate of W thin films was raised and incubation time was reduced by raising the laser energy. Thus concentrated photo-activated precursors and increased surface temperature caused faster deposition rate of W thin films. In case of too high laser energy the morphology and quality of W thin films were degraded.
The LCVD deposited W thin films were carbon-free, and consist of W and O. The reason of carbon-free W thin films can be expected that the W(CO)6 precursor on locally heated surface and oxygen in atmospheric pressure can react with each other and can easily be formed COx gases. And the O content in W thin film was decreased with raising laser energy, it can be expected that surface of substrate has high temperature and O can be easily reacted. The XRD data shows that dominant metallic W and WO3 phases were mixed in W thin films.
To investigate electrical characteristics in W thin films, the Transmission Line Model (TLM) device was used. The resisitivity of those films had the electrical resistivity of ~100mu;Omega;-cm, which their fascinating electrical performance can be applied circuit repairing and fabrication of micro device.

In order to implement porous SiOCH films in ILD integration, restoration process for recovering plasma damages and pore-sealing for prevention of barrier metal penetration into the film has been pursued. We have developed a process enabling ultra-thin sealing (1nm) of porous SiOCH with k=2.0 by combining UV-assisted restoration and plasma-enhanced ALD (PEALD) pore-sealing process. This process provides a damage-free porous SiOCH integration, where plasma damage and chemical diffusion into the film are greatly reduced.
Extreme porous low k with k=2.0 was formed by PECVD using porogen removal by UV cure (hereafter denoted as k2.0). The film porosity and the average pore diameter were estimated to be 42% and 3.3 nm, respectively, by ellipsometric porosimetry analysis. As a pore sealing film, PEALD SiN was employed due to film conformality and precise thickness control even at low temperature below 300C.
As a restoration process, we have compared thermal, plasma and UV-assisted processes. Restoration performance was examined with O2 plasma damaged SiOCH films. As increasing restoration process time, OH group decreased and k-value recovered, irrespective of restoration methods. Among these methods, UV-assisted restoration was found to be the most effective in removing of OH group and enabled full recovery of k-value of damaged k2.0.
In order to assess the pore-sealing capability of the PEALD SiN film, penetration of thermal ALD TiN precursor and liquid chemical into the SiOCH film was examined after pore-sealing deposition. The metal diffusion was evaluated by back-side SIMS, and the liquid chemical diffusion was determined by optical inspection. Impact on k-value was also investigated by comparing k-values before and after pore-sealing deposition. Two types of samples were prepared. One is a pristine k2.0 and another is a restored k2.0, which was prepared by treating O2 plasma damaged k2.0 with UV-assisted restoration. The required thickness of PEALD SiN for complete sealing of the pristine k2.0 was about 3 nm, which induced serious deterioration of k-value. The SiN diffusion into the pores was observed due to high porosity from cross-sectional TEM analysis and mass metrology. This might have induced degradation of k-value and hampered robust pore-sealing layer formation, requiring thick SiN to seal the surface. On the other hand, the restored k2.0 required thinner PEALD SiN of only 1 nm for complete sealing. Prevention of SiN diffusion was also confirmed, leading to negligible impact on k-value. In addition, the leakage current characteristics were not degraded. These results suggest that the pores in SiOCH are coated by the restoration layer and it suppressed SiN diffusion into the pores, allowing robust SiN pore sealing film formation at thickness as low as 1nm.
According to these results, it was confirmed that the combination of UV-assisted restoration and PEALD SiN formation is a promising processes for integration of porous SiOCH with k=2.0.

Low dielectric constant (low-k) materials are developed to meet the ever increasing challenges in IC industry in terms of RC delay. In this respect, SiCOH low-k materials with k value as low as 2.0 show a huge application potential. Nevertheless, ca. 50% porosity and pore diameters larger than 3nm are introduced to decrease the k value which amplifies the potential issues of precursor penetration from subsequent processing (atomic layer deposition (ALD), chemical vapour deposition (CVD) or electroless deposition (ELD)). In our work, a novel pore sealing approach is engineered by depositing firstly a self-assembled monolayer (SAM) and then a thermally grown CVD-like thin TiN film or an ALD HfO2 film. The sealing properties of SAMs against TiN and HfO2 precursors were thoroughly characterized and discussed.
The low-k films used in this study were deposited by PECVD (plasma enhanced chemical vapour deposition) on Si substrates for 300mm blanket wafer. In order to introduce hydroxyl groups which are indispensible for subsequent SAM deposition, low-k materials were pretreated with plasma in a CCP 300 mm single wafer system. Different plasma pretreatment conditions (time, temperature, power, composition and chemistries) were evaluated in order to achieve an optimal surface activation without significant low-k damage. Sealing and electrical properties of SAMs with different chain length (8, 11, 18 and 22 carbons in the chain) and different tail group (cyano- vs. CH3-) were characterized and discussed. Afterwards, SAMs were deposited by immersing the low-k material in a 5mM trichlorosilane precursor solution in toluene. A ~2nm thick SAMs sealing layer was deposited followed by the deposition of TiN/HfO2 film. Characterization techniques employed focused on SAM&’s electrical properties and their sealing efficiency: water contact angle for surface hydrophobity, AES and FTIR for layer chemistry, AFM for topology, XRR for film thickness and density, ellipsometry for thickness, porosimetry for porosity and pore size. The dielectric constant before and after SAMs deposition was extracted from the C-V curves measured on a minimum number of five Pt dots of different size. Sealing against metallization precursor was achieved with Δk less than 0.28 (after SAMs deposition).
In this contribution, the relationship between intrinsic material chemistry, thin film morphology and final sealing properties are explored.

Ruthenium, as a rare transition metal inert to environment, has increasingly become a new barrier liner material in interconnect at advanced technology nodes. The goal of this work is to evaluate ruthenium compatibility with PlanarCleantrade; and improved versions of PlanarCleantrade; in post CMP clean applications to achieve a controlled galvanic corrosion between copper and ruthenium. Galvanic corrosion refers to corrosion damage induced when two dissimilar metals are coupled in a corrosive solution. When a galvanic couple forms, the metal with less noble open circuit potential becomes the anode and corrodes faster than it would by itself, while the other becomes the cathode and is protected from corrosion. Electrochemical Tafel curves showed that, in the presence of 60:1 diluted PlanarCleantrade;, ruthenium is cathodically protected and copper has an accelerated corrosion rate of 3.88Å/min. For an improved chemistry, PlanarCleantrade;AN, copper corrosion rate is reduced to 0.06Å/min and ruthenium is still inhibited from corrosion. Good ruthenium compatibility of PlanarCleantrade; and PlanarCleantrade;AN was confirmed by a major fab customer. Continuous work is carried out to further improve cleaning performance and materials compatibility based on additional customer needs.

Ultralow-k (uLK) spin-on dielectrics (SODs) will likely be used for CMOS nodes below 20 nm. Nodes currently in development (16 nm and smaller) may require SOD k values lower than 2.0. In addition the CMOS industry wants to reduce BEOL process temperatures, and would prefer to cure SOD films below 400 °C.
We report the results of our investigations of k ~ 1.8 SOD films and k ~ 1.8-2.2 SOD films cured at temperatures cooler than 400 °C. Significant influences on material properties include organic functionalization of the silica monomers in the SOD, and the thermal sequence between spin and final cure. Of particular interest are the balance of alkyl and aryl functional groups, as well as the ratio of bridging (Si-R-Si) to terminal (Si-R) groups. Small changes in these ratios yield substantial effects on the k vs. [porogen] curve, as well as parameters that affect integration such as film modulus, hardness, wet etch rate, ash resistance, pore size distribution, water contact angle, and adhesion to the etch stop layer. The relationships between these film properties and film composition and thermal history will be discussed.

A fundamental understanding of electronic transport in low-k materials is of great interest as these material are utilized in inter layer dielectrics in integrated circuits. In this study we explore the link between electronic transport and defect structure in a leading family of low k materials, those based on SiOC:H. We utilize electron spin resonance (ESR) via conventional and fast passage measurements as well as electrically detected magnetic resonance (EDMR) via spin dependent trap assisted tunneling (SDT). We have also explored electronic transport as a function of field and temperature. We have made both conventional EPR and EDMR measurements on multiple material systems based on SiOC:H with dielectric constants ranging from 2.0 to 3.9 with various compositions of Si, O, and C. We observe multiple defects including E&’ centers, silicon and carbon dangling bond centers, and -SiH3 radicals. Our results provide strong evidence that these defects play important roles in determining electrical leakage. Of potentially greatest interest, EDMR measurements made over time at relatively high fields in some low -k films may provide some fundamental physical understanding of an important reliability phenomenon, time dependent dielectric breakdown (TDDB). We observe time dependent changes in EDMR which may be linked to TDDB phenomena. Measurements of leakage currents versus temperature in some of these films are consistent with the expression σ=A*exp (-B/Tn) where A and B are constants and n is, equal to or less than .5. This result is consistent with variable range hopping transport.

Highly porous ultra low dielectric constant organosilicate glasses (OSGs) are being integrated as back-end-of-line (BEOL) interconnect dielectrics . These porous OSG&’s are commonly deposited by plasma enhanced chemical vapor deposition (PECVD) of a structure former, such as DEMS® precursor (diethoxymethylsilane), together with a porogen, such as ATRP (alpha-terpenine); followed by UV exposure to remove the sacrificial porogen. In an effort to better control the structural framework and the nature of the pores in these OSGs, alternative structure formers (ASFs) with bulky organic groups bonded directly to the silicon atom in order to facilitate incorporation of potentially smaller porogens into the framework have been reported earlier (1). In this context, this paper further builds on the relationship between the porosity and its impact on film properties for ASF-based OSG films. The percent porosity and pore interconnectivity of these films were measured by ellipsometric porosimetry (EP) and positron annihilation spectroscopy (PALS) respectively. Porosity and pore-size distribution for films deposited using several different types of bulky organic groups were examined using EP in an effort to understand the impact of the chemical nature of the precursor on pore morphology. While smaller average open pore sizes are feasible with ASFs, PALS shows that larger pores are also present. A qualitative correlation was observed between shrinkage and porogen removal post UV cure, and the total porosity did not exceed 20%. Therefore ultra low k values were not obtained. Earlier work had demonstrated that addition of a separate porogen (ATRP) to the ASF led to lower k values; and further addition of DEMS® precursor increased mechanical strength (1). For these DEMS®/ASF/porogen films, changing the porogen had a larger impact on film properties than changing the ASF. When the cured films are subjected to plasma damage as might be experienced during integration followed by a dilute HF dip; the thickness of the layer removed (proxy for extent of damage) did not correlate strongly with the open pore size; but showed some correlation to total porosity. These results confirm that film structure and composition continue to play a dominant role in highly porous OSG films. (1) I.J Hsu et al.; MRS 2012 talk and online proceedings library Vol 1428 , Jan 2012; pp mrss12-1428-c01-10

The development of stable low-dielectric-constant (i.e., low-κ) materials for intra/interlayer dielectrics (ILDs) and diffusion barriers/etch stop layers in ultra-large-scale integrated circuits has become an essential target for the semiconductor industry. Toward this end, several low-Z boron nitrides and boron carbonitrides have been investigated and have demonstrated favorable κ values on the order of 2-3, but have been limited for ILD applications due to film adhesion and environmental instability issues. Amorphous hydrogenated boron carbide (a-B_xC:H_y) may turn out to be another class of promising low-κ boron-based materials, boasting low-Z, low-polarity constituents (B-C bonds and hydrocarbon chains), but with potentially greater adhesion and environmental stability. In particular, a-B_xC:H_y films grown by plasma-enhanced chemical vapor deposition (PECVD) from carborane precursors exhibit tunable properties of interest, including a range of hydrogen content (5-50 at. %), densities (0.8-2.5 g/cm³), bandgaps (2-4 eV), Young&’s Moduli (200-500 GPa), and—importantly—resistivities in excess of 10¹² Omega; cm, essential for low leakage current. For any material to be considered as a low-κ ILD, it has to meet a stringent set of integration requirements. Meeting these will depend on a combined matrix of dielectric, electronic, chemical, and mechanical properties. Therefore, the ability to correlate material properties and growth parameters will ultimately lead to the optimization and maturation needed to establish a material for low-κ ILD application. This talk will describe the correlations and causal connections between the experimentally measured properties of a-B_xC:H_y films—including dielectric constant, bandgap, Urbach energy, defect density, resistivity, leakage current, breakdown voltage, hardness, Young&’s Modulus, void volume, density, B/C ratio, hydrogen and oxygen content, film stress, environmental stability and chemical etch selectivity—as a function of the PECVD growth parameters (power, pressure, substrate temperature, growth time and precursor gas flow/ratio) in the context of determining whether a-B_xC:H_y meets the grade as a next-generation low-κ material.

Nowadays, scaling of ultra-large-scale integrated circuits requires mechanically robust materials with ultra-low dielectric constant (k-value) [1]. The reliability requirements of low-k dielectrics address many factors, as for example outstanding fracture and adhesion properties and the ability to withstand both intrinsic device stresses and thermo-mechanical stresses of packaging, among others. An often used way to decrease the k-value is by increasing the film&’s porosity. Therefore, it is crucial to understand the intrinsic effect of porosity on the mechanical and fracture properties of porous low-k dielectrics. From the experimental point of view, studying the intrinsic effect of porosity in porous low-k dielectrics is complicated because of the difficulty to control porosity and matrix properties separately [2, 3] and because in case of porous materials the measured elastic modulus is an effective elastic modulus, which depends on the stiffness of the matrix, film porosity, pore structure, among others. In this work, we demonstrate the intrinsic effect of porosity on mechanical and fracture properties of PECVD ultralow-k dielectrics using an alternative curing process that allows a separate control of porosity and matrix properties [4, 5]. Mechanical properties of the films are studied with different techniques including laser-induced surface acoustic waves [6], ellipsometric porosimetry [7] and nano indentation using different tip geometries (berkovich, cube corner, sphere). Fracture strength and interfacial adhesion was studied using the four-point bending technique. The stiffness results show that the microstructure evolves with increasing porosity, from a structure containing mesopores interconnected with microporous channels at porosities below 25%, to one with heavily interconnected mesopores at higher porosity levels. The fracture energy decreases linearly with increasing porosity, consistent with a planar through pore fracture mechanism.
[1] K. Maex, M. R. Baklanov, D. Shamiryan, F. Iacopi, S. H. Brongersma, Z. S. Yanovitskaya, J. Appl. Phys. 93 (11), 8793-8841 (2003).
[2] A. Grill and V. Patel, Appl. Phys. Lett. 79, 803 (2001).
[3] A. Urbanowicz, K. Vanstreels, D. Shamiryan, S. De Gendt and M. R. Baklanov, Electrochemical and solid-state letters 12 (8), H292-H295 (2009).
[4] A. M. Urbanowicz, K. Vanstreels, P. Verdonck, D. Shamiryan, S. De Gendt, and M. R. Baklanov, J. Appl. Phys. 107, 104122 (2010).
[5] A. M. Urbanowicz, P. Verdonck, D. Shamiryan, K. Vanstreels, M. Baklanov, and S. De Gendt, Fabrication of porogen residues free and mechanically robust low-k materials,” U.S. patent No. 20110006406 (2011).
[6] D. Schneider, P. Siemroth, T. Schülke, J. Berthold, B. Schultrich, H. H. Schneider, R. Ohr, B. Petereit, and
H. Hilgers, Surf. Coat. Technol. 153, 252 (2002)
[7] K. P. Mogilnikov and M. R. Baklanov, Electrochemical and Solid-State Letters, 5 (12) F29-F31 (2002).

A new class of porous pSiCOH dielectrics made by PECVD for high performance VLSI interconnects is introduced and characterized here. One unique feature is inclusion of a high concentration of Si-CH2-Si bonding in combination with a Si-O bond skeleton. At a given k value, these materials have higher modulus by a factor of 1.2 to 1.3X and a plasma damage that is lower compared to the widely used Si-O based interconnect dielectrics. Having studied k values from 2.3 to 2.6, we will discuss physical properties of these materials as a function of k value. Measurements on thin films will be presented that help predict success when the porous dielectrics are integrated in copper damascene interconnects. Finally, integration will be examined in 40 nm line and space damascene structures.

Plasticity in films plays a crucially important role in the adhesion of interfaces in microelectronic interconnects. While it&’s possible to toughen interfaces with embedded Cu metal [1] and polymer films, both have significant limitations. Cu metal films become “hard” at small length scales in microelectronic interconnects, and polymers are mostly too soft and have poor thermal stability.
Here, we show how remarkable toughening can be achieved with ceramic-like amorphous silicon carbide (a-SiC:H) films. They plastically deform and have outstanding thermal stability (up to ~400oC). We demonstrate strategies for using these films even at the nanoscale where Cu metal films would exhibit strong size-dependent plasticity and provide no toughening. Adhesion energy (1.6 J m-2) at an interface between low-k dielectrics (k=2.5) and silicon carbon nitride was dramatically increased by more than multiple times because of the plasticity contribution from the ceramic-like a-SiC:H films. The films can be processed with existing PECVD platforms, making them appealing to current and emerging nanoscience and energy device technologies. To our knowledge, this is the first time that such significant toughening has been achieved at the nanoscale with very thin and thermally stable ceramic-like films. The multi-functionality and ease of processing of the films has the potential to open new avenues for mechanical reliability of nanoscale device structures.
[1] Lane M, Dauskardt RH, Vainchtein A, Gao HJ. Plasticity contributions to interface adhesion in thin-film interconnect structures. J Mater Res 2000;15:2758.

Nanoindentation is commonly used to evaluate the mechanical properties of hardness and elastic modulus on low dielectric constant thin films. While there are general guidelines for conducting nanoindentation tests, there are no widely employed standards for testing thin films. Test labs and research facilities are using a large array of different test parameters and analysis techniques for evaluating properties of elastic modulus and hardness on low-k films. In this presentation, the effects of test parameters - such as loading rate, relaxation hold time, strain rate, harmonic oscillation size, and tip radii - on nanoindentation results will be analyzed for a new class of low-k thin films using quasi-static and Continuous Stiffness Measurement (CSM) indentation techniques. In addition, results from Oliver-Pharr, thin film modeling, and Hertzian analysis techniques will be compared. In the absence of a widely accepted standard for testing low-k films, understanding the influences of test parameters, variables, and analysis techniques on the measured mechanical properties is critically important when comparing results supplied by different vendors.

A new ultra low-k dielectric intended for spin coating was developed basing on new class of new fluorinated aromatic polyimides (PI) combined with polyoxometallates (POM) -the inorganic nanoclusters having high porosity. The oxometallates were introduced directly into the polymer chain and the ratios up to 20 wt.% of oxometallate groups in composite were obtained
The resulting PI-POM composites are dissolved in common organic solvents, possess good film forming properties and exhibit dielectric constant value as low as 1.7 (1 MHz)at densities 1.5 g/cm³.
To obtain the ultra-low-k dielectrics basing on so-obtained PI-POM composites, they were treated in supercritical CO₂ optimizing saturation pressure, saturation temperature and foaming temperature. In the process of CO₂ dissolution by polymer and following evaporation the highly porous structure is obtained, with the pore size critically depending on three mentioned parameters.
The PI-POM films which undergone CO₂ treatment were highly porous,with the density decreaing down to 0.9 g/cm³ and possessed the k value as low as 1.31, pertaining reasonable mechanical and thermal properties. The films developed in the frame of this study are intended for spin coating deposition in copper based ULSI interconnects and fit well into ITRS requirements on ultra-low-k dielectrics. The high content of inorganic clusters in polymer backbone promises higher stability of these films, comparing with full polymer based and thus closer to PECVD-obtained films. It is anticipated, that POM content can be further increased if it appears to be necessary for long term stability.

Electrical leakage in low-k/Cu interconnect structures is a growing, vital concern as the nano-electronics industry moves to sub-16 nm technology nodes and continues to implement new materials with increased porosity and lower dielectric constants. In order to understand the various possible leakage mechanisms in low-k/Cu interconnects, knowledge of the band gap and defects states in low-k dielectrics is needed but has gone mostly unreported in many cases. In this regard, we have utilized Reflection Electron Energy Loss Spectroscopy (REELS) to determine the band gap of both non-porous and porous low-k dielectric inorganic silicate materials. We demonstrate that for most cases, the band gap of these materials is consistent with that of SiO2 and > 8 eV. However in some cases, we have observed that the REELS analysis can be complicated by the existence of defect states within the band gap of these materials. While troublesome for band gap measurements, we demonstrate that this sensitivity can be utilized to determine the energy level of various defects in pristine and sputter damaged low-k SiOC:H dielectrics and in some cases identify the chemical identity of the defect. The energy level for the observed defects are consistent with surface Si dangling bond defects previously observed on single crystalline SiO2 Quartz surfaces. The implications to electrical leakage paths and reliability in low-k/Cu interconnects will be discussed.

Low-k dielectric films can be substantially damaged during plasma processing. High energy UV and VUV photons emitted by plasma play the key role in damaging the porous low-k films directly or indirectly by stimulating chemical reactions with radicals in plasma and plasma afterglow. The different ULK samples (k: 2.0-2.2, porosity: 30-50%, pore radius: 1-2 nm) were studied by exposing to five radiation sources at various wavelengths (VUV: 193 nm, 147 nm, 104-106 nm, 58.3 nm, and EUV: 13.5 nm). Time-spatial behavior of the ULK damage as a function of photons fluence was studied by FTIR spectroscopy and XRF analysis. It is shown that the degree of damage depends on wavelength of UV light. The major UV damage was observed at the wavelengths below 193 nm. The maximum damage corresponds to 147 nm while the degree of damage at 58.3 nm was much smaller. In the case of organosilicate (OSG) based ULK materials, the degree of damage, as a rule, increases with porosity. Organic low-k materials are damaged more than OSG at 193 nm, but at shorter wavelengths (147, 106, 58.3 and 13.5 nm) they are more stable than OSG. One-dimensional model for radiation absorption and dynamics of CH3 group destruction in ULK films was developed. The cross-sections of photons absorption and photo-stimulated Si-CH3 bond breaking in ULK films for 13.5 -147 nm wavelength range were derived from a combined experimental and modeling study. The obtained values allow to simulate the VUV/EUV induced modifications of low-k materials with different composition, to understand better the mechanisms of plasma damage and to generate ideas for controllable modifications of low-k materials.

Package-induced failure for BEOL interconnects in sub-45nm technology nodes has drawn attention to the great silicon and packaging integration challenges introduced by the weak mechanical properties of ULK-containing metallization elements. Empirical data and modeling studies for a range of silicon and packaging factors at 20nm node reveal fundamental insights into susceptibility to damage and approaches for recovery. Analysis of increase in degradation as BEOL layouts evolve to finer dimensions leads to understanding of changes needed to enable continued device scaling.

The key features are bumpless interconnects for the three-dimensional (3D) integration including vertical wiring without bumps for Chip-on-Wafer (COW) and Wafer-on-Wafer (WOW) as a second-generation alternative to the use of micro-bump. Wafer-based 3D technologies are the fabrication of three-dimensional structures in which any number of thinned 300 mm wafers can be stacked back-to-front realizing further large-scale devices with low cost instead of the scaling using extreme ultraviolet (EUV) lithography which will be expected at 18~22 nm and beyond.
The two-dimensional (2D) scaling based on planar technology that has led the semiconductor industry so far no longer makes economic sense in many situations. For instance, the industry is facing a major turning point in how to realize the next generation of large-scale integration. In this context, 3D approaches have been proposed on the basis of next-generation 2D transistors and 3D architectures, and recent attention has focused on productivity and the costs involved in volume production. WOW is the third-generation replacement for Chip-on-Chip (COC) technology and is also applicable to wafer-based COW. Stacking at the wafer level drastically increases the processing throughput, and bumpless interconnects provide an appropriate yield using existing technology which is equivalent to or greater than that achievable with 2D scaling beyond 22 nm nodes. Also, since it is compatible with existing wafer processing facilities, transistors with three-dimensional structures can be designed in a continuous manufacturing line.
In combination with 3D logic, memory, and cooling devices, it is possible to construct a roadmap towards high-density integration, low power consumption, and miniaturization of 3D chip-sets, especially next-generation logic-memory stacks for personal digital assistants (PDAs) such as Smartphones and high-end servers. Because wafer thinning to 10 mu;m or less provides small features, it is possible to realize a total 3D stack height of less than 500 mu;m, even after stacking seven dies. This satisfies current package standards. In addition, stacking 32 or more layers of 16 Gb/cm^2 devices fabricated by 22 nm technology, which is two generations ahead, would achieve terabit (Tb) capacity.
From the viewpoint of a technology roadmap, the issues of scaling technology and technology for fabricating three-dimensional structures are often discussed separately. However, these two technologies are not always mutually exclusive. Scaling and wafer enlargement to 450 mm will be relieved of the stringent requirements by using 3D high-density integration combined with mass production. In other words, a sufficiently long learning period can be ensured and further cost reductions for 45 nm to 22 nm nodes are expected by minimizing process validation and the number of critical layers.

To fabricate a highly-reliable Cu/glass structure has been required for electric devises, however the Cu/glass structure has generally a low adhesion strength. In order to overcome this problem, we inserted an Os oxide, which has a slightly larger standard free energy of oxide formation than SiO2, and a Ni, which is miscible in Cu at all composition ratios, as adhesion layers between glass substrate and Cu film in the present study. Adhesion strength of the Cu/Ni/OsOx/glass structure was investigated and relationship between adhesion strength and interfacial microstructure was examined. Effect of the annealing treatment on adhesion strength was also investigated and interfacial reaction such as diffusion behavior is discussed.
A 10 nm thick OsOx layer was deposited by sputtering method. Depositions of Ni and Cu films were carried out in a supercritical CO2 solution from each complex via hydrogen reduction. The obtained structure was annealed at temperature of 573 K for 30 min. Adhesion strength was evaluated by using a scratch tester. Microstructural observations and analyses were mainly examined by using a scanning transmission electron microscope.
At first, we prepared a Ni/OsOx/glass structure. Nano-sized rod-shaped grains were observed at Ni surface. Surface roughness of the Ni surface was 12.4 nm. Adhesion strength was similar to that of glass/Cu. When the Ni/OsOx/glass was annealed (hereafter Ni(anneal)/OsOx/glass), equiaxed Ni grains with about 100 nm diameter were obtained. Smooth surface with surface roughness of 8.2 nm was also formed at the Ni surface. Adhesion strength of the Ni(anneal)/OsOx/glass was extremely higher than that of the Ni/OsOx/glass and glass substrate was fractured before delamination. This indicates that the annealing treatment benefits increment of adhesion strength for the Ni/OsOx/glass.
We prepared four Cu/Ni/OsOx/glass structures such as samples which deposited Cu film on a Ni/OsOx/glass and a Ni(anneal)/OsOx/glass (hereafter Cu/Ni/OsOx/glass and Cu/Ni(anneal)/OsOx/glass, respectively), samples which annealed a Cu/Ni/OsOx/glass and a Cu/Ni(anneal)/OsOx/glass (hereafter Cu(anneal)/Ni/OsOx/glass and Cu(anneal)/Ni(anneal)/OsOx/glass, respectively). Delamination by scratch tester occurred at OsOx/glass interface in all samples. Adhesion strength of the Cu/Ni/OsOx/glass and Cu(anneal)/Ni/OsOx/glass was lower than that of the Cu/Ni(anneal)/OsOx/glass and Cu(anneal)/Ni(anneal)/OsOx/glass. This indicates that the annealing treatment benefits increment before Cu deposition. Cu atoms were observed in Ni film in all samples, suggesting that high adhesion strength of Cu/Ni interface is due to Cu diffusion into Ni film. Cu atoms and Si atoms existed in OsOx layer in Cu/Ni(anneal)/OsOx/glass and Cu(anneal)/Ni(anneal)/OsOx/glass but scarcely existed in Cu/Ni/OsOx/glass and Cu(anneal)/Ni/OsOx/glass. These Cu and Si diffusion into OsOx layer are considered to result in high adhesion strength of Cu/Ni/OsOx/glass structure.

Through-silicon via (TSV) offers continued performance enhancement and increased functionality for electronic devices without the need of further scaling, which has become increasingly difficult and expensive. The implementation of the TSV technology requires a comprehensive understanding of the properties of TSV materials, including the oxide liner for electric isolation and the copper diffusion barrier. These materials have to be deposited onto challenging TSV topologies and endure the harsh subsequent process conditions, yet they are expected to provide adequate structural support and electrical protection. We report our investigation on TSV structures with different liner and barrier combinations through spectrometric and electrical characterization. Specifically, arrays of 5×50 mu;m TSVs with different inter-via spacing are studied at the wafer level. Titanium and tantalum barriers are compared using secondary ion mass spectrometry (SIMS), transmission electron microscopy (TEM), and electron energy loss spectroscopy (EELS). They exhibit different characteristics with the oxide liners tested, which include high-aspect-ratio process (HARP) oxide and proprietary ozone/tetraethylorthosilicate (TEOS)-based CVD oxides. Capacitance-voltage (C-V) and current-voltage (I-V) measurements are also performed to evaluate film quality in terms of deposition uniformity, breakdown, and leakage. Good fabrication process control is maintained across the wafer, as demonstrated by the tight distribution of parametric results.

Power consumption and dissipation during electrical operation lead to temperature rise in the package. Elevated temperature in the package structure induces thermal mechanical stresses which impose reliability risks. Robust and reliable package design for power systems requires comprehensive analysis of system electrical, thermal and mechanical behaviors. This paper presents a self-consistent approach for package reliability analysis with coupled electrical-thermal and thermal-mechanical modeling.
A high power dissipation density in power systems is very important to analyze the electrical and thermal management. In this paper, the switching losses of Unclamped Inductive Switching (UIS) system including power MOSFET are simulated in mixed-mode TCAD tool and then the power dissipation of MOSEFET in UIS system is transferred to package system as an input boundary condition. The heat flux is communicated between electrical contact in MOSFET and thermal contact in package. Finally 3D thermal equation for package structure is solved self-consistently with coupled electrical-thermal modeling. To get the accurate switching losses, the TCAD calibration for power MOSFET, which has temperature-dependent electrical behavior with lumped elements, is essential. In this approach, the electrical behavior of power MOSFET and thermal distribution of package would be analyzed to optimize the process/device characteristics of power devices and package - heat sink structures in static and dynamic modes.
Once the system thermal behavior is characterized by the coupled electrical-thermal modeling, the coupled thermal-mechanical modeling is then performed to obtain the corresponding mechanical stress cycles during operations. The mechanical stress cycles impose several reliability risks, including cracking, delamination, plastic damage and fatigue. These reliability risks are driven by the local maximum principal stress, the interfacial traction, Von Mises effective stress, and the magnitude of the stress cycles. In this study, our self-consistent approach allows seamless transition of temperature distributions obtained from the coupled electro-thermal modeling directly into the thermal mechanical modeling employing the identical package structure. The resulting mechanical stress distributions are further analyzed for reliability assessments. All possible failure modes are examined. It is demonstrated that a coupled electro-thermal and thermal-mechanical modeling methodology is essential for package reliability analysis in power systems.

The presence of copper oxides has severe implications on the adhesion, moisture sensitivity and stress migration of Cu/epoxy bondlines in advanced packaging. To lower costs, packaging technologies must rely solely on organics for bonding and barrier function but face severe challenges inhibiting Cu migration especially as scaling necessitates finer pitch and line spacings. Multi-process and multi-layer solutions exist, however, the costs to implement these solutions on the package are prohibitive.
Previous attempts to improve Cu/epoxy adhesion have relied on methods such as plasma treatment to control the formation/structure of the Cu-oxide and the use of amino-silanes or thiol-based adhesion promoters. These methods have achieved limited success improving moisture sensitivity and preventing Cu stress migration. In this work, we introduce a new concept involving a novel low-cost sol-gel synthesis route used to deposit a graded hybrid ZrOx/epoxysilane film capable of acting both as an adhesion layer for Cu/epoxy interfaces as well as a barrier film that prevents moisture degradation and Cu migration. By forming a dense interconnected molecular network of organic and inorganic molecular components in a reducing acidic solution, we can simultaneously reduce the Cu-oxide, obtain high bond density with the reduced Cu surface, and deposit a new hybrid surface with epoxy ring functionality for bonding to adjacent epoxies.
Hybrid reinforced Cu/epoxy bondlines will be presented, demonstrating a viable low-cost technique for improving adhesion four-fold in emerging packaging technologies. By measuring debond growth rates in high humidity environments, we will demonstrate how the dense transition-metal oxide in the graded hybrid structure can act as a barrier layer capable of inhibiting moisture-assisted debond phenomena in these bonded structures. The efficacy of these hybrid films in mitigating stress migration at the Cu/hybrid interface will be addressed.

Wafer level metal bonding involving copper material is widely used to achieve 3D functional integration of ICs [1] [2] and ensure effective packaging sealing for various applications [3]. In this paper we focus on thermocompression bonding technology where temperature and pressure are used in parallel to assist the bonding process. More specifically a broad range of conditions was explored and unexpected results were observed and are reported. Indeed, despite a relatively high roughness, the presence of a native oxide and the lack of surface preparation, there still exists a process window where wafer level bonding is allowed. In these conditions limiting the bonding mechanisms to basic copper diffusion is no longer satisfactory. To understand the way the bonded system overcomes the coarse initial state to permit the sealing of the interface, 200mm silicon wafers with 1µm-copper layer obtained by electro-chemical deposition were prepared. Grain size, surface metal oxide and mechanical properties of the bonding layer were characterized by respectively XRD, ellipsometry and nanoindentation measurements. Shearing stress tests coupled to bonding interface inspection were performed for process temperatures going from room temperature to 400°C and applied forces going from 3000N up to 90kN. In addition, for specific process conditions, acoustic microscopy, EDX analysis and TEM cross section observations were used to bring out details on copper interface closure.
In this study, the asperity contact model, first introduced by Hertz et al. [4] to describe silicon oxide direct bonding and subsequently extended by Johnson et al. [5] and Ventosa et al. [6], shows its limitations. Therefore a specific scenario inspired by both wafer bonding and metal welding state of the art is put forward. Accordingly, pure copper diffusion through the bonding interface [7] is lined with plastic deformation and metallic oxide fracture [8]. In addition, polycrystalline film deformation due to thermomechanical stress is highlighted and recrystallization [9] and power-law creep [10] are observed and confirmed. Based on these models the functional process windows are explained and some examples will be disclosed in the final paper.
[1] GUEGUEN P. et al., J. Electrochem. Soc., 156(10): H772-H776, 2009
[2] TAIBI R. et al., Electron Devices Meeting (IEDM), p. 6.5.1 - 6.5.4 , 2011
[3] FAN J. et al., J. Micromech. Microeng., Vol 22 (105004), 2012
[4] HERTZ H., Journal Reine Angew. Math., Vol 92, 1881
[5] JOHNSON K. L. et al. ,Proceeding of the Royal Society of London A, Vol 324, pp 301-313, 1971
[6] VENTOSA C. et al., J. Appl. Phys. 104, 123524, 2008
[7] CHEN K. N. et al., Journal of Materials Science, Vol 37, No 16, pp3441-3446, 2002
[8] MOHAMED H. A. et al., Weld. J. (Miami), p 302-s, 1975
[9] HUMPHREYS F.J. et al., Pergamon, Oxford (1995)
[10] MADE R. I. et al., Acta Materalia, Vol 60, pp 578-587, 2012

Wireless communications such as those in cell phones are utilizing increasing chip design complexity. For example analog mixed-signal chips can contain RF capability which requires integrated inductors [1,2]. High performance RF designs are enabled by the use of thick copper and aluminum wires (>3um). In particular, the quality factor of the inductor, which is the ratio of magnetic stored energy over average dissipation, is dependent on the metal thickness. High quality factors, can be achieved by using thick Cu inductors. In some applications, the total thickness of Cu in the inductor can be as much as 12 um.
The fabrication of thick Cu layers is in many ways easier than that of thin Cu layers. For example, there are no limitations in terms of lithography or liner and seed layer thickness. However, there are still challenges with fabrication due to stress. Cracking of the dielectric can occur, due to the mismatch in coefficient of thermal expansion between Cu and SiO2, and due to the thick Cu layers in the inductor stack. Both the layout and the processing must be optimized to ensure that cracking does not occur.
This paper will discuss current applications, inductor design, and the reliability challenges and solutions associated with thick Cu interconnects.

The adhesion of polymeric materials to inorganic substrates is of critical importance in flip chip and emerging 3D packing technology. In these applications, delamination of epoxy layers from passivated silicon die substrates can lead to package failure. It is well known that the synergistic effects of mechanical stresses, temperature cycling, and moisture can significantly weaken the adhesion of such epoxy-silicon interfaces. As a result, the epoxy tends to fail adhesively with significantly lower fracture energy compared to the cohesive fracture energy of the epoxy layer. Even in the presence of well-known silane adhesion promoters, epoxy-silicon interfaces are known to be susceptible to moisture-assisted debonding.
Previous research has demonstrated the effects of introducing micro and nano sized particles into epoxy resins to adjust thermal expansion and elastic properties. The effects of such additions have also been explored on strength and fracture resistance. The role of such particle additions on the resistance to moisture assisted adhesive or cohesive cracking, however, has received less attention but is critical for package performance.
We demonstrate techniques to quantitatively measure the kinetics of moisture assisted cracking in epoxy resins containing a wide range of filler particle additions, from core shell particles to nanometer sized silica. With the introduction of filler particles into a bisphenol-F-based resin, the fracture energy at the epoxy/Si interface was increased compared to the unfilled epoxy/Si interface. We then report on the moisture-assisted debonding kinetics in controlled humidity and temperature environments, including those typically employed for accelerated testing. At elevated temperature and humidity, commonly used bisphenol-F based underfill epoxies exhibit the absence of a debond threshold, resulting in continued growth of defects even at very low loads. With reaction kinetic models, we show how we can account for these environmental effects, which could lead to more reliable 3D structures and microelectronic packages.

Production of stacked silicon packages with through-silicon vias (TSV) requires thin wafer handling, which is commonly accomplished by temporary bonding or wafer support systems (WSS). A problem with current WSS is that processes following the attachment of a WSS must be performed at temperatures ~ 250 degree C or below, while conventional polyimides for passivation should be cured at above 300 degree C for several hours. One solution for this problem is to employ newer materials such as low-temperature polyimides or high-temperature temporary adhesives, but the reliability data are often limited and their mechanical and electrical performance may be significantly different from those of the established materials. A better solution is to find an alternative method to process the established polyimides at a low temperature. In this study, we demonstrate that microwave energy can successfully cure conventional high-temperature polyimides at low temperatures compatible with temporary bonding materials within a relatively short time. A low-CTE (coefficient of thermal expansion) polyimide PI 2611, one of the candidate dielectric materials for Invensas&’s silicon TSV interposers, was cured by variable frequency microwave (VFM) technique by Lambda Technologies. This technique induces fast movement of dipoles in uncured polyimide chains and efficiently accelerates full imidization, while fast sweeping of microwave frequency eliminates any possibility of arcing between metal components. We controlled the microwave-induced temperature at the PI 2611 films to remain at around 200 degree C, which is substantially lower than the standard oven cure temperature of ~ 375 degree C. Fourier-transform infrared (FTIR) indicated that the extent of imidization became very high in several minutes and approached 100 % within 90 minutes. We will show the process compatibility, polyimide modulus, chemical-mechanical polishing rate, electrical properties, and wafer- and die-level warpage in test structures for the Invensas silicon interposer. Low-temperature processing and good CTE match result in a low warpage, which can provide a wider process window for stacked silicon package assembly. We will also discuss the imidization mechanism under microwave in comparison with the standard convection model.

At the scale of sub-20 nm features, line undulation and pattern collapse in ultralow-k dielectrics are two of the most challenging problems facing BEOL fabrication. Line undulation (wiggling) results when the strength of the ILD (Inter-Layer Dielectric) being patterned is not able to withstand the intrinsic stresses of the sacrificial dielectric and/or metal hardmasks required to form small features. Modeling of the forces associated with line undulation depends on the accurate description of the mechanical properties of all the materials in the integrated stack. However, the patterning process and integration scheme used to form trenches and vias can change the mechanical properties of both the ILD and the hardmasks, severely limiting the ability to predict the onset of line undulation.
Pattern collapse, another failure mechanism associated with the patterning of small dimension features, occurs during wet clean processing. BEOL wet processing must remove post-etch polymer residues, be compatible with dielectric materials that continue to scale k-value at the expense of mechanical strength and also be compatible with Cu and the other metals on the wafer used for liners or caps. Pattern collapse has been associated with high aspect ratio's, non-uniform drying, surface tension, and low dielectric material strength. Models used to describe this phenomenon in resist have been applied to patterned ILDs. However, the resist model is not as applicable to patterned low-k dielectrics because the absence of material interfaces, the presence of sidewall polymer residues and degraded mechanical properties of the ILD as a result of plasma processing.
In this presentation, we focus on the issues facing BEOL patterning that are specific to the problems created by small features. A process flow used to create sub-20 nm features will be described and within this context, many of the parameters which were found to either enhance or mitigate line undulation and pattern collapse will be discussed. As demonstrated by the ability to create a wiggle and collapse-free pattern, it is clear that as the semiconductor industry transitions from process development to manufacturing, maintaining pattern fidelity is one of the biggest challenges facing continued scaling.

The interconnect structures of VLSI devices include dielectric Cu caps which are barriers to inter- and intra-level Cu diffusion in the interconnect dielectric and barriers to oxygen or humidity penetration to the Cu wiring. Robust caps are required to maintain the reliability of the VLSI circuits. The dielectric caps contribute to the capacitance of the interconnect stack and, having dielectric constants larger then the interconnect ILDs, they increase the total capacitance of the interconnect. In the quest to reduce the power consumption of the microprocessors and minimize the signal delays, the capacitance has to be minimized as much as possible. Towards that goal, the dielectric constant of the Cu cap needs to be reduced, especially for the latest technology nodes, where the thickness of the caps does not scale at the same rate as the rest of the dimensions. The thickness scaling of the cap is prevented by the need of maintaining the requirements of the cap such as good barrier to Cu diffusion, etch selectivity, strong adhesion to Cu and ILD, oxidation resistance, and robust mechanical properties. The first reduction of the dielectric constant of the Cu cap was introduced at the 90 nm node when C was introduced in SiN (k~7) to create SiCNH (k~5.2) caps. As the metallization pitch decreases, further reductions in cap thickness and/or k are required, while maintaining it properties mentioned above.
The paper presents the development of advanced caps comprising various ultrathin single and multilayers of SiCNH and SiN and will discuss their properties and their impact on the reliability of the interconnect stacks, as well as their effects in reducing the capacitance of the stacks. A new in-situ integrated preclean/selective CVD Co/dielectric cap process will also be presented as the next generation cap candidate, with strong potential of improving electromigration reliability.
Acknowledgments: This work was performed by Alliance Teams at various IBM Research and Development Facilities.

A thin diffusion barrier is desirable to prevent copper diffusion into the dielectric layers and silicon channel in MOS ICs. In general, a good barrier should have low resistivity, be thermally stable, and as thin as possible with good barrier properties. Examples of common diffusion barriers are Ta, TaN, and TiN. These materials are polycrystalline, and they typically fail from Cu diffusion through the grain boundaries, which serve as fast diffusion paths. Alternately, amorphous materials provide an advantage by eliminating the grain boundaries. In fact, it has been shown that amorphous Ta is a better barrier than nanocrystalline Ta. Several amorphous or “near-amorphous” diffusion barriers have been proposed and appear to be effective barriers. However, these either have too high resistivity, are not really truly amorphous, or require relatively thick films in order to be adequate barriers. In general, the high concentration of non-metal elements helps in amorphous phase stabilization. As a result, good thermal stability often means high resistivity. Hence, very thin and truly amorphous barriers with good thermal stability and low resistivity need to be developed.
In this work, a Ta35W35Si15C15 amorphous diffusion barrier is studied. With an increased concentration of metal component, the TaWSiC thin film has a low resistivity of ~200 mu;Omega;-cm. Furthermore, having these four elements helps in good thermal stability in terms of staying amorphous during annealing. It has been shown previously that the TaWSiC film remains amorphous up to annealing temperatures as high as 1120°C. The TaWSiC film is further investigated in this work using XRD phase analysis, TEM cross-sectional images, and AES depth profiles. The results demonstrate its effectiveness in preventing Cu diffusion and maintaining structural integrity down to a very thin layer of 5 nm and up to annealing temperature of at least 550°C for 30 min. Copper silicide formation was observed at annealing temperature of 650°C and above. In comparison, a 5-nm thick nanocrystalline Ta barrier already fails at 550°C with copper silicide formation. In addition to being a good barrier, TaWSiC also enhances copper (111) texture even though TaWSiC itself is amorphous. As-deposited Cu on a 5-nm TaWSiC layer shows rocking curve FWHM of 6.3°. With a 600°C anneal for 30 min, the texture improves as FWHM reduces to 2.8°. In comparison, Cu directly on SiO2, even annealed at 600°C for 30 min, has a FWHM of 24.3°. This highly textured (111) copper is very desirable since it provides better electromigration resistance as well as better wetting of Cu on barrier materials. With it being truly amorphous, having low resistivity and good thermal stability with good barrier properties, and enhancement of (111) Cu texture, TaWSiC is a very promising candidate for future interconnect technologies.

LSI technology for 22 nm node and beyond needs ultra-low-k films having k-value below 2.1. In order to reduce the dielectric constant, porous low-k film is indispensable and widely studied. However, porous low-k film is sensitive to process-induced stimuli caused by plasma and metallization process, because such plasma or metals may diffuse via open pores of film. Therefore, the pores must be sealed to prevent diffusion of those species. Considerable efforts have been devoted to the development of pore seal layer or metal barrier which suppresses the diffusion of metals into porous low-k film.
Recently, we succeeded in fabricating ultra-thin (< 3 nm-thick ) layer on top of the surface of porous low-k which suppresses the diffusion of metal into porous low-k film and in discovering that the ultra-thin layer is stable after thermal cycle stress and bias stress. It was also reported that molecular structure of pore sealant determines the pore seal performance. In order to apply the pore seal layer in future ULSI Cu interconnect, the understanding how the species of plasma or metals is blocked by the pore seal layer or diffuse into the pore seal layer is highly important. However, it has not yet fully understood.
In this paper, we focus on understanding the relationship between the structure of the pore seal layer and pore seal property using toluene molecule as a probe of diffusion species with ellipsometric porosimeter. Pore seal layers were fabricated on porous low-k with the variation of thickness from 0 to 5 nm respectively by adjusting spin coating condition. Structural analyses were carried out by ellipsometry and so on. Critical parameters which determine the pore seal property will be discussed.

Barriers are important to protect low-k films from copper diffusion and moisture uptake. This barrier should be as thin as possible to reduce the resistance-capacitance (RC) delay while maintaining reliable performance. The intra-metal low-k materials are becoming more porous as the dielectric constant is decreasing below 2.3. Thus, it could be very challenging to seal the large open pores of a low-k film with a thin barrier. This paper focused on barrier integrity on ultra low-k (uLK) films with different porosities. According to previous studies, barrier integrity depends not only on the porous structure of a low-k material but also on its chemical composition, such as carbon content. We have used SiC and SiCN as dielectric barriers and TaN/Ta as metallic barrier in this paper. The barriers under study were deposited on top of three different uLK films with a pore radius varying from 0.8 nm to 3.2 nm and a dielectric constant varying from 2.5 to 1.8. By using the Ellipsometric Porosimetry (EP) technique and toluene penetration as a barrier integrity probe, we were able to find out how the critical thickness of the selected barriers changed with composition, porosity and pore radius of uLK films. By depositing SiCH barriers from dimethylsilacyclopentane (DMScP) in a PECVD reactor, we studied the effect of density on barrier properties. It was demonstrated that the low-density films (1.23 - 1.35 g/cm^3) with k-value 3.4 - 4.1 had poor barrier integrities, while the high-density films (1.62 - 1.86 g/cm^3) with k-value 4.5 - 5.8 were efficient as barriers against moisture penetration. The analyses showed that the barrier density had essential influences on barrier performance. The conclusions made in this paper can be useful to analyze the critical issues of future technology nodes.

As dimensions continue to shrink in back-end-of-line (BEOL) on-chip Cu interconnect structures by a factor of 0.7 with every new generation, the integrated circuit (IC) chips now have devices with dimensions in the tens of nm. The types of materials used and the profile dimensional controls of lines, vias and via chamfer have become increasingly critical to ensure time dependent dielectric break down (TDDB) and electromigration (EM) reliabilities. Low resistance Cu metallization and ultra-low dielectric constant k (ULK) dielectric materials are still the front-up for the 10 nm technology node and beyond. To ensure extendibility of Cu and ULK materials in Cu-BEOL applications, it&’s important to focus not only on process control and materials but also to examine the TDDB acceleration and EM scaling models being used and to fully characterize Cu metallization, ULK and capping materials. Several studies have shown that films with lower k (lower porosity) are easier to breakdown and the EM lifetimes decrease with every new CMOS generation. A film with a given k, porosity and carbon content can significantly affect TDDB performance. Given the aggressive top spaces expected for 10 nm and beyond, it is necessary to use accurate prediction models and to build in reliability margins by choosing robust dielectric and capping materials. As interconnect dimensions are scaled down, the fraction of copper atoms at interfaces and grain boundaries increases and the EM-induced void size that will cause interconnect failure decreases, reducing the Cu EM lifetime. In order to extend a reliable Cu interconnect technology to the 10 nm technology and below, the physical properties of Cu alloys/metal liners and ULK in the Cu damascene structures are important parameters to explore. In this talk, we will present the materials and scaling effect issues that are important to BEOL reliability, such as the effect of impurities, microstructure, liners and metal caps, etc. as they relate to the size effect on Cu EM and high-field/low-field TDDB testing for acceleration model comparison. In addition, the Cu line size effect on the Cu conductivity will also be presented.
This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities

We have studied electromigration (EM) at ultra-small metal junctions and investigated elementary processes of EM by introducing a novel spectroscopic approach. We observed successive step-like conductance drops by one quantum conductance G₀ (equiv; 2e²/h; e: the elementary charge, h: the Planck constant), which correspond to one-by-one removal of gold atoms, only when the junction voltage exceeded certain critical values. Surprisingly, the histogram of the critical voltage clearly showed a peak that is consistent with the activation energies for the surface self-diffusion process of metal atoms. Furthermore, it coincides with the activation energy for the mean time to failure (MTTF) of metal wires, which has been empirically determined from the reliability data. The result clearly indicates that the EM process at atomic-scale metal nanocontacts has a non-thermal origin and its elementary process is the surface diffusion of atoms induced by kinetic energy transfer from a single conduction electron to a single metal atom at grain boundaries [1-3].
By using nanogap electrodes fabricated by the electrical break junction method, we fabricated single molecular junctions with C60 molecules and measured the current-voltage (I-V) characteristics. Single C60 molecule transistors with ferromagnetic Ni source-drain electrodes exhibited a negative tunneling magnetoresistance (TMR) as large as -80 % [4], indicating realization of single molecule transistors with memory effects.
References
1. A. Umeno and K. Hirakawa, Appl. Phys. Lett., Appl. Phys. Lett. 94, 162103 (2009).
2. K. Yoshida, A. Umeno, S. Sakata, and K. Hirakawa, Appl. Phys. Express, 3, 045001 (2010).
3. S. Sakata, A. Umeno, K. Yoshida, and K. Hirakawa, Appl. Phys. Express, 3, 115201 (2010).
4. K. Yoshida, I. Hamada, S. Sakata, A. Umeno, M. Tsukada, and K. Hirakawa, submitted for publication.

Electrical current leads to a directed motion of atoms in metallic films, called electromigration. Our novel three-dimensional self-learning kinetic Monte Carlo model (SLKMC, Latz et al 2012 J. Phys.: Condens. Matter 24 485005) was used to study the anisotropy of electromigration-induced island and void drift on unpassivated surfaces of single crystal metallic films at the atomic scale. Depending on the combination of the surface texture and the direction of the applied electric field, the void or island drift direction is not necessarily aligned anti-/parallel to the electric field direction.
The SLKMC method combines the accuracy of rates calculated from a realistic potential with the efficiency of a rate catalog, using a pattern recognition scheme.
Excessive on-the-fly calculations of rates can be avoided by setting up an initial database, which can be done perfectly in parallel.
This work has been supported by German Science Foundation within SFB 616: Energy Dissipation at Surfaces.

Due to the shrinking dimensions of interconnects below their mean grain size, diffusion mechanisms inside the grains become more important for electromigration (EM). To investigate EM processes in different lattice configurations, we use well-defined Ag test structures as a model system. On a clean Si(111) surface, bi-crystalline Ag islands are formed by self-assembly. Such islands are a composition of a Ag(111) part - where the [111] direction is perpendicular to the surface - and a Ag(001) part - where the [001] direction is perpendicular to the surface. The two areas are separated by a single grain boundary (GB) [1]. Using focused ion beam (FIB) milling, the Ag islands are structured into wires [2]. During electrical stressing, the void development in time is captured in-situ with scanning electron microscopy (SEM). The movie of the SEM image sequence visualizes void properties, e.g. formation, shapes, and propagation. The influence of the lattice symmetry is strongly reflected in the void shape. In test structures with wires perpendicular to the GB, voids exhibit a triangular top view shape in the Ag(111) part and pronounced rectangular top view shapes in the Ag(001) part [3]. We can also vary the azimuthal angle of the crystal lattices with respect to the direction of electron flow, i.e. modify the angle comprised by the wires and the GB. For a test structure with a parallel GB (90° rotated), the Ag(001) lattice is the same, due to the 4-fold lattice symmetry. For the Ag(111) lattice with the 3-fold symmetry, the direction of electron flow, i.e. the EM force direction, is changed from a <112 > to a <110> direction. In this lattice configuration the voids again exhibit triangular top view shapes, but are rotated by 30°. Surprisingly, the motion direction of voids is also rotated by various angles between 20° and 60°. The motion direction of voids does not coincides with the EM force direction.
[1] D. Wall et al. IBM J. Res. and Dev., 55 (2011) 9;
[2] S. Sindermann et al. Rev. Sci. Instrum. 82 (2011) 123907;
[3] A. Latz et al. Phys. Rev. B 85 (2012) 035449

Scaling of interconnect metal lines as technology improves leads to an increase in the resistance and capacitance in the metal and dielectric. Copper and low-k dielectric system was used to replace the older aluminum and silicon dioxide system to decrease the resistance and capacitance. However, low-k dielectrics have lower mechanical, electrical and chemical properties as compared to silicon dioxide, hence the need to study reliability.
This paper will focus on the study of the interaction between two common reliability problems found in the backend interconnects; electromigration (EM) [1] and time dependent dielectric breakdown (TDDB) [2]. EM will cause the stress to build up at the anode due to atom migration. Copper out-diffusion is one of the main failure modes identified for dielectric breakdown in the Cu/low-k interconnects, this stress build up in the metal line may become an issue as it can cause copper to diffuse more easily, further exacerbating the TDDB.
This study was conducted by a newly designed structure, which combines the long metal line used for inducing EM, and head-to-head metal lines [3] at each end of the long metal line, designed to study dielectric breakdown. The copper metal line consists of Ta/TaN barrier and SiCN cap, the dielectric is SiOCH, with a dielectric constant of 2.7. EM was first conducted to induce a certain amount of stress in the metal line, after which, TDDB was conducted. The stress in the metal line can be estimated using XSIM, which is a numerical solver based in MATLAB environment developed by [4]. The breakdown lifetimes were compared with those with no stress in the metal line. From the experimental results, there was indeed a reduction in the TDDB lifetime.
The failure mechanism will be studied in detail by physical failure analysis. Possible failure mechanism could be due to the stress in the metal line leading to delamination of the capping layer, or copper out-diffusion into the dielectric. If the stress in the metal line is very high, it could even lead to bulging of the metal line, causing the dielectric spacing to decrease and hence affecting the TDDB lifetime. This implies that it is not just the voltage in adjacent lines that will affect the TDDB lifetime, but the current flowing in the lines has an impact as well.
[1] R. G. Filippi et al, “The Effect of a Threshold Failure Time and Bimodal Behavior on the Electromigration Lifetime of Copper Interconnects”, Proc. Intl. Reliability Phys. Symp. (IRPS), pp. 444-451, 2009
[2] F. Chen et al, “A Comprehensive Study of Low-k SiCOH TDDB Phenomena and Its Reliability Lifetime Model Development”, Proc. Intl. Reliability Phys. Symp. (IRPS), pp. 46-53, 2006
[3] T.L. Tan, “Delamination-induced dielectric breakdown in Cu/low-k interconnects”, J. Mater. Res., Vol. 23, No. 6, Jun 2008.
[4] Frank L. Wei et al, “Electromigration-induced extrusion failures in Cu/low-k interconnects”, Journal of Applied Physics, Vol.104, No. 2, Jul 2008.