We have investigated the charge injection efficiency of carbon nanotube (CNT) electrodes on organic semiconductors and compared their performance to that of traditional metal electrodes. Our study was conducted on three different organic semiconductors: pentacene, phenyl-C61-butyric acid methyl ester (PCBM) and copper phthalocyanine (CuPc) in a three-terminal FET configuration. The carbon nanotube electrodes are arrays made of individual single-walled carbon nanotubes bonded at one end to a Ti metal pad and embedded at the other end in the semiconducting layers. Compared to conventional Au electrodes, these CNT array electrodes provided better injection efficiency at low bias, improved switching behavior, higher electron mobility, and lower contact resistance. Despite large offsets between the CNT work function and the energy levels of the organic layers, the injection characteristics were Ohmic irrespective of the type of carrier being injected. These good performance characteristics appear general and indicate that carbon nanotubes should be considered as better alternatives to the traditional metal electrodes for next-generations of field-effect transistors. The mechanism of injection will also be discussed on the basis of tunneling across the Schottky barrier, a process that appears to be enhanced by the strong electrostatic effects at the CNT/organic interfaces. Work done in collaboration with F. Cicoira, C. M. Aguirre and P. Desjardins

Due to their unique structural and electrical properties, carbon nanotubes (CNTs) are promising candidates for next-generation electronic and optoelectronic devices, and the CNT-metal contact plays a crucial role in their performance. In this talk, we discuss our recent theoretical and modeling work to examine the nature of charge injection at metal contacts to individual CNTs and CNT arrays. The simulations reveal a variety of phenomena that govern the efficiency of charge injection in CNT devices. Electrostatic modeling shows that competing length scales can result in a potential barrier that prevents charges from crossing the channel-contact interface, which can significantly increase the contact resistance. We also show that the contact resistance is affected by the length of the contact, as indicated by recent experiments, and we provide an atomistic calculation of the relevant charge injection length, and discuss the factors that govern it. A charge transport model based on non-equilibrium Greenâ?Ts functions allows us to examine the importance of tunneling in CNT Schottky contacts. Our results will be discussed in the context of a variety of devices, including single-tube field-effect transistors, Schottky diodes, and CNT arrays.

Charge carriers in graphene show intrinsically ultrahigh mobility, and thus graphene is now recognized as a promising material for future electronic devices. The carrier transport properties should be measured using metallic electrodes. However, metal-graphene contacts introduce an additional resistance, known as contact resistance, RC. This resistance is a limiting factor for the performance of electronic devices. The relative contribution of RC to the total device resistance becomes larger in devices with shorter inter-electrode spacings, i.e., in shorter channel devices. Therefore, RC becomes a predominant factor to consider when attempting to achieve miniaturization and integration of graphene devices. We have studied the effect of metal contacts to transfer characteristics (the gate-voltage dependence of the drain current) of graphene field-effect transistors [1-4]. The metal contacts have been reported to affect the electronic property through charge transfer (CT) from the metals to graphene [5]. In this presentation, we show that the CT is accountable for apparently-appeared "negative" RC extracted by the transmission line model (TLM) or four-terminal measurement, which should include a contribution from an additional resistance due to the metal-contact doping RCD, in addition to the actual tunnel resistance precisely at the metal-graphene contacts, RCI. The apparently negative RC is considered to be a characteristic feature of Dirac-cone systems such as graphene and topological insulators. [1] R. Nouchi, M. Shiraishi and Y. Suzuki, Appl. Phys. Lett. 93, 152104 (2008). [2] R. Nouchi and K. Tanigaki, Appl. Phys. Lett. 96, 253503 (2010). [3] R. Nouchi, T. Saito and K. Tanigaki, Appl. Phys. Express 4, 035101 (2011). [4] R. Nouchi and K. Tanigaki, Jpn. J. Appl. Phys. 50 (2011) 070109. [5] G. Giovannetti et al., Phys. Rev. Lett. 101, 026803 (2008).

Metal-Semiconductor (MS) junction is one of the most important interfaces for many technologies including Si technology. However, for the most MS junctions, Fermi-level of metals at the interface is pinned at a certain level regardless of the metals, and reducing the Fermi-level pinning effect has been a critical technical challenge. [1]

In our recent results, we discovered that inserting graphene between MS junction reduces the Fermi-level pinning effect, selectively decreasing the Schottky barrier height of the MS junction.[2] Graphene is chemically inert and does not form silicide with Si unlike transition metals when it is transferred onto Si surface. Instead, graphene keeps the surface termination of Si surface as it is prepared. Thus, when graphene is transferred onto a completely saturated Si surface, the stable Si termination atoms/molecules remain and create van der Walls interaction between graphene and Si.

Based on the above idea, we demonstrated a method, inserting graphene at the MS junction, to reduce or even potentially eliminate the Schottky barrier at the junction of MS junction. We especially focused on n-type Si and Ni junction, since n-type Si forms higher Schottky barrier height with any metals including Ni than p-type Si. With the new contact structure and the knowledge that Ni reduces the work function of graphene [3], we were able to diminish the Schottky barrier height substantially and to demonstrate near Ohmic contact between Ni and Si. We also investigated the effect of other metals. We found that the metal/graphene interaction exists and the work function of graphene on metal was not a simple function of the work function of pure metal as it was predicted. [3] In addition, we tried various interfaces between graphene and Si with several functionals. We believe that this research opens an innovative way to control MS junction for new technology.

[1] F. J. Himpsel, G. Hollinger, R. A. Pollak, Phys Rev B 1983, 28, 7014

[2] H. Yang, J. Heo, S. Park, H. J. Song, D. H. Seo, K.-E. Byun, P. Kim, I. Yoo, H.-J. Chung, and K. Kim, Submitted.

[3] G. Giovannetti, PA Khomyakov, G Brocks, VM Karpan, J van den Brink and PJ Kelly, Phys Rev Lett 2008, 101, 026803

Conductance histograms have been routinely used to characterise metallic nanocontacts. These histograms typically present a broad dispersion with a lack of characteristic conductance values as a result of the lack of reproducibility of the crystalline structure at the nanoscale. I will present experimental evidence of how to obtain, in a reproducible and reversible mechanical manner, crystalline structures and conductance values ranging from a few atom section and a few quanta down to a single atom and one conductance quantum. I will also present evidence of the possible formation of a two-dimensional topological insulator in Bismuth nanocontacts with its concomitant robust conductance quantization.

Carbon nanotubes (CNTs) synthesized by plasma-enhanced chemical vapor deposition (PECVD) offer a potentially suitable material for vias in next-generation integrated circuits. One advantage of PECVD over other techniques is the vertically-aligned geometry that is critical to the via manufacturing process. One important consideration in the via formation is the contact resistance between CNT and the underlayer metal at the as-grown interface, which tends to dominate the overall resistance of the interconnect via [1]. A clear understanding of the nature of that interface and the resulting contact resistance is essential for assessing the potential of CNT for via applications. Recently our group presented evidence for aluminum oxide formation when aluminum is used as a metal underlayer [2]. Further, chromium and titanium were found to be partially oxidized [2], which is believed to be a cause for the high contact resistance between the metal and CNT. An earlier study reported larger lattice spacing in titanium at the interface of PECVD-grown CNTs, which was attributed to the formation of titanium carbide [3]. In the PECVD process, ammonia is used as a reducing agent during the catalyst particle formation process. Our current results, obtained using high-resolution transmission electron microscopy (TEM) with energy dispersive x-ray spectroscopy (EDX), reveal a large amount of nitrogen incorporated into the underlayer metal, thus changing its surface morphology and interface electrical properties. In this study, we focus on the nanostructure-electrical property relationship at the as-grown contact between the CNT and underlayer metal, using electrical measurements as well as TEM/EDX, as part of our objective to optimize the PECVD growth process for CNT vias. [1] Q. Ngo, T. Yamada, M. Suzuki, Y. Ominami, A. M. Cassell, J. Li, M. Meyyappan, and C.Y. Yang, IEEE Transactions on Nanotechnology 6, 688-695 (2007). [2] X. Sun, K. Li, R. Wu, P. Wilhite, T. Saito, J. Gao, and C.Y. Yang, Nanotechnology 21, 045201 (6pp) (2010). [3] Y. Ominami, Q. Ngo, M. Suzuki, A.J. Austin, C.Y. Yang, A.M. Cassell, and J. Li, Applied Physics Letters 89, 263114-1-3 (2006).

significantly modify the fundamental properties of materials. Specifically, the charge injection and transport properties of semiconductors can be drastically altered. Using the model system of ultra-thin InAs membranes, we investigate the dominant role of quantum confinement on the field-effect device properties. By varying the thickness of free-standing InAs membranes between 5-50 nm, the effect of quantization is systematically studied. The thickness directly affects the subband spacing, as shown by absorption studies of the InAs membranes. These sub-bands determine the contact resistance of the system, with the experimental values consistent with the expected number of quantum transport modes available for a given thickness. Additionally, the effective electron mobility of InAs membranes is shown to exhibit anomalous field and thickness dependencies that are in distinct contrast to the conventional MOSFET models, arising from the strong quantum confinement of carriers. The results provide an important advance toward establishing the fundamental device physics of two-dimensional semiconductors. References: [1] K. Takei, H. Fang, S. B. Kumar, R. Kapadia, Q. Gao, M. Madsen, H. S. Kim, C.-H. Liu, Y.-L. Chueh, E. Plis, S. Krishna, H. A. Bechtel, J. Guo, A. Javey. "Quantum Confinement Effects in Nanoscale-Thickness InAs Membranes", Nano Letters, 2011, ASAP

Group III-nitride semiconductors play an important role in high speed electronic and optoelectronic devices. The band gaps reach up to 6.3 eV for wurtzite AlN, making nitrides ideal for high power applications. In this work we focus on the zinc blende variant of AlN. Using density functional theory we study the band alignment at metal/AlN interfaces as a first step towards a theoretical description of a metal contact to AlN. We deduce the Schottky barriers of Al, Cs, Au, W, Hf and Pt to AlN. Comparing results of first principles calculations to those predicted by the metal induced gap states (MIGS) theory we find good agreement with the Schottky limit for Al, Au, Pt, Hf and W while Cs shows significant deviation. Our results can be explained when allowing for an effective change in AlNâ?Ts electron affinity when in contact with a metal. Simulating a monolayer of Cs on AlN we find a shift in electron affinity from 1.9 eV for the bare AlN surface to -1.2 eV for the â?ocesiatedâ? surface.

ZnO nanowires (NWs) synthesized by bottom-up method can be used for electronic devices such as field effect transistors, light emitting diodes, and sensors. Conventional methods for the alignment and integration of NWs have been dielectrophoresis, an external magnetic-field and so on. However, when they were aligned onto the electrodes, mechanical and electrical contacts between NWs and electrodes were not stable due to incomplete bonding and weak adhesion based on Van der Waals force. Therefore, post-processes such as focused ion beam deposition or selective electrodeposition were needed to enhance the mechanical and electrical contacts, which increases the complexity and cost of manufacturing process. In this paper, we present a novel process based on two-step transfer printing of nanowires on the metal electrodes with low melting temperatures, which allows robust bonding of nanowires onto metal electrodes without the need of additional bonding processes. The procedure of thermocompression bonding is as follows: In the first transfer step, ZnO NWs randomly grown on Si substrate by CVD method were transferred to intermediate Si/SiO2 substrate. In this process, we used contact printing method where normal and shear forces were applied to the intermediate substrate to form parallelly aligned ZnO NWs. In the second transfer step, parallelly aligned ZnO NWs on intermediate substrate was pressed against target substrate with metal electrodes by thermocompression at P=5 bar and T=100°C for 5 minutes. After intermediate substrate was removed from the target substrate, we could observe that ZnO NWs were successfully aligned and formed a robust bonding on metal electrodes. We used double layer metal (Au/In and Cu/In) having low melting temperature because they are softened at elevated temperature (~100°C). ZnO NWs can be easily embedded into metal electrodes with low pressure (~5 bar) since the metal electrodes are mechanically soft. Consequently, ZnO NWs and metal electrodes are bonded with high mechanical strength. Mechanical strength of ZnO NW â?" metal electrode bonding was measured by applying lateral force microscopy (LFM) at center of ZnO NWs. It could be observed that ZnO NWs were broken before the failure of NW-electrode joints, proving the mechanical robustness of bonding. We could also find that the bonding between metal electrodes and ZnO NWs form a stable Ohmic contact property from electrical measurement. In summary, we demonstrated a novel method for the alignment and robust bonding of NWs onto metal electrodes by using two-step transfer printing technique. Mechanically robust bonding and stable ohmic contact between NWs and metal electrodes could be achieved by this high-speed and low-temperature process. We believe that this method will be very useful for the large-area fabrication of NW-based electrical devices such as field effect transistors, light emitting diodes, and sensors.

Introducing organic molecules in electronics is limited by the ability to connect them electrically to the outside world. This involves the formation of top metal overlayers on the organic surfaces. This is not a trivial task because most known methods to make such contacts are likely to damage the molecules [1]. Understanding the atomic and molecular level interaction of metal atoms with organic surfaces is becoming increasingly important as the number of applications involving metalâ^'organic interfaces grows. The design of silicon/alkyl layer/metal junctions for the formation of optimal top metal contacts requires the knowledge of the mechanistic and energetic aspects of the interactions of metal atoms with the modified surface. This involves a) the interaction of the metal with the terminal groups of the organic layer, b) the diffusion of metal atoms through the organic layer and c) the reactions of metal atoms with the silicon surface atoms. The diffusion through the monolayer and the metal catalyzed breakage of Siâ^'C bonds must be avoided to obtain high quality junctions. In this work we developed a complete mechanistic and energetic picture of all the processes involved in the formation of silicon/alkyl layer/metal junctions. Our results are in agreement with the available experimental observations and provide detailed information on the reaction pathways and energy barriers involved in the formation of the junction. We performed a comprehensive density functional theory investigation to identity the reaction pathways of all the processes involved [2]. The diffusion of gold atoms through the alkyl layer was compared for two systems: compact alkyl monolayers on Si(111) and compact alkanethiol monolayers on Au(111). In the absence of a reactive terminal group, gold atoms penetrate through the monolayers with small energy barriers. However, the presence of thiol terminal groups introduces a high energy barrier which blocks the diffusion of metals into the monolayer. On the alkylated Si(111) surface, the diffusion barriers increase in the order Ag < Au < Cu and correlate with the stability of metalâ^'thiolate complexes whereas the barriers for the formation of metal silicides increase in the order Cu < Au < Ag in correlation with the increasing metallic radii. The reactivity of gold clusters with functionalized Si(111) surfaces was also investigated. Metal silicide formation can only be avoided by a compact monolayer terminated by a reactive functional group. The mechanistic and energetic picture obtained in this work contributes to understand the factors that influence the quality of top metal contacts during the formation of silicon/organic layer/metal junctions. [1] H. Haick and D. Cahen, Prog. Surf. Sci., 2008, 83, 217-261 [2] M. F. Juarez, F. A. Soria, E. M. Patrito, P. Paredes-Olivera. Phys. Chem. Chem. Phys. 2011, DOI: 10.1039/c1cp22360g

TiO₂ is the most intensively investigated class of materials for the applications of photocatalysts' support and photoanodes of solar cells and water splitting. Among them, nanotubular structures of TiO₂ are even more interesting due to their 1 dimensional morphology as a direct pathway of the photo-induced charge carriers. For the applications, local characterizations of the nanometer scale contacts and charge separation and transport behavior through 1D nanomaterials are of paramount importance. Here, we present nanoscale electrical as well as photoelectric properties of TiO₂ nanotubes (TNTs) by the modified scanning probe microscopy (SPM). SPM is an ideal tool for the local electric characterization. It could be addressed the phenomena of the trapped and/or injected charges on the nanoscale functional materials. In this presentation, two examples are to be discussed: 1) Light-induced charge separation on nanostructures of Au/TiO₂ nanotubes(TNTs) characterized by modified electrostatic force microscopy (EFM), and 2) Nanometer scale Schottky contact at anatase TiO₂ nanotubes/Pt interfaces. Schottky interfaces at both distal ends of the nanotube, the ideality factor and Schottky barrier height are obtained based on thermionic emission theory, revealing the enhanced tunneling. The reduced effective Schottky barrier heights are in the range of 0.28 to 0.43 eV.

Nanoelectromechanical systems (NEMS) switches have been identified by the International Technology Roadmap for Semiconductors as a possible "beyond CMOS" technology. However, the reliability of the contact interface is currently a key challenge for the commercialization of these devices. The adhesiveness of conventional metallic contact materials in combination with the nanoscale dimensions of NEMS switches results in failure through permanent adhesion of the contact interface. In addition, many non-adhesive contact materials are reactive and can form insulating tribolayers after many switching cycles. This motivates the need for contact materials that are highly conductive, chemically inert, minimally adhesive, and amenable to CMOS fabrication processes. Platinum silicide is a promising candidate material that may satisfy these complex demands. In this work, we show for the first time that the surface chemical composition of platinum silicide (PtxSi) formed through amorphous silicon (a-Si) and platinum (Pt) diffusion may be tuned by changing the amount of a-Si available during silicidation. This gives direct control over the selection of highly conductive and chemically inert Pt-rich variants, or low-adhesion Si-rich forms. PtxSi is a promising next-generation switch contact material because it possesses metallic conductivity, is compatible with current CMOS fabrication, is chemically inert, and can be used for the etchant-free in-situ release of freestanding NEMS switches. However, successful integration of platinum silicide contacts into many NEMS switch architectures requires the use of a-Si rather than the more heavily studied single-crystalline silicon-based (sc-Si) PtxSi. Little is known about the growth sequence, growth kinetics, growth rates, and resulting chemical composition of the PtxSi formed using a-Si. In the present study, PtxSi was synthesized by annealing a 40-nm a-Si layer on a 70-nm Pt layer and a 100-nm Pt layer on a sc-Si wafer using both rapid thermal (RTA) and high vacuum (HV) annealing. Diffusion of Pt from the a-Si/Pt bilayer into the sc-Si carrier wafer was prevented through the use of an aluminum nitride diffusion barrier - a topology similar to that employed in some current micro/nano-scale switches. Differences in the formation behavior of the resulting silicides were then characterized using in-situ and ex-situ X-ray photoelectron spectroscopy. a-Si was shown to form a Pt-rich silicide (Pt3Si) in comparison to the PtSi and Pt2Si stoichiometries usually found in sc-Si/Pt silicidation. This Pt-rich stoichiometry is believed to be the result of using a thin a-Si layer - essentially robbing the silicidation process of sufficient Si for full conversion to Pt2Si or PtSi. This suggests that the thickness of thin a-Si on Pt has a direct impact on the stoichiometry and may be tuned to confer properties associated with either Pt-rich (high conductivity and inertness) or Si-rich (low adhesion) compositions.

Electron-beam-induced deposition (EBID) of tungsten (W) has been demonstrated to yield substantial improvement in the contact resistance between carbon nanomaterials and their metal electrodes [1]. EBID could provide a lower-cost alternative to Ion-Beam Induced Deposition (IBID) schemes such as focus-ion beam (FIB), and has the ability to produce structures with high positional accuracy. Additionally, FIB has the risk of damaging the on-chip devices because of its high beam energy, resulting in the implantation of gallium from the ion beam which could lead to alteration of device properties. Therefore, we have developed an EBID technique for W deposition using a variable-pressure scanning electron microscope (VP-SEM). In this technique, the source gas (WF6) is delivered via a specially designed gas injection system (GIS) [2] and guided by the focused electron beam to yield deposition on a selected target at a lower energy than FIB. We have performed surface analysis of the deposited areas using energy-dispersive x-ray spectroscopy (EDS), and compared them with depositions performed by FIB using W(CO)6 on similar structures. Additionally, in order to assess the viability of this technique, we have performed a series of experiments to determine the localization of W in the area surrounding the deposits. We find that for EBID, the W content in the deposited area is generally higher than that for IBID. A detailed analysis of W composition between the electrode contacts reveals that the EBID depositions are fairly localized at the electrodes, though there is evidence that trace amounts of W are present along the length of the nanocarbon interconnect. This small lateral spread of W in the EBID is probably a result of secondary electron induced deposition, or through other migration paths such as atomic W diffusion subsequent to dissociation from the WF6 molecule. The extent of the impact of this lateral spread of W deposits on the electrical properties of the nanocarbon interconnects will be discussed. [1] Shusaku Maeda, Patrick Wilhite, Nobuhiko Kanzaki, Toshishige Yamada, and C. Y. Yang, AIP Advances 1, 022102 (2011). [2] D. C. Joy and P. D. Rack, Microscopy and Microanalysis 11, 816 (2005).

Rapid progress has recently been made in the quantitative analysis of electrical conductance of metal/molecule/metal junctions through the development of a mechanically controllable break junction (MCBJ) method. However, experimental studies on the single molecular junctions have been focused on a charge transport and have not made use of spin degree of freedom. Theoretical studies have predicted that single molecule is useful for the transport and generation of spin-polarized electrical current [1]. Recently Schmaus et al. have reported that the magnetoresistance (MR) of single molecular junctions reaches several tens of % using scanning tunneling microscope [2]. We also have succeeded in measuring the MR of the single molecular junctions by using the MCBJ method [3]. In this study we found that molecular junctions showed anomalous giant MR (GMR) at room temperature. We used A thin Si plate as a substrate. Au/Cr electrodes were prepared by conventional photolithography. Au and Ni layers were prepared by electrochemical deposition on Au/Cr electrodes to form a contact of Ni electrodes. A droplet of mesitylene containing 1 mM benzenedithiol (BDT) was then placed on the Ni electrodes to modify the electrodes. The Ni contact is broken by bending the substrate. When the molecular junction is formed, plateau is observed in the current transient. We conducted MR measurement of single molecular junctions by applying external magnetic field in Ar atmosphere at room temperature. When the magnetic field was changed from H = -2000 Oe to H = 2000 Oe, the resistance reached maximum around H = 300 Oe. MR of Ni/BDT/Ni junctions. The typical MR ratio was tens of %. Since the tunnel junction without the molecule showed only a few % of negative MR, we can attribute the origin of MR to the Ni/BDT/Ni junctions. [1] L. Bogani and W. Wernsdorfer, Nature Mater. 7, 179 (2008). [2] S. Schmaus et al., Nat. Nanotechnol. 6, 185 (2011). [3] R. Yamada et al., Appl. Phys. Lett. 98, 053110 (2011).

Silicides have been widely studied and used for the low-resistance contacts, gate electrodes and local interconnections in metalâ?"oxideâ?"semiconductor field effect transistors (MOSFET) for decades. Although nickel silicide (NiSi) offers lower resistivity, the greater thermodynamic stability of cobalt disilicide (CoSi2) makes it more suitable for structures which high processing temperatures are needed. Traditionally, CoSi2 has been prepared by annealing of sputtered or evaporated cobalt films on silicon substrates. Industry is moving towards 3D transistors to continue the pace of technology advancement, however, cobalt films made by physical vapor deposition methods (sputtering or evaporation) are non-conformal over the complex 3D architectures and thus fail to meet the challenge. In this presentation, we will demonstrate the formation of CoSi2 by in-situ annealing of highly-conformal cobalt nitride films inside holes with aspect ratios over 30 to 1. The cobalt nitride films are prepared by chemical vapor deposition (CVD) using a cobalt amidinate precursor and a reactant mixture of NH3 and H2 at low substrate temperatures. We studied the reaction of cobalt nitride films with silicon under different annealing conditions. Morphological stability and interfacial smoothness are crucial for application of cobalt disilicide as a material for contacts, gates or local interconnects. We developed a method to measure the roughness of CoSi2/Si interfaces by selective backside etching followed by atomic force microscopy. Using this method, we optimized the deposition and processing conditions to make smooth interfaces between CoSi2 and various crystalline orientations of silicon.

Nanowires are attracting a growing interest in the semiconductor industry due to their numerous potential applications including field-effect transistors, elementary logic gates and light-emitting diodes. It has also been demonstrated that nanowires could be used as Josephson elements in superconducting devices. Indium arsenide (InAs) nanowires are of special interest as InAs can form Schottky-barrier-free contacts with metals. However a native oxide layer is known to form easily on InAs nanowires and thus must be removed prior to metallization to achieve highly transparent contacts. While most of the studies involving InAs nanowires report the use of a wet etching process to treat the nanowires before deposition of the contacts, there have been few reports of the sputter-cleaning process and no quantitative comparison between the two techniques. Here we present a systematic comparative study of the contact resistance between InAs nanowires and metals following the use of (a) a wet etching process or (b) a sputter cleaning process. The InAs nanowires are grown via molecular beam epitaxy on Si (111) substrates without the use of metal catalysts. They have a diameter between 50 and 100nm and an average length of 3µm. HRTEM measurements show that the structure of the nanowires is a mixture of hexagonal and cubic phases. The metallic contacts are attached to the nanowires by using an electron-beam lithography process. From field-effect measurements, we have established that the InAs nanowires are n-type and that their mobility at room temperature lies between 100cm² V^-1s^-1 and 600cm² V^-1s^-1. Before the contact metallization, the InAs nanowires are treated either by wet etching or by argon milling. In the wet etching process, the contact area of the InAs nanowires is etched and passivated by an ammonium polysulfide solution. Different dilution levels of the solution and exposure times are investigated. In the sputter cleaning process, the InAs nanowires are milled by argon-ion sputtering with a voltage of 200V. Nanowires treated by either of these two processes exhibit lower contact resistances by up to three orders of magnitude compared with untreated nanowires . While both processes exhibit similar values of optimized contact resistance, the use of argon milling tends to give more systematic results with a smaller sample-to-sample variance. Its use is also simpler as the metallic deposition can be done in-situ following the milling. We have also examined the influence of the material used for the drain and source electrodes (Cr/Au, Ni/Au, Ti/Au or Nb/Au) and the stability of the contacts as a function of storage time in vacuum or air.

Non-Ohmic contacts to Ge pose a significant challenge to future high performance CMOS and low thermal budget selector devices for cross-point memories.[1] Low resistance n-type Ohmic contacts are more difficult to achieve due to large Schottky barrier heights (0.49-0.64 eV) [1] resulting from Fermi level (E_F) pinning near the valence band and low dopant activation levels.[1,2] A thin, insulating dielectric between the metal and Ge layers unpins E_F but the high tunneling resistance of the dielectric layer limits the contact resistance.[2] Recently, a high-doped Si interfacial layer having good conduction band alignment with Ge has been used to realize low resistance Ohmic contacts to n-Ge.[1] In this work we demonstrate n-type ZnO as another suitable interfacial semiconductor layer that can form Ohmic contacts on n-Ge due to a negative (-0.1 eV) conduction band offset at the ZnO/Ge interface, low E_F pinning for metal contacts on ZnO, and high doping levels that can be realized at metal/ZnO interfaces.[3] Thin ZnO layers (0.7-2.1 nm) were deposited on HF:DI cleaned n-Ge (1e17 cm^-3) substrates using RF sputtering. X-ray diffraction on thick lpayers confirms the deposition of crystalline, c-axis oriented ZnO (0002). Hall and sheet resistance measurements show that the ZnO films are low-doped (1e17 cm^-3). Metal contacts were formed using Ti/Au e-beam evaporation and backside metallization was done using Al. I-V characteristics of as-deposited contacts show a strong dependence on ZnO thickness. Thin ZnO (0.7nm) gives a significant increase in forward (10x) and reverse-bias (100x) currents due to the low (0.3 eV) barrier of the unpinned Ti/ZnO interface [4] as compared to the pinned 0.54 eV barrier of the control Au/Ti/n-Ge sample. However, the current decreases with increasing ZnO thickness due to significant tunneling resistance from the depletion width of the low-doped ZnO layer. Annealing the Au/Ti/ZnO/n-Ge contacts at 400 °C for 60s gives nearly identical, Ohmic I-V characteristics that are independent of ZnO thickness. This can be attributed to the formation of a highly doped ZnO layer at the Ti/ZnO interface due to accumulation of oxygen vacancies during anneal.[5] The increased doping reduces the thickness of the depletion tunneling barrier at the Ti/ZnO interface resulting in Ohmic contacts that are lower in resistance than the as-deposited devices. Additionally, the tunneling depletion width, and hence the I-V curves, are nearly independent of ZnO thickness for the highly doped interface. The Ohmic I-Vs on annealed Au/Ti/ZnO/n-Ge contacts show 500x higher current densities at low bias (± 0.1 V) versus control Au/Ti/n-Ge devices. This project was funded with a research grant from Applied Materials, Inc., USA. References: 1] K. Martens et al., APL 98, 013504 (2011) 2] D. Lee et al., APL 96, 052514 (2010) 3] L. J. Brillson et al., JAP 109, 121301 (2011) 4] C. A. Mead, Sol. St. Elect. 9, 1023 (1966) 5] K. Vanheusden et al., APL 68, 403 (1996)

The nonlinear Poissonâ?Ts equation along with the electron and hole continuity equations are simultaneously solved by fixed point iterative method in one dimension to obtain the potential inside the semiconductor bulk near the metal semiconductor interface. After potential calculation the electron and hole current densities are calculated to obtain total current at various forward bias. Simulations were performed for different inverse layer thickness and doping concentrations at different temperatures. The barrier height (BH) and ideality factor obtained by fitting of simulated current voltage (I-V) data into thermionic emission diffusion (TED) current equation shows that the BH increases initially with the increase in inverse layer thickness and then attains an almost constant value beyond certain thickness. On increasing inverse layer doing concentration the BH starts increasing at low thickness and becomes constant thereafter. Thus the BH attains maximum saturation value at relatively lower thickness for highly doped surface layer than for the less doped surface layer. However, the maximum saturation value of BH with large inverse surface layer is same for all doping concentrations. The variation of derived ideality factor of the diode with inverse surface layer thickness was also studied. The ideality factor start increasing with increase in inverse layer thickness and attains a maximum value at a particular thickness and thereafter it starts decreasing and finally approach almost unity for larger inverse layer thicknesses at which the barrier height attains maximum saturation value. The maximum ideality factor occurs at thickness for which the barrier height values starts rising. It is observed from the inverse layer thickness and doping concentration dependence of BH and ideality factor that for large inverse layer thickness the BH attains a maximum value with unity ideality factor. Thus depending on the layer thickness and its doping concentration there are two regimes, namely, the non-ideal regime corresponding to lesser inverse layer thickness and/or its doping concentration and the ideal regime corresponding to large inverse layer thickness and/or its doping concentration. The temperature dependence of the BH and ideality factor of the Schottky diodes with inverse doped surface layer were also studied by numerical simulation at low temperatures. It is observed that for diode in non-ideal regime the BH found to decrease and ideality factor increases with decrease in temperature. However, in ideal regime the Schottky diode BH increases linearly with decrease in temperature with unity ideality factor at all temperatures. The overall barrier enhancement as a function of inverse layer thickness was found to occur from 0.71V to 0.92V. Further barrier height enhancement as a function of temperature is observed for 120nm thickness for which it is found to increase from 0.92V at 300K to 1.18V at 40K with decrease in temperature.

In-situ imaging and characterization of ohmic contact formation mechanism between metal nanoparticles and semiconductor micro/nanoscale wires/pillars is important for several emerging device applications. We describe an experiment to interface and characterize Ag nanoparticle aggregates that are self-assembled and plastically deformable on Au film deposited on glass substrate. The electrical characterization is done using an electrical nanoprobe attached to a nano-manipulator inside a scanning electron microscope (SEM). Electrical current-voltage (I-V) measurements are made between the electrical nanoprobe in contact with the nanoparticle and the Au film. The Ag nanoparticles have diameters ranging between ~600-800nm and are self-assembled on a thiolated 100nm Au film. Application of contact force via the nanoprobe even after substantial particle deformation reveals initially only a small non-linear current. Upon current annealing through Joule heating, significant improvement in the electrical contact at the AgNP/substrate interface was observed. This is most likely based on the particle bonding to the substrate after passing a high current. The need for such an annealing step might be critical in forming good ohmic contacts at ambient conditions during transfer printing of semiconductor micro/nanopillars.

Investigation of low-frequency noise in Schottky barriers based nanoscale Field-effect Transistors (SB-FETs) is of prime importance due to its large amplitude in emerging bottom-up devices. In addition, noise can give additional information on the charge transport mechanisms. Here, we study the 1/f noise in nanoscale silicon-on-insulator SB-FETs which we consider as a test bed because of an excellent process control of the gate oxide interface and flexible engineering to control SB height Φ through dopant segregation. First, we propose an analytic model for 1/f noise in SB-diodes and SB-FETs. We consider that noise is related to a voltage fluctuation across the SB, which can be obtained analytically from Richardson expression for thermoionic emission. The contribution of two fluctuators in series (SB and a serial resistance or FET channel) is then considered to get an equation valid for low SB heights. Second, SB diodes and SB-FETs were studied through DC current, 1/f noise and shot noise measurements. Barrier heights as low as 80 and 50 meV (for N- and P- type respectively and estimated independently through temperature dependence measurements) are achieved using dopant segregation. We show that even for very small Φ<0.1 eV, the contribution from the SB to the noise is not negligible even if the current is dominated by the channel resistance. In addition, there is an exponential decay of normalized noise with Vd, which is in perfect agreement with the proposed model. Transistor channel length Lg has been varied from 30 nm to 1 µm. Noise dependence with Lg at Vd = 0.2 V is very different for N- and P- type segregated SB-FETs (independent on Lg and following 1/Lg, respectively). 50 meV can be considered as a maximum barrier height for low impact of SB on the noise when Vd >> 0 V. Tuning Φ by technological means such as dopant segregation tends to reduce the noise amplitude, although additional generation-recombination and trapping noise is noticed at small Vd for P-type devices. In agreement with SOI-SBFETs experimental results, the proposed analytic model can be considered for any diffusive SB FET including nanowires, graphene sheets and carbon nanotubes devices. It could be used either for noise amplitude comparison, interfacial quality and SB height evaluation. N.Clement, G. Larrieu and E. Dubois, « Low-Frequency noise in Schottky barriers based Nanoscale Field-Effect Transistors » IEEE Trans.El.Dev., in press. TED-.2011.2169676

Molecular spintronics, the combination of chemistry potential to the spin degree of freedom provided by spintronics, is considered to be more than an alternative to conventional spintronics with inorganic materials. Unconventional properties and strong potentialities offered by the flexibility, chemical engineering and low production costs of molecules, add to the opportunity that spin lifetime could be enhanced by several orders of magnitude compared with inorganic materials. Very recently it has been highlighted that the metal/molecule hybridization could strongly influence interfacial spin properties going from spin polarization enhancement to its sign control in spintronics devices [1]. A very promising direction is going towards new spintronics devices based on tailored thin organic layers such as SAMs, ultrathin polymerand organic semiconductor films. However, one of the major obstacles to be faced is the possible presence of topographic heterogeneities and electrical defects in the organic barrier. This limits the reliability and reproducibility of the devices and results in a lack of control of the metal-molecule interfaces eventually hampering the proper study of transport in wide-area devices. In this contest nanocontacts become indispensable to allow a deeper investigation on the metal-molecule interface properties. We developed the idea of nanoindentation lithography as a highly versatile and easily adaptable technique allowing the realization of nanojunctions based on the different organic barriers. During nanoindentation a conducting AFM tip is used to notch a nanohole into a previously deposited mask resist. The originality of the process relies on the real-time monitoring of the indentation process through a tipâ?"sample resistance measurement which allows controlling the indentation depth and the contact area with sub-nm precision [2]. Different types of Ferromagnet/Organic/Ferromagnet spintronics nanodevices can be realized: ones where the nanocontact is first elaborated, enlarged by the exposition of the sample to an additional plasma treatment and then filled with the desired organic layer; others where the nanohole is directly dug through the masking resist and into the organics leaving just a thin layer. The top electrode is finally deposited onto the organic layer to complete the device. The nanometric size of the contact (ø=10nm) reduces heterogeneities and allows us to explore the local properties of the junction. We will demonstrate the versatility and potential of our technique showing transport characterization for three types of organic tunnel junctions: thin polymer films, aliphathic SAMs and small molecules organic semiconductors. We will especially focus on SAMs based devices for which a significant TMR effect is measured and found to be exceptionally robust with bias voltage up to 2V. M.G. thanks EU-FP7 HINTS project. [1] C. Barraud et al.Nature Phys.2010,6,615 [2] K. Bouzehouane et al.Nano Lett.2003,3,1599

Two types of interfaces can be formed between metals and graphene depending on the strength of the metal-graphene interaction: weak (metal physisorption) and strong (metal chemisorption) interfaces.1,2 â?oPhysisorptionâ? interfaces (e.g., with Al, Ag, Cu, Ir, Pt and Au) are characterized by a larger metal-carbon distance (>3 Ã.) with some charge transfer between metal and graphene (i.e. doping of graphene) that maintains its overall Ï?-band dispersion. â?oChemisorptionâ? interfaces (e.g. with Ni, Co, Pd, and Ti) are characterized by a smaller metal-carbon distance (<2.5 Ã.) and strong orbital hybridization between metal-d and carbon-pz orbitals, resulting in the destruction of the grapheneâ?Ts Ï?-band dispersion around the Dirac point. Consequently, metals like Ni, Co, Pd, and Ti are commonly used as electrode materials because they form stable contacts due to their strong chemical interaction with graphene, although the graphene electronic properties are essentially destroyed. The issue therefore is to keep grapheneâ?Ts intrinsic Ï? bandstructure by using weakly interacting metals while enhancing the interface stability. In this work, we propose to use sandwiched metal/graphene/metal structures, using weakly interacting metals. The structures thus fabricated are characterized mainly by Raman and x-ray photoelectron spectroscopy (XPS). Large graphene sheets are grown by chemical vapor deposition (CVD) of gaseous methane on copper foils.3 Both Raman and XPS are used to identify the doping level and interface binding energy change before and after the formation of the sandwich structures. These structures make it possible not only to adjust the doping levels in graphene by selecting a combination of appropriate metals, but also to form stable contacts with graphene with metal films on top and bottom. Density functional theory (DFT) calculations are carried out to provide an atomic level understanding of the electronic properties of sandwiched metal-graphene-metal structures. We find that the increased interface binding strength of sandwiched structures arises from an increased interface electron repulsion effect by metal contacts at both sides of graphene. This work suggests that sandwiched structures provide a means to optimize the metal-graphene contact for device applications. [1] Giovannetti et al. Phys. Rev. Lett. 101, 026803 (2008). [2] Gong et al. J. Appl. Phys. 108, 123711 (2010). [3] Li, et al. Science 324, 1312-1314 (2009).

For modern third generation solar cells and optoelectronic devices, conventional contacts made of metallic and alloys can no longer satisfy device requirements in the nanoscale range. As the thickness is decreased, ultra-thin metal films become discontinuous, thus their optical and electrical properties drastically change and so does their functionality. The coverage reduction leads to island formation and local microstructure variations. Therefore, the understanding of optical and electrical properties of metallic nano-layers thinner than a critical thickness is extremely important. We are reporting on layers of high purity Al and Ag sputter-deposited in high vacuum chamber on prime mirror polished silicon wafers. Emphasis are put on the properties of sputtered Al and Ag films with thickness in the coalescence range. Sputtered Al, with aimed uniform film thinner than 10 nm, showed by FE-SEM scattered fragments on the silicon surface. The formation of nano-sized Al islands starts at film thicknesses above 10 nm, which defines a critical thickness for coalescence of sputtered nano-particles. Depth profile of a 38nm thick Al layer exhibits roughness higher than that of the initial silicon wafer, which suggests a continuous involvement of Al nanoparticles during the film growth, even after full coalescence. Al film reflectance appeared to decreases with the thickness to reach its minimum at 50nm, then increases and peaks at 80 nm, and ultimately decays linearly as the film thickness increases. We believe that reduction of the reflectance at early stages of film formation is due to an increased scattering of the incident light by small islands formed at the initial sputtering stage. As the deposition proceeds, the reflectance increases and reaches its maximum when the inter-island regions are totally filled. With further deposition, the reflectance slowly decreases. A strong dependence of ultra-thin Al film electrical resistivity on thickness was found. The resistivity dramatically increases as the thickness (<50nm) decreases due to the discontinuity of the grown Al islands/grains. Non-conventional conduction mode occurs between those metallic nano-particles to enable current transmission from one islands to its neighbors. Beyond 50 nm film thickness, the resistivity becomes almost stable with a value of 6.1Ã-10^-8 Ω-m, which is still higher than the resistivity of the bulk Al (i.e., 2.8Ã-10^-8 Ω-m). The change in the conduction mode is suggested to be a determining factor for the observed conductivity transition. We found that discontinuous Ag layer produces strong fluorescence due to an oxidized phase. AFM imaging of annealed Ag ultra-thin layers showed islands formed on the silicon surface, these appeared well separated from each other. Such nanosized features offer the potential of absorption enhancement via surface plasmon modes. Raman spectroscopy has shown Ag related lines much higher than that of the Si line.

Recent observations of chemically induced hot electron flow over Schottky barriers in planar metal-semiconductor nanostructures provide interesting possibilities for electrolyte-free conversion of chemical energy into electricity and ultra-fast biomimetic sensing applications. Meanwhile, the short-lived nature of the hot electrons in metals imposes special requirements for the Schottky contact morphology, material selection, physical and chemical properties explained in this presentation. Thermal and chemical resilience of the Schottky contact properties and electrical continuity of the wide-area nanometer thickness cathodes play an important role for the potential practical applications. An efficient hot electron harvester must utilize a wide bandgap semiconductor anode, and therefore a fabrication procedure is required to produce both a sharp barrier layer and a diffusive Ohmic contact layer on the same semiconducting wafer; that alone imposes a remarkable challenge. The presentation involves discussion of the relevant theoretical guidelines, practical methods and techniques leading for high quality Pt/GaP/Sn, Pt/SiC/Ag, Rh/SiC/Ag and other Schottky nanodiodes, and prospects of their practical utilization.

Germanium (Ge) is one of possible candidates to replace silicon (Si) as the channel material in complementally metal-oxide-semiconductor (CMOS) technology due to its high electron and hole mobility.[1] However, Fermi-level pining (FLP) effect at metal/Ge interfaces is a critical issue, disturbing the development of high-performance CMOS devices with metallic source and drain contacts.[2] In order to solve this issue, it is important to understand the origin of FLP at metal/Ge junctions. Although it has so far been considered that the origin of FLP is metal induced gap states (MIGSs)[3], we have obtained some results which can not be explained only by MIGSs.[4]
In this paper, we fabricated Fe₃Si/Ge(111) Schottky diodes with atomically matched interfaces with a size (S) of ~10⁶ and ~1 μm², and measured their electrical properties at low temperatures. We found that the diodes with S = ~1 μm² show the two different current-voltage (I-V) characteristics at 100 K, i.e., Ohmic behavior and rectifying behavior. On the other hand, almost all diodes with S = ~10⁶ μm² showed nearly Ohmic behavior at 100 K. This S dependence cannot be explained by MIGSs. Assuming Poisson distribution, we can regard the S dependence as a result of the influence of the number of defects at the interface between Fe₃Si and Ge(111). In short, we infer that the number of the interfacial defects depends on S. When S is ~10⁶ μm², there are some interfacial defects at the Fe₃Si/Ge(111) interface. When S is reduced to ~1 μm², we can encounter two different interfaces, the strong contribution with defects and almost no contribution with ones. From these considerations, we can also infer that the Ohmic and rectifying behavior are arising from the defective and high-quality interfaces, respectively. Therefore, FLP at metal/Ge interfaces can be explained by the extrinsic mechanism.[5] For discussing the formation of the Schottky barrier at metal/Ge interfaces, one should distinguish between intrinsic and extrinsic mechanisms.
K.K and S.Y. acknowledge JSPS Research Fellowships for Young Scientists. This work was partly supported by Industrial Technology Research Grant Program from NEDO and Grant-in-Aid for Young Scientists (A) from JSPS. [1] C. H. Lee et al., IEDM Tech. Dig., 416 (2010). [2] A. Dimoulas, A. Toriumi, and S. E. Mohney, MRS bulletin 34, 522 (2009). [3] T. Nishimura et al., Appl. Phys. Exp. 1, 051406 (2008). [4] K. Yamane et al., Appl. Phys. Lett. 96, 162104 (2010). [5] K. Kasahara et al., Phys. Rev. B (in press).

The four-point resistance, R, of electrodeposited gold nanowires was measured in situ through a laser zone annealing process. A stage and sample attached to a piezoelectric motor translated the nanowire over a 532nm, confocal laser spot at rates as low as 7nm/s. These nanowires were synthesized at height of 20nm and at varying widths (from 76nm to 274nm) using an electrodeposition method known as Lithographically Patterned Nanowire Electrodeposition (LPNE). The resulting resistivity of one such wire measured a reduction of 60% from its initial resistance of 2.5x10-7Ωm to 1.1x10-7Ωm. Transmission electron microscopy (TEM) was used to analyze the change in the internal grain structure and measure the large increase in the in-plane grain diameters (from 27±14nm as-grown state to 90±31nm post annealed condition). The average grain growth diameter was limited to the wire width as the wire neared a complete bamboo structure. The sharp heating profile of the concentrated laser spot could be observed in TEM micrographs as a distinct boundary in the grain structure between annealed and as-grown sections. Theoretical values of resistivities were calculated with grain diameters using analytical models primarily considering grain boundary and surface scattering. The agreement between experimental results and these calculations illustrated that significant contribution to the enhanced conductivity was primarily the reduction of grain boundary density. The improved performance was obtained without suffering instability along the wire, namely grain boundary grooving or wire discontinuity observed in bulk thermal annealing. This zone annealing technique is of interest in improving the microstructure and conductivity of interconnects without the introduction of high thermal energy.

Nanostructures such as carbon nanotubes, nanowires and graphene are being intensively explored for future electronic, photonic, and energy applications. In order for these nanosystems to progress from the research laboratory to technology, it is critical to precisely understand and control charge injection at the electrical contacts. While the scientific community and the semiconductor industry have invested significant resources to develop and control metal contacts to bulk semiconductor materials, charge injection at metal/nanostructure interfaces has received much less attention despite the obvious technological importance. Because nanostructures possess unique properties that differ significantly from bulk semiconductors, existing models of electrical contacts in bulk devices are often inapplicable at the nanoscale. In this presentation, experimental and theoretical works that have highlighted the much different physics and materials science of electrical contacts to nanostructures will be discussed, and key research and development challenges that must be addressed to understand and control nanocontacts will be addressed.

Unlike in Si or even GaAs technology, understanding complex relations between the macroscopic device performance and the metallurgy of contact formation on the atomic level in cadmium zinc telluride (CdZnTe) radiation detectors, remains a formidable challenge. To bridge that macro-nano knowledge gap, we conducted a series of controlled experiments aimed at correlating electrical properties of the In contact to n-type CdZnTe(110) surface with a step-by-step contact formation process, which could only be achieved by using high spatial resolution techniques, capable of conducting highly localized measurements on the nano- and subnano-scale. More specifically, scanning tunneling microscopy was used in-situ to monitor the behavior of various In atom coverages on atomically flat and ordered CdZnTe surface under well-controlled molecular beam epitaxial conditions in ultra-high vacuum, whereas electrical derivatives of atomic force microscopy, such as contact potential difference and spreading resistance in torsion resonance tunneling mode, were used ex situ to measure the electrical contact properties. It was concluded, that In atoms preferentially reacted with Te atomic-rows already at room temperature, forming nanometric patches of indium-telluride Schottky-type contacts, in particular at very low and moderate coverages. At a relatively high In coverage, the dominant morphology consisted of large three-dimensional hillocks, that transformed into quantum rings and "camel humps" upon annealing. The transformation model was proposed. The methods developed in this study, in terms of both nano-contact fabrication and characterization, should be applicable and beneficial in basic and applied research of any metal-semiconductor system.

The intense work of the nanotechnology community has increased the capabilities of researchers to produce new materials at the nanometric scale. As a result, novel physical and chemical behaviors are frequently reported opening opportunities for creating new kind of devices. These new devices will require a precise knowledge of the physical properties of atomic-size contacts and nanowires (NW)/interconnects. The generation of these atomic-size metal wires by the mechanical stretching has allowed the study of a wide range of metals at nanoscale. Due to the dominant role of surface energy in this size regime, several anomalous wire structures have already been reported to form during the stretching of very tiny wires, as hollow tubular metals and the size-limit to the existence of defects in NWs [1-3]. In this work we have studied the relevance of thermal effects on the structural and transport response of Ag atomic-size nanowires generated by mechanical elongation. Our study involve time-resolved atomic resolution transmission electron microscopy imaging and quantum conductance measurement using a ultra-high-vacuum mechanically he controllable break junction in association with quantum transport calculations. We have observed drastic changes in conductance and structural properties of Ag nanowires generated at different temperatures (150 and 300 K). By combining electron microscopy images, electronic transport measurements and theoretical modeling we have been able to establish a consistent correlation between the conductance and structural properties of Ag NWs. In particular, our study has revealed the formation of metastable rectangular rod-like Ag wire (3/3) along [001] direction. [1] M. J. Lagos, F. Sato, J. Bettini, V. Rodrigues, D. S. Galvao and D. Ugarte, Nature Nanotechnology v4, 149 (2009) [2] P. A. S. Autreto, M. J. Lagos, F. Sato, J. Bettini, V. Rodrigues, D. Ugarte, and D. S. Galvao, Phys. Rev. Lett. v106, 065501 (2011). [3] M. J. Lagos, F. Sato, D. S. Galvão, and D. Ugarte, Phys. Rev. Lett. v106, 055501 (2011).

Devices made of few molecules constitute the miniaturization limit that both inorganic and organic-based electronics aspire to reach. However, integration of millions of molecular junctions with less than 100 molecules each has been a long technological challenge requiring well controlled nanometric electrodes. Here we report molecular junctions fabricated on a large array of sub-10 nm single crystal Au nanodots electrodes, a new approach that allows us to measure the conductance of up to a million of junctions in a single conducting Atomic Force Microscope (C-AFM) image. We focus on alkylthiol junctions (with 8, 12 and 18 carbon atoms) as an archetype and for the sake of comparison with an abundant litterature for this molecule. We show that the number and respective amplitudes of the conductance peaks vary, depending on the molecular organisation in the junctions and the atomic structure of the electrodes (i.e. single crystal, polycrystal, amorphous). Since nanodot dimensions are much smaller than that of AFM tip, at constant force, the force per surface unit is increased compared to molecular junctions with substrate electrodes. As a consequence, we observe a lower decay factor than usually measured for molecular junctions with such molecules. By reducing the force to few nN, decay factor increases significantly. We also investigate, using the transition voltage spectroscopy (TVS) method, the electronic structure of junctions belonging to each of the observed conductance population, and we demonstrate how the energy position of the molecular orbitals (with respect to the electrode Fermi energy) depends on chain length, molecular organisation, electrode structure and C-AFM applied force. N. Clement, G. Patriarche, K. Smaali, F. Vaurette, K. Nishiguchi, D. Troadec, A. Fujiwara and D. Vuillaume, Small 7, 2541 (2011) K. Smaali, N. Clement, G. Patriarche and D. Vuillaume, submitted to ACS Nano

For realizing silicon-based spintronic devices with low power consumption, spin injection and detection technologies for silicon (Si) channels without an insulating tunnel barrier have been explored.[1,2] In this study, we demonstrate atomically controlled epitaxial growth of CoFe layers directly on Si by means of molecular beam epitaxy,[3] and realize room-temperature spin injection into a Si channel in a metal-oxide-semiconductor field effect transistor (MOSFET) structure with the fabricated CoFe/n⁺-Si Schottky-tunnel-barrier contact. By applying electric fields to the Si channel, the magnitude of the spin-accumulation signals can be manipulated at room temperature.[4]
To demonstrate spin injection into Si using Schottky-tunnel-barrier contacts, the 10-nm-thick CoFe layer was grown directly on 75-nm-thick (111)-oriented silicon on insulator (SOI) (N=~4.5Ã-10¹⁵ cm^-3) at 60 ^oC. An atomically flat interface was demonstrated without the formation of any silicide materials.[3] An n⁺-Si layer (Sb: 1Ã-10¹⁹ cm^-3) was inserted between CoFe and SOI. Conventional processes with electron-beam lithography and Ar⁺ ion milling were used to fabricate three-terminal lateral devices with a backside gate electrode. With a constant source-drain bias voltage, the source-drain current I gradually increased by applying the gate voltage (V_G). This means that the conduction channel was formed from the vicinity of the interface between SOI and BOX, indicating that this device can operate as a MOSFET.
The three-terminal Hanle-effect measurements were performed at room temperature by a dc method. For V_G = 8.0 V at I = -1.0 µA, where the electrons were injected from the CoFe electrode into the Si channel, a clear voltage change (Î"V) caused by the spin accumulation and its depolarization in the Si channel was observed even at room temperature. The magnitude of Î"V, |Î"V|, was ~11.5 µV. When the gate voltage was further applied up to V _G = 54 V, |Î"V| was decreased to ~7.8 µV surprisingly despite the same value of the injection current. A lower limit of spin lifetime for V _G = 8.0 and 54 V can be estimated to be ~ 1.30 and ~ 1.27 nsec, respectively. According to the simple spin-diffusion model, the reduction in the |Î"V| can be explained by the change in the channel resistance by applying V _G . Therefore, this feature indicates reliable evidence for the spin injection into an intrinsic Si channel.
This work was partly supported by PRESTO-JST and STARC.
[1] Y. Ando et al., Appl. Phys. Lett. 94, 182105 (2009). [2] Y. Ando et al., Appl. Phys. Lett. 99, 012113 (2011). [3] Y. Maeda et al., Appl. Phys. Lett. 97, 192501 (2010). [4] Y. Ando et al., Appl. Phys. Lett. 99, 132511 (2011).

Thermal Diode (rectifier), in which thermal conductance depends on the sign of the thermal gradient, representing an advanced thermal management, is critical for thermal energy conversion and the future electronic cooling. Despite the fact that multiple mechanisms have been proposed for thermal rectification, high performance thermal rectification has rarely been achieved. Here for the first time, thermal rectification (20%) is observed in metal-insulator interfaces. More strikingly, the thermal rectification can be turned on/off by a third terminal. Therefore it represents a significant advancement towards a three-terminal thermal transistor. With the high performance, nanoscale size and unique property, this type of thermal rectifier can serve as a novel building block for the future development of thermal circuit.

In this work, we investigated the electronic structure of various molecule/electrode interfaces by Transition Voltage Spectroscopy (TVS). We fabricated molecular junctions with various electrodes: semiconductor (silicon with and without native oxide), oxide-free metal (gold) and oxidized metals (aluminum, mercury and eutectic GaIn). Self Assembled Monolayers (SAM) formed the organic materials in the junctions: alkyl-thiol molecules (CH3-(CH2)n-SH) grafted on gold substrate, alkyl-alcene molecules (CH=CH2-(CH2)n-CH3) on hydrogenated silicon and alkyl-trichlorosilane (CH3-(CH2)n-SiCl3) on naturally oxidized silicon. Various approaches were used to electrically characterize the SAM: from nanocontact (Conducting-AFM with gold tip) to macroscopic contact (micro-pore junction, aluminum patterns, eGaIn and mercury drop). The TVS was introduced to measure the energy offset Î" (i.e. the position of one of the molecular orbitals with respect to the electrode Fermi energy) at the electrode/molecule interface in a molecular junction [1;2]. The voltage Vmin obtained at the minimum of the Fowler-Nordheim graph (i.e. a plot of ln(I/V^2) against 1/V) scales linearly with the energy offset (Î"=α.Vmin with 1<α<2) [3;4]. Albeit, the exact value of α and the physical origin of Vmin are still under debate [3-5] TVS has became an increasingly popular tool in molecular electronics. Our results show that Vmin measured for the thiol junctions by C-AFM (without oxide at both interfaces), is 1.27±0.07V, in agreement with Beebe et al. [1;2]. In the same way, for the Si/alcene junctions measured by C-AFM, the value of Vmin of 0.96±0.15V is close to the LUMO-Si CB offset of 1.5eV as measured by transport experiments and IPES [6] (regardless the α factor). These two families of â?ocleanâ? junctions (without oxide at the interfaces) present higher values for Vmin than junctions with oxide. Indeed, by using an oxidized electrode (Al, Hg or eGaIn) on alcene SAM, Vmin decreases to 0.2-0.4V. Similarly, for trichlorosilane junctions on slightly oxidized Si substrate, Vmin values are also low ca. 0.25V. These results are understood if Vmin is ascribed to the situation when the tail of a density-of-states (DoS) enters the energy window defined by the applied bias [5], this DoS being related to the molecular orbitals (HOMO or LUMO) in the case of "clean" junctions (with Vmin>1V), and due to some oxide states in the other cases (Vmin<0.4eV). To conclude, even if the precise determination of the molecular orbital energy by TVS is still under debate, this method seems a good approach for a quick assessment of the quality of the molecule/electrode interfaces in molecular junctions. [1] J.M. Beebe et al., Phys. Rev. Lett., 2006, 67, 026801 [2] J.M. Beebe et al., ACS Nano, 2008, 2, 827 [3] E.H. Huisman et al., Nano Letters, 2009, 9, 3909 [4] J. Chen et al., Phys. Rev. B, 2010, 82, 121412 [5] M. Araidi et al., Phys. Rev. B, 2010, 235114 [6] A. Salomon et al., Phys. Rev. Lett., 2005, 95, 266807

Nanomechanical logic based on nanoelectromechanical systems (NEMS) switches promises a significant reduction in total switching energy over conventional, solid-state logic. This has merited its inclusion in the International Technology Roadmap for Semiconductors as an Emerging Research Device. However, the reliability of the contact interface of these ohmic switches is a crucial barrier to their commercialization. The adhesiveness and reactivity of conventional contact materials (i.e. metals) results in permanent adhesion, or the buildup of insulating tribofilms, at the contact. In the present study, atomic force microscopy (AFM) was used to efficiently evaluate 1) the lifetime response of conductivity and adhesion for conventional, metallic nanocontacts (platinum) and 2) the robustness of a possible next-generation contact material (conductive diamond). The lifetime response of conductivity and adhesion of platinum-platinum single asperity contacts subjected to forces relevant to NEMS logic operation were investigated using amplitude modulation AFM. Applied electrical potentials at the contact interface and relative humidity (RH) during testing were chosen to mimic anticipated (<1 V and near 0% RH) and extreme (5 V and 50% RH) variants of the operational environment of NEMS logic. We simultaneously measured the electrical and adhesive performance of the nanocontacts for up to 200 million contact cycles. Results show significant fluctuations in contact resistance and adhesive force when tested in high RH with high (5.0 V) electrical potentials. This behavior illustrates the need to consider alternate materials for NEMS contacts. Ultrananocrystalline diamond (UNCD) is a promising candidate for a next-generation NEMS logic contact material; it has chemical inertness, tunable electrical conductivity via nitrogen incorporation (N-UNCD), and ultralow adhesion and wear. Here we assess the robustness of N-UNCD under applied contact stresses and electrical potentials. A platinum-coated AFM tip was raster-scanned over N-UNCD surfaces with MPa-to-GPa applied contact stresses, a variable bias (0.0-10.0 V), and variable relative humidity (<5 - 45%). Changes to carbon and oxygen bonding in the scanned surface regions were then interrogated using photoelectron emission microscopy. N-UNCD showed no observable chemical modification or buildup of insulating tribofilms in the absence of wear-through of the platinum coating on the AFM tip. These findings show that N-UNCD is tribologically robust under extreme contact stresses and electric fields, which are relevant to NEMS switch environments. Together, these results demonstrate the critical advantage of using AFM to study contact reliability. Specifically, AFM enables quantitative, fundamental studies at single asperity contacts which can be evaluated both in situ and ex situ to elucidate, for the first time, the physical processes that dominate nanoscale switch contact performance.

Recent advances in nanotechnology have offered the hope of extending Mooreâ?Ts law of large scale integration of semiconductor device circuits to nanodevices. Nanostructures based on Si and silicides will play an important role in future semiconductor technology. Transition metal silicide nanowires are strong candidates for circuit elements in one-dimensional nanodevices, with applications including ohmic contacts, Schottky barriers, gate electrodes and interconnects. In this talk, I will present in-situ high resolution transmission electron microscopy of solid-state chemical reactions in such nanostructures. Silicidation reactions take place at the point contact between adjacent nanowires or nanoparticles, and high resolution imaging allows the reaction to be followed in real time as each layer of Si is transformed. It is possible to control the formation of the metal silicide accurately enough to fabricate nano-gap heterostructures, where silicide regions are separated by just a few atomic planes of Si. The atomic-level details of the growth process can also be examined directly, and I will show axial epitaxial stepwise growth of CoSi2, NiSi, and NiSi2 in silicon nanowires. This growth process is unique, in that each atomic plane of silicide nucleates at the center of the nanowire cross-section in a homogeneous nucleation event that had been theoretically predicted but not observed previously. The oxidized surface structure of the nanowire is of key importance in this nucleation and growth process, and I will discuss the differences in growth mechanism and morphology when silicidation reactions are carried out in-situ on nanowires with atomically clean surfaces. I will finally discuss new nanostructures in free standing nanowires and the integration between group IV nanowire silicides and group III-V materials which are potentially useful in future nanodevices.

Nickel silicide (NiSi) is being used as an industry standard for ohmic contacts and local interconnect. Low resistance contacts have been a great challenge for the semiconductor industry. To achieve these it is really important to understand the silicide growth on silicon. This study is to model the growth of nickel silicide accurately using the level set method [1] for interface propagation that has been used previously for etching, deposition and SPER [2]processes. NiSi growth has been observed to follow a linear-parabolic law which takes into account both diffusion and interfacial reaction. This linear-parabolic system is very similar to the Deal and Grove model of SiO2 growth, our model uses similar diffusion transport and reaction rate equations. We have modeled the growth of silicide coupling diffusion solutions to level-set techniques. Dual level sets has been used for top and bottom interface propagation of silicide; velocities were estimated based on nickel concentrations at both interfaces as well as diffusivity and reaction rate of nickel. This is important to predict precise shape of silicide that will allow current crowding and field focusing effects to be modeled in transport out of the intrinsic device into the contacting layers. These simulation models can be used for latest technology nodes at 45, 32, 22nm and special devices such as FinFETâ?Ts etc. We have successfully implemented and verified the shapes in FLOOPS (Florida Object Oriented Process Simulator) and they match well with the literature TEM (Transmission Electron Microscope) data. [1] Level set methods and fast marching methods. J.A. Sethian, Cambridge University Press, 1999 [2] Level set modeling of the orientation of SPER. Journal of Vac. Sci. Tech. B 26(1) 2008. S. Morarka and M.E.Law

In this study we describe a novel process to induce a Rectifying-to-Ohmic phase transformation in Silicon. Nickel-rich amorphous Silicon surface layers were prepared in crystalline substrates by ion-implantation. The surface layers were then mechanically deformed via controlled nanoindentation. The â?oin-situâ? electrical response of the various films during indentation was found to be extremely sensitive to the amount of implanted Nickel, with a substantial increase in the measured through-tip current (through the indented zone), and the formation of a highly conductive surface region upon unloading. The current-voltage curves extracted within this conductive surface region show that for Ni concentrations in excess of 3.3 at. %, a Rectifying-to-Ohmic phase transformation occurs. The transformation was observed in samples both with, and without a characteristic â?opop-outâ? event related to the formation of the high pressure phases of Silicon, indicative that only the mechanical confinement of this material is needed to induce this transformation. Post-indentation characterization of the indents with Raman spectroscopy also show a concentration-dependent formation of high-pressure phases, with no clear evidence of the formation of a silicide phase. Our results have potential applications in the controlled fabrication of Ohmic contacts in low-dimensional electronic device structures, where overcoming the negative effects of contact resistance are important for improving device performance.

Recent attention has shifted to nickel silicide as a replacement for CoSi₂ as a contact material for device structures due to its lower resistivity at smaller dimensions, uniform planar growth, and lower silicon consumption [1]. The presence of impurities at the Ni/Si interface changes the kinetics of the corresponding solid-state reaction, hence nickel silicide formation. The presence of oxygen at the original Ni/Si interface was observed to induce source-limited growth while SiO₂ layers as thin a 0.5 nm can serve as ideal diffusion barriers for nickel [2]. Films with nominal thicknesses of 5nm and 15nm were deposited on silicon substrates that were covered with a native oxide layer. In-situ heating techniques were used inside a Transmission Electron Microscope to observe the kinetics of the Ni thin film when oxygen is present at the interface. Scanning Transmission Electron Microscopy (STEM) together with Electron Energy Loss Spectroscopy (EELS) was used to characterize structural and compositional gradients across the interface before and after in-situ annealing. Multi-layered interface structures were observed from the as-deposited films. It was found that Ni atoms diffused through the oxide layer to form nickel silicides with varying compositions. Instrinsic stress in the metallic nickel film were found to be the significant driving force for diffusion at low temperatures. In an attempt to reach thermodynamic equilibrium two competing mechanisms occurred during in-situ annealing, where Ni continued to diffuse through the SiO₂ layer to from NiSi₂, while the remaining Ni film agglomerated. Alloying of nickel films with 5-10% Pt was observed to change the kinetics of silicide formation, increasing the formation temperature of NiSi₂ and preventing NiSi agglomeration [3]. Ni films alloyed with 0%, 5%, and 10% Pt were sputtered on Si (100). The Ni_xPt_1-x films underwent two rapid thermal annealing (RTA) steps, with the first RTA step at either 280°C or 330°C and a finial RTA step of 500°C. STEM-EELS was used to characterize the atomic structure and chemistry at the Ni(Pt)Si/Si interface. Minimal Pt segregation was observed at the film/substrate interface. A chemically diffuse interface with a width ranging between 10-20 nm developed through Ni diffusion into the Si substrate. Ni was found to occupy several different interstitial configurations as well as substitutional sites in the Si lattice. The presence of small amounts of Pt as well as the diffuse interface structure caused alterations of the Schottky barrier height with characteristics typical for a PtSi/Si interface.[1] Lavoie C, d'Heurle FM, Detavernier C, Cabral C., Microelectronic Engineering 70, 144 (2003).[2] Mayer JT, Lin RF, Garfunkel E., Surface Science 102, 265 (1992). [3] Mangelinck D, Dai JY,Pan JS, and Lahiri SK, Applied Physics Letters 75, 1736 (1999).

Using density functional theory we study platinum monosilicides which have recently attracted significant interest. PtSi has a low p-type Schottky barrier height (SBH) (0.2eV) to Si (001) and exhibits excellent thermal stability. However, it suffers of relatively low conductivity compared for example to pure Pt which can be traced to the low density of states (DOS) at the Fermi level. We investigate the possibility of manipulating the DOS at the Fermi level by alloying PtSi with Ti. Ti is almost equal in size with Pt but contributes only 4 valence electrons (versus ten contributed by Pt). For increasing Ti concentrations we find a general increase in the carrier density at the Fermi level compared to bulk PtSi. We determine the solubility limit of Ti in PtSi and analyze its influence on the work function and Schottky barrier height to Si (001). We estimate the change in conductivity in TixPt1-xSi compared to bulk PtSi due to ion impurity scattering using Boltzmann transport theory with the collision integral calculated from first principles. We find that co-doping with gallium or aluminum can further increase Tiâ?Ts solubility limit in PtSi.

With continued scaling of CMOS technology, the metallurgical contact between the interconnect metallization and the semiconductor device increasingly contributes to the overall external resistance of devices, causing significant degradation in performance. As a result, a better understanding of the fundamental factors affecting the resistance of the silicide contact to the semiconductor device becomes critical in order to mitigate the impact of scaling. To address this unacceptable increase in resistance of the silicide-semiconductor interface when the contact length is reduced below 50 nm, we have developed a methodology and built corresponding test sites to accurately determine specific contact resistivity of selected materials and processes. Using this method we have demonstrated a variety of ways to engineer the effective Schottky barrier height in nano dimensions which results in improved device performance. In addition to the degraded electrical behavior of the silicide/semiconductor interface for reduced dimensions, the microstructural development and phase formation during annealing also becomes a significant source of variability. Utilizing a high intensity synchrotron x-ray source coupled with a sample heater and fast multipoint detectors, we have performed rapid collection of crystallographic data in-situ as a function of temperature. With this approach we have studied thin film silicide phase evolution for Ni based alloys. Using this in-situ system with customized test sites, we have determined the impact of physical dimensions on both microstructure evolution and silicide phase formation. In particular, we show a delay in the formation of the monosilicide for the Ni-Pt alloy system at smaller dimensions.

This talk will focus on recent advancements in the formation of ultrathin Ni_1-xPt_x silicide films targeting CMOS technology nodes beyond 22 nm where silicide films much thinner than 10 nm are required according to the technology roadmap. The past experience in using metal silicides for various generations of CMOS technology indicates that control of the silicide formation in the sub-10 nm regime is a foremost urgent issue especially for devices fabricated on UTB/ETB-SOI (ultrathin-body/extremely-thin-body silicon-on-insulator) substrates or with nanowire-like Fins. Our recent results show that both initial metal thickness and Pt fraction in the as-deposited Ni_1-xPt_x films are critical parameters determining the resultant silicide films in terms of phase formation, film thickness, specific resistivity, interfacial morphology and morphological stability at elevated temperatures. The phenomenon is discussed with a particular mention of thermodynamic effects. Surface energy plays an increasingly important role for thinner films with an increasing surface to volume ratio. To illustrate the critical importance of the entropy of mixing in the formation of ternary Ni-Pt-Si silicide alloy films, our recent results on silicide formation and subsequent morphological stability starting with ultrathin Co_1-xNi_x films are presented and discussed as well. The talk will end with the presentation of a novel and economical process for a controllable formation of Ni_1-xPt_x silicide films below 8 nm in thickness, as well as its implications in advanced CMOS technology.

For the past 40 years the subject of contact formation to n-type silicon has been one of the key areas of research in the photovoltaic community. Much recent work has been focused on two key aspects of the contacting interface in a solar cell. Firstly, what makes a good contact? Secondly how can one optimize a process to form the best contact? The first question relates to charge transport between the semi-conductor and the metal. Ideally one desires an ohmic contact, however the majority of metal/semi-conductor contacts are found to be rectifying. Although the precise pathway of an electron from the silicon to the conducting finger remains a subject of debate, it is of little doubt that the barrier which must be overcome by a carrier at the silicon/metal interface is also of great importance to the overall contact resistance. In this presentation we will demonstrate how ab initio atomistic simulations can be used to gain insight into the fundamental properties which result in a good contacting interface. We use a combination of classical inter-atomic potentials and density functional theory (DFT) methods to investigate the geometrical structure of three important Si/Ag interfaces, 111//111, 110//110 and 100//100 interfaces. Having established the geometrical structure we then investigate the electronic structure, considering electron density, gap states induced by the interface and calculate Schottky barriers for the various interfaces. The calculations reveal how different interfaces result in significantly different charge distributions at the interfaces, which in turn can be related to Schottky barrier heights by considering the dipole created by such charge distributions. Another factor which can have an important effect on the Schottky barrier at the contacting interface is the presence of phosphorous. We show how atomistic simulation can predict the degree of segregation of P to the Si/Ag interface and also examine how this affects the Schottky barrier. At high concentrations the P is found to segregate preferentially to the boundaries, although again the degree of segregation is very dependent on the Si surface involved. This segregation results in a decrease in the Schottky barrier which we can explain by investigating the charge density in the interface region. By considering the theoretically calculated Schottky barriers, we can also estimate how these factors can affect the macroscopic contact resistance. In the spirit of recent publications we use Schottky theory with a Bardeen model to estimate the effects of various interface areas and P doping levels on the contact resistance.

Higher carrier mobilities in Ge and introduction of High-K gate dielectrics in Si CMOS technology [1] have generated significant interest in Ge CMOS research. A key challenge for realization of high performance nFETs has been the high contact resistance arising from Fermi level pinning (FLP) near the valence band and low dopant activation levels.[2] The main approach to overcome this problem has centred on the introduction of a thin interfacial dielectric layer between the metal and Ge layers to alleviate FLP.[2] However, the interfacial film adversely impacts the contact resistance by adding a series tunneling resistance, and converts p-Ge contacts from Ohmic to rectifying.[2] A process that can form low resistance n and p contacts simultaneously would be highly beneficial from the viewpoint of process integration complexity and fabrication costs. In this work we demonstrate a method for forming quasi-Ohmic contacts to n-Ge and Ohmic contacts to p-Ge simultaneously using metal work function (WF) engineering. A triple interface is formed on Ge surface by embedding self-assembled nanocrystals (NC) of a higher WF metal (Au) in a lower WF metal (Ti). The difference in WF at this triple interface of Ti/Au/Ge creates a high local electric field which reduces the tunneling depletion width of the Schottky contacts. This significantly enhances the tunneling current for pinned n-Ge Schottky contacts without degrading Ohmic p-Ge contacts. While this method has been previously shown to reduce contact resistance on Si [3], this is the first report of its application to Ge contacts. N-Ge (0.01 Ohm cm) and p-Ge (1-10 Ohm cm) wafers were cleaned using a HF:DI process and a thin (2 nm) film of Au was deposited using a PVD process. Annealing at 400oC for 30s resulted in the formation of Au NCs (~10nm in diameter) along with the growth of a thin surface/interface layer (IL, ~3-5nm). I-V characteristics of samples that skip the Au deposition, but go through the anneal process, show that the IL partially unpins the Fermi level on n-Ge but undesirably converts p-Ge contacts from Ohmic to rectifying. A short 120s HF:DI wet etch was used after NC formation to remove the IL without affecting the NCs. Finally, a top Ti metal contact was deposited using e-beam evaporation. The resulting I-V characteristics for the Ti/Au NC devices on n-Ge are quasi-Ohmic (Ion/Ioff10 [2]) with 1000x increase in current versus Au and Ti control Schottky contacts. The Ti/Au NC/p-Ge contacts stay Ohmic, similar to the control Ti/p-Ge devices. Temperature-based measurements on the NC contacts show tunneling-dominated transport as expected from the enhanced electric field at the Au/Ti/Ge interface. In summary, this work demonstrates a potential â?oCMOSâ? solution (i.e., a single process for both p and n FETs) to the problem of Fermi-level pinning on n-Ge. References: [1] K. Mistry et al., IEDM, 2007. [2] T. Nishimura et al., Appl. Phys. Exp. 1, 2008. [3] V. Narayanan et al., IEDM, 2000.

The formation of Ohmic contacts in the presence of interface states requires high doping of the near-contact region. In the absence of quantitative knowledge of the dopant distribution, contact optimization in nanowires proceeds empirically. We have used atom probe tomography (APT) to establish the concentration and distribution of dopants in silicon nanowires, finding that substantial unintentional enrichment in surface doping has facilitated the formation of Ohmic contacts to nanowires grown by metal nanoparticle catalyzed chemical vapor deposition. Specific contact resistances are in general agreement with measured near-interface doping levels. However, geometry is understood to play an important role in modification of contact resistance, and the presence of additional interface states at the nanowire surface may also modify the junction characteristics compared 1-D models of planar interfaces. In this context, improved measurements and models of Schottky barrier heights and their voltage dependencies are needed to enable contact optimization. We will describe a multi-pronged approach to quantitative analysis of nanowire contacts, focused on barrier height measurement by internal photoemission employing spectrally resolved scanning photocurrent microscopy (SPCM). Such measurements are an essential addition to I-V characterization given their insensitivity to the ideality factor (or Richardson constant). In addition, we will describe complementary measurements by Kelvin probe force microscopy (KPFM) and ballistic electron emission microscopy (BEEM) carried out by collaborators in the Rosenwaks and Pelz groups, respectively. Modeling and simulation are used to reveal the influence of nanowire surface states and bulk impurities on the junction characteristics.

Contacts to semiconductor nanowires are required for a variety of electronic and optoelectronic devices under development today, including transistors, chemical and biological sensors, and solar cells. Depending on the intended application, the nanowires may truly be nanoscale in diameter or may actually approach the microscale. In addition, the nanowires may be prepared from vapor sources using techniques such as vapor-liquid-solid (VLS) growth, or they may be etched from wafers or epilayers. This presentation will focus on contacts to both types of nanowires from the group IV and III-V families of semiconductors. The discussion will begin with a description of techniques to measure the specific contact resistance of ohmic contacts and barrier heights of Schottky contacts, with special attention paid to how to handle the effect of inhomogeneous doping and tapering that occurs in some VLS nanowires, as well as the influence of the semiconductor surface adjacent to the contacts when the nanowires are very small. Next, the influence of the nanowire geometry on phase transformations will be explored, relying primarily on data from transmission electron microscopy and field emission scanning electron microcopy. Because of the wide availability of thin-film data for comparison, special attention will be paid to interfacial reactions that occur upon annealing contacts to silicon nanowires. Trends for metals across the periodic table will be described, including the behavior of early (Ti and V), middle (Fe) and late (Co, Ni, Pd, and Pt) transition metal contacts. Data will also be presented on the effect of nanowire orientation and diameter on the particular silicides that form and their growth rates. These results will be interpreted considering crystallographic, thermodynamic, and kinetic factors. Finally, challenges worthy of future study will be highlighted.

The realization of low resistive electrical contacts on semiconductor nanowires (NWs) is one of the major challenges for the development of performant NW-based devices. The formation of silicided NWs is a promising approach to get a better contact reliability and reduce the defect density at the metal/NW interface. However, the silicidation process at the nanoscale as well as the current injection mechanism in such 1D nanocontacts are not yet well understood. In this paper, we investigate in detail the formation of platinum silicide/Si NW heterostructures by combining the chemical analysis of the formed phases and the kinetics of their formation with the electrical characterization of such realized nano-contacts. Firstly, the silicidation of thin NWs (down to 14nm) has been characterized by high resolution TEM coupled to EDX analysis. We demonstrate that the phase formation kinetics is reduced compared to planar silicidation and this is all the more true when the NW diameter is small. In addition, in contrast with the known silicidation of thin planar layers, the coexistence of three phases (metallic Pt, Pt2Si and PtSi) has been observed for the NWs with the smallest diameter. Based on the results of the structural analysis, the carrier injection at the nanocontact level was investigated in selected test structures containing a fully silicided PtSi/Si interface. In order to considerably attenuate variability issues associated to the stochastic nature of the fabrication process at the nanoscale, we implemented 2-terminal test structures on vertical Si NW arrays (up to 5100 NWs in parallel) defined by a top-down approach with a ultra-high density (3Ã-109 NWs/cm2), a yield of 100% and a precise control of their position and diameter (from 14 to 150 nm). In addition, vertical NWs with a reduced height (200 nm) and a high doping level (8Ã-1018 cm-3) were used so to minimize the silicon body resistance and make it lower than the contact resistance. Each NW termination was silicided and contacted to an external metal line thanks to a novel 3-dimensional process. Temperature-dependent current-voltage (I-V) measurements were performed and a systematic analysis of the carrier transport in such nanodevices has been carried out. The temperature dependence and the non-linearity of the I-V characteristics are interpreted as a clear signature of the predominance of the nanocontacts over the whole resistance of the NWs arrays. It is demonstrated that this behaviour is observed for all the investigated NWs, including those with the smallest radius (7 nm). In addition, trap-induced surface depletion is found to reduce the contact injection cross-section. As a consequence, the electrostatic environment at the border of the silicide-to-semiconductor contact interface is dominated by the field effect imposed by the peripheral surface states rather than the Schottky barrier height.

Si wire solar cells are one of the promising candidates for next-generation solar cells owing to the advantages of less silicon consumption, flexibility, and superior optical absorptance. Given wiring the emitter contacts, however, radial junction wire solar cells still face critical challenges. Most recent works regarding radial p-n junction Si wire solar cell have commonly used transparent conductive oxide (TCO) for Ohmic connection with metal grids as emitter contact, in which the optical shading loss with a high series resistance resulted critically in degrading the fill factors (FF) of Si wire solar cells. Here, we suggest a novel design for emitter metal wiring that utilizes silver emitter contacts integrated at the bottom of a wire array, not a top region of wires typically adopted in conventional wire solar cells. Finger and bus bars with TCO which were generally required for top electrodes in conventional solar cells were no longer necessary in our proposed contact design in which a high fill factor (FF) without optical shadowing loss was realized due to the low resistive nature of silver. Moreover, a silver electrode surrounding all the bottoms of wires provided a superior charge carrier collection. We experimentally varied the contact height, i.e., a thickness of a silver thin film, to determine the optimal minimum thickness of an Ag thin film for efficient conduction. As a result, a contact resistance (Rc) was found to decrease as a contact height increased; specifically, a minimum Rc was observed to saturate as a contact height was greater than 700 nm. In comparison with a Si wire solar cell integrated using a conventional front electrode at top of wires, our surrounded contact structure revealed a lower Rc due to further lowering the effective Schottky barrier height between electrode and semiconductor, which then caused a high current injection from semiconductor into electrode. In our work, use of a surrounded contact structure caused a contact resistance to decrease enough to obtain a FF of ~65%.

In low dimensional structures, unique material properties and superior functions are available due to the geometry effect. While the unique electronic, magnetic and mechanical properties of nanostructured materials have been discovered and interrogated extensively in the past few decades, fundamental material processes at this scale yet leave much to be desired for. In this talk, we present a kinetic competitive model for first phase formation of silicides in Si nanowires (Si NW) templates through systematic studies. The coexistence of multiple phases at initial stage is observed. Details of systematic behaviour about kinetic parameters are obtained through silicidation in Si NW with diameter of 20-230 nm from 300-800 Celcius. NiSi2 is found to experience the liner-parabolic transition in crystalline Si NW template. From in-situ TEM studies, key parameters such as Ni diffusivity and the activation barriers in NiSi2, the reaction constant and the reaction activation barrier at NiSi2/Si interface are systematically extracted. The parameters extracted allow for quantitative analysis of the kinetic competition which leads to the size dependant first phase selection observed in Si NWs. With the established model, we subsequently demonstrate the pathways by which we can selectively retard the growth rates of either the diffusion-controlled phase or the reaction-controlled phase and realize switching of the first phase in designed Si NW structures.

The development of Ni/Au contacts to randomly dispersed Mg-doped GaN nanowires (NWs) is examined. Current-voltage (I-V) measurements of these Mg-doped nanowire devices frequently exhibit a strong degradation after annealing. This degradation is proposed to originate from the poor wetting behavior of Ni and Au on SiO2 which can cause cracking and delamination of the metal film as well as excessive void formation at the metal/NW interface. The 3D morphology of the NWs also contributes to void formation due to the non-uniform deposition of the contact metal using electron beam evaporation. Void formation at the metal/NW interface reduces the contact area, which increases the resistance. The morphology and composition of annealed Ni/Au contacts on SiO2 and p-GaN films was investigated using scanning electron microscopy (SEM), energy-dispersive x-ray spectroscopy (EDS), and x-ray diffraction (XRD) measurements. Adhesion experiments were performed in order to determine the degree of adhesion of the Ni/Au films to the SiO2 as well as observe and analyze the morphology of the filmâ?Ts underside using SEM. Several factors that affect adhesion and void formation of the metal films have been investigated. The factors that had proven to have a considerable affect were optimized in order to minimize the degree of void formation. Pretreatment prior to metal deposition that involved the use of UV ozone treatment coupled with other cleaning processes was shown to have a significant effect on both adhesion and void formation. To address the void formation caused by the 3D morphology of the NW, the evaporator was customized to produce conformal deposition of the contact metal around the NW which increased the contact area. Use of a Ti-based adhesion layer deposited prior to the nanowire dispersal and Ni/Au deposition resolved the issue of poor adhesion of the Ni/Au to the SiO2 but did not alleviate the void formation at the metal/NW interface that is caused by the difference in diffusivity of Ni and Au. In order to decrease the void formation related to diffusion, the use of a specific adhesion layer of (Ti/Al/Ni) was necessary. XRD measurements after annealing show the formation of Al alloys with both the Ni and Au, which is believed to be the cause of the decreased void formation.

Current-voltage (I-V) measurements on GaN nanowires (NWs) are an essential and frequently-used tool for characterizing NW resistivity and contacts to NWs. As we show in this report, however, the varying morphology of NWs can have a profound impact on their I-V curves. It is therefore imperative that NW morphology be carefully considered before drawing conclusions about material transport properties or contact characteristics from I-V measurements. The NWs in this study were c-axis GaN, grown by catalyst-free MBE on Si 111. Due to the spontaneous nucleation mechanism, a variety of NW shapes and sizes was obtained from each growth run examined here. Test structures on individual NWs were fabricated by dispersing the NWs onto a SiO₂ substrate, then depositing Ti/Al pads separated by 2 to 6 µm gaps and annealing. We investigated the effects of two aspects of NW morphology. The first aspect was NW coalescence. Coalescence occurs when neighboring NWs fuse into small coalesced structures during growth. In contrast, single-crystalline NWs nucleate at a single point and remain separate from their neighbors. We measured several dozen devices made from coalesced and single-crystalline NWs, as classified by SEM inspection, from the same undoped growth run. All of the single-crystalline NW devices failed to conduct measurably above the noise level (10^-11 A), indicating that these NWs were fully depleted of free carriers due to surface band bending. In the coalesced NW devices, about 15% failed to conduct. However, the other 85% showed resistances (R_NW) ranging from 1 GΩ down to 20 kΩ, even at NW diameters (d_NW) comparable to those of single-crystalline NWs. This suggests that NW coalescence can introduce donors in numbers significantly higher than the background concentration that exists in single-crystalline NWs. Furthermore, there was no correlation between R_NW and d_NW of the coalesced NWs, and the shape of the I-V curves varied wildly, from fully rectifying to completely linear. These results would be consistent with conduction through defects introduced by coalescence rather than bulk conduction. The second aspect of NW morphology that we studied was the effect of d_NW on the shape of I-V curves in Si-doped (N_D ~ 10¹⁷ cm^-3), single-crystalline NWs. Here, conductive NWs with d_NW120 nm showed non-linear I-V curves when tested in ambient air. Ordinarily, non-linear I-V behavior is an indication of poor contacts. However, for d_NW > 120 nm from the same growth run, all I-V curves were linear, and R_NW decreased as expected with increasing d_NW. Furthermore, the linearity of the thin-NW I-V curves increased significantly when the devices were retested under vacuum. These results suggest that the deviation from linear I-V cannot be attributed to the contacts. We continue to investigate several possible alternative mechanisms for the non-linear I-V in thin NWs.

We report an experimental investigation on employing Ag nanoparticles to provide electrical and mechanical contacts between transfer-printed semiconductor devices in the shape of micro/nano wires and pillars. The Ag nanoparticles have diameters ranging between 200-600nm and are self-assembled on a 100nm Au film deposited on glass substrates. With a customized tool, an ensemble of silicon pillars were brought into contact with the Ag nanoparticles by precisely controlling the displacement and applied force (pressure). Current-voltage measurements were done at force resolution of ~0.2N. The load limit for low contact resistivity without causing pillar failure by buckling can be determined. The test method aims to illuminate the pillar-particle contact mechanism using the nanoparticles as conductive fillers for the next generation of high performance heteroepitaxial device transfer-printing applications.

CdTe based thin film solar cells represent one of the most successful solar energy harvesting technologies on the market today. Nevertheless, at â?^13 percent efficiency, commercial p-CdTe / n-CdS cells are well below the theoretical maximum value (â?^28 percent) possible for this materials system under 1-Sun illumination (100 mW/cm2). The underlying physical mechanisms which limit the efficiency of commercial CdTe / CdS cells are presently not well understood. To address this challenge, we use micro/nanocontacts to measure spatially resolved photocurrent-voltage characteristics in a scanning electron microscope and atomic force microscope and correlate these results with the local morphology, microstructure, and chemical composition. We use electron beam lithography and standard semiconductor processing to fabricate 50 nm thick Au Ohmic metal contacts that range in dimensions from the nano- to the micro- scale on the surface of p-CdTe / n-CdS junctions extracted from a commercial solar cell. Using either light or electron beam for large area or local injection of carriers, we collect the carriers locally from the contacts fabricated in the middle of the grains or at the grain boundaries. Such sets of current-voltage characteristics allow us to evaluate the impact of charge transport and recombination at the grain boundaries on device performance.