Meetings & Events

Fall 2006 logo2006 MRS Fall Meeting & Exhibit

November 27 - December 1, 2006 | Boston
Meeting Chairs:
 Babu R. Chalamala, Louis J. Terminello, Helena Van Swygenhoven

 

Symposium Y : Enabling Technologies for 3-D Integration

2006-11-27   Show All Abstracts

Symposium Organizers

Chris Bower RTI International
Phil Garrou RTI International
Kenji Takahashi Toshiba Corporation
Peter Ramm Fraunhofer Institute IZM
Y1: Fabrication of 3-D ICs
Session Chairs
Phil Garrou
Monday AM, November 27, 2006
Room 305 (Hynes)

9:30 AM - **Y1.1
CMOS-Compatible Silicon Through-vias for 3D Process Integration.

Cornelia Tsang 1 , Paul Andry 1 , Edmund Sprogis 2 , Chirag Patel 1 , Steven Wright 1 , Bucknell Webb 1 , Dennis Manzer 1 , Raymond Horton 1 , Robert Polastre 1 , John Knickerbocker 1
1 , IBM T. J. Watson Research Center, Yorktown Heights, New York, United States, 2 , IBM Systems and Technology Group, Essex Junction, Vermont, United States

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10:00 AM - **Y1.2
Recent Advances in 3D Integration at IMEC

Piet De Moor 1 , Wouter Ruythooren 1 , Philippe Soussan 1 , Bart Swinnen 1 , Kris Baert 1 , Chris Van Hoof 1 , Eric Beyne 1
1 MCP, IMEC, Leuven Belgium

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10:30 AM - **Y1.3
Integration Technologies for 3D Systems

Armin Klumpp 1 , Peter Ramm 1 , Robert Wieland 1 , Karl-Reinhard Merkel 1
1 Si & VSI, Fraunhofer Institute IZM-Munich, Munich Germany

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11:00 AM -
BREAK

11:30 AM - **Y1.4
High Density Direct Bond Interconnect Technology™ for Three Dimensional Integrated Circuit Applications.

Paul Enquist 1
1 , Ziptronix, Inc., Morrisville, North Carolina, United States

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12:00 PM - **Y1.5
3-D Integration Latest Developments at LETI.

Barbara Charlet 1
1 LETI/DIHS/LTFC, CEA/Grenoble, Grenoble France

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12:30 PM - **Y1.6
Through Wafer Interconnects for 3-D Packaging.

Amy Moll 1 , Rex Oxford 1 , William Knowlton 1
1 Materials Science and Engineering, Boise State University, Boise, Idaho, United States

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Y2: Modeling and Design for 3-D Integration
Session Chairs
Chris Bower
Monday PM, November 27, 2006
Room 305 (Hynes)

2:30 PM - **Y2.1
Exploration of the Scaling Limits of 3D Integration.

Scott Pozder 1 , Robert Jones 1 , Vance Adams 1 , Hui-feng Li 2 , Michael Canonico 1 , Stefan Zollner 1 , Sang Hwui Lee 2 , Ronald Gutmann 2 , Jian Lu 2
1 Technology Solutions Organization, Freescale Semiconductor Inc., Austin, Texas, United States, 2 Interconnect Focus Center, Rensselaer Polytechnic Institute, Troy, New York, United States

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3:00 PM - **Y2.2
Modeling and Simulation of Parasitic Effects in Stacked Silicon.

Gunter Elst 1 , Peter Schneider 1 , Peter Ramm 1
1 EAS, FhG-IIS, Dresden, Saxony, Germany

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3:30 PM -
BREAK

4:30 PM - **Y2.3
Contactless and Via'd High-Throughput 3D Systems.

Paul Franzon 1 , Rhett Davis 1 , Michael Steer 1 , John Wilson 1 , Jian Xu 1 , Hua Hao 1 , Steve Lipa 1 , Korey Schoenfliess 1
1 ECE, NC State University, Raleigh, North Carolina, United States

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5:00 PM - **Y2.4
Thermo-Mechanical Reliability of 3D-integrated Microstructures in Stacked Silicon

Bernhard Wunderle 1 , Eberhard Kaulfersch 3 , Peter Ramm 2 , Bernd Michel 1 , Herbert Reichl 4
1 MMCB, Fraunhofer IZM, Berlin Germany, 3 , AMIC, Berlin Germany, 2 VSI, Fraunhofer IZM, Munich Germany, 4 , Technical University Berlin, Berlin Germany

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2006-11-28   Show All Abstracts

Symposium Organizers

Chris Bower RTI International
Phil Garrou RTI International
Kenji Takahashi Toshiba Corporation
Peter Ramm Fraunhofer Institute IZM
Y3: Applications of 3-D Integration
Session Chairs
Peter Ramm
Tuesday AM, November 28, 2006
Room 305 (Hynes)

9:30 AM - **Y3.1
3D Integration of Silicon Chips for Automotive Applications- Getting Started -

Werner Weber 1
1 AIM TI MUC FP, Infineon Technologies, Munich Germany

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10:00 AM - **Y3.2
Design and Fabrication of 3D Microprocessors.

Patrick Morrow 1 , Bryan Black 1 , Mauro Kobrinsky 1 , Sriram Muthukumar 1 , Don Nelson 1 , Chang-Min Park 1 , Clair Webb 1
1 , Intel Corporation, Hillsboro, Oregon, United States

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10:30 AM - **Y3.3
Three Dimensional lsi Integration Technology by ``chip on chip", ``chip on wafer" and ``wafer on wafer" with ``system in a package".

Manabu Bonkohara 1 2 , Makoto Motoyoshi 1
1 President, ZyCube Co., Tkoyo Japan, 2 Collaborative research Center for Advanced Science and Technologies, Osaka Univ., Suita Japan

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11:00 AM -
BREAK

11:30 AM - **Y3.4
3-D Integration Technology for High Performance Detector Arrays

Dorota Temple 1
1 Center of Materials and Electronics Technologies, RTI International, Research Triangle Park, North Carolina, United States

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12:00 PM - **Y3.5
Three-Dimensional Integrated Circuit Fabrication Technology for Advanced Focal Planes.

Craig Keast 1 , Brian Aull 1 , James Burns 1 , Chenson Chen 1 , Jeff Knecht 1 , Brian Tyrrell 1 , Keith Warner 1 , Bruce Wheeler 1 , Vyshi Suntharalingam 1 , Peter Wyatt 1 , Donna Yost 1
1 , MIT Lincoln Laboratory, Lexington, Massachusetts, United States

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12:30 PM - **Y3.6
Development of 3D-Packaging Process Technology for Stacked Memory Chips

Toshiro Mitsuhashi 1 , Yoshimi Egawa 1 , Osamu Kato 1 , Yoshihiro Saeki 1 , Hidekazu Kikuchi 1 , Shiro Uchiyama 2 , Kayoko Shibata 2 , Junji Yamada 2 , Masakazu Ishino 2 , Hiroaki Ikeda 2 , Nobuaki Takahashi 3 , Yoichiro Kurita 3 , Masahiro Komuro 3 , Satoshi Matsui 3 , Masaya Kawano 3
1 , Oki Electric Industry, Tokyo Japan, 2 , Elpida Memory, Kanagawa Japan, 3 , NEC Electronics, Kanagawa Japan

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Y4: Wafer Bonding Technology
Session Chairs
Thorsten Matthias
Tuesday PM, November 28, 2006
Room 305 (Hynes)

2:30 PM - **Y4.1
Silicon Layer Stacking Enabled by Wafer Bonding

Chuan Seng Tan 1
1 Electrical Engineering, MIT, Cambridge, Massachusetts, United States

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3:00 PM - **Y4.2
Damascene Patterned Metal/Adhesive Redistribution Layers.

Ronald Gutmann 1 , J. Jay McMahon 1 , Jian-Qiang Lu 1
1 Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York, United States

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3:30 PM - Y4.3
Capillary Assisted Wafer-Level Alignment

Michael Tupek 1 , Kevin Turner 1
1 Mechanical Engineering, University of Wisconsin-Madison, Madison, Wisconsin, United States

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3:45 PM - Y4.4
Room-Temperature Cu-Cu Bonding: Implications for 3D ICs.

Rajappa Tadepalli 1 , Carl Thompson 1
1 Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States

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4:00 PM -
BREAK

4:30 PM - **Y4.5
Vertical Integration: A Confederacy of Alignment, Bonding, and Materials Technologies.

Shari Farrens 1
1 , Suss Microtec, Waterbury Center, Vermont, United States

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5:00 PM - Y4.6
Characterization and Requirements for Cu-Cu bonds for 3D Integrated Circuits.

Rajappa Tadepalli 1 , Carl Thompson 1 , Kevin Turner 2
1 Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States, 2 Mechanical Engineering, University of Wisconsin-Madison, Madison, Wisconsin, United States

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5:15 PM - Y4.7
Low Temperature Copper-Nanorod Bonding for 3D Integration

Pei-I Wang 1 , Tansel Karabacak 1 , Jian Yu 1 , Hui-Feng Li 1 , Gopal Pethuraja 1 , Jian-Qiang Lu 1 , Toh-Ming Lu 1
1 Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York, United States

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5:30 PM - Y4.8
3D Process Integration – Wafer-to-Wafer and Chip-to-Wafer Bonding.

Thorsten Matthias 2 , Markus Wimplinger 2 , Stefan Pargfrieder 1 , Paul Lindner 1
2 , EV Group Inc., Tempe, Arizona, United States, 1 , EV Group, St. Florian/Inn Austria

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5:45 PM - Y4.9
High-Performance Temporary Adhesives for Wafer Bonding Applications

Rama Puligadda 1 , Sunil Pillalamarri 1 , Chad Brubaker 2 , Markus Wimplinger 2 , Stefan Pargfrieder 3
1 R&D, Brewer Science,Inc., Rolla, Missouri, United States, 2 , EV Group, Tempe, Arizona, United States, 3 , EV Group, Scharding, St. Florian , Austria

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2006-11-29   Show All Abstracts

Symposium Organizers

Chris Bower RTI International
Phil Garrou RTI International
Kenji Takahashi Toshiba Corporation
Peter Ramm Fraunhofer Institute IZM
Y5: 3-D Packaging
Session Chairs
Kenji Takahashi
Wednesday AM, November 29, 2006
Room 305 (Hynes)

9:30 AM - **Y5.1
Silicon Through-hole Interconnection for 3D-SiP Using Room Temperature Bonding

Naotaka Tanaka 1 , Yasuhiro Yoshimura 1 , Takahiro Naito 2 , Takashi Akazawa 2
1 , Hitachi, Ltd. Mechanical Engineering Research Laboratory, Hitachinaka, Ibaraki, Japan, 2 , Renesas Technology Corp., Kodaira-shi, Tokyo, Japan

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10:00 AM - **Y5.2
Current Status of LSI Micro-fabrication and Future Prospect for 3D System Integration.

Kazuya Okamoto 1
1 Center for Advanced Science and Innovation, Osaka University, Osaka Japan

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10:30 AM - **Y5.3
Active Interposer : Combination of Through-Si Vias and Redistribution.

Kazumi Hara 1
1 Advanced technology development center, Seiko Epson corporation, Fujimi-machi,Suwagun,, Nagano-ken, Japan

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11:00 AM -
BREAK

11:30 AM - **Y5.4
Multi-Stacked Flip Chips with Copper Plated Through Silicon Vias and Re-distribution for 3D System-in-Package Integration.

Ricky Lee 1 2 , Ronald Hon 1
1 Center for Advanced Microsystems Packaging, Hong Kong University of Science and Technology, Kowloon Hong Kong, 2 Advanced Materials, Nano and Advanced Materials Institute (NAMI), Kowloon Hong Kong

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12:00 PM - **Y5.5
CMOS Proximity Wireless Communications for 3-D Integration

Tadahiro Kuroda 1
1 EE, Keio University, Yokohama Japan

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12:30 PM - Y5.6
Fabrication and Evaluation of 3-D SiP with Through Hole Via.

Dong Min Jang 1 , Byeong Hoon Cho 1 , Kwang Yong Lee 2 , Chung Hyun Ryu 1 , Gun Ho Chang 2 , Min Seung Yoon 4 , Yang Ho Kim 3 , Won Jong Lee 1 , Tae Sung Oh 2 , Jae Ho Lee 2 , Young Ho Kim 3 , Joung Ho Kim 1 , Young Chang Joo 4 , Jin Yu 1
1 Center for Electronic Packaging Materials, KAIST, Daejeon Korea (the Republic of), 2 Center for Electronic Packaging Materials, Hongik University, Seoul Korea (the Republic of), 4 Center for Electronic Packaging Materials, Seoul National University, Seoul Korea (the Republic of), 3 Center for Electronic Packaging Materials, Hanyang University, Seoul Korea (the Republic of)

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12:45 PM - Y5.7
Filling of Very Fine via Holes for 3-D SiP by Using Ionized Metal Plasma Sputtering and Electroplating.

Byung-Hoon Cho 1 , Jae-Jin Yoon 1 , Jae-Seung Moon 1 , Won-Jong Lee 1
1 Center for Electronic Packaging Materials (CEPM), KAIST, Taejon Korea (the Republic of)

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Y6: Enabling Materials and Processes for 3-D Integration
Session Chairs
Amy Moll
Wednesday PM, November 29, 2006
Room 305 (Hynes)

2:30 PM - **Y6.1
Materials Aspects to Consider in the Fabrication of Through-Silicon Vias.

Susan Burkett 1 , L. Schaper 2 , T. Rowbotham 2 , J. Patel 2 , T. Lam 2 , I. Abhulimen 2 , M. Gordon 3 , L. Cai 2
1 , NSF, Arlington, Virginia, United States, 2 Electrical Engineering, University of Arkansas, Fayetteville, Arkansas, United States, 3 Mechanical Engineering, University of Arkansas, Fayetteville, Arkansas, United States

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3:00 PM - **Y6.2
Through-Silicon-Via Copper Deposition for Vertical Chip Integration.

Bioh Kim 1
1 ECD Division, Semitool, Inc., Kalispell, Montana, United States

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3:30 PM - Y6.3
Grinding and Mixed Silicon Copper CMP of Stacked Patterned Wafers for 3D Integration.

Koen De Munck 1 , Jan Vaes 1 , Lieve Bogaerts 1 , Piet De Moor 1 , Chris Van Hoof 1 , Bart Swinnen 1
1 , IMEC vzw, Leuven Belgium

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3:45 PM - Y6.4
Superconformal Film Growth: Mechanism and Quantification.

Thomas Moffat 1 , Daniel Wheeler 1 , Soo-Kil Kim 1 , Daniel Josell 1
1 , NIST, Gaithersburg, Maryland, United States

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4:00 PM -
BREAK

4:30 PM - **Y6.5
Novel Wafer Dicing and Chip Thinning Technologies Realizing High Chip Strength

Shinya Takyu 1 , Tetsuya Kurosawa 1 , Noriko Shimizu 1 , Susumu Harada 1
1 , Toshiba Corpration, Kawasaki, Japan

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5:00 PM - Y6.6
Assembly and Integration of Thin Bare Die Using Laser Direct-Write.

Alberto Pique 1 , Ray Auyeung 1 , Heungsoo Kim 1 , Scott Mathews 2
1 Materials Science & Technology Division, Naval Research Laboratory, Washington, District of Columbia, United States, 2 Department of Electrical Engineering, The Catholic University of America, Washington, District of Columbia, United States

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5:15 PM - Y6.7
Crystallization of semiconductor islands on amorphous substrates.

Filip Crnogorac 1 , Daniel Witte 1 , Qiangfei Xia 2 , Shashank Sharma 3 , Amir Yasseri 3 , Stephen Chou 2 , Ted Kamins 3 , Fabian Pease 1
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 Electrical Engineering, Princeton University, Princeton, New Jersey, United States, 3 Quantum Science Research, Hewlett-Packard Laboratories, Palo Alto, California, United States

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5:30 PM - Y6.8
The Deposition Kinetics of Thin Ruthenium and Copper Films in Supercritical Carbon Dioxide for 3-D Structures.

Christos Karanikas 1 2 , James Watkins 2
1 Chemical Engineering, University of Massachusetts - Amherst, Amherst, Massachusetts, United States, 2 Polymer Science and Engineering, University of Massachusetts - Amherst, Amherst, Massachusetts, United States

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5:45 PM - Y6.9
Highly (100) Oriented Si Thin Films onto Insulator Substrates using Ultra-thin γ–Al2O3 by Oxidized (002) AlN Buffer Layer.

Wenxu Xianyu 1 , Hyuck Lim 1 , Huaxiang Yin 1 , Hans s Cho 1 , Junho Lee 2 , Youngnam Kwon 2 , Junghyun Lee 3 , Youngsoo Park 1
1 Semiconductor Device & Material Lab, Samsung Advanced Institute of Technology, Suwon, Gyunggi-Do, Korea (the Republic of), 2 AE Center, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of), 3 Nano Fabrication Technology Center, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of)

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