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Symposium F: Materials, Technology, and Reliability of Low-k Dielectrics and Copper Interconnects

Symposium F: Materials, Technology, and Reliability of Low-k Dielectrics and Copper Interconnects Image

Chairs | Symposium Support | Tutorial  | Original Call for Papers

Tuesday Sessions | Wednesday Sessions | Thursday Sessions | Friday Sessions

April 17 - 21, 2006
Chairs
Ting Y. Tsui     Texas Instruments, Inc.
Young-Chang Joo     Seoul National University
Alex A. Volinsky     University of South Florida
Lynne Michaelson     Freescale Semiconductor Inc.
Michael Lane     IBM T.J. Watson Research Center

Symposium Support
Air Products and Chemicals, Inc.
Applied Materials, Inc.
Tokyo Electron America, Inc.


TUTORIAL F


Processing, and Electrical and Mechanical Reliability of Future Interconnects
Monday April 17, 2006
9:00 AM - 4:00 PM
Room 2004 (Moscone West)

The tutorial will cover four areas of challenge for future interconnect technology. The first session will begin with discussion on the electrical and mechanical reliability of the ultra-low-dielectric constant (ULK) materials. Generally, ULK materials have lower density, higher porosity, and lower fracture strength than dense silicon-oxide films. The respective instructors will present experimental results and newly developed theoretical models to predict ULK material failures such as TDDB, dielectric breakdown, and cohesive and adhesive fractures. Copper interconnect reliability will also be included in the tutorial and presented to the audience with the latest developments concerning electromigration and metal stress-voiding defects. The final session will cover the processing and properties of carbon nanotube interconnects, revealing recent work on ballistic transport and high-field diffusive transport phenomenon of this new material.

Instructors:
Hongjie Dai, Stanford University
James R. Lloyd, IBM TJ Watson Research Center
J. W. McPherson, Texas Instruments
Zhigang Suo, Harvard University



* Invited paper
SESSION F1: Processing and Characterizations of Low-k Dielectrics
Chairs: Michael Lane and Joost Vlassak
Tuesday Morning, April 18, 2006
Room 3009 (Moscone West)


8:30 AM *F1.1
Development of Ultralow-k SiCOH Dielectrics with K Values Down to 1.80. Alfred Grill, Vishnubhai Patel, Son Nguyen, Deborah Neumayer, Muthumanickam Sankarapandian, Yuri Ostrovski, Eric Liniger and Eva Simonyi; IBM - T.J. Watson Research Center, Yorktown Heights, New York.

9:00 AM *F1.2
Impact of Pore Size and Morphology of Porous Organosilicate Glasses on Integrated Circuit Manufacturing. Mark L. O'Neill1, Raymond N. Vrtis1, Brian K. Peterson2, Mary K. Haas1, Scott J. Weigel1, Dingjun Wu1, Mark D. Bitner1 and Eugene J. Karwacki1; 1Electronics Technology, Air Products and Chemicals, Inc., Allentown, Pennsylvania; 2Computational Modeling Center, Air Products and Chemicals, Inc., Allentown, Pennsylvania.

9:30 AM F1.3
Pore Engineering: Ultra Low k Porous SiCOH For 45nm And Beyond Sang Ahn, Josephine Chang, Thomas Nowak, Nagarajan Rajagopalan, Kangsub Yim, Khaled Elsheref, Alex Demos, Sanjeev Jain, Derek Witty and Hichem MSaad; Applied Materials, Inc., Santa Clara, California.

9:45 AM BREAK

10:15 AM *F1.4
Novel Polysilsesquioxane Systems for Ultralow-Dielectric Films with High Modulus, Low CTE, and Closed-Pore Morphology Do Yeung Yoon1, Hyun Wook Ro2, Jie Hye Park1, Jae Hwan Shim1, Eun Su Park1, Jin-Kyu Lee1, Hee-Woo Rhee3, Hae-Jeong Lee2, Christopher Soles2 and David Gidley4; 1Department of Chemistry, Seoul National University, Seoul, South Korea; 2Polymer Division, National Institute of Standards and Technology, Washington, District of Columbia; 3Department of Chemical Engineering, Sogang University, Seoul, South Korea; 4Department of Physics, University of Michigan, Ann Arbor, Michigan.

10:45 AM F1.5
Matrix Structure of Organo-Silicate Glasses and Thermo-Mechanical Properties of Thin Low-K Films. Francesca Iacopi1, Gerald Beyer1, Kristof Houthoofd2, Peter Adriaensens3, Carlo Waldfried4, Steven Demuynck1, Youssef Travaly1, Salvador Eslava-Fernandez1,2, David M Gage5, Simone Giangrandi1, M Rennau6, Knut Schulze6, Stefan E Schulz6, Giovanni Carlotti7 and Reinhold H Dauskardt5; 1IMEC, Leuven, Belgium; 2Bio-Engineering Dept., Katholieke Universiteit Leuven, Leuven, Belgium; 3Chemistry Dept., Universiteit Hasselt, Diepenbeek, Belgium; 4Axcelis technologies, Beverly, Massachusetts; 5Meterials Science and Engineering, Stanford University, Stanford, California; 6Center for Microelectronics, TU Chemnitz, Chemnitz, Germany; 7Physics Dept., University of Perugia, Chemnitz, Italy.

11:00 AM F1.6
Film Characterization of Ultra Low-k Dielectrics Modified by UV Curing with Different Wavelength Bands. Masazumi Matsuura1, Kinya Goto1, Noriko Miura1, Shinobu Hashii2 and Koyu Asai1; 1Renesas Technology Corp., Itami, Japan; 2Renesas Semiconductor Engineering Corp., Itami, Japan.

11:15 AM F1.7
Fracture Property Improvements of a Nanoporous Thin Film via Post Deposition UV Curing. Jeannette M. Jacques, Ting Y. Tsui, Andrew J. McKerrow and Robert Kraft; Silicon Technology Development, Texas Instruments, Inc., Dallas, Texas.

11:30 AM F1.8
Characterization of Chemical Bonding in Low-K Dielectric Materials for Interconnect Isolation: A XAS and EELS Study. Patrick Hoffmann1, Dieter Schmeisser1, Ehrenfried Zschech3, Hans-Juergen Engelmann3, Franz Himpsel2, Heiko Stegmann4 and Jonathan Denlinger5; 1Applied Physics II, Brandenburg University of Technology Cottbus, Cottbus, Brandenburg, Germany; 2University of Wisconsin / Madison, Madison, Wisconsin; 3AMD Saxony LLC & Co KG, Dresden, Saxony, Germany; 4Carl Zeiss NTS GmbH, Oberkochen, Germany; 5Advanced Light Source, Berkeley, California.

11:45 AM F1.9
Ultra Low-k Film Deposition by PEVCD Using a Novel Organosilane as a Precursor Yonghua Xu, Ikuyo Muramoto, Masato Ishikawa and Hideaki Machida; Tri Chemical Laboratories Inc., Uenohara, Yamanashi, Japan.

SESSION F2: Reliability of Low-k Dielectrics
Chairs: Alfred Grill and Dorel Toma
Tuesday Afternoon, April 18, 2006
Room 3009 (Moscone West)

1:30 PM *F2.1
Reliability of Interconnect Dielectrics. Gaddi S Haase, SiTD, Texas Instruments, Dallas, Texas.

2:00 PM F2.2
Detection of Copper and Water in low-k dielectrics by Triangular Voltage Sweep measurements. Ivan Ciofi, Zsolt Tokei, Marco Saglimbeni and Marleen Van Hove; IMEC, Leuven, Belgium.

2:15 PM F2.3
Suppression of Moisture-induced Electrical Instabilities in Mesoporous Silica Films Through Molecular Capping. Amit P Singh, Darshan D Gandhi, Victor Pushpraj and G. Ramanath; Materials Science & Engineering, Rensselaer Polytechnic Institute, Troy, New York.

2:30 PM F2.4
Morphological and Structural Evolution of an Ultra-low-k Dielectric During the Porogen Removal. Diane Rebiscoul1, Helene Trouve2, Bruno Remiat1, Laurence Clerc3, Didier Louis1 and Gerard Passemard1; 1DRT/LETI/D2NT/Laboratoire Back End, CEA, Grenoble, France; 2LETI, Rohm and Haas Electronic Materials LLC, Grenoble, France; 3DRT/LETI/DPTS/SDOT, CEA, Grenoble, France.

2:45 PM BREAK

3:15 PM *F2.5
Effect of Water Diffusion in Organosilicate Glass Film Stacks on Adhesion Youbo Lin1, Ting Y. Tsui2 and Joost J. Vlassak1; 1Division of Engineering & Applied Sciences, Harvard University, Cambridge, Massachusetts; 2Silicon Technology Development, Texas Instruments, Dallas, Texas.

3:45 PM F2.6
Moisture Induced Degradation of Porous Low-k Materials. Mikhail R Baklanov, David O'Dwyer, Adam M Urbanowicz, Quoc Toan Le and Steven Demuynck; SPDT, IMEC, Leuven, Belgium.

4:00 PM F2.7
Methodology To Determine The Toughness Of A Brittle Thin Film By Nanoindentation. Helene Brillet-Rouxel1,2, Marc Verdier2, Muriel Braccini2, Michel Dupeux2 and Stephane Orain3; 1Mechanical and Thermal Simulations, STMicroelectronics, Crolles, France; 2LTPCM (CNRS/INPG/UJF), Grenoble, France; 3PHILIPS semiconductors, Crolles, France.

4:15 PM F2.8
Supercritical Carbon Dioxide Process to Improve Dielectric and Mechanical Properties of Porous ULK Thin Films. Julien Beynet1, Vincent Jousseaume2, Alain Madec1, Bruno Remiat2, Regis Mercier3, N. Dominique Alberola3 and Gerard Passemard4; 1AIR LIQUIDE, Jouy-en-Josas, France; 2CEA/LETI, Grenoble, France; 3LMOPS, Le Bourget du Lac, France; 4STMicroelectronics, Crolles, France.

4:30 PM F2.9
Mechanics and Fracture of Low-k Organosilicate Thin Films: Effects of UV Curing. David Maxwell Gage, Eric P. Guyer and Reinhold H. Dauskardt; Materials Science and Engineering, Stanford University, Stanford, California.

4:45 PM F2.10
Critical and Sub-critical Debonding in Nano-clustering Porous Low-k Films. Ryan Scott Smith1, Chihiro J. Uchibori2 and Paul S. Ho1; 1Laboratory for Interconnect and Packaging, The University of Texas, Austin, Texas; 2Fujitsu Laboratories of America, Inc., Sunnyvale, California.

SESSION F3: Poster Session I
Chairs: Gaddi Haase, Mark O'Neill and Joost Vlassak
Tuesday Evening, April 18, 2006
8:00 PM
Salons 8-15 (Marriott)


F3.1
Modelling of Thermal Conduction Mechanisms in Amorphous Inter-layer Dielectrics (ILDs). Manu Shamsa, Patrick Morrow and Shriram Ramanathan; Components Research, Intel, Hillsboro, Oregon.

F3.2
Structures and Properties of an Ultra-Low-k Material: Classical Molecular Dynamics and First-Principles Calculations. Jiro Ushio1, Tomoyuki Hamada2, Takahisa Ohno1,2, Shin-Ichi Nakao3, Manabu Kato3, Katsumi Yoneda3 and Nobuyoshi Kobayashi3; 1Computational Materials Science Center, National Institute for Materials Science, Tsukuba, Ibaraki, Japan; 2Collabolative Research Center of Frontier Simulation Software for Industrial Science, Institute of Industrial Science, University of Tokyo, Meguro-ku, Tokyo, Japan; 3Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan.

F3.3
Modeling the Impact of Layout Variation on Process Stress in Cu/Low k Interconnects. Xiaopeng Xu, Dipu Pramanik and Greg Rollins; TCAD, Synopsys, Inc., Mountain View, California.

F3.4
Low-k Dielectric Obtained by Noble Gas Implantation in Silicon Oxide. Hanan Assaf1, Esidore Ntsoenzok1,2, Marie Odile Ruault3 and S. Ashok4; 1CERI-CNRS, Orleans, France; 2LESI, University of orleans, Chartres, France; 3CSNSM, CNRS-IN2P3, Orsay, France; 4departement of Engineering Science, Pennsylvania state university, Pennsylvania, Pennsylvania.

F3.5
Channel Cracking Technique For Toughness Measurement Of Sioch Low-K Films. Helene Brillet-Rouxel1,2, Michel Dupeux2, Muriel Braccini2 and Stephane Orain3; 1Mechanical and Thermal Simulations, STMicroelectronics, Crolles, France; 2LTPCM (CNRS/INPG/UJF), Grenoble, France; 3PHILIPS semiconductors, crolles, France.

F3.6
Thermal and Dielectric Stability of Parylene X Jay J Senkevich1, Brad Carrow1 and Pei-I Wang2; 1Brewer Science Inc., Rolla, Missouri; 2Rensselaer Polytechnic Institute, Troy, New York.

F3.7
Transferred to F1.7

F3.8
Zeolite Film Properties Dependence on Particle Size Salvador Eslava-Fernandez1, M.R. Baklanov1, F. Iacopi1, S.H. Brongersma1, C. Kirschhock2 and K. Maex1; 1IMEC, Leuven, Belgium; 2Centrum voor Oppervlaktechemie en Katalyse, K. U. Leuven, Leuven, Belgium.

F3.9
The Electrical and Chemical Properties of Ultra Low-k SiOCH Film Deposited by PECVD using decamethyl-cyclopentasiloxane and cyclohexane as the Precursors. Jaeyoung Yang1, Sungwoo Lee1, Heeyeop Chae2 and Donggeun Jung1; 1Physics, Sungkyunkwan University, Suwon, Kyunggi, South Korea; 2Chemical Engineering, Sungkyunkwan University, Suwon, Kyunggi, South Korea.

F3.10
Synthesis and Characterization of Nanoporous Ultralow Dielectric Films by Dual Porogen Approach Jae Hwan Sim1, Hyun Wook Ro2, Hee-Woo Rhee3, David W. Gidely4 and Do Yeung Yoon1; 1Department of Chemistry, Seoul National University, Seoul, South Korea; 2Polymer Division, National Institute of Standards and Technology, Gaithersburg, Maryland; 3Department of Chemical Engineering, Sogang University, Seoul, South Korea; 4Department of Physics, University of Michigan, Ann Arbor, Michigan.

F3.11
Mechanical Properties of Organosilicate Glass Coatings Youbo Lin1, Ting Y. Tsui2 and Joost J. Vlassak1; 1Division of Engineering & Applied Sciences, Harvard University, Cambridge, Massachusetts; 2Silicon Technology Development, Texas Instruments, Dallas, Texas.

F3.12
Ordered Hydrophoic Mesorpous Furionated Silica Thin Film Mingming Du1, Denis W Mueller2, Phil D Matz3, Smith Eben Casey1, Pawan Nerusu1 and Richard F Reidy1; 1Materials Science and Engineering, University of North Texas, Denton, Texas; 2Physics Department, University of North Texas, Denton, Texas; 3Silicon Technology Development, Texas Instruments Inc, Dallas, Texas.

F3.13
Effects of Solution Chemistry on Fracture of Nanoporous Low-k Thin-Films. Nathan David Stein and Reinhold Dauskardt; Materials Science and Engineering, Stanford University, Stanford, California.

F3.14
Cu Via Filling Behavior and Electrical Characteristics of the 3D Cu Interconnects for Chip Stack Package Kwang-Yong Lee, Teck-Su Oh and Tae-Sung Oh; Materials Science and Engineering, Hongik University, Seoul, South Korea.

F3.15
Low-Temperature Wafer Bonding of PETEOS-to-PETEOS Using Ti as Intermediate. Jian Yu1, Richard L. Moore2, Hui-Feng Li1, Sang-Hwui Lee1, J. Jay McMahon1, Jian-Qiang Lu1 and Ronald J. Gutmann1; 1Rensselaer Polytechnic Institute, Troy, New York; 2University at Albany-SUNY, Albany, New York.

F3.16
Abstract Withdrawn

SESSION F4: Low-k Dielectrics: Processing and Integration Issues
Chairs: Francesca Iacopi and Alex Volinsky
Wednesday Morning, April 19, 2006
Room 3009 (Moscone West)

8:30 AM *F4.1
Chemical, Mechanical and Electrical Properties of Non-Thermally Cured CVD Low-k Films for a 65nm Technology. Kurt H. Junker1, Gregory Imbert2, Aurelie Humbert3, Laurent-Luc Chapelon2, Yannick Le-Friec2, Julien Vitiello4, Anissa Lagha5, Michael Turner1, Michelle Rasco1, Cindy Goldberg5 and Narayanan Ramani1; 1Freescale Semiconductor, Austin, Texas; 2STMicroelectronics, Crolles, France; 3Philips Research Leuven, Leuven, Belgium; 4Philips Semiconductor, Crolles, France; 5Freescale Semiconductor, Crolles, France.

9:00 AM F4.2
Challenges of Ultra Low-k Dielectric Measurement and Plasma Damage Assessment. Thomas Abell1, Jeffery Lee2 and Mansour Moinpour1; 1Intel Corp., Santa Clara, California; 2Intel at IMEC, Leuven, Belgium.

9:15 AM F4.3
The Effect of Plasma Damage on the Material Composition and Electrical Performance of Two Generations of SiOCH Low k Films Aurelie Humbert, D Ernur and R.J.O.M Hoofman; Philips Research Leuven, Leuven, Belgium.

9:30 AM F4.4
Tailored Repair of low-k Dielectrics Using Mono- and Di- Functional Silanes Dissolved in Supercritical CO2. Casey Eben Smith1, Richard Reidy1, Dennis Mueller2 and Phil Matz3; 1Materials Science, University of North Texas, Denton, Texas; 2Physics, University of North Texas, Denton, Texas; 3Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.

9:45 AM BREAK

10:15 AM F4.5
Evaluation of Damages and Pore-sealing Capabilities of Oxidizing and Reducing Etch Plasmas for Single and Dual Damascene Patterning of Porous Ultra-low-k Materials. Emmanuel Ollier1, Mathieu Clain2, Robert Fox2, Philippe Brun3 and Stephane Jullian1; 1Crolles2Alliance, Philips Semiconductors Crolles R&D, Crolles, France; 2Crolles2Alliance, Freescale Semiconductors, Crolles, France; 3Crolles2Alliance, CEA-Leti, Crolles, France.

10:30 AM F4.6
PECVD Versus Spin-on to Perform Porous ULK for Advanced Interconnects: Chemical Composition, Porosity and Mechanical Behavior. Vincent Jousseaume1, Charles Le Cornec1, Frederic Ciaramella1, Laurent Favennec2, Aziz Zenasni1, Gurvan Simon1, Jean Paul Simon3, Guillaume Gerbaud4 and Gerard Passemard2; 1CEA-LETI-D2NT, Grenoble, France; 2STMicroelectronics, Grenoble, France; 3CNRS-LTPCM, St Martin d'Heres, France; 4CEA-DRFMC, Grenoble, France.

10:45 AM F4.7
Fracture Properties of Porous MSSQ Films: Impact of Porogen Loading and Burnout. Markus Daniel Ong1, Vincent Jousseaume2, Sylvain Maitrejean2 and Reinhold H. Dauskardt1; 1Materials Science and Engineering, Stanford University, Stanford, California; 2CEA-LETI, Grenoble, France.

11:00 AM F4.8
New Spin-On Oxycarbosilane Low-K Dielectric Materials With Exceptional Mechanical Properties. Geraud Jean-Michel Dubois, Robert Miller, Willi Volksen and Teddie Magbitang; Advanced Organic Materials, IBM, San Jose, California.

11:15 AM F4.9
Generation of Porosity in Spin-on Oxycarbosilane Ultra low-ê Dielectric Films. Marcus Andre Worsley1, Geraud Dubois2, Stacey F. Bent1, Teddie Magbitang2, Robert D. Miller2, Willi Volksen2 and Mark Sherwood2; 1Chemical Engineering, Stanford University, Stanford, California; 2Almaden Research Center, IBM, San Jose, California.

11:30 AM F4.10
Effects of Dielectric Thermal Expansion and Elastic Modulus on the Stress and Deformation Fields in Copper Interconnects. Yu-Lin Shen, Mechanical Engineering, University of New Mexico, Albuquerque, New Mexico.

11:45 AM F4.11
Comparison of the Fracture Behavior of Brittle ILD Films used in the BEOL in Dry and Wet Environment using Nanoindentation. Eva Simonyi, Michael Lane, Erick Liniger and Alfred Grill; IBM, Yorktown Heights, New York.

SESSION F5: Barrier Metals and Copper Plating
Chairs: Romano Hoofman and Lynne Michaelson
Wednesday Afternoon, April 19, 2006
Room 3009 (Moscone West)

1:30 PM *F5.1
Cu Alloy Metallization for Self-Forming Barrier Process Junichi Koike, Dept. of Materials Science, Tohoku University, Sendai, Japan.

2:00 PM F5.2
In-situ Plasma-enhanced Atomic Layer Deposition of Tantalum Nitride Liner and Ruthenium Seed Materials for Copper Interconnect Applications. Oscar van der Straten, Stephen Rossnagel and Ken Rodbell; T.J. Watson Research Center, IBM Research, Yorktown Heights, New York.

2:15 PM F5.3
Thin, Continuous and Highly Conformal Copper Films by Reduction of ALD Copper Nitride. Zhengwen Li and Roy G. Gordon; Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts.

2:30 PM F5.4
Evaluation of integrity and barrier performance of ultra thin ALD-diffusion barriers on PECVD SiO2 and SiOCH low-k dielectrics for Cu metallization Ki-Su Kim1, Moon-Sang Lee1, Sung-Soo Yim1, Ki-Bum Kim1 and Hyung-Sang Park2; 1School of Materials Science and Engineering, Seoul National University, Seoul, South Korea; 2ASM Genitech, Inc., Daejeon, South Korea.

2:45 PM BREAK

3:15 PM F5.5
Characteristics of cobalt and cobalt silicide film deposited by Remote Plasma ALD method Keunjun Kim, Keunwoo Lee, Sejin Han, Wooho Jeong and Hyeongtag Jeon; Hanyang Univ., Seoul, South Korea.

3:30 PM F5.6
Improved Atomic Layer Deposited TaN Thin Film Properties by Supplying Additional Energy. Daniela Schmidt1, Christoph Hossbach1, Matthias Albert1, Johann W. Bartha1 and Siegfried Menzel2; 1Technische Universitaet Dresden, Semiconductor and Microsystems Technology Laboratory, 01062 Dresden, Germany; 2Leibnitz Institute for Solide State and Materials Research (IFW) Dresden, 01069 Dresden, Germany.

3:45 PM F5.7
Real Time Study of Cu Diffusion through Ru Thin Film by Photoemission Electron Microscopy (PEEM) Wei Wei1, Xiong Gang2, Y.-M. Sun1, Alan G Joly2, Kenneth M Beck2, J. M. White1 and Wayne P Hess2; 1Chemistry and Biochemistry, University of Texas at Austin, Austin, Texas; 2Pacific Northwest National Laboratory, Richland, Washington.

4:00 PM F5.8
Copper Electroplating on Zero-Thickness ALD Platinum for Nanoscale Computer Chip Interconnects. Alain E. Kaloyeros, Yu Zhu, Kathleen Dunn, Chris Miller and Michael Breslin; college of nanoscale science and engineering, the university at albany-suny, albany, New York.

4:15 PM F5.9
Thermal Oxidation of Ni and Co Alloys Formed by Electroless Plating. Jeff Gambino1, Igor Ivanov2, Ed Adams1, Scott Hazel1, Dave Meatyard1, Phil Pokrinchak1, Fen Chen1 and Pat DeHaven3; 1IBM, Essex Junction, Vermont; 2Blue29, Inc., Sunnyvale, California; 3IBM, Hopewell Junction, New York.

4:30 PM F5.10
Electroless CoWP as a Catalyst of Self-Aligned CNT Growth for Future CMOS Interconnect Via Applications Tzu-Chun Tseng and Tri-Rung Yew; Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu, Taiwan.

4:45 PM F5.11
Thin and Smooth Cu Seed Layer Deposition using the Reduction of Low Temperature Deposited Cu2O. Hoon Kim1, Yasuhiko Kojima2, Hiroshi Sato2, Naoki Yoshii2, Shigetoshi Hosaka2 and Yukihiro Shimogaki1; 1the materials engineering, The Univ. of Tokyo, Bunkyo ku, Tokyo, Japan; 2Technology Development Center, Tokyo Electron AT Limited, 650 Mitsuzawa, Hosaka-cho, Nirasaki-city, Yamanashi, Japan.

SESSION F6: Copper Interconnects Relibility
Chairs: Gaddi   Haase and Young-Chang Joo
Thursday Morning, April 20, 2006
Room 3009 (Moscone West)

8:30 AM *F6.1
Scaling of Statistical and Physical Electromigration Characteristics in Cu Interconnects Martin Gall1, Meike Hauschildt1, Patrick Justison1, Koneru Ramakrishna1, Richard Hernandez1, Matthew Herrick1, Lynne Michaelson2 and Hisao Kawasaki2; 1CMOS Platform Device Development, Freescale Semiconductor Inc., Austin, Texas; 2Advanced Products Research and Development Laboratory, Freescale Semiconductor Inc., Austin, Texas.

9:00 AM F6.2
Resistivity of Fine Cu Interconnects at Low Temperatures: Understanding of the Origin of the Size Effect. Wenqi Zhang1,2, Sywert H. Brongersma1, zhen Li1, dagang Li2, Olivier Richard1, gerald beyer1 and karen maex1,2; 1IMEC, leuven, Belgium; 2E.E. Dept., K.U.Leuven, leuven, Belgium.

9:15 AM F6.3
In-Situ Characterizarion Of Interfaces Induced Resistivity In Nanometric Dimensions. Hagay Marom and Moshe Eizenberg; Technion - Israel Institute of Technology, Haifa, Israel.

9:30 AM F6.4
In-situ Grain Growth Investigation of Copper Electrodeposits for ULSI. Heung Nam Han1, Hyo-Jong Lee1, Do Hyun Kim1, Ui-hyoung Lee1, Pil-Ryung Cha2 and Kyu Hwan Oh1; 1Material Science and Engineering, Seoul National University, San 56-1, Shinrim-dong, Kwanak-gu, Seoul, South Korea; 2School of Advanced Materials Engineering, Kookmin University, 861-1, Chongnung-dong, Songbuk-gu, Seoul, South Korea.

9:45 AM BREAK

10:15 AM *F6.5
Electromigration-Induced Plastic Deformation in Cu Damascene Interconnect Lines as Revealed by Synchrotron X-Ray Microdiffraction. Arief S. Budiman1, N. Tamura2, B. C. Valek2, K. Gadre3, J. Maiz3, R. Spolenak4, J. Patel1,2 and William D. Nix1; 1Materials Science & Engineering, Stanford University, Stanford, California; 2Advanced Light Source (ALS), Lawrence Berkeley National Laboratory (LBNL), Berkeley, California; 3Intel Corporation, Hillsboro, Oregon; 4ETH Swiss Federal Institute of Technology Zurich, Zurich, Switzerland.

10:45 AM F6.6
Thermal and Electromigration-Induced Strains in Copper Conductor Lines: X-ray Microbeam Measurements and Analysis Gan Wang1, Hongqing Zhang1, G. S. Cargill1, C. K. Hu2, W. Yang3, B. C. Larson3 and G. E. Ice3; 1Materials Science and Engineering, Lehigh University, Bethlehem, Pennsylvania; 2IBM Research, Yorktown Heights, New York; 3Oak Ridge National Lab., Oak Ridge, Tennessee.

11:00 AM F6.7
Effect of Cu migration in a field induced dielectric failure Sang-Soo Hwang, Sung-Yup Jung and Young-Chang Joo; School of Materials Science & Enginnering, Seoul National University, Seoul, South Korea.

11:15 AM F6.8
Electrical Resistance Anomalies During Electromigration Testing of Cu Conductor Lines: Examples of Local Melting? H. Zhang, G. Wang and G. S. Cargill; Materials Science and Engineering, Lehigh University, Bethlehem, Pennsylvania.

11:30 AM F6.9
Influence of Grain Orientation on the Microstructural Characterization in Cu During (self)-anneal Using a Surface Acoustic Wave Technique. Atsuko Sekiguchi1, Kris Vanstreels2, Steven Demuynck1, Laure Carbonell1, Jan D`Haen2, Karen Maex1 and Sywert Brongersma1; 1IMEC, Leuven, Belgium; 2IMOMEC, Diepenbeek, Belgium.

11:45 AM F6.10
Barrier Formation and Thickness Effects on Electromigration Reliability of Cu/Low-k Interconnects. Jung Woo Pyun1, Won-Chong Baek1, Paul S Ho1, Larry Smith2, Kyle Neuman2 and Klaus Pfeifer2; 1The University of Texas at Austin, Austin, Texas; 2SEMATECH, Austin, Texas.

SESSION F7: Advanced Metrology Techniques: Metallization
Chair: Seung-Hyun Rhee
Thursday Afternoon, April 20, 2006
Room 3009 (Moscone West)

1:30 PM *F7.1
New Characterization Metrology for low-k/Cu Interconnect Integration: Voltamometry and Its Applications Choong-Un Kim1, DongMei Meng1, Nancy Lyn Michael1, Y.-J. Park2, Laura Matz2 and Sri Satyanarayana3; 1Materials Science and Engineering, The University of Texas at Arlington, Arlington, Texas; 2Texas Instruments, Dallas, Texas; 3Sematech, Austin, Texas.

2:00 PM F7.2
Feasibility of Thermal Microscopy of Embedded Voids in Layered Geometries. Sanjiv Sinha1 and Shriram Ramanathan2; 1Systems Technology Lab, Intel Corporation, Portland, Oregon; 2Components Research, Intel Corporation, Portland, Oregon.

2:15 PM F7.3
Advanced X-ray Fluorescence: and Innovative Interconnect and Process Metrology Solution for 45 nm and Beyond. Jean Paul Gueneau de Mussy1, Gerardo Bottiglieri1, Nancy Heylen1, Laure Carbonell1, Jeremy O Dell2, Dileep Agnihotri2, Alex Tokar3 and Isaac Mazor3; 1SPDT/ITS, IMEC, Leuven, Belgium; 2Jordan Valley, Austin, Texas; 3Jordan Valley, Migdal HaEmek, Israel.

2:30 PM F7.4
A Study on the Stepwise Cross-sectional Crystalline Analyses of the Stress Induced Voiding in Cu Interconnect by Focused Ion Beam and Electron Backscattered Diffraction Hyo-Jong Lee1, Kyu Hwan Oh1, Heung Nam Han1, Suk Hoon Kang1, Jeong-Yun Sun1, Sun-Jung Lee2 and Hong-Jae Shin2; 1Material Science and Engineering, Seoul National University, San 56-1, Shinrim-dong, Kwanak-gu, Seoul, South Korea; 2Advanced Process Development Team, System LSI Business, Samsung Electronics Co., Ltd., San 24, Nongseo-ri, Kiheung-eup, Youngin-city, Kyunggi-do, South Korea.

2:45 PM BREAK

SESSION F8: Stress in Copper Interconnects
Chair: Junichi Koike
Thursday Afternoon, April 20, 2006
Room 3009 (Moscone West)


3:15 PM *F8.1
The Effects of Interconnect Structures on Thermal Mechanical Stress of Cu lines and the Impact of Unstressed Lattice Spacing Determination. Seung-Hyun Rhee1, I. C. Noyan2, Conal Murray3 and Paul Besser4; 1AMD Logic Technology Development, Advanced Micro Devices, ASTA (AMD/IBM/Sony/Toshiba) Alliance, Hopewell Junction, New York; 2Dept. of Applied Physics & Applied Mathematics, Columbia University, New York, New York; 3T J Watson Laboratory, IBM Research Division, Yorktown Heights, New York; 4Advanced Process Development, Technology Dev. Group, AMD, Sunnyvale, California.

3:45 PM F8.2
Plastic Deformation of Cu in Thin Films, Interconnect Lines and Other Confined Structures.  J. J. Vlassak and Y. Xiang; Division of Engineering and Applied Sciences, Harvard University, Cambridge, Massachussetts.

4:00 PM F8.3
Kinetics of Void Drift in Copper Interconnects Zung-Sun Choi, Reiner Moenig and Carl Vernette Thompson; Materials Science and Engineering, MIT, Cambridge, Massachusetts.

4:15 PM F8.4
Theoretical Analysis Of Current-Driven Interactions Between Voids In Metallic Interconnect Lines. Jaeseol Cho, M. Rauf Gungor and Dimitrios Maroudas; Department of Chemical Engineering, University of Massachusetts, Amherst, Massachusetts.

4:30 PM F8.5
Abstract Withdrawn

SESSION F9: Poster Session II
Chairs: Junichi Koike, Michael Lane, Lynne Michaelson and Alex Volinsky
Thursday Evening, April 20, 2006
8:00 PM
Salons 8-15 (Marriott)


F9.1
Investigation of W-Ge-N Deposited on Ge as a Diffusion Barrier for Cu Metallization. Seemant Rawal1, David Norton1, Tim Anderson2 and Lisa McElwee White3; 1Materials Science and Engineering, University of Florida, Gainesville, Florida; 2Chemical Engineering, University of Florida, Gainesville, Florida; 3Department of Chemistry, University of Florida, Gainesville, Florida.

F9.2
Comparison of Ru/Ta and Ru/TaN as Barrier Stack for Copper Metallization. Xin-ping Qu, Jing-Jing Tan, Qi Xie, Guo-Ping Ru and Bing-zong Li; Department of microelectronics, Fudan University, Shanghai, China.

F9.3
A Novel MO Precursor for Metal Tantalum and Tantalum Nitride Film Kenichi Sekimoto1,2, Taishi Furukawa1,2, Norikaki Oshima2,1, Ken-ichi Tada1 and Tetsu Yamakawa1; 1Sagami Chemical Research Center, Ayase, Kanagawa, Japan; 2Tokyo Research Center, Tosoh Corporation, Ayase, Kanagawa, Japan.

F9.4
Pulsed CVD of Thin Ru metal Films Using an Amidinate Precursor. huazhi li, Titta Aaltonen and Roy G Gordon; Chemistry, Harvard University, cambridge, Massachusetts.

F9.5
Post Etch/Ash Cleaning Process Development and Integration into 65nm Cu/low-k Dual Damascene Process Flow using Metal Hard Mask Miao Chun Lin, Advanced Etching Dept., UMC, Tainan Science Park, Sinshih Township, Tainan County, Taiwan.

F9.6
A Ruthenium Seed Layer and Copper Deposited by Electrochemical Plating. Hyung-Il Kim1, Kim Young-Soon1, Chul-Hee Jeon1, Young-Mo Kim1, Hyung-Kee Seo1, Choong-Un Kim2 and Hyung-Shik Shin1; 1School of Chemical Engineering, Chonbuk National University, Jeonju, Jellabuk-do, South Korea; 2Material Science and Engineering, University of Texas-Arlington, Arlington, Texas.

F9.7
Cu Resistivity in Narrow lines: Dedicated Experiments for Model Optimization. Sylvain Maitrejean1, Roland Gers1, Thierry Mourier1, Alain Toffoli1 and Gerard Passemard2; 1CEA LETI, Grenoble, France; 2STMicroelectronics, Crolles, France.

F9.8
Low Temperature Plasma Etching of Copper for Minimizing Size Effects in sub-100 nm Features Nagraj S. Kulkarni1, Dennis Hess2, Galit Levitin2 and Prabhakar Tamirisa2; 1Metals & Ceramics, Oak Ridge National Laboratory, Knoxville, Tennessee; 2School Of Chemical & Biomolecular Engineering, Georgia Institute of Technology, Atlanta, Georgia.

F9.9
Improvement of Barrier Properties of TaN Film by Plasma Enhanced Atomic Layer Deposition In Cheol Baek1, Han-choon Lee1, Jae-Won Han1, Kee-Ho Kim1, Soo Hyun Kim2 and Sahng Kyoo Lee2; 1Advanced Nano-tech Development, DongbuAnam Semiconductor, Eumseong-gun, South Korea; 2Advanced Development Team, IPS Ltd., Pyeongtaek, South Korea.

F9.10
The Copper Corrosion and Sulfur Contamination Generated by a Three-step Copper Chemical-mechanical Polishing Process. Chun-Ping Liu1, Y. S. Ho2, T. C. Hu3 and Bae-Heng Tseng1; 1Institute of Materials Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan; 2Department of Electrical Engineering, National Kaohsiung University of Applied Science, Kaohsiung, Taiwan; 3Institute of Engineering Management, National Chen Kung University, Tainan, Taiwan.

F9.11
Passive Film Growth and Removal during Copper post-CMP Cleaning. Jun Liu, Darryl Peters, Mike Hughes, Monica Hilgarth and Mackenzie King; MLS R&D, ATMI, Inc., Danbury, Connecticut.

F9.12
Slurry Chemistries for Chemical Mechanical Polishing of Gold. Saurabh Agrawal1,2 and Jay Jayashankar1; 1Seagate Research, Seagate Technology, Pittsburgh, Pennsylvania; 2Materials Science and Engr., Rensselaer Polytechnic Institute, Troy, New York.

F9.13
Abstract Withdrawn

F9.14
Electrochemical Characteristics of CMP Copper in a Low Abrasive Slurry. Amanda Bozak1, Arthur Diaz2, Ashwani Rawat1, Hokkin Choi1 and Mansour Moinpour1; 1Intel Corp., Santa Clara, California; 2Department of Chemical and Materials Engineering, San Jose State University, San Jose, California; 3Intel Corp., Santa Clara, California; 4Intel Corp., Santa Clara, California; 5Intel Corp., Santa Clara, California.

F9.15
Investigation of the Rate of Copper Deposition onto Silicon via Galvanic Displacement. Calvin Paul daRosa, Enrique Iglesia and Roya Maboudian; Chemical Engineering, University of California, Berkeley, California.

F9.16
Design an Electroplated Frame Freestanding Specimen for Microtensile Testing of Submicron thin TaN and Cu Film. Ming-Tzer Lin1,2, Chi-Jia Tong1 and Chung-Hsun Chiang1; 1Institute of Precision Engineering, National Chung Hsing University, Taichung, Taiwan; 2Center for Nano Science and Nanotechnology, National Chung Hsing University, Taichung, Taiwan.

F9.17
Non-destructive Deep Embedded Copper Interconnection Defects Measurements Using Photoacoustic Microscope. Lu Xu, Donnacha Lowney and Patrick J. McNally; School of Electronic Engineering, Dublin City University, Dublin, Ireland.

F9.18
Relationship between interfacial adhesion and dielectric reliability of Cu alloy films Seol-Min Yi1, Kwang-Ho Jang1, Yong-Hak Huh2, Young-Bae Park3 and Young-Chang Joo1; 1School of Materials Science and Engineering, Seoul National University, Seoul, South Korea; 2Strength Evaluation Group, Korea Research Institute of Standards and Science, Daejeon, South Korea; 3School of Materials Science and Engineering, Andong National University, Andong, South Korea.

F9.19
Effect Of Overburden Layer On Microstructure In Damascene Cu Lines. Jong-Min Paik, Young-Hoo Kim, Jung-Kyu Jung and Young-Chang Joo; School of Material Science & Engineering, Seoul National University, Seoul, South Korea.

F9.20
Novel Reducing Chemistry for Supercritical Fluid Deposition of Copper. Takeshi Momose1, Tomohiro Ohkubo1, Masakazu Sugiyama2 and Yukihiro Shimogaki1; 1Materials Engineering, the University of Tokyo, Tokyo, Tokyo, Japan; 2Electronic Engineering, the University of Tokyo, Tokyo, Japan.

F9.21
Abstract Withdrawn

F9.22
Computer Simulations of Grain Boundary Grooving and Cathode Voiding in Bamboo-like Metallic Interconnects by Surface Drift-diffusion under the Capillary and Electromigration Forces. Tarik Omer Ogurtani and Oncu Akyildiz; Metallurgy&Materials Engineering, Middle East Technical University, Ankara, Turkey.

F9.23
Feasibility Study for Usage of Diluted Fluorine for Chamber Clean Etch Applications as an Environmental Friendly Replacement of NF3. Ronald Hellriegel2, Bernd Hintze2, Matthias Albert1, Johann W. Bartha1 and Michael Pittroff3; 1TU-Dresden, Dresden, Germany; 2Infineon Technologies, Dresden, Germany; 3Solvay Fluor GmbH, Hannover, Germany.

SESSION F10: Future Interconnects
Chair: Choong-Un Kim
Friday Morning, April 21, 2006
Room 2004 (Moscone West)

8:30 AM *F10.1
Benefits and Trade-offs in Multi-Level Air Gap Integration. Romano Hoofman1, Roel Daamen1, Viet Nguyenhoang1, Julien Michelon1, Laurent Gosset2, Vincent Arnal3, Jean de Pontcharra4, Phillippe Lyan4, Frederic Gaillard4, David Bouchu4, Rudy Caluwaerts5, Christophe Bruynseraede5 and Gerald Beyer5; 1Philips Research Leuven, Leuven, Belgium; 2Philips Semiconductors R&D, Crolles, France; 3STMicroelectronics, Crolles, France; 4CEA-LETI, Grenoble, France; 5IMEC, Leuven, Belgium.

9:00 AM F10.2
Routes to the Formation of Air Gap Structures Using PECVD. Raymond N Vrtis, Dingjun Wu, Mark L O'Neill, Mary K Haas, Scott J Weigel and Eugene J Karwacki; Electronics, Air Products and Chemicals Inc., Allentown, Pennsylvania.

9:15 AM F10.3
Growth of Individual Vertically Aligned Nanotubes for Interconnects. Mohammad Shafiqul Kabir1, R. E. Morjan2, P Lundgren1, O. A. Nerushev2, S. bengtsson1, P. Enoksson1 and E. E. B. Campbell2; 1Microtechnology and Nanoscience, Chalmers University of Technology, Gothenburg, Sweden; 2Dept. of Experimental Physics, Gothenburg University and Chalmers University of Technology, Gothenburg, Gothenburg, Sweden.

9:30 AM F10.4
A Deep Silicon Tapered via Etch Process for Through-wafer Interconnects in Three Dimensional Integrated Circuits. Nagarajan Ranganathan1, Krishnamachar Prasad2, Dayong Lee2 and Narasimhan Balasubramanian1; 1Institute of Microelectronics, Singapore, Singapore; 2School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore, Singapore.

9:45 AM F10.5
Deep Sub-Micron Wafer-to-Wafer Self-Alignment for Wafer-Level 3D ICs Sang Hwui Lee1, Frank Niklaus2, Ravi Kumar1, Hui-feng Li1, J. Jay McMahon1, Jian Yu1, James Lu1, Timothy Cale1 and Ronald Gutmann1; 1CIE, RPI, Troy, New York; 2KTH, Stockholm, Sweden.

10:00 AM BREAK

SESSION F11: Advanced Metrology Techniques: Dielectrics
Chair: Do Y. Yoon
Friday Morning, April 21, 2006
Room 2004 (Moscone West)

10:30 AM F11.1
Elastic Properties Measurements of Porous ULK : a Comparison Between Nanoindentation and Brillouin Light Scattering. Frederic Ciaramella1, Giovanni Carlotti3, Vincent Jousseaume1, Marc Verdier2, Gianni Socino3, Sylvain Maitrejean1, Aziz Zenasni1, Charles Le Cornec1 and Gerard Passemard4; 1D2NT/LBE, CEA-LETI, Grenoble, France; 2LTPCM, CNRS, Grenoble, France; 3Dipartimento Di Fisica, INFM, Perugia, Italy; 4STMicroelectronics, Crolles, France.

10:45 AM F11.2
Studies of the Coefficient of Thermal Expansion of Low-k ILD Materials by X-Ray Reflectivity. George Andrew Antonelli1,4, Michael David Goodner2, Mansour Moinpour2, Tran My Phung3, Clay Dustin Mortensen3 and David Charles Johnson3; 1Portland Technology Development, Intel Corporation, Hillsboro, Oregon; 2Fab Materials Operations, Intel Corporation, Hillsboro, Oregon; 3Materials Science Institute and Chemistry Department, University of Oregon, Eugene, Oregon; 4Physics Department, Brown University, Providence, Rhode Island.

11:00 AM F11.3
Chemical Bonding, Permittivity and Elastic Properties in Locally Modified Organosilicate Glass Ehrenfried Zschech1, Heiko Stegmann2, Patrick Hoffmann3, Dieter Schmeisser3, Pavel Potapov1, Hans-Juergen Engelmann1, Dmytro Chumakov1 and Holm Geisler1; 1Materials Analysis Department, AMD Saxony LLC & Co. KG, Dresden, Germany; 2Carl Zeiss NTS GmbH, Oberkochen, Germany; 3Angewandte Physik - Sensorik, BTU Cottbus, Cottbus, Germany.

11:15 AM F11.4
Determination of Poisson's Ratio of Thin low-k Films using Bidirectional Thermal Expansion Measurement. Jiping Ye, Satoshi Shimizu, Shigeo Sato, Nobuo Kojima and Junnji Noro; Research Dept., NISSAN ARC Ltd., Yokosuka, Japan.

11:30 AM F11.5
Non-contact Dielectric Constant Metrology for low-k Films on Semiconductor Production Wafers. Vladimir V. Talanov, Andre Scherz and Andrew R. Schwartz; Neocera, Inc., Beltsville, Maryland.

11:45 AM F11.6
Characterization of the Structural Changes of a Porous SiOC During a Curing Process with Ellipsometric Porosimetry. Adrien Darragon, Jean Philippe Piel, Yann Turcant and Patrice Heinrich; SOPRA, Bois-colombes, France.

SESSION F12: Chemical-Mechanical Planarization
Chair: Young-Chang Joo
Friday Afternoon, April 21, 2006
Room 2004 (Moscone West)

1:30 PM F12.1
Single and Mixed Surfactant Systems for Post-CMP Cleaning. Deenesh Kumar Bundi1, Yuzhuo Li1, Dedy Ng2 and Hong Liang2; 1Chemistry, Clarkson Univeristy, Potsdam, New York; 2Mechanical Engineering, Texas A & M University, College Station, Texas.

1:45 PM F12.2
Applications of Raman Spectroscopy in Cu CMP: In-situ Detection of Chemical Species in the Slurry Siddartha Kondoju1, Pierre Lucas1, Srini Raghavan1, Paul Fischer2, Mansour Moinpour3 and Andrea Oehler4; 1Materials Science and Engineering, University of Arizona, Tucson, Arizona; 2Components Research, Intel Corp, Portland, Oregon; 3Fab Materials Operation, Intel Corp, Santa Clara, California; 4Fab Materials operation, Intel Corp, Portland, Oregon.

2:00 PM F12.3
The Role of Arginine as a Complexing Agent in Copper CMP. Surya Sekhar Moganty1 and Srinivasan Ramanathan2; 1Chemical Engieering, Indian Institute of Technology Madras, Chennai, Tamil Nadu, India; 2Chemical Engineering, Indian Institute of Technology Madras, Chennai, Tamil Nadu, India.

2:15 PM F12.4
Characterization of Post-CMP Cleaning of Advanced PDEMS® Dielectrics. Dnyanesh Tamboli, Mark O'Neill, Madhukar Rao, Thomas Wieder, Scott Weigel, Gautam Banerjee and John Langan; Air Products & Chemicals, Allentown, Pennsylvania.

2:30 PM BREAK

3:00 PM F12.5
AFM Measurements of Adhesion between CMP Slurry Particles and Copper Ruslan Burtovyy1, Yong Liu1, Bogdan Zdyrko1, Alex Tregub2, Mansour Moinpour2, Mark Buehler3 and Igor Luzinov1; 1School of Materials Science and Engineering, Clemson University, Clemson, South Carolina; 2CMO/FMO, Intel Corporation, Santa Clara, California; 3PTD, Intel Corporation, Hillsboro, Oregon.

3:15 PM F12.6
A Novel Optical Technique to Measure Pad-Wafer Contact Area in Chemical-Mechanical Polishing. Carolina L Elmufdi and Gregory P Muldowney; Pad Engineering Research Group, Rohm and Haas Electronic Materials CMP Technologies, Newark, Delaware.

3:30 PM F12.7
CMP-induced Peeling in Multi-level Ultra Low-k / Cu Interconnects. Patrick Leduc1, Thierry Farjot1, Mylene Savoye1, Sylvain Maitrejean1 and Gerard Passemard2; 1D2NT, CEA-LETI, Grenoble, France; 2STMicroelectronics, CROLLES, France.

3:45 PM F12.8
Asperity-Scale Fluid Flow and Heat Transfer in Chemical Mechanical Planarization. Gregory Muldowney, Rohm and Haas Electronic Materials CMP Technologies, Newark, Delaware.

4:00 PM F12.9
Evaluation of Inhibitors for ECMP of Copper Using Electrochemical Quartz Crystal Microbalance (EQCM) Technique Ashok Muthukumaran, Viral Lowalekar and Srini Raghavan; Materials Science and Engineering, The University of Arizona, Tucson, Arizona.

4:15 PM F12.10
Abstract Withdrawn


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