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Symposium D: Transistor Scaling - Methods, Materials, and Modeling

Symposium D: Transistor Scaling - Methods, Materials, and Modeling Image

Chairs | Symposium Support | Tutorial  | Original Call for Papers

Tuesday Sessions | Wednesday Sessions


April 17 - 19, 2006
Chairs
Scott Thompson     University of Florida
Faran Nouri     Applied Materials Inc.
Wilman Tsai     Intel Corporation
Wen-Chin Lee     TSMC

Symposium Support
Taiwan Semiconductor Manufacturing Co., Ltd.


TUTORIAL C/D/E


The Transistor Scaling Dilemma--A Look at Status, Requirements, and Issues
Monday April 17, 2006
1:30 PM - 5:00 PM
Rooms 2010 / 2012 (Moscone West)


  • General Transistor Scaling Challenges
  • ITRS requirements and implications for new materials and techniques
  • Process-induced strain
      Compressive and tensile SiN layers
      Recessed epitaxial SiGe and SiC

    Gate Stack
  • High-k dielectrics
  • Metal electrodes
  • Characterization and reliability issues in advanced gate stacks


    • Ultra-Shallow Junctions
  • Extended defect formation and evolution
  • SPER (solid-phase epitaxial regrowth)
  • MSEC annealing techniques


    • Instructors:
    Kevin Jones,     University of Florida
    Byoung-Hun Lee, SEMATECH (IBM)
    Scott Thompson, University of Florida


    * Invited paper

    SESSION D1: SOI, FDSOI, SGOI, GOI, Multi-Gate and Schottky SD Technologies
    Chairs: Wen-Chin Lee and Scott Thompson
    Tuesday Morning, April 18, 2006
    Room 3006 (Moscone West)


    NOTE EARLY START

    8:00 AM *D1.1
    Amorphization/templated Recrystallization (ATR) Method for Hybrid Orientation Substrates. K. L. Saenger1, J.P. de Souza1, K. E. Fogel1, J. A. Ott1, A. Reznicek1, C. Y. Sung1, D. K. Sadana1 and H. Yin2; 1Research Div. / T.J. Watson Research Ctr., IBM Semiconductor Research & Development Center, Yorktown Heights, New York; 2Microelectronic Division, IBM Semiconductor Research & Development Center, Hopewell Junction, New York.

    8:30 AM D1.2
    Systematic Characterization of Pseudomorphic (110) Intrinsic SiGe Epitaxial Films for Hybrid Orientation Technology with Embedded SiGe Source/Drain. Christine Ouyang1,2, Anita Madan2, Nancy R. Klymko2, Jinghong Li2, Richard J. Murphy2, Horatio S. Wildman2, Robert E. Davis2, Conal E. Murray1,2, Judson R. Holt2, Siddhartha Panda2, Meikei Ieong1,2 and Chun-Yung Sung1,2; 1IBM TJ Watson Research Center, Yorktown Heights, New York; 2IBM SRDC, Systems and Technology Group, Hopewell Junction, New York.

    8:45 AM D1.3
    Source/Drain Stressor Device Development on SOI Substrate. Da Zhang, Bich-Yen Nguyen, Brian Goolsby, John Hackenberg, veer dhandapani, jill hildreth, ross noble, mo jahanbani, stan filipiak, ted white, michael mendicino, amr haggag, melissa zavala, patrick montgomery, david theodore, sharon murphy, raghaw rai, jack jiang, kiwoon kim, david sieloff, nigel cave, venkat kolagunta, jon cheek, suresh venkatesan and joe mogab; Technology Solutions Organization, Freescale Semiconductor, Austin, Texas.

    9:00 AM D1.4
    Schottky Source/Drain Transistor on thin SiGe on Insulator integrated with HfO2/TaN gate stack. Fei Gao1,2, Sungjoo Lee1, Rui Li1, S. Balakumar2, Chin-Hang Tung2, Dong-Zhi Chi3 and Dim-Lee Kwong2; 1, Silicon Nano Device Lab, Department of ECE, National University of Singaproe, Singapore, Singapore; 2Institute of Microelectronics Engineering, Singapore, Singapore, Singapore; 3Institute of Materials Research Engineering, Singaproe, Singapore, Singapore.

    9:15 AM D1.5
    Large Optimisation of Source/Drain Architecture in Double Gate CMOS using Combined Static and Transient Analysis. Christophe Krzeminski1 and Dubois Emmanuel2; 1ISEN, IEMN, Villeneuve d'Ascq, France; 2ISEN, IEMN, Villeneuve d'Ascq, France.

    9:30 AM *D1.6
    Perspective on Emerging Devices and their Impact on Scaling Technologies. Thomas Hoffmann, Serge Biesemans and Malgorzata Jurczak; IMEC, Leuven, Belgium.

    10:00 AM BREAK

    10:15 AM D1.7
    Schottky-barrier height tuning using dopant segregation in Schottky-barrier MOSFETs on fully-depleted SOI Joachim Knoch, Min Zhang, Qing-Tai Zhao and Siegfried Mantl; Institute of Thin Films and Interfaces, ISG1, Forschungszentrum Juelich, Juelich, Germany.

    10:30 AM D1.8
    Self-Aligned, Self-Organized Epitaxial Metal Source/Drain for Advanced SOI-MOSFETs. Nobuyuki Mise1, Yukimune Watanabe1, Shinji Migita2, Toshihide Nabatame1, Hideki Satake1 and Akira Toriumi2,3; 1MIRAI-ASET, Tsukuba, Ibaraki, Japan; 2MIRAI-ASRC, Tsukuba, Ibaraki, Japan; 3The University of Tokyo, Bunkyo-ku, Tokyo, Japan.

    10:45 AM D1.9
    Visualisation of Ge Condensation in SOI Kristel Fobelets1, Benjamin Vincent1,3, Anthimos Christofi2, Munir Ahmad1, David Stuart McPhail2 and Jing Zhang1; 1Electrical and Electronic Engineering, Imperial College London, London, United Kingdom; 2Materials, Imperial College London, London, United Kingdom; 3LETI, Grenoble, France.

    11:00 AM D1.10
    Structure and Process Parameter Optimization for Sub-10nm Gate Length Fully Depleted N-Type SOI MOSFETs by TCAD Modeling and Simulation Yawei Jin, Lei Ma, Chang Zeng and Doug barlage; Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina.

    11:15 AM D1.11
    Schottky Barrier Height of CVD TiSiN, PVD TiN, and ALD TiN on p-Si (100). Kaveri Mathur1, Daniel Pham1,2, Barry Sassman1, Lisa Widodo1, George A. Brown1, Peter Zeitzoff1, Howard R. Huff1 and Larry Larson1; 1SEMATECH, Austin, Texas; 2Freescale Semiconductor, Austin, Texas.

    11:30 AM *D1.12
    CMOS Scaling Challenges and Performance Enhancers. Witek Maszara and Zoran Krivokapic; AMD, Sunnyvale, California.

    SESSION D2: Process and Substrate-Induced Strained-Si Development
    Chairs: Wen-Chin Lee and Scott Thompson
    Tuesday Afternoon, April 18, 2006
    Room 3006 (Moscone West)

    1:30 PM D2.1
    A Novel High-Stress Pre-Metal Dielectric Film to Improve Device Performance for sub-65nm CMOS Manufacturing. Y.W. Teh1, J. Sudijono1, S. Thirupapuliyur2, S. Venkataraman2 and Alok Jain2; 1Chartered Semiconductor, Hopewell Jn., New York; 2Applied Materials, Sunnyvale, California.

    1:45 PM D2.2
    Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features. Claude Ortolland1, Pierre Morin2, Franck Arnaud2, Stephane Orain1, Chandra Reddy3, Catherine Chaton4 and Peter Stolk1; 1Philips Semiconductors, Crolles, France; 2ST Microelectronics, Crolles, France; 3Freescale, Crolles, France; 4CEA-LETI, Crolles, France.

    2:00 PM *D2.3
    Strain-Si Technologies for Nano-CMOS Devices Ken-Ichi Goto, TSMC, Hsinchu, Taiwan.

    2:30 PM D2.4
    Process-Induced Strained P-MOSFET Featuring Nickel-Platinum Silicided Source/Drain. Rinus Tek Po Lee1, Tsung-Yang Liow1,2, Kian-Ming Tan1, Kah-Wee Ang1,2, King-Jien Chui1, G.-Q. Lo2, D.-Z. Chi3 and Yee-Chia Yeo1; 1Silicon Nano Device Lab, Electrical and Computer Engineering, National University of Singapore, Singapore, Singapore; 2Institute of Microelectronics, Singapore, Singapore; 3Institute of Materials Research and Engineering, Singapore, Singapore.

    2:45 PM D2.5
    Thermal stability of thin virtual substrates for high performance devices Sarah H Olsen1, Steve J Bull1, Peter Dobrosz1, Enrique Escobedo-Cousin1, Anthony G O'Neill1, Howard Coulson2, Cor Claeys3, Roger Loo3, Romain Delhougne3 and Matty Caymax3; 1University of Newcastle, Newcastle upon Tyne, United Kingdom; 2Atmel North Tyneside, Newcastle upon Tyne, United Kingdom; 3IMEC, Leuven, Belgium.

    3:00 PM BREAK

    3:30 PM *D2.6
    Strain Engineering and Body Biasing for Optimization of Sub-45nm CMOS Performance Kyoungsub Shin1, Sriram Balasubramanian1, Xin Sun1,2 and Tsu-Jae King2,1; 1Electrical Engineering and Computer Sciences Dept., University of California, Berkeley, California; 2Advanced Technology Group, Synopsys, Inc., Mountain View, California.

    4:00 PM D2.7
    Impact of In-situ C Doping on Implant Damage and Strain Relaxation in Epitaxial SiGe Layers on Si Jinping Liu1, Anthony Domenicucci2, Anita Madan2, Jinghong Li2, Judson Holt2, Richard Murphy2, Andrew Turansky2, Robert E. Davis2, Lindsay E. Burns2 and John Sudijono1; 1Technology Development, Chartered Semiconductor Manufacturing Ltd., Hopewell Junction, New York; 2IBM Systems and Technology Group, Hopewell Junction, New York.

    4:15 PM D2.8
    Optimization of Device Parameters for Strained Silicon on Insulator MOSFETs Yan Du, Saurabh Chopra, Nivedita Biswas, Veena Misra and M.C. Ozturk; ECE Department, North Carolina State University, Raleigh, North Carolina.

    4:30 PM D2.9
    The Importance of Grain Orientation in Process Induced Strain. Cristina Torregiani2,1, Alessandro Benedetti1, Hugo Bender1 and Karen Maex2,1; 1spdt, IMEC, Leuven, Belgium; 2Electrical Engineering, KULeuven, Leuven, Belgium.

    4:45 PM D2.10
    Impact of Heavy Boron Doping and Nickel Germanosilicide Contacts on Biaxial Compressive Strain in Pseudomorphic Silicon-Germanium Alloys on Silicon. Saurabh Chopra1, Mehmet C. Ozturk1, Veena Misra1, Kristopher McGuire2 and Laurie E. McNeil2; 1Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, North Carolina; 2Department of Physics and Astronomy, University of North Carolina, Chapel Hill, North Carolina.

    SESSION D3: Poster Session
    Tuesday Evening, April 18, 2006
    8:00 PM
    Salons 8-15 (Marriott)

    D3.1
    Raman Spectroscopy Based All Stress Tensor Component In-line Metrology for SOI and SiGe Device Manufacturing. Wojciech J. Walecki, Talal Azfar, Alexander Pravdivtsev, Manuel Santos, Jae-sok Ryu, Tim Wong, Aiguo Feng and Ann Koo; FSM, San Jose, California.

    D3.2
    Evidence of Reduced Self Heating with Partially Depleted SOI MOSFET Scaling. Mikael Casse1, Georges Guegan1, Romain Gwoziecki1, Olivier Gonnard2, Gilles Gouget2, Christine Raynaud1 and Simon Deleonibus1; 1CEA/DRT-LETI, Grenoble, France; 2ST Microelectronics, Crolles, France.

    D3.3
    Quantum Well Nanopillar Transistors. Shu-Fen Hu, National Nano Device Laboratories, Hsinchu, Taiwan.

    D3.4
    Effect of Spacer Scaling on MOS Transistors. Wai Shing Lau, School of EEE, Nanyang Technological University, Singapore, Singapore.

    D3.5
    Growth of InGaAs on Nanometer-scale Patterned Si substrates by Metalorganic Vapor Phase Epitaxy Robyn L Woo, Dick Cheng and Robert F Hicks; Chemical Engineering, UCLA, Los Angeles, California.

    D3.6
    Selective Oxidation Of Sige Alloys To Make Ge-On-Insulator Structures. Nevran Ozguven and Paul C McIntyre; Materials Science and Engineering, Stanford University, Stanford, California.

    D3.7
    Quantitative X-ray Probes for Strain in Silicon Nanostructures. Rebecca J. Sichel1, P. G. Evans1, M. M. Roberts1, D. S. Tinberg1, M. G. Lagally1 and Z. Cai2; 1Materials Science Program, University of Wisconsin, Madison, Madison, Wisconsin; 2Argonne National Laboratory, Argonne, Illinois.

    D3.8
    High Quality Low Temperature Silicon Dioxide. Hood Chatham, Yoshi Okuyama, Karl Williams, Martin Mogaard and Helmuth Treichel; Aviza Technology, Inc., Scotts Valley, California.

    D3.9
    Strain Relaxation and Solid Phase Epitaxial Regrowth in Ion-Implanted Strained Silicon on Relaxed SiGe Michelle Phen1, Kevin Jones1 and Valentin Craciun1; 1University of Florida, Gainesville, Florida; 2Intel Corporation, Chandler, Arizona; 3University of Aarhus, Aarhus, Denmark.

    D3.10
    A Single Nanoparticle Transistor Stephen Alan Campbell1, Yongping Ding1, Ying Dong1, Ameya Bapat2, Julia Deneen3, C. Barry Carter3 and Uwe Kortshagen2; 1ECE, University of Minnesota, Minneapolis, Minnesota; 2mechanical Engineering, University of Minnesota, Minneapolis, Minnesota; 3Chemical Engineering / Materials Science, University of Minnesota, Minneapolis, Minnesota.

    D3.11
    Sub-aF resolution C-V characterization of small-scale MOSFETs Ali Gokirmak and Sandip Tiwari; Electrical and Computer Engineering, Cornell University, Ithaca, New York.

    D3.12
    BCl3/N2 Plasma for Advanced non-Si Gate Patterning Denis Shamiryan, Vasile Paraschiv, Salvador Eslava-Fernandez, Marc Demand, Mikhail Baklanov and Werner Boullart; IMEC, Leuven, Flemis Brabant, Belgium.

    D3.13
    Layer Transfer of Hydrogen-implanted Silicon Wafers by Thermal-Microwave Co-Activation T. -H. Lee1,2, Y. Y. Yang2, C. -H. Huang2, Y. K. Hsu2, S. Lee2, Q. Gan3 and C. S. Chu4; 1Institute of Materials Science and Engineering, National Central University, Chung-Li City, Taiwan; 2Mechanical Engineering, National Central University, Chug-Li City, Taiwan; 3United SOI Corporation, Berkeley, California; 4Shenyang SOI Corporation, Shenyang, China.

    SESSION D4: Characterization and Methods of New Materials and Structures
    Chairs: Faran Nouri and Wilman Tsai
    Wednesday Morning, April 19, 2006
    Room 3006 (Moscone West)


    8:30 AM D4.1
    Introduction of Airgap Deeptrench Isolation in STI Module for High Speed SiGe : C BiCMOS Technology. Eddy Kunnen1, Li Jen Choi2, Stefaan Van Huylenbroeck2, Andreas Piontec2, Frank Vleugels2, Tania Dupont1, Katia Devriendt3, Xiaoping Shi4, Serge Vanhaelemeersch5 and Stefaan Decoutere2; 1Etch, IMEC, Heverlee, Belgium; 2BiCMOS Integration, Imec, Heverlee, Belgium; 3CMP, Imec, Heverlee, Belgium; 4Thin Films, Imec, Heverlee, Belgium; 5AMPS, Imec, Heverlee, Belgium.

    8:45 AM *D4.2
    Si and SiGe Epitaxy: Defining the Transistor Roadmap Arkadii V. Samoilov, Maxim Integrated Products, San Jose, California.

    9:15 AM D4.3
    Ultra-High Growth Rate of Epitaxial Silicon by Chemical Vapor Deposition at Low Temperature with Novel Precursor. Keith H Chung1, Nan Yao1, James C Sturm1, Kaushal K Singh2, David Carlson2 and Satheesh Kuppurao2; 1Princeton Institute of Science and Technology of Materials (PRISM) and Department of Electrical Engineering, Princeton University, Princeton, New Jersey; 2Applied Materials, Santa Clara, California.

    9:30 AM D4.4
    A Side-gated MOSFET: Electrostatic Suppression of Short-channel and Edge Effects for sub-70 nm Gate Length CMOS Technology. Ali Gokirmak and Sandip Tiwari; Electrical and Computer Engineering, Cornell University, Ithaca, New York.

    9:45 AM D4.5
    Low Temperature Selective Si and Si-Based Alloy Epitaxy For Advanced Transistor Applications. Yihwan Kim, Ali Zojaji, Errol Sanchez, Zhiyuan Ye, Andrew Lam, Nicholas Dalida and Satheesh Kuppurao; Epi KPU, Applied Materials, Sunnyvale, California.

    10:00 AM BREAK

    10:30 AM D4.6
    Electrical Properties of Silicon Nanoparticles Deposited by Low Pressure Chemical Vapor Deposition Deepthi Gopireddy1, Christos Takoudis1, Dan Gamota2, Jie Zhang2 and Paul Brazis2; 1Chemical Engineering, University of Illinois - Chicago, Chicago, Illinois; 2Motorola Advanced Technology Center, Motorola, Shaumburg, Illinois.

    10:45 AM D4.7
    Nano-scale MOSFET Devices Fabricated Using a Novel Carbon-Nanotube-based Lithography. Jaber Derakhshandeh1, Yaser Abdi1, Shamsoddin Mohajerzadeh1, Mohammad Beikahmadi1, M D Robertson2 and J C Bennett2; 1electrical, thin film lab, tehran, tehran, Iran; 2Physics, Acadia University, Wolfville, NS, Quebec, Canada.

    11:00 AM D4.8
    Electron Thermal Transport Properties of a Quantum Dot. Xanthippi Zianni, Dept. of Applied Sciences, Technological Educational Institute of Chalkida, Chalkida, Greece.

    11:15 AM *D4.9
    CMOS Performance Enhancement from a Combination of NiSi Metal Gate (FUSI) and Uniaxial Strained Silicon Channels Kelin Kuhn, Chris Auth, Tahir Ghani and Pushkar Ranade; Intel Corporation, Hillsboro, Oregon.

    SESSION D5: Modeling and Metrology
    Chairs: Faran Nouri and Wilman Tsai
    Wednesday Afternoon, April 19, 2006
    Room 3006 (Moscone West)

    1:30 PM D5.1
    Using Quantitative TEM Analysis of Implant Damage to Study Surface Recombination Velocity in Silicon. Sophia Nadya Morghem, Jennifer Gasky and K. S. Jones; Materials Science and Engineering, University of Florida, Gainesville, Florida.

    1:45 PM D5.2
    Diffraction from Periodic Arrays of Oxide-filled Trenches in Silicon: Investigation of Local Strains. Michel Eberlein1,2, Stephanie Escoubas1, Olivier Thomas1, Pascal Rohr2 and Romain Coppard2; 1TECSEN CNRS, Universite Paul Cezanne, MARSEILLE, France; 2ATMEL Rousset, Rousset, France.

    2:00 PM D5.3
    Stress and Strain Measurements in Semiconductor Device Channel Areas by Convergent Beam Electron Diffraction Jinghong Li, Anthony Domenicucci, Dureseti Chidambarrao, Brian Greene, Nivo Rovedo, Judson Holt, Derren Dunn, Hung Ng and Ken Rim; STG Division, IBM, Hopewell Junction, New York.

    2:15 PM D5.4
    A Physically Based Quantum Correction Model for DG MOSFETs Markus Karner1, Martin Wagner1, Tibor Grasser2 and Hans Kosina1; 1Institute for Microelectronics, TU Wien, Vienna, Austria; 2Christian Doppler Laboratory for Microelectronics, TU Wien, Vienna, Austria.

    2:30 PM *D5.5
    TCAD Modeling of Strain-Engineered MOSFETs. Lee Smith, Synopsys, Inc., Mountain View, California.

    3:00 PM BREAK

    3:30 PM D5.6
    Fundamental Modeling of Group V Dopant Diffusivity and Clustering in Strained Si and SiGe Alloys. Mohit Kumar Haran, James Catherwood and Paulette Clancy; Chemical and Biomolecular Engineering, Cornell University, Ithaca, New York.

    3:45 PM D5.7
    Predictive model for diffusion in strained SiGe based on atomistic calculations. Chihak Ahn1, Jakyoung Song2 and Scott T Dunham1,2; 1Physics, University of Washington, Seattle, Washington; 2Electrical Engineering, University of Washington, Seattle, Washington.

    4:00 PM D5.8
    3D Modelling of the Novel nanoscale Screen-Grid FET. Pei Wern Ding1, Kristel Fobelets1 and Jesus Enrique Velazquez Perez2; 1Electrical and Electronic Engineering, Imperial College London, London, United Kingdom; 2Fisica Aplicada, University of Salamanca, Salamanca, Spain.

    4:15 PM D5.9
    TCAD Modeling and Simulation of Sub-100nm Gate Length Silicon and GaN based SOI MOSFETs Lei Ma, Yawei Jin, Chang Zeng and Doug Barlage; ECE, North Carolina State University, Raleigh, North Carolina.

    4:30 PM D5.10
    Direct Measurements of Nanoscale Local Lattice Strains in Si CMOS Devices by TEM/CBED. Jiang Huang1, D.K. Cha1, P.R. Chidambaram2, R.B. Irwin2, P.J. Jones2 and M.J. Kim1; 1Electrical Engineering, The University of Texas at Dallas, Richardson, Texas; 2Texas Instruments, Dallas, Texas.



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