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Symposium H: Characterization of Oxide/Semiconductor Interfaces for CMOS Technologies

April 10 - 12, 2007

Chairs

Yves Chabal Dept. of Chemistry and Chemical Biology Rutgers University 136 Frelinghuysen Rd. Piscataway, NJ 08854-8019 732-445-8248		Alain Esteve LAAS/MIS 7 CNRS Ave. du Colonel Roche Toulouse cedex 4, 31077 France 33-5-6133-6353
Nicolas Richard Dept. de Conception et Realisation des Experimentations BP 12 Bruyeres-le-Chatel, 91680 France 33-1-6926-5578		Glen Wilk Transistor and Capacitor Products ASM America 3440 E. University Dr. Phoenix, AZ 85034 602-470-5825

Symposium Support
ANR-LN3M
CEA
Freescale, Inc.
LAAS CNRS
PREA
SAFC Hitech


Proceedings to be published online
(see Proceedings Library at www.mrs.org/publications_library)
as volume 996E
of the Materials Research Society
Symposium Proceedings Series.
This volume may be published in print format after the meeting.

---

* Invited paper

SESSION H1: Si Oxidation, High-k Growth
Chairs: Alex Demkov and David Vanderbilt
Tuesday Morning, April 10, 2007
Room 3007 (Moscone West)
8:30 AM *H1.1
Atomic-scale Modeling of Kinetic Processes During Silicon Oxidation. Alfredo Pasquarello, EPFL-SB-ITP-CSEA, Lausanne, Switzerland.

We model the fundamental kinetic processes occurring during silicon oxidation at the atomic scale.We first focus on the diffusion of the neutral O2 molecule through the oxide layer. Using a multiscale approach [1,2], we find that the diffusion of O2 is a percolative process, critically influenced by both energetical and geometrical features of the potential energy landscape [1,2]. Then, we use first-principles calculations to address the oxidation reaction of the O2 molecule at the Si(100)-SiO2 interface. To this end, we employ model interface structures reproducing atomic-scale features consistent with a broad range of experimental probes, including photoemission and ion scattering [3,4]. We find that the O2 oxidation reaction occurs by crossing small energy barriers, regardless of the spin or charge state of the molecular species [5,6]. Our findings are consistent with a picture of silicon oxidation solely dominated by the oxygen transport properties through the oxide. [1] A. Bongiorno and A. Pasquarello, Phys. Rev. Lett. 88, 125901 (2002). [2] A. Bongiorno and A. Pasquarello, Phys. Rev. B 70, 195312 (2004). [3] A. Bongiorno et al., Phys. Rev. Lett. 90, 186101 (2003). [4] A. Bongiorno and A. Pasquarello, Appl. Phys. Lett. 83, 1417 (2003). [5] A. Bongiorno and A. Pasquarello, Phys. Rev. Lett. 93, 086102 (2004). [6] A. Bongiorno and A. Pasquarello, J. Phys.: Condens. Matter 17, S2051 (2005).


9:00 AM H1.2
Silicon and Oxygen Self-Diffusion in SiO₂: A Contribution From First-principles Calculations. Guido Roma¹, Yves Limoge¹, Layla Martin-Samos^2,1 and Nicolas Richard³; ¹Service de Recherches de Métallurgie Physique, CEA-Saclay, Gif sur Yvette, France; ²S3-center, University of Modena e Reggio Emilia, Modena, Italy; ³CEA-DIF, Bruyère le Châtel, France.

Silicon dioxide, although widely used as an insulator in microelectronic devices, is still lacking a satisfactory description of its diffusion properties. The measurement of oxygen self-diffusion in crystalline and amorphous SiO₂ has been the object of several works since the sixties, but the large spread in experimental results, probably due to a variety of experimental conditions, has not been thoroughly explained. Similarly, silicon self-diffusion has given rise more recently to a variety of experimental works especially in connection with the Si/SiO₂ interface; nevertheless, several points need to be clarified concerning experimental conditions. Theoretical works, based on ab-initio calculation, have given up to now partial explanations, adapted to peculiar situations and/or diffusion mechanisms, but still a comprehensive explanation is lacking. In the light of a number of ab-initio results that we have obtained in the last few years for formation and migration energies of point defects in crystallin and amorphous SiO₂, we will propose an explanation of the variety of experimental results on the basis of a common framework, including the effect of self-doping and the role of hydrogen/hydroxyl impurities. We will discuss some results about the effects of charge states on the migration of defects and we will point out questions which are still open, together with suggestions of experiments that could lead to the answers.


9:15 AM H1.3
Using OXCAD Monte Carlo Package as a Characterization Tool of Silicon Oxide Growth. Anne Hemeryck¹, Alain Estève¹, Nicolas Richard², Mehdi Djafari Rouhani¹, Andrew J. Mayne³, Yves J. Chabal⁴, Gérald Dujardin³ and Geneviève Comtet³; ¹LAAS - CNRS, Toulouse, France; ²CEA - DIF, Bruyères Le Châtel, France; ³LPPM - CNRS, Orsay, France; ⁴Laboratory for Surface Modification, Rutgers University, New Jersey.

Recent experimental techniques allow the microscopic characterization of systems at the atomic scale. But, it is not yet possible experimentally to study the interface at an atomic scale during growth because of the rapid evolution of the systems, the stringent external conditions not always reproducible in experimental vessels, the signal to noise ratio compared to the experimental resolution of the technique or simply due to an accessibility problem, for example to reach defects inside the bulk. All these limitations can be avoided when using virtual tools which allow to follow the evolution of the system step by step, to perform simulations in all unusual conditions, to access easily inside the bulk and to focus on a single atom property, eliminating all noise from other sources. The present work provides an atomistic picture for the oxygen incorporation mechanisms during silicon oxidation based on a multiscale strategy, combining DFT calculations, Monte Carlo simulations and experimental results, to span a wide range of appropriate scales. ab initio methods allow to determine elementary mechanisms and their thermodynamic parameters such as activation energies, but are restricted in terms of number of atoms and experiment time scales. In order to perform a realistic simulation, this work presents a first large scale modelling of the early stages of the SiO2/Si interface growth. Using a Kinetic Monte Carlo approach, we have been able to model complex processes on large systems with long experiment durations. Ab initio studies used in parallel with the kinetic Monte Carlo simulations provide the necessary input parameters. The SiO2 model is built by introducing oxygen, molecule by molecule, on a crystalline Si(100). Once dissociated, the oxygen atoms move individually, via a random sampling, to explore the ensemble of possible topologies, making the simulation closer to the real experiments. The advantage of such simulations, in contrast with a static Monte Carlo, is that each iteration leads to a physically occurring step. Simulations of the early first stages of the silicon oxide growth and comparisons with different kind of experimental data at atomic scale (notably Infrared Spectroscopy and Scanning Tunnelling Spectroscopy) will be shown.


9:30 AM H1.4
XPS and STM Studies on Initial Oxidation of Si(110)-16x2 Maki Suemitsu¹, Hideaki Togashi¹, Atsushi Kato¹, Yuya Takahashi¹, Atsushi Konno¹, Yoshihisa Yamamoto¹, Yuden Teraoka², Akitaka Yoshigoe² and Hidehito Asaoka³; ¹CIR, Tohoku University, Sendai, Japan; ²Japan Atomic Energy Agency (JAEA), Kouto, Mikazuki-cho, Japan; ³Japan Atomic Energy Agency (JAEA), Tokai, Ibaraki, Japan.

From its enhanced hole mobility as well as its inevitable usage in the multi-gated FETs, Si(110) surface has attracted much attention as an orientation for the active layer(s) in the next-generation CMOS devices. Despite the importance, little is known so far regarding the kinetics of the initial oxidation on Si(110) surface, which should be the key process in the fabrication of (110)-based devices. We have in this study conducted real-time synchrotron-radiation XPS measurements as well as in-situ STM measurements on the initial dry oxidation of Si(110)-16x2 clean surface. One of the striking feature in the oxidation of this surface is the presence of a rapid initial growth regime, in which 20 to 30% of the surface Si atoms are immediately reacted after introduction of the oxygen molecules. Structural analysis using STM strongly suggests selective reactions at the "pentagon pairs", a building block in the 16x2 reconstruction, being behind the phenomena. By detailed analysis of the O1s spectrum, several oxidation states, represented by corresponding subpeaks, are found to exist. The different time evolutions of the subpeaks result in a peak shift of the O1s spectrum, caused by a shift from the dominance of a lower binding-energy state to that of a higher binding-energy state. Based on the resuls, possible oxidation mechanism is discussed.


9:45 AM H1.5
Experimental Measurement of Surface Valence Charge Density in Silicon. James Ciston¹, Laurence D Marks¹, Robert Feidenhans’l², Oliver Bunk³, Bin Deng¹, Arun Subramanian^6,1, Erik M Lauridsen⁵ and Gerard Falkenberg⁴; ¹Materials Science and Engineering, Northwestern University, Evanston, Illinois; ²Niels Bohr Institute, University of Copenhagen, Copenhagen, Denmark; ³Paul Scherrer Institut, Swiss Light Source, PSI, Switzerland; ⁴HASYLAB, Hamburg, Germany; ⁵Materials Research Department, Risø National Laboratory, Roskilde, Denmark; ⁶Intel Corporation, Santa Clara, California.

Measurement of charge density, the distribution of valence electrons important to bonding, in bulk materials is a very well established field in the diffraction community. The majority of current studies have used x-ray diffraction but in some cases transmission electron diffraction has been applied as well. In principle, being able to directly measure the charge density at a surface is at least as scientifically interesting as in the bulk, if not more so. Surfaces and interfaces of materials are becoming increasingly important as devices shrink to the nanoscale. Knowing where the electrons are at surfaces is one of the most important pieces of information one can have to understand how different materials behave, for example in materials used as catalysts that greatly reduce the amount of energy required to produce fuels and other useful products. The exact structure of these surfaces determines their usefulness and, in particular, the charge density at the surface determines the physical, chemical, and electronic properties important to building a device or designing a reaction. We have recently reported the first experimental three-dimensional refinement of the valence charge density for a surface using x-ray diffraction; this particular study was for the Si(100)-2x1H surface. This has been accomplished through the development of a new theoretical and experimental methodology using a combination of transmission electron microscopy, x-ray diffraction, and first-principles quantum mechanics calculations to determine the location of these important valence electrons at the surface. This new model parameterizes the details of the valence charge density in terms of closed functions of the Si-Si bond length implicitly refining the charge density concurrently with the atomic position refinement. This was the first time that this was accomplished for any surface of any material. To test the validity of the methodology, experimental data for the Si(100)-2x1H reconstruction was collected at the wiggler beamline BW2 of the 2nd generation synchrotron radiation facility HASYLAB in Hamburg, Germany. The use of the proposed model yielded a reduced χ figure of merit of 1.261 which is an improvement over the traditional neutral-atom model at a significance level of 99.9%. Therefore, our model is a more accurate representation of the charge density. We were also able to stably refine the positions of the surface hydrogen atoms to an 86% confidence level which has never previously been accomplished for any surface using x-ray diffraction data. Without the use of our improved model, the hydrogen refinement had only a 0.2% confidence level. The future implications of the use of this model will be discussed with preliminary results presented for other semiconducting surfaces.


10:30 AM *H1.6
Modeling Defects in High-K Dielectrics on Silicon. Jacob Gavartin, David Munoz Ramo and Alexander Shluger; London Centre for Nanotechnology, University College London, London, United Kingdom.

Understanding factors controlling electrical properties of the dielectric/semiconductor interfaces is of fundamental importance for silicon based microelectronics. The origin of bands alignment and interfacial defects, their effect on device performance, and a degree to which these parameters can be controlled, are still actively debated. In particular, introduction of novel materials with high dielectric constant (high-k) into complimentary metal-oxide-dielectric (CMOS) technology promises significant improvement in performance and power consumption of novel devices. However, electrical properties of prototypes critically depend on the quality of the high-k thin films and their interface with silicon. Thus, minimization of impact of electrically active defects is a key objective in high-k gate stack engineering. Unambiguous thin film and interface characterization using structural, optical and electrical probes is often limited and data interpretation increasingly depends on underlying models and calculations. In this paper we review recent progress in atomistic studies of defects in high-k materials with a particular attention to two topics: 1. Modeling of HfO2/Si interfaces and establishing interrelations between the oxide growth kinetics, interface morphology and electrical properties. 2. Effects of defects, atomic disorder and electron-phonon coupling on the electrical properties of high-k dielectrics. Using ab initio density functional calculations, we analyze various possibilities for bonding at the Si/SiO2/HfO2 interface and argue that i) depending on the degree of hydroxylation of the Si substrate, a subsequent film growth may occur on either 2x1 or 1x1 reconstructions of the (001)Si surface, or on a a-SiOx surface; ii) depending on the Hf precursors and the deposition conditions, density of Hf ions in the first atomic layer may vary between ½ and a full monolayer. Our modelling of initial ALD growth suggests interface structures significantly different from either epitaxial models or kinetically justified models considered previously. We discuss the implications of the interface morphology on its electrical properties. Next, we address effects of amorphisation of a high-k dielectric film. We propose that the kinetics of interface growth stipulates some degree of oxygen non-stoichiometry in hafnia. The resulting oxide films are characterized by reduced atomic density (typically 95-98% of a bulk value) and certain degree of disorder manifested by appreciable concentration of sub-coordinated oxygen and over-coordinated Hf ions. Importantly, obtained structures are thermally stable and they do not contain defect states (understood as localized states in the band gap). However, we demonstrate that electron injection into the conduction band of HfO2 may lead to its spontaneous trapping by the lattice and a small polaron formation. We discuss relations between a polaron-like trapping in the materials and their dielectric permittivity.


11:00 AM H1.7
Diffusion of O Vacancies near Si:HfO2 Interfaces: A First Principles Investigation. Chunguang Tang and R. Ramprasad; University of Connecticut, Storrs, Connecticut.

Driven by a need for device miniaturization in the microelectronic industry, high-permittivity materials have gained interests as potential substitutes for conventional SiO2 gate dielectrics. Among them, HfO2 and ZrO2 are emerging as promising candidates because of their high dielectric constant and thermodynamic stability. Nevertheless, the quality of the interface between HfO2 (or ZrO2) and Si has important implications for device performance. While HfO2 and ZrO2 are expected to be thermodynamically stable on Si, undesired interfacial phases such as silicides and silicates are known to form. It has been postulated that segregation to the interface of point defects such as O vacancies and interstitials provide a mechanism for such interfacial phase formation. In this work, we have performed detailed first principles computations on several O-terminated Si:HfO2 heterostructures (i.e., heterostructures with an O-layer of HfO2 interfacing with Si), including those based on tetragonal and monoclinic HfO2, to assess their relative stability. To understand the tendency for the atomic level diffusion of O vacancies in such heterostructures, we performed first principles vacancy formation and migration energy calculations at various distances from the interface within two relatively stable heterostructures. Regardless of the actual interface model employed, the O vacancy formation energy decreased monotonically as the Si:HfO2 interface was approached, and was about 1.2-1.5 eV smaller than the corresponding bulk values. The barriers for migration of an O vacancy was about 1.6-2.4 eV in the bulk and reduced to about 0.4 eV as the interface was approached. The computed energies for the two different heterostructures were very close if the O sites involved in the calculations were similarly coordinated, indicating that local chemistry predominantly determines the defect properties. These computations result in the general conclusion that strong thermodynamic and kinetic driving forces exist for the segregation of O vacancies to the interface. Although O-terminated interfaces (the ones thought to be the most thermodynamically stable interfaces) were considered in this work, our results indicate that in the presence of point defects such as O vacancies, these interfaces may be unstable to the formation of Hf silicides due to the segregation and accumulation of O vacancies to the interface, consistent with prior experimental work.


11:15 AM H1.8
Oxygen Vacancy in Monoclinic HfO₂: a Consistent Interpretation of Trap Assisted Conduction, Direct Electron Injection, and Optical Absorption Experiments Peter Broqvist^1,2 and Alfredo Pasquarello^1,2; ¹EPFL-SB-ITP-CSEA, Lausanne, Switzerland; ²IRRMA, Lausanne, Switzerland.

HfO₂ is the most promising candidate high-κ material to replace SiO₂ as gate oxide in metal-oxide semiconductor devices. However, device performance is affected by comparatively high densities of bulk defects, which give rise to flatband voltage instabilities. The occurrence of such defects is revealed in a variety of experiments which include (Poole-Frenkel-type) trap assisted electron conduction [1], direct electron injection [2], and optical absorption [3]. While the measured defect energy levels differ considerably among the various experiments, the oxygen vacancy is generally indicated as their common physical origin. Early electronic-structure calculations on the oxygen vacancy in HfO₂ were based on standard density-functional methods. However, difficulties arise when comparing calculated energy levels with experiment due to the well-known band-gap problem from which these calculations suffer. Xiong et al. [4] realized that it was necessary to use electronic structure methods such as screened exchange to more reliably locate defect energy levels in the band gap. Along these lines, Gavartin et al. [5] recently studied the oxygen vacancy in HfO₂ using another hybrid density functional. However, significant quantitative differences are still found between the calculated energy levels in the latter two investigations. Hence difficulties in the interpretation of experimental data persist. We here calculate energy levels of the oxygen vacancy in HfO₂ which correspond to defect levels measured in various experiments [1]-[3]. To ensure quantitative accuracy for the energy levels, we adopt a hybrid functional (PBE0) and use a framework based on pseudopotentials and plane waves, a set-up which is particularly suitable for solid-state electronic-structure calculations. Further, we express defect levels as total energy differences specific to each experiment. Our results provide a consistent picture in which different states of the oxygen vacancy account for trap assisted conduction [1], direct electron injection [2], and optical absorption experiments [3]. This global interpretation results from the consideration of both the threefold and fourfold coordinated vacancies and their various charge states. [1] Bersuker et al., in Defects in High-k Gate Dielectric Stacks , edited by E. Gusev (Springer, Dordrecht, 2006), Vol. 220, p. 227; Ribes et al., IEEE Trans. Dev. Mat. Rel. 5, 5 (2005). [2] Mitard et al., in Defects in High-k Gate Dielectric Stacks , edited by E. Gusev (Springer, Dordrecht, 2006), Vol. 220, p. 75. [3] Takeuchi et al., J. Vac. Sci. Technol. A 22, 1337 (2004). [4] Xiong et al., Appl. Phys. Lett. 87, 183505 (2005). [5] Gavartin et al., Appl. Phys. Lett. 88, 082901 (2006).


11:30 AM H1.9
Two Types of Oxygen Vacancies in Hf-based High-k Dielectrics - Existence of “Alive” and “Dead” Oxygen Vacancies. Kenji Shiraishi^1,2, Takashi Nakayama³, Seiichi Miyazaki⁴, Naoto Umezawa⁵, Kikuo Yamabe¹, Heiji Watanabe⁶, Toyohiro Chikyow⁵, Yasuo Nara⁷ and Keisaku Yamada⁸; ¹Graduate School of Pure and Applied Physics, University of Tsukuba, Tsukuba, Ibaraki, Japan; ²CREST-JST, Kawaguchi, Saitama, Japan; ³Department of Physics, Chiba University, Chiba, Chiba, Japan; ⁴Grauate School of Advanced Sciences of Matter, Hiroshima University, Higashi-Hiroshima, Hiroshima, Japan; ⁵National Institute for Material Science, Tsukuba, Ibaraki, Japan; ⁶Graduate School of Engineering, Osaka University, Suita, Osaka, Japan; ⁷Semiconductor Leading Edge Technologies Inc., Tsukuba, Ibaraki, Japan; ⁸Nano Technology Research Laboratory, Waseda University, Shinjuku, Tokyo, Japan.

It has been reported that oxygen vacancies (Vo) play crucial roles for both Fermi level pinning (FLP) [1] and reliability issues [2] in Hf-based high-k dielectrics. In this study, we have clarified that the energy distribution of Vo levels in amorphous Hf-based high-k oxides does not affect the FLP and Vo can be categorized into two types. According to our proposed Vo model, effective work functions (WF) are determined by the energetics of the interface reaction accompanied with Vo formation [1]. However, the energy distribution of Vo levels has not been discussed yet. In this study, we describe the Vo with energy level E as Vo(E). The energy gain of interface reaction accompanied with Vo(E) formation can be divided into two parts. One is the energy loss of neutral Vo(E) formation (G), and the other is the energy gain by the electron transfer from neutral Vo in dielectrics into gate electrodes (F). Accordingly, the total energy gain of the reaction is given by F-G. Thus, if F-G is positive, the reaction proceeds with the elevation of gate Fermi level by the generation interface dipoles until F-G becomes zero [1]. Next, we discuss the effect of Vo level distributions by investigating the generation of Vo(E’). Vo(E’) gives electron transfer energy gain (F’=F+2(E’-E)), since energy level of Vo(E’) is located higher than Vo(E) by (E’-E). This difference also increases the neutral Vo(E’) formation energy loss G’ by 2(E’-E). Accordingly, total energy gain of interface reaction accompanied with the Vo(E’) formation is given as F’-G’=(F+2(E’-E))-(G+ F+2(E’-E))=F-G, which is the same value with Vo(E) formation. Thus, the distribution of Vo level does not affect the FLP. However, if Vo level is located lower than the FLP position, Vo generation occurs without electron transfer (interface dipole generation) (“dead Vo”). In this sense, we can categorize Vo into two types by the above discussions, taking into account the Vo level distribution. One is “alive Vo” that affects the FLP, and the other is “dead Vo” that does not affect the FLP. [1] K. Shiraishi et al., Tech. Dig. VLSI Tech. p.108 (2003). [2] K. Torii et al., Tech Dig. IEDM, p.129 (2004).


11:45 AM H1.10
Fluorine Passivation of Vacancies in HfO2 Gate Oxide. Koon-yiu Tse and John Robertson; Engineering, Cambridge University, Cambridge, United Kingdom.

High dielectric constant oxides such as HfO2 are very important as gate dielectrics in future CMOS devices. However compared to SiO2 they suffer from much higher defect concentrations which cause charge trapping, threshold voltage instability, and mobility degradation. The main defect is the oxygen vacancy. It has been found experimentally that fluorine is able to passivate these defects. The mechanism of defect passivation is calculated using ab-initio methods. Substitutional fluorine is found to remove all deep states from the HfO2 band gap. F is implanted as interstitial F, and this is found to kick out lattice oxygen, during its diffusion process. The general principles of defect passivation in ionic oxides are discussed. K Tse, J Robertson, App Phys Lett 89 142914 (2006)


SESSION H2: Si and Oxidation and High-k Growth
Chairs: A. Esteve and A. Pasquarello
Tuesday Afternoon, April 10, 2007
Room 3007 (Moscone West)
1:30 PM *H2.1
Density Functional Theory of High-k Dielectric Gate Stacks. Alex Demkov, Department of Physics, The University of Texas, Austin, Texas.

The semiconductor industry is responsible for much of the world’s extraordinary economic expansion over the past fifty years. However, as the industry matures, the rate of innovation tends to saturate, and so does the growth. To continue scaling semiconductor devices below 45 nm, radically new materials need to be introduced into Si-dominated technology. One of the most active areas of research and development is a search for a new gate dielectric (so-called high-k dielectric) with a dielectric constant higher than that of silicon dioxide and silicon oxynitride. Transition metal (TM) oxides and in particular hafnium dioxide quickly emerged as leading candidates to replace SiO2. However, the intrinsic complexity of these materials has been underestimated, which made their integration into Si processing rather difficult. The rich physics and chemistry of TM oxides come from the presence of d-electrons. Being credited for the high polarizability and therefore a large dielectric constant (thus the high-k) of the material they are also responsible for lattice instabilities, multiple charge state defects, and rather daunting interface chemistry. Another complication arises from the early decision to use a dual metal solution for the gate electrode. Theoretical work and especially materials models based on density functional theory added much to our understanding of TM oxides and their interfaces with Si and other semiconductors, SiO2 and various metals in the context of semiconductor manufacturing. In this talk I will review recent progress in the ab-initio theory of high-k dielectrics, and outline the main ideas of the theory of polarizability, Schottky barriers, and correlated electrons as they apply in materials research. In particular, I will describe studies of the band alignment and dielectric response at high-k interfaces and their relation to the local stoichiometry. I will focus on the analysis of the thermodynamics and electronic structure of hafnia interfaces with semiconductors, oxides and metals performed in our group.


2:00 PM H2.2
First-Principles Calculations of the Structure and Dielectric Properties of HfO₂-SiO₂-Si Stacks Eric Cockayne, Ceramics Division, NIST, Gaithersburg, Maryland.

First-principles density function theory calculations were used to investigate the structure and dielectric properties of HfO₂-Si stacks with a SiO₂ interface layer. Periodic boundary conditions were used, with a vacuum layer between the repeating stacks. Relaxed interface structures were determined via ab-initio molecular dynamics followed by total energy minimization. The dangling Si bonds on the free Si surface were hydrogenated. A bandgap was opened by terminating the free HfO₂ surface with O bridging between two Hf. The Born effective charges tensors of the ions were calculated using the Berry's phase method of King-Smith and Vanderbilt. The effective charge components within the layers are nearly the same as the values in the corresponding bulk oxides, except near the surfaces, where they are suppressed. The effective charge components perpendicular to the stack are suppressed due to depolarizing fields. Phonons and dielectric properties were also calculated. Phonons with frequency near 330 cm^-1 contribute most to the permittivity, as in bulk HfO₂. The results are discussed in terms of the macroscopic electrostatics of parallel capacitors.


2:15 PM H2.3
Local Dielectric Permittivity of HfO2 Based Multi-layers: A First Principles Study. Ning Shi and Rampi Ramprasad; Department of Chemical, Materials & Biomolecular Engineering,Institute of Materials Science, University of Connecticut, Storrs, Connecticut.

Alternative gate dielectric materials are sought after for future micro- and nano-electronic devices. Thin films based on high dielectric constant (high-k) materials are being proposed to replace SiO2, the currently used dielectric material. HfO2 is the most promising candidate due to its high dielectric constant, wide band gap, and thermal stability in contact with Si substrates. However, the Si:HfO2 interface, and defects at the interface are expected to play a dominant role in determining the dielectric properties of these next generation dielectric stacks. This calls for an accurate determination of atomic-scale dielectric permittivity profile across the Si:HfO2 heterostructure. In this work, first principles density functional theory based methods are used to determine the position dependent dielectric permittivity profiles of several coherent Si:HfO2 heterostructures, using a recently developed method [N. Shi and R. Ramprasad, Phys. Rev. B, 74, 045318 (2006)]. This new procedure allows for the treatment of both the high frequency (when only the electrons are allowed to respond to the external electric field, while the ionic cores are held fixed) and low frequency (when both the electronic and ionic degrees of freedom are allowed to relax) contributions to the dielectric permittivity. We have considered Si:HfO2 interfaces with and without point defects at the interface. In the case of defect-free interfaces, we find that at regions close to the interfaces, the dielectric permittivity is enhanced compared to the corresponding bulk values, while in interior regions, it approaches the bulk values. The calculated bulk optical and static dielectric constant values of these systems are in excellent agreement with experimental results, and other more involved computational treatments. Point defects such as O vacancies result in deviations based on their location. This work has resulted in a simple method for determining both the electronic and total dielectric permittivity profile of a multi-layered dielectric stack, including interfaces and defects using standard total energy methods


2:30 PM H2.4
Fluorine Incorporation at HfO₂/SiO₂ Interfaces in High-k Metal-Oxide-Semiconductor Gate Stacks. Jeong-Hee Ha¹, Paul C. McIntyre¹ and Kyeongjae (KJ) Cho²; ¹Materials Science and Engineering, Stanford University, Stanford, California; ²Department of Physics, Department of Electrical Engineering, University of Texas at Dallas, Dallas, Texas.

For several decades, silicon semiconductor devices have been dramatically scaled down to sub-100 nm MOSFET channel lengths in order to achieve higher device density and performance. In this regime, high-k dielectrics which can give large gate capacitances with dielectric films that are physically thicker than corresponding silicon oxide or oxynitride gate dielectrics are needed to reduce the substantial gate leakage current resulting from direct quantum mechanical tunneling across the dielectric layer. Recently research on materials selection for alternative gate stack has converged on HfO₂ based high-k oxides (HfO₂, HfSiO₄, or HfSiON) deposited in a process which results in controlled formation of an ultra-thin SiO₂-like passivation layer on the Si (100) surface. This SiO₂-based interface layer provides the advantages of relatively low defect density and possible hydrogen passivation of dangling bonds afforded by the Si/SiO₂ interface. However, it has been reported that defects at the internal dielectric interface between HfO₂ and SiO₂ may produce fixed charge and threshold voltage instability under bias. In this presentation, we explore the possibility of passivating such defects by fluorine incorporation, using both computational and experimental analyses. Both ab-initio simulations and electrical measurements show that highly electronegative F atoms are able to remove midgap states that provide positive fixed charge, an intrinsic defect feature of HfO₂/SiO₂ gate stacks. Our results also indicate F incorporation increases the leakage current if an excessive amount of F is incorporated in the dielectric films after passivating under-coordinated Hf ions at HfO₂/SiO₂ interface. However, considering the passivating ability of F ions for under-coordinated Hf ions at this interface and the strength of their bonding, a fluorination process is advantageous for improving the reliability of high-k gate stacks. Approaches to maximize the advantages of F incorporation in high-k gate stacks are also discussed.


2:45 PM H2.5
Chemical Properties of HfSiO:N / Si Stacks Studied by Auger and Photoemission Spectroscopy. Eugenie Martinez, Lionel Fourdrinier, Olivier Renault and François Martin; CEA-LETI, Grenoble, France.

Hf-based dielectrics emerge as leading candidates for high-K insulators in CMOS devices instead of SiO2. In order to prevent the dielectric crystallization, thermal stability is improved by addition of Si thus forming Hf-silicates. A subsequent nitridation helps to improve thermal stability, reduces oxygen vacancies and increases the dielectric constant [1]. Thick films of HfSiO (8 nm) are deposited on top of Si(100) substrates using low temperature MO-CVD with Hf and Si based precursors. A controlled plasma nitridation is performed and followed by a N2 anneal at 700°C. We investigate the chemical properties of Hf silicates, in terms of chemical binding and depth profiles, before and after nitridation. For Hf-silicates, a strong relationship exists between material properties, e. g. chemical binding, and devices performances [2]. Photoemission spectroscopy is used to perform an accurate analysis of the bonding states. Synchrotron Radiation PhotoElectron Spectroscopy (SR-PES) is done at the Elettra storage ring with high energy resolution (50 meV) and high signal to noise ratio. A detailed analysis of bonding states before and after nitridation of Hf-silicates will be presented. Angle-Resolved XPS is also carried out with an S-Probe spectrometer equipped with a monochromated, micro-focussed Al source (1486.6 eV). Photoelectrons are collected at several angles between 10° and 75° with an energy resolution of 700 meV. Results at 10° and 35° are compared to the synchrotron measurements. Experiments at 75° enable to probe the whole film thickness to investigate the chemical bonds at the interface with Si. The ratio of Hf-N and Si-N bonds, known to increase the dielectric constant, can be accurately determined at several angles, with no contribution of the interfacial SiO2 layer. AR-XPS measurements are also used together with a reconstruction tool based on the maximum entropy method to estimate the nitrogen depth profile. The impact of a high temperature anneal under O2 will be outlined. The nitridation is also studied using Auger Electron Spectroscopy (AES) together with Ar+ ions bombardment to sputter the HfSiO:N layers. The depth profiles will be compared to the reconstructed profiles obtained with AR-XPS and discussed in terms of interface chemical properties before and after nitridation. [1] E. P. Gusev, V. Narayanan and M. M. Frank, IBM J. Res. and Dev. 50, 387 (2006). [2] M. Koike, T. Ino, Y. Kamimuta, M. Koyama, Y. Kamata, M. Suzuki, Y. Mitani, A. Nishiyama and Y. Tsunashima, Proceedings of the IEDM Conference, 107 (2003). Acknowledgements The authors would like to thank N. Barrett for his assistance during experiments at Elettra. This work has been carried out in the frame of the Philips, Freescale Semiconductor, ST Microelectronics Alliance and CEA-LETI collaboration.


3:30 PM *H2.6
Density Functional Theory Simulations of the Interfacial Electronic Structure of HfO₂ Films on Ge. Charles B. Musgrave, Stanford University, Stanford, California.

We use density functional theory to investigate the electronic properties of Ge-HfO₂ interfaces. A series of interface structures are generated including epitaxially connected HfO2 on Ge, defective HfO₂ on Ge, HfO₂ on Ge with germanium suboxide interlayers and disordered HfO₂ on Ge and on Ge with a GeOx interlayer. The projected density of states of these interfaces indicate the source of gap states for these interfaces and the effect of passivants on these states. We also use Born-Oppenheimer quantum molecular dynamics and simulated annealing to evolve interface structures and also to investigate bias temperature instabilities of these interfaces.


4:00 PM H2.7
Theoretical Study of the Insulator/insulator Interface: Band Alignment at the SiO2/HfO2 Junction. Onise Sharia¹, Alex Demkov¹, Gennadi Bersuker² and Byoung Hun Lee²; ¹Physics, The University of Texas, Austin, Texas; ²SEMATECH, Austin, Texas.

Hafnia has emerged as a front runner for replacing silica as a gate oxide in CMOS technology. One of the problems which still remains outstanding is finding a p-type gate metal for hafnia. Thus the problem of band alignment at the hafnia/metal and hafnia/Si interfaces has recently received significant attention. However, it is worth noting that during the deposition of hafnia on a silicon substrate a thin layer of silica is always created. And the band alignment between silica and hafnia can dramatically change the overall alignment across the gate stack. In this presentation we will discuss the band alignment at the SiO2/HfO2 interface. As we shall show it can be significantly different from the simple Schotky limit. We perform ab-initio studies of the interface using density functional theory in the local density approximation. We construct several atomic level models of the interface which connect hafnia to silica via an oxygen plane as required by the electron count rule that ensures the absence of electronic states in the gap. The models differ by the interfacial oxygen coordination, HfO2 phases, and strain, and are fully relaxed. All interfaces can be categorized by the interfacial oxygen average coordination number. The calculated valence band offset varies from 1.0 eV to -2.0 eV and most strongly depends on the average coordination of the interface oxygen. The Schottky limit (1.6 eV) is recovered for the highest oxygen coordination. Results of our ab-initio calculations can be understood if the problem is cast as that of a plane capacitor where the interface oxygen atoms play a role of a dielectric medium. The deviation from the Shcottky rule arises in two steps. First the dipole layer is formed caused by the charge transfer from hafnia to silica due to the difference of the charge neutrality levels of the oxides. Second, the field of that dipole is screened by the interfacial layer. We argue that the leading contribution comes from the lattice screening. The dependence of this lattice screening on the oxygen coordination can be understood as follows. Ignoring for simplicity the variation in phonon frequencies from interface to interface we extract the dependence of the oxygen Born effective charge (BEC) on the oxygen coordination from the dielectric constant given by the capacitor model. The BEC scales almost linearly with the average coordination of the interface oxygen, and reaches approximately correct values for the limiting cases of silica (coordination is 2) and hafnia (coordination is 3). The maximum possible Born effective charge of -3 corresponds to the highest coordinated oxygen atoms and the Schottky limit is recovered.


4:15 PM H2.8
Defect States in HfO2 Caused by Silicate Formation or Oxygen Vacancies. Dieter Schmeisser¹, Hans-Juergen Engelmann² and Ehrenfried Zschech²; ¹Applied Physics, BTU Cottbus, Cottbus, Germany; ²AMD Saxony, Dresden, Germany.

We report on the electronic structure of HfO2 films deposited by ALD on Si(001). We employ synchrotron based photoelectron spectroscopy to analyze the Si2p core levels as well as the va-lence band emissions using excitation energies around the Si2p and the O1s thresholds, respec-tively. We compare such data to the X-ray absorption spectra and the electron energy loss data obtained from an TEM analysis. In addition we determine the value of the band gap by a electron energy loss spectrometer operated at 50eV primary energies. In our studies we focus on two issues. First, the presence of Si in the dielectric film (silicate for-mation) is found to depend on the choice of the precursor material. We identify electronic states within the band gap which vary in their amount dependent on the relative amount of Si within the dielectric Hf-Ox-Si films. Second, we find that oxygen vacancies have a significant feature in the spectroscopic data at the O1s threshold, in particular in films which have almost no Si contri-butions.


4:30 PM H2.9
High-Resolution X-ray Phototoelectron Spectroscopy Investigations on the Core-shell Interface of Nitrided Si Nanocrystals. Joel Dufourcq¹, Olivier Renault², Corrado Crotti⁵, Nick Barrett⁴, Sylvie Bodnar¹, Gilles Festes¹, Pierre Mur², Thierry Baron³ and Romain Coppard¹; ¹Atmel Rousset, Rousset, France; ²CEA-LETI-MINATEC, Grenoble, France; ³CNRS-LTM, Grenoble, France; ⁴CEA-DSM-DRECAM, Saclay, France; ⁵C.N.R. Istituto Struttura Della Materia, Trieste, Italy.

Silicon nanocrystals (Nc-Si) embedded in SiO2 matrix are a promising candidate to replace continuous polysilicon floating gate in future flash memories. The robustness of Nc-Si in term of resistance to thermal treatment (mainly oxidation) during the elaboration process of a memory stack is a key parameter that can be improved by a nitridation of the nanocrystal core-shell interface. Moreover, nitridation processes may generate interfacial traps which can affect the electrical performances of flash memory devices. Synchrotron Radiation X-ray Photoelectron Spectroscopy (SRXPS) has been recently used to characterize nc-silicon/SiO2 oxide interface: it has been reported that an oxide shell growth of 0.7nm can induce a high structural disorder into the silicon nanocrystals, probably due to mechanical stress (1). In this study, an attempt is done to correlate chemical bound analysis of Nc/SiO2 interface and electrical device performances. Silicon nanocrystals with an 8E11 cm-2 density and a 6 nm mean diameter were deposited on 3 nm thick alumina film and nitrided using ammonia anneals at 650°C and 750°C. The effects of ammonia nitridation on Nc-Si core-shell interface were investigated by the VUV-Photoemission beamline at the ELETTRA synchrotron source (Trieste, Italy), providing photons in the 20-900 eV range. The investigation of high-resolution Si 2p core-level spectra evidences an oxide re-growth during the nitridation treatment. This re-growth is estimated to be less than 0.5nm in both nitridation conditions. The high-resolution N(1s) core-level spectra analysis reveals a change in the nitrogen profile between the different ammonia anneals: N-Si-O bounds are almost identically detected at 398.3 eV, whereas a second peak, at lower binding energy (396.6 eV), appears more intense for the 750°C anneal. This second peak is attributed to N-Si-N bounds corresponding to the formation of silicon nitride-like structure. 650°C and 750°C nitrided Nc-Si were then integrated in memory devices. The programming windows were measured about 500mV larger in the 750°C nitridation case than in the 650°C case. This result is attributed to a higher resistance to oxidation of silicon nitride-like layer formed around the nanocrystals at 750°C. (1) Olivier Renault & al. Applied Physics Letters 87, 163119 (2005)


SESSION H3: High-k/Semiconductor Interfaces I
Chairs: Y. Chabal and D. Schlom
Wednesday Morning, April 11, 2007
Room 3007 (Moscone West)
8:30 AM *H3.1
Scaling of Hafnium-based High-k Dielectrics. Dina H Triyoso¹, Rama I Hegde¹, Rich Gregory², David C Gilmer¹, James K Schaeffer¹ and Srikanth B Samavedam¹; ¹ASTS, Freescale Semiconductor Inc., Austin, Texas; ²MMSTL, Freescale Semiconductor Inc., Tempe, Arizona.

Hafnium-based dielectrics are the most promising candidates for SiO2 replacement. As the implementation of high-k in CMOS platform is targeted for 45 nm node and beyond, the high-k dielectrics transistors must be scaled to yield thin CET (<13Å). This presentation will cover various approaches to extend scalability of Hafnium-based dielectrics. Among the three crystal phases of HfO2 (monoclinic, cubic and tetragonal), the tetragonal phase has been reported to have the highest dielectric constant. In bulk HfO2, a high temperature of 1720°C is required for monoclinic to tetragonal transformation. Crystallizing the thin HfO2 using a metal capping layer in place helps to partially stabilize the tetragonal phase at room temperature. The room temperature tetragonal and monoclinic densities of HfO2 are estimated to be 10.5 g/cc and 10.1 g/cc respectively. The mechanical constraint imposed by having the capping layer in place during the anneal step appears to favor the formation of the tetragonal phase which has a lower specific volume. The capping layer approach also results in significant reduction in film roughness and improved electrical results. Further stabilization of tetragonal phase of high-k dielectrics is observed when Zr is alloyed into HfO2. The microstructure, morphology, band-gap properties and impurities of HfxZr1-xO2 dielectrics (for 0<x<1) are extensively studied using VUV-SE, AFM, XRR, SIMS, TEM, FTIR, RBS and XRD. Some subtle but important modification resulting from addition of Zr into HfO2 responsible for improved scalability, mobility and reliability observed on HfxZr1-xO2 transistors will be discussed. To further boost the dielectric constant of HfxZr1-xO2, incorporation of TiO2, which has been reported to have very high (>80) dielectric constant, is explored. Impact of TiO2 addition to improve HfxZr1-xO2 scalability will be shown. As the dielectrics thicknesses are scaled down, an increase in PMOS threshold voltage is observed. Here we report on the use of thin dielectric capping layers to modulate threshold voltage. Finally, dielectric scaling by increasing the dielectric constant or reducing the thickness of the Si/high-k interfacial layer is attempted. Several approaches of interfacial layer scaling using nitrogen incorporation and ‘thin metal scavenging layer’ on HfxZr1-xO2 dielectrics will be presented.


9:00 AM H3.2
The Correlation Between the Growth Conditions and the Local Crystal Structure in Hf and Zr Based Oxide Thin Films. Mehmet Alper Sahiner¹, Rebecca Weeks¹, Brendan Benapfl¹ and Joseph C Woicik²; ¹Physics, Seton Hall University, South Orange, New Jersey; ²NIST, Gaithersburg, Maryland.

In this work, the effects of the growth conditions, on the thin film structural properties of Hf and Zr oxides have been investigated. The objective is to correlate and understand the intricate relation between thin film growth mechanisms and the resulting local structure of these oxide films. Thin films of HfO₂, ZrO₂, and Hf_xZr_1-xO₂ (x=0.1-0.9) were synthesized using pulsed laser deposition (PLD) on Si(100) substrates at various substrate deposition temperatures ranging from 100^oC to 800^oC. The detailed local structural information, obtained from extended x-ray absorption spectroscopy (EXAFS) on these films, have been correlated with (i) the deposition temperature for HfO₂ and ZrO₂ thin films (ii) with the Hf to Zr composition ratio in Hf_xZr_1-xO₂ thin films. EXAFS, being very sensitive to slight modifications of the local structural environment around Hf or Zr atom caused by temperature variations or compositional differences, yield interesting results on the competing crystal phases of HfO₂ and ZrO₂ in the thin films. Specifically, we have observed a narrow deposition temperature range, where the amorphous structure transforms into the tetragonal or monoclinic phases. The response of the local structural environment to growth conditions will be presented in the light of detailed EXAFS modeling. This work is supported by NSF Award #:DMI-0420952 and Research Corporation Award #:CC6405


9:15 AM H3.3
A Nanoanalytical Investigation of Elemental Composition in High-k Dielectric Gate Stacks for GaAs Based MOSFET Devices. Paolo Longo¹, Alan James Craven¹, Jamie Scott¹, Martin Holland² and Iain Thayne²; ¹Department of Physics and Astronomy, University of Glasgow, Glasgow, United Kingdom; ²Department of Electronics & Electrical Engineering, University of Glasgow, Glasgow, United Kingdom.

Planar Si MOSFET technology using Si(ON) is rapidly approaching its theoretical limit. n-type GaAs has a mobility 5 times higher than Si. This makes it a suitable candidate for MOSFETs devices. So far, GaAs has not been used for practical MOSFETs because of the difficulties of making a good dielectric oxide layer in terms of leakage current and unpinned Fermi Level. Using processes pioneered by Passlack et al [1], dielectric gate stacks consisting of a template layer of amorphous Ga2O3 followed by amorphous GdGaO have been grown on GaAs substrates. Careful deposition of Ga2O3 can leave the Fermi Level unpinned. The introduction of Gd is important in order to decrease the leakage of current. The electrical properties of the Ga2O3/GdxGa0.4-xO0.6 dielectric stack are related to the Gd concentration and the quality of the GaAs/Ga2O3 interface. Electron energy-loss spectroscopy (EELS), carried out in a nano-analytical electron microscope, has been shown to be an excellent method to characterise Ga2O3/GdxGa0.4-xO0.6 dielectric stacks. Spectrum imaging (SI) uses computer control to position the electron beam and to record one or more spectra at each point, building up an N-dimensional data set. In many of the systems of current interest, it is possible to collect information from all of the relevant elements in a single dataset. It is also possible to quantify the amount of each element present, making it possible to measure the homogeneity within and across the layers with extremely high spatial resolution. We are currently investigating a number Ga2O3/GdxGa0.4-xO0.6 dielectric stack layers, with different Gd concentration, grown onto a GaAs surface by molecular beam epitaxy (MBE) using high temperature effusion cell. By using the SI technique we have determined the composition of each element across the dielectric oxide layer. In particular for the case of GdGaO with Gd concentration, of 37.5%, we have found a Gd content decreasing towards the Ga2O3/GdGaO interface. This behaviour is completely opposite to the case of Gd%<25. The movement of the Gd towards the interface is strictly related to the Gd content. Another effect also associated with the Gd concentration in the oxide layer is the phase separation that may cause the partial crystallisation of the GdGaO layer. In particular in the case of dielectric stack layer with a Gd content of 25% we have observed an initial random ordering of the amorphous structure. This ordering seems to increase with the Gd concentration. We have also seen that in the oxide layer where there is a Gd content of 37.5%, there is the formation of a highly oriented crystalline structure. Further XRD experiments have shown the presence of Gd2O3 crystals in this oxide layer. The paper will discuss the detailed analysis of such oxide layers and the precision and accuracy with which it can be carried out. [1] Passlack M., Medendorp N., Gregory R. and Braddock D., Appl. Phys. Lett.83, 5262, 2003


9:30 AM H3.4
Effect of Systematic Changes of Ti and Hf Si-oxynitride Alloys by Nitrogen Incorporation as a Bond Constraint on Electrical and Material Properties. Sanghyun Lee¹, Gerry Lucovsky^1,2, L. B. Fleming² and Jan Luning³; ¹Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina; ²Department of Physics, North Carolina State University, Raleigh, North Carolina; ³Stanford Synchrotron Radiation Labs, Stanford University, Menlo Park, California.

As semiconductor devices are scaled below a 70nm feature size, high k dielectrics with thicker physical thickness than SiO₂ and Si oxynitrides are required to provide improved performance. Transition (TM) and Rare Earth (RE) elemental oxides, and silicate and oxynitride alloys based on HfO₂, ZrO₂, La₂O₃ and TiO₂, etc., are among high k materials that have been researched. Two major concerns for these silicate alloys are chemical stability upon annealing and electron and hole traps. To overcome these problems, optimization by novel processing and chemical design are required for TM/RE oxynitride dielectrics. In this work, we have studied the effect of Si₃N₄ content in (Ti(Hf)O₂)_x(Si₃N₄)_y(SiO₂)_1-x-y pseudo-ternary alloys by tracking systematic changes of electrical properties, including electrically active defects. Results from Soft x-ray photoelectron spectroscopy (SXPS) studies indicate no detectable hole traps for Hf/Ti Si oxynitrides with Si₃N₄ content >35%; these alloys have equal concentrations of Hf(Ti)O₂ and SiO₂, ~30-32%, and additionally are stable for annealing in Ar ambients to temperatures of 1100°C. Derivative near edge x-ray absorption spectroscopy (NEXAS) comparisons for the O K1 edges of TiO₂ and optimized Ti Si oxnitride alloys provides a significantly reduced average crystal field d-state splitting from 1.9 to 1.6 eV, as well as decreased electron trapping, and is correlated with a four-fold coordination of Ti in the Ti Si oxynitride alloys. The flat band voltage shift with varying frequency from 10 kHz to 1MHz in these alloys is less than 12 mV. It will be shown that the compositional dependence of current-voltage characteristics on Si₃N₄ composition results in the lowest leakage current at a Si₃N₄ content of ~40 % with the smallest equivalent oxide thickness (EOT) as well. Based on these studies, TM Si oxynitride alloys are anticipated to yield EOTs <1 nm for scaled CMOS devises.


9:45 AM H3.5
Negative Bias Stressing Interface Trapping Centers in Metal Gate Hafnium Oxide Field Effect Transistors Using Spin Dependent Recombination. Corey Cochrane¹, Patrick Lenahan¹, Gennadi Bersuker² and Arnost Neugroschel³; ¹The Pennsylvania State University, University Park, Pennsylvania; ²SEMATECH, Austin, Texas; ³University of Florida, Gainsville, Florida.

Although great progress has recently been made in the development of HfO2 based metal oxide field effect transistor (MOSFET) technology, very little is known about the reliability problems associated with this new materials technology. One of the most vexing problems of conventional Si/SiO2 and SiO2/nitrided oxide MOS devices is the negative bias temperature instability (NBTI) which causes reduced drain current and shifts in threshold voltage when pMOSFETs are subjected to modest negative gate bias, typically at an elevated temperature. We combine conventional metal oxide semiconductor (MOS) gated diode measurements and very sensitive electrically detected electron spin resonance (ESR) measurements to detect and identify negative bias temperature instability (NBTI) generated defect centers in fully processed HfO2 pMOS field effect transistors (pMOSFETs). The spectra of the short stress-generated defects were found to be quite different from those generated by NBTI in conventional Si/SiO2 based devices. The defect spectra generated by long term stressing differ from the short term stressing signals and are somewhat similar to those observed in plasma nitrided oxide Si/SiO2 based devices. Our results suggest that, in these HfO2 based devices, NBTI defects are located in the interfacial SiO2 layer.


10:30 AM *H3.6
Atomic Layer Deposition of High-k Gate Dielectrics onto Si, Ge, and III-V Semiconductors: Interface Chemistry. Martin M. Frank, IBM T.J. Watson Research Center, Yorktown Heights, New York.

The impact of interface chemistry on the structure and quality of novel metal-oxide-semiconductor field-effect transistor (MOSFET) gate stacks will be reviewed. We focus on the high-permittivity (‘high-k’) gate dielectrics HfO₂ and Al₂O₃ grown by atomic layer deposition (ALD) on conventional (Si) and high carrier mobility (Ge, GaAs, InAlAs/InGaAs) channels. Surface preparation schemes considered include native oxide formation as well as hydrogen, nitrogen, sulfur, and silicon passivation. A variety of chemical spectroscopies and microscopies is employed both in situ and ex situ. In this way, we shed light on the ways processing parameters (choice of materials; surface preparation; high-k dielectric deposition process; thermal history) determine stack structure/composition (continuity of the high-k layer; interfacial oxide thickness; detrimental channel-dielectric interactions) and hence electrical quality. Trends will be rationalized based on thermodynamic properties of semiconductor substrates, high-k materials, and precursors. Example A - Interfacial oxide growth: Interfacial SiO₂ formation on Si during (and after) high-k growth can be observed pulse-by-pulse with in situ infrared spectroscopy [1]. SiO₂ formation can be prevented, e.g., by nitrogen passivation or by high-k deposition near room temperature [2]. By contrast, for high-mobility channel materials such as Ge or GaAs, with their low oxidation enthalpies, sharp high-k/channel interfaces are more easily formed, in particular when employing metal precursors with low free enthalpy of formation and/or thermal processing in reducing (or only mildly oxidizing) environments [3]. Example B - High-k/channel interactions and passivation: Structural analysis of HfO₂/Ge stacks indicates that poor electrical quality is caused by a direct HfO₂-Ge interaction in the absence of a passivating stable interfacial oxide. The conventional solution, nitridation, induces detrimental fixed charge. We will show that a sulfur passivation layer on Ge reduces interface state density while creating little fixed charge [4]. [1] M.M. Frank et al., Appl. Phys. Lett. 82, 4758 (2003). [2] M.M. Frank et al., J. Electrochem. Soc., in press. [3] M.M. Frank et al., Appl. Phys. Lett. 86, 152904 (2005). [4] M.M. Frank et al., Appl. Phys. Lett. 89, 112905 (2006).


11:00 AM H3.7
Texture and Crystallinity Development in Ultra-thin HfO2 Films Studied by Electron Microscopy. Fakhruddin Bohra^1,2, Bin Jiang^1,2, Kevin D Johnson³, Zhiyong Ma³ and Jian-Min Zuo^1,2; ¹Materials Science and Engineering, UIUC, Urbana, Illinois; ²Frederick-Seitz Materials Research Laboratory, UIUC, Urbana, Illinois; ³Intel Corporation, Hillsboro, Oregon.

We show the evidences of texture and crystallinity in ultra-thin (~ 2 nm) HfO2 films obtained by high-resolution electron microscopy and diffraction as a function of annealing temperatures. The study is motivated by the need to develop high dielectric constant (high-k) materials for further reducing the critical dimension in CMOS devices. HfO2 possess several desirable properties for CMOS applications, such as a much higher dielectric constant (k), thermal stability on silicon, low leakage etc. But, the stability of pure HfO2 films against crystallization under thermal annealing is a major issue for its application. Questions such as the onset temperature of crystallization, crystalline structure as a function of film thickness and annealing temperatures and the role of the underlying Si substrates remain unclear. We are addressing these by examining the structure of HfO2 films using electron microscopy. The 2nm-thick HfO2 films (provided by Intel) were grown on Si (100) and SiO2 substrates by the ALD method at SEMATECH. The films were then subjected to rapid thermal annealing (RTA) at three different temperatures: 600°C, 800°C and 1000°C in N2 environment for 30s. We used several electron microscopy techniques; namely nano-area electron diffraction (NED), selected area electron diffraction (SAED), high resolution electron microscopy (HREM), scanning transmission electron microscopy (STEM) and fluctuation electron microscopy (FEM) to study the structure and phase of these films in plan view and cross-sectional geometries. As-deposited HfO2 films were found to have an amorphous structure with a 1-nm amorphous SiO2 transition layer beneath. HfO2 films on Si (100) substrates after annealing at 800°C (and 1000°C) crystallized into an orthorhombic phase with a strong out of plane texture along the [1 -2 0] direction and no in-plane texture. The films were polycrystalline with grains of about 5 nm in size. On the other hand, films grown on the SiO2 substrates after annealing at 1000°C had similar sized grains, but a completely different polycrystalline phase without any texture. We will discuss the texture and orthorhombic phase development in films on Si (100) substrates based on the role of substrate orientation and a possible role of thin SiO2 transition layer. We found that the thickness of SiO2 transition layer increases with annealing temperature as a result of enhanced oxygen diffusion and at higher temperatures the SiO2 layer crystallizes as detected by electron diffraction. Medium range order (MRO) in films annealed at 600°C was revealed by fluctuation electron microscopy, although the films seemed to have an amorphous structure from HREM images and electron diffraction. The MRO in films suggests that the onset of crystallization occurs close to 600°C.


11:15 AM H3.8
Study of Pt/ Epitaxial Gd2O3 /Si Stacks. E. Lipp¹, M. Eizenberg¹, M. Czernohorsky² and H. J. Osten²; ¹Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa, Israel; ²Institute of Electronic Materials and Devices, Leibniz University of Hannover, Hannover, Germany.

The successful downscaling of Si Field Effect Transistors has been accompanied by a reduction in the thickness of the SiO2 gate dielectric. However, as the thickness of the gate oxide reduces, tunneling-dominated leakage current becomes unacceptably high. As a result, a high dielectric constant (high-k) material will replace the conventional SiO2 as gate dielectric in the near future. Furthermore, in order to prevent gate depletion and boron penetration into the future gate dielectric, the currently used poly-Si should be replaced by a metal as the gate electrode. Lanthanide oxides have promising properties as gate dielectrics for future devices, as they are thermally stable in contact with Si, have sufficiently high k value, and have a relatively high gap energy and band offset to Si. Many lanthanide oxides can be grown epitaxially on Si, enabling the formation of single-crystalline dielectrics. Among the lanthanide oxides, Gd2O3 is the most promising material since it does not appear in other stoichiometries and has the smallest lattice mismatch to Si. In this work, the properties of Pt/ epitaxial Gd2O3/ Si stacks are studied as a function of oxide crystal structure and orientation. Single-crystalline, domain-structured, and amorphous Gd2O3 layers are deposited by Molecular Beam Epitaxy and capped with Pt dots without air exposure. The microstructure, composition, and chemical bonding at Gd2O3/ Si and at Pt/ Gd2O3 interfaces are studied by high-resolution transmission electron microscopy and by x-ray photoelectron spectroscopy. Oxide capacitance and conduction mechanism are characterized by electrical measurements and correlated with the microstructure of the dielectrics. Atomic ordering and chemical binding are correlated with the density of states at the oxide/Si interface and with the effective work function at the Pt/ oxide interface. The results show that the microstructure of the Gd2O3 layer has a dominant effect on oxide leakage current, and on the density of states at the oxide/Si interface. The stability of the stacks is studied by monitoring the chemical and electrical properties after thermal treatments. No chemical reactions were detected at the Pt/Gd2O3 interface, even after 30min at 600°C. These results suggest that Pt is a suitable metallization for future Gd2O3-based transistors.


11:30 AM H3.9
Nucleation studies of HfO₂ thin films produced by Atomic Layer Deposition Justin C. Hackley¹, John Derek Demaree² and Theodosia Gougousi¹; ¹Department of Physics, UMBC, Baltimore, Maryland; ²Weapons & Materials Research Directorate, Army Research Laboratory, Aberdeen Proving Ground, Maryland.

A hot wall Atomic Layer Deposition (ALD) flow reactor equipped with a Quartz Crystal Microbalance (QCM) has been used for the deposition of HfO₂ thin films on H-terminated Si and SC1 chemical oxide starting surfaces using tetrakis (ethylmethylamino) hafnium (TEMAHf) and H₂O as precursors. Spectroscopic ellipsometry and QCM measurements confirm linear growth of the films with a growth rate of ~1.1Å/cycle at 250°C. Nucleation and initial growth behavior of the films were examined using x-ray photoelectron spectroscopy (XPS), Rutherford backscattering spectrometry (RBS) and atomic force microscopy (AFM). H-terminated Si surfaces are generally regarded as nucleation barriers for the deposition of metal oxide thin films and in our process we find that for the first 3-5 cycles the surface coverage for H-terminated Si is only about a quarter of that for the chemical oxide surface. However, within a few cycles this difference is compensated and the surface coverage for both samples becomes similar. A possible explanation for this enhancement of the growth rate for the H-terminated Si is that the film structure is rougher, providing a larger surface area for subsequent nucleation. RBS results show that the initial growth period lasts approximately 40 cycles until the complete transition to linear ALD growth is achieved. Angle-resolved XPS at take-off angles of θ=0, 15, 30, 45 and 60° measured from the normal to the sample surface is used to probe the interfacial region of thin films (15 and 25 cycles) on H-terminated samples. We observe the “paradox” that the 25 cycle film has a thinner interfacial layer (7Å vs. 10Å comprised of a SiO_x/silicate mixture), even though it receives a longer exposure to the ALD process environment (250°C) which is favorable to oxidation of the Si substrate. We explain that in terms of unreacted Si-H bonds that persist in the interface and oxidize post deposition. The 25 cycle film has fewer unreacted Si-H bonds and thus is less susceptible to post-deposition oxidation. XRD data on thicker films indicate that the as-deposited films are mainly amorphous but begin to crystallize upon annealing at 300°C (2 min in Ar).


11:45 AM H3.10
Abstract Withdrawn


SESSION H4: High-k Interfaces: High Mobility Substrates and Metal Electrodes
Chairs: D. Muller and J. Robertson
Wednesday Afternoon, April 11, 2007
Room 3007 (Moscone West)
1:30 PM *H4.1
Atomic-layer-deposition Grown Al₂O₃ on III-V Compound Semiconductors - Surface Passivation and Energy-band Parameters. M. L. Huang^1,3, Y. C. Chang¹, C. H. Chang¹, Y. J. Lee¹, T. D. Lin¹, P. Chang¹, T. B. Wu¹, J. Kwo² and M. Hong¹; ¹Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu, Taiwan; ²Department of Physics, National Tsing Hua University, Hsinchu, Taiwan; ³Research Division, National Synchrotron Radiation Res. Ctr., Hsinchu, Taiwan.

III-V compound semiconductor metal-oxide-semiconductor field-effect-transistors (MOSFET’s) would give several advantages over their Si-based counterparts, due to the high electron mobility, semi-insulating substrates, and high breakdown fields, which lead to high-speed devices and high-power applications. Efforts in searching insulators on GaAs with a low interfacial density of states (D_it), one of the key challenges in the III-V devices over the past four decades [1], have found a solution in in-situ ultra-high vacuum (UHV) deposition of amorphous Ga₂O₃(Gd₂O₃) [2] and single crystal Gd₂O₃ on GaAs surfaces [3]. Recently, Al₂O₃ was deposited on In_0.15Ga_0.85As/GaAs using ex-situ atomic layer deposition (ALD). [4,5] Without any surface preparation or post thermal treatment [5], excellent electrical properties of Al₂ O₃ /InGaAs/GaAs heterostructures were obtained, in terms of low electrical leakage current density (10^-8 to 10^-9 A/cm²) and low Dit in the range of 10¹²cm^-2eV^-1. The depth profile of high-resolution x-ray photoelectron spectroscopy (HR-XPS) exhibited no residual arsenic oxides at interface. The removal of the arsenic oxides from Al_2O3/InGaAs heterostructures during ALD process ensures the Fermi level unpinning, which was observed in the capacitance-voltage (C-V) measurements. The high-resolution transmission electron microscopy (HR-TEM) shows sharp transition from amorphous oxide to single crystalline semiconductor. Moreover, the valence-band offset has been determined to be 3.83±0.05 eV at the Al₂ O₃/In_0.15Ga_0.85As interface using XPS. The Au/Al₂O₃/In_0.15Ga_0.85As MOS diode exhibits current-voltage characteristics dominated by Fowler-Nordheim tunneling. A conduction-band offset of 1.6±0.1 eV at the Al₂O₃/InGaAs interface and an electron effective mass ~0.28±0.04 m₀ of the Al₂O₃ layer have been extracted. Consequently, combining the valence-band offset, the conduction-band offset, and the energy-band gap of In_0.15Ga_0.85As, the energy-band gap of the ALD Al₂O₃ is 6.65±0.11 eV. [6] [1] M. Hong, C. T. Liu, H. Reese, and J. Kwo, in Encyclopedia of Electrical and Electronics Eng, edited by J. G. Webster, (Wiley, New York, 1999), Vol. 19, p. 87. [2] M. Hong, et al, J. Crystal Growth, 175/176, 422, 1997. [3] M. Hong, et al, Science 283, 1897, 1999. [4] P. D. Ye, et al, Appl. Phys. Lett. 84, 434, 2004. [5] M. L. Huang, et al, Appl. Phys. Lett. 87, 252104, 2005. [6] M. L. Huang, et al, Appl. Phys. Lett. 89, 012903, 2006.


2:00 PM H4.2
Influences of Plasma Processed Interface Layers on Germanium MOS Devices with ALD Grown HfO2. Takuya Sugawara^1,2, Raghavasimhan Sreenivasan², Yasuhiro Oshima^3,2 and Paul C. McIntyre²; ¹Leading-edge Process Development Center, Tokyo Electron Ltd., Nirasaki, Yamanashi, Japan; ²Dept. of Materials Science and Engineering, Stanford University, Stanford, California; ³Development and Planning Department, Tokyo Electron America, Santa Clara, California.

As the dimensional scaling of MOSFETs continues, silicon is approaching its fundamental scaling limits. Germanium is an alternative candidate for future channel material because of its high carrier mobility, small band gap for voltage scaling and the high solubility of p-type dopants. HfO2 is a leading candidate of high-k gate dielectrics because of its relatively large band gap, high dielectric constant and thermal stability. Therefore, we have performed a systematic study of the effects of plasma processed interface layers interposed between Ge (100) substrates and ALD grown HfO2 gate dielectrics. In this study, GeO2 and GeON interface layers were formed using high pressure remote plasma oxidation and nitridation processes [1]. Electrical results show negative flat band voltage (Vfb) shift from the ideal value for both Si and Ge MOS capacitors. We find that Hf alkylamide ALD process and nitrided substrate surface causes a negative Vfb shift, and the shift of Si MOS capacitors can be explained by these two factors. Ge MOS capacitors exhibit larger negative Vfb shift (-0.5V). XPS results show evidence of Ge diffusion into HfO2 layer, which suggests that the water solubility of remote plasma processed GeO2 and GeON may be the origin of the Ge diffusion and the larger negative Vfb shift [2], [3]. Tantalum oxynitride (TaON) interface layers were formed using remote plasma enhanced ALD (PEALD) process [4]. Ge MOS capacitor with the TaON interface layer show superior electrical properties. These results indicate that the selection of the interface layer strongly influences Ge MOS capacitor electrical properties. [1] J. Vac. Sci. Technol. B 24. 2442 (2006) [2] J. Vac. Sci. Technol. B 24, 2449 (2006) [3] J. Electrochem. Soc. 153, F160 (2006) [4] MRS 2006 Spring Meeting, E8-2


2:15 PM H4.3
Interface Analysis Between ALD high-κ HfO2 and Sulfur Passivated GaAs. Po-Ta Joseph Chen¹, Yun Sun², Chi On Chui³, Eunji Kim¹, Michael Garner³, Piero Pianetta^2,4, Niti Geol³, Wilman Tsai³, Paul McIntyre¹ and Yoshio Nishi⁴; ¹Materials Science and Engineering, Stanford University, Stanford, California; ²Stanford Synchrotron Radiation Laboratory, Stanford Linear Accelerator Center, Menlo Park, California; ³Intel Corp., Santa Clara, California; ⁴Electrical Engineering, Stanford University, Stanford, California.

The ever increasing need for higher speed and lower power computing has already pushed the Si-based transistors close to their performance limit. Alternative materials with high carrier mobility like III-V compound semiconductors are being actively evaluated in research to supplement the present infra-structure. GaAs in particular embraces the advantages of higher electron mobility and larger bandgap as compared to Si. In order to sustain a better gate capacitance scalability for metal-oxide-semiconductor (MOS) device applications, atomic-layer deposited (ALD) HfO2 has been put down onto differently cleaned and passivated GaAs surfaces. In this work, we focus our study on the HfO2/GaAs interface bonding configuration and surface morphology by using synchrotron radiation photoemission spectroscopy (SRPES), atomic force microscopy (AFM), and transmission electron microscopy (TEM). The starting substrates were semi-insulated (100)GaAs wafers. A two steps surface treatment was implemented, which includes an aqueous HCl surface cleaning for native oxide removal followed by a sulfide passivation in aqueous (NH4)2S solution to prevent the GaAs surface from re-oxidation. Subsequently, 250 cycles of ALD HfO2 was deposited ex-situ at 150 oC with the tetrakisdiethylaminohafnium (TDEAH) and H2O precursors. After the sulfide passivation treatment, Ga 3d, As 3d, S 2p, and O 1s photoemission spectra were measured to verify its stability. It was found that both Ga-S and As-S bonds were formed on the GaAs surface, while the stable Ga-S bonds became dominant after the in-situ anneals at 150oC and 350oC for 15min apiece. AFM images on the S-treated GaAs surface showed slightly increased RMS roughness to 0.266nm (versus 0.187nm before the treatment). After the HfO2 deposition, TEM images were taken on the HfO2/S-treated GaAs interface that revealed one to three monolayers of interfacial sulfide and an as-deposited HfO2 thickness of 22nm. Whereas from the HfO2/non-treated GaAs interface, 3nm Ga(As)O native oxide was evident together with a thinner as-deposited HfO2 thickness of 18nm. The HfO2 films were then stripped back near to the GaAs interface by using hydrofluoric acid (HF) for interfacial bonding analysis. During the HF etching, angle resolved Hf 4f spectra indicated that Hf-F bonds were formed on top of HfO2. The HfO2/GaAs interface was observed after 75 seconds of HF etching. No re-oxidation of Ga was observed but the As-S signal decreased otherwise near the HfO2/GaAs interface, which implies possible re-oxidation of surface As during the water-based ALD process. In addition, MOS capacitors with W/HfO2 gate stack had resulted in improved electrical characteristics on S-treated N-(100)GaAs surface versus the non-treated samples. To summarize, (NH4)2S appears to provide a superior passivation for GaAs and a better starting surface for ALD HfO2 deposition.


2:30 PM H4.4
Characteristics of HfN/HfO₂ Gate Stacks deposited by Remote Plasma Atomic Layer Deposition Method Keunwoo Lee, Seungho Lee, Keunjun Kim, Wooho Jeong, Taeyong Park and Hyeongtag Jeon; Division of Materials Science and Engineering, Hanyang University, Seoul, South Korea.

Metal oxide films with high dielectric constants (high-k) have been studied recently to overcome the current disadvantages of SiO₂ material. This high-k oxide material also needs to apply a new gate electrode because of the problems of poly-Si/high-k gate stacks such as poly-Si depletion effect, Fermi level pinning, surface phonon scattering, high threshold voltage(V_th) and channel mobility degradation in real devices. Current poly-Si as a gate electrode results in poor transistor performance. Due to these problems new metal gate materials are needed to solve these problems because the metal/high-k/Si gate stack is very effective in improving the current gate electrode properties. And the use of metal gate electrode eliminates poly-Si depletion effect and Fermi level pinning. Among the many candidates the refractory metal nitrides such as HfN, TiN and TaN are considered as the solutions to replace current poly-Si gate electrode. HfN exhibits various advantages such as thermal stability and low lattice mismatch with HfO₂ and is considered as one of the most suitable candidates as gate electrode. In this work, we studied HfN film deposited by remote plasma atomic layer deposition (RPALD) method using tetrakis dimethylamino hafnium(TDMAH), Hf[N(CH₃)₂]₄ as a Hf precursor with NH₃ plasma. The chemical composition of HfN films were analyzed by RBS. The carbon and oxygen contents of HfN film were below 5at.% and 1at.%, respectively. The AES data showed a 1:1.2 ratio of Hf:N in HfN film. This HfN gate electrodes were deposited on the HfO₂ gate oxide. After deposition, the physical and chemical characteristics were evaluated with TEM, AES, XPS, and SIMS and MOS capacitors were fabricated with the HfN/HfO₂ gate stacks to measure the electrical properties.


3:15 PM H4.5
Characterization of Interfacial Stability by Differential Scanning Nano-calorimetry. Lawrence Cook, Richard Cavicchi, Mark Vaudin, Christopher Montgomery, William Egelhoff, Nabil Bassim and Martin Green; NIST, Gaithersburg, Maryland.

A revolution of sorts in CMOS technology is taking place, as a replacement is sought for SiO2 dielectrics, a mainstay of the semiconductor industry for decades. While the SiO2 native oxide has built-in stability with regard to the Si semiconductor, new dielectric materials for MOSFET application must be evaluated for stability with regard to both the Si as well as the overlying metallization. Thin-film differential scanning calorimetry (DSC) provides sensitivity on a nano-scale (in terms of both energy and mass), and is ideally suited to the study of interfacial stability in CMOS materials. In this method, thin-film bilayers are deposited on MEMS sensors, which can then be thermally ramped over a wide range of rates to determine reaction enthalpies and kinetic stability parameters. In principle, very small amounts of interfacial reaction can be detected. To test this approach we have selected the Ni/Si interface, which has well-known instability, resulting in the formation of useful nickel silicides, as a model system. We have prepared both single bilayer interfaces of 100 nm Ni on 100 nm Si by magnetron sputter deposition, as well as multilayer interfaces (10 bilayer sequences of 10 nm individual layer thickness) with the same total thickness of material (200 nm). Reaction enthalpy measurements were calibrated using the melting point of Pb. Two DSC scan rates, corresponding to 1000 K/s and 4000 K/s were used. Results were similar for all sets of experiments, with onset near 500 K, and measured enthalpies approach that for the reaction: Ni + Si → NiSi (-90 kJ/mol). A large signal-to-noise ratio for these measurements indicates that reactions much less intense than Ni/Si can be detected. Surprisingly, reaction kinetics were not substantially different among the experiments. However in certain of the multilayer experiments, a bimodal enthalpy distribution suggests a multiplicity of reactions, perhaps involving both Ni2Si and NiSi. This raises the possibility that by further varying the ramp rates the kinetics of individual reactions taking place at the interface can be sorted out. The limits of sensitivity of the method for detecting interfacial reactions are being probed, and applications to other CMOS materials are being explored.


3:30 PM H4.6
Improving the Electrical Properties of TiN/HfSiO Gate Stacks using the PVD-based In-situ Fabrication Method Naomu Kitano^1,2, Shinya Horie², Takashi Minami¹, Motomu Kosuda¹, Takayoshi Shimura², Kenji Shiraishi³ and Heiji Watanabe²; ¹Canon ANELVA Corp., Tokyo, Japan; ²Graduate School of Engineering, Osaka University, Osaka, Japan; ³Graduae School of Pure and Applied Physics, University of Tsukuba, Ibaraki, Japan.

Combination of high-k gate dielectrics with metal electrodes is a promising candidate technology for advanced low-power, high-performance MOSFETs. Among the various high-k dielectrics, hafnium silicate (HfSiO) and its nitrided (HfSiON) films showed excellent properties, such as sufficiently high carrier mobility and thermal stability in contact with Si substrates. Titanium nitride (TiN) is a good candidate for a p-metal electrode due to its compatibility with the conventional Si-LSI process. CVD is a preferred growth method from the viewpoint of process damage and productivity and, thus, commonly used for fabrication of metal/high-k gate stacks. However, it has been reported that residual impurities within high-k films and at metal/high-k interfaces, which degrade device performance, have become a serious problem. Previously, Watanabe demonstrated a method for fabricating high-quality silicate gate dielectrics by utilizing a solid phase interface reaction (SPIR) between a PVD-grown metal-Hf and a SiO2 underlayer [1]. Recently, we also proposed an in-situ PVD method, which continuously fabricates high-k gate dielectrics by SPIR and metal electrodes using a newly developed cluster tool with a low-damage sputtering system [2]. This in-situ process enables us to precisely control SPIR and reduce impurity of the metal/high-k gate stacks. We fabricated TiN/HfSiO stacks by the in-situ method and demonstrated electrical properties superior to the conventional CVD and ex-situ SPIR methods. This paper describes the physical characteristics of TiN/HfSiO gate stacks prepared using the in-situ fabrication process and the electrical reliability of the gate stacks, including EOT and Vfb stability against thermal and electrical stressing. Our results showed that carbon impurity causes a Vfb shift in as-fabricated MOS devices and accelerates thermal degradation in terms of EOT versus Jg characteristics and changes in effective work function of the gate electrodes. We also found that air exposure before SPIR annealing caused severe electrical degradation due to intense impurity adsorption on the metal surface. Details of the degradation mechanism caused by carbon impurity are also presented. [1] H. Watanabe et al., Appl. Phys. Lett. 85, 449 (2004). [2] S. Horie et al., Ext. Abst. SSDM, pp.414 (2006).


3:45 PM H4.7
Si-based Resonant Tunneling Devices (RTD) using UHV wafer Bonding Taehun Lee, M. J. Kim, J. Kim, R. M. Wallace and B. E. Gnade; EE, University of Texas at Dallas, Richardson, Texas.

The resonant tunneling-based quantum devices have been studied extensively in compound semiconductors. However, there are limited studies on scaled silicon CMOS processing. It has been shown that the fabrications of high quality dielectric-semiconductor interface and single crystalline silicon quantum well are critical to the resonant tunneling-based quantum devices. Nowadays, most attempts on silicon-based RTDs have been performed by using single crystal, epitaxial dielectrics with similar lattice constant to that of silicon, such as CaF2. These approaches have been hampered by the difficulty to fabricate high quality silicon on single crystal CaF2 and thus, resulting in poor quality interfaces. The ultra high vacuum wafer bonding is a promising technique to fabricate high quality silicon-based RTD. It eliminates the need for lattice-matched, crystalline dielectrics since the crystalline silicon quantum well is bonded directly to the dielectric. In this work, the wafer bonding was used twice in order to produce double dielectric barrier with an ultra thin single crystal silicon quantum well (<5nm) in between. The first step is to bond a SOI wafer with a thin Si layer to a high quality thin SiO2 layer, which forms the first tunnel barrier. After mechanical polishing, silicon wet etching and HF dipping process, the first Si/SiO2 interface is then bonded to another SiO2/Si interface to produce final structure. C-V and I-V measurements, as well as high resolution transmission electron microscopy (HRTEM) and electron energy loss spectroscopy (EELS) have been employed to examine the quality of interface and the performance of the device. Our results show that the ultra high vacuum wafer bonding is an essential technique to produce electrically active interfaces for appropriate performance of RTD devices.


4:00 PM H4.8
Metal-HfO2 Interfaces and Work Function Control. Koon-yiu Tse and John Robertson; Engineering, Cambridge University, Cambridge, United Kingdom.

High K oxides are needed to reduce gate leakage current in CMOS devices. But it is proving quite difficult to develop the necessary metal gate electrodes. The effective work functions of the metals must be able to be controlled to within 0.1 V of the Si valence or conduction band edge energies, but a Fermi level pinning appears to inhibit this. In order to understand the reasons for this, we have carried out super-cell calculations on many metals interfaces with HfO2. Various interface terminations were studied, both O-terminated, Hf-terminated, and non-polar. The need to lattice match the metal and oxide is a problem in such simulations. It is found that O- or metal terminated interfaces have the highest work of adhesion. Metals with a low work function are found to prefer O-terminated interfaces, whereas high work function metals prefer non-polar interfaces. For a given interface type, it is found that the calculated valence band offset varies strongly with metal work function, and shows little evidence of Fermi level pinning. The Fermi level can swing fully across the Si gap, The VB offset depends strongly on the termination, unlike for the oxide-Si interface. Thus, it is unclear from theory why the Fermi pinning problem is still so hard.


4:15 PM H4.9
Systematic Study on Effective Work Function Instability of Metal/High-k Gate Stacks Yuki Kita¹, Shiniti Yoshida¹, Takayoshi Shimura¹, Kiyoshi Yasutake¹, Heiji Watanabe¹, Kenji Shiraishi², Yasuo Nara³ and Keisaku Yamada⁴; ¹Graduate School of Engineering, Osaka University, Osaka, Japan; ²Graduate School of Pure and Applied Physics, University of Tsukuba, Tsukuba, Japan; ³Semiconductor Leading Edhe Technologies, Inc. (SELETE), Tsukuba, Japan; ⁴Nano Technology Research Laboratory, Waseda University, Tokyo, Japan.

The main concern about high-k gate transistors is controlling the effective work function (WF) for various kinds of gate materials. Fermi level pinning (FLP) in poly-Si gates and oxygen-pressure-dependent WF instability of p-metals have been reported by many groups [1, 2]. These studies reported that the effective WFs of the electrodes shifted (decreased) toward the Si-midgap. In contrast, the effective WFs of inert p-metals, such as Au and Pt, were found to increase under specific interface conditions [3]. Recently, Shiraishi proposed a universal model for the unusual behaviors of metal/high-k gate stacks, which explains decrease in WF by oxygen vacancy (Vo) formation in the Hf-based oxides (Vo model) and increase in WF by interface hybridization between occupied states of metal electrodes and unoccupied states of Hf-oxides (generalized charge neutrality level (Φ^G_CNL) model) [4, 5]. However, elucidating these complicated phenomena requires systematic experiments that consider both the Vo and Φ^G_CNL models. In this study, we fabricated metal/HfSiON gate stacks and investigated instability of the effective WFs of the metal/high-k stacks in detail. The HfSiON dielectrics were formed using MOCVD and plasma nitridation. To precisely control the electrode interface, the HfSiON dielectrics were either annealed or exposed to hydrogen radicals before metal deposition. Conventional C-V measurements were carried out to estimate effective WFs. In the case of the inert p-metal Au electrode, we observed an apparent positive shift in C-V curves after hydrogen radical exposure. This indicates strong hybridization at the metal/high-k interface (increased WF) due to a cleaning effect on the HfSiON surface by the atomic hydrogen. We also found that the hybridization is unstable and that the C-V shift gradually recovered and showed an ideal flat band voltage (Vfb) after being exposed to air for a few days. These results are fully explained by the Φ^G_CNL model and by modification of the interface hybridization by diffusion of species through the metal electrode from the air. Furthermore, a negative Vfb shift, which indicates Vo formation in the Hf-based oxides, was also observed when the dielectrics were exposed to radicals after formation of an ultrathin (<10nm) Au layer on the high-k film. This result agrees well with the Vo model, which is driven by electron transport from the Vo levels in the Hf-based oxides to the p-type electrodes. These experimental results clearly showed that the universal theory is valid for effective WF at the metal/high-k interface. Further experimental results on physical characterization and n-metal electrodes will also be presented in detail. [1] C. Hobbs et al., Tech. Digest VLSI Tech. p.9 (2003). [2] E. Cartier et al., Tech. Digest VLSI Tech. p.230 (2005). [3] M. Koyama et al., Tech. Digest IEDM, p.499 (2004). [4] K. Shiraishi et al., Tech. Digest VLSI Tech. p.108 (2004). [5] K. Shiraishi et al., Tech. Digest IEDM, p.43 (2005).


4:30 PM H4.10
Work Function Extraction from TayAl1-yNx Composition Spreads on HfO2 using Combinatorial Methodologies for the Advanced Gate Stack Kao-shuo Chang^1,2, Martin L. Green¹, Nabil D. Bassim¹, John Suehle¹, Jason Hattrick-Simpers², Ichiro Takeuchi² and Stefan De Gendt³; ¹Materials Science and Engineering, NIST, Gaithersburg, Maryland; ²Materials Science and Engineering, U. of Maryland, College Park, Maryland; ³IMEC, Leuven, Belgium.

The identification of new metal gate electrodes requires the work functions (Φm) to be aligned with the conduction and valence bands of Si, for n- and p-MOS applications, respectively. Metal nitrides might be good choices because of their robust thermal stability with underlying gate dielectrics. However, the exploration of metal nitrides is not trivial, since fabrication based on a one-composition-at-a-time approach is too time consuming to investigate. Combinatorial methodology offers a viable approach, since it allows a large number of samples to be made and characterized at a time. We demonstrate the efficiency of the combinatorial technique to enable rapid exploration of the TayAl1-yNx metal gate electrode on HfO2, through the deposition of a combinatorial composition spread. TayAl1-yNx composition spreads were fabricated with a moving shutter using reactive radio-frequency (RF) sputtering. We have systematically measured the equivalent oxide thickness (EOT) and Vfb shift from the C-V characteristics. From the map of EOT, a maximum of 30 ~ 40% Al content is confirmed to maintain sufficient conductivity for the metal gate application. The extracted Φm values of the TayAl1-yNx (x <1) composition spreads were ~ 5 eV, which show promise for the p-MOS application. Φm as a function of N content will be presented as well.


SESSION H5: Poster Session: High-k Dielectrics/Semiconductor Interfaces
Chair: Nicolas Richard
Wednesday Evening, April 11, 2007
8:00 PM
Salon Level (Marriott)
H5.1
Microstructure and Electronic Structure Characterization of Interface Between the Hf-based high-K Thin Film and Si Using Spatially Resolved Electron Energy Loss Spectroscopy. Quan Li, Physics, The Chinese University of Hong Kong, Hong Kong, Hong Kong.

Being of the most promising material to replacing SiO2 as the future gate dielectric, HfO2 based high-K materials have aroused much research interest. In particular, their interfacial microstructure and electronic structure are of intense focus, as they significantly affect the final device performance. Using scanning transmission electron microscope (STEM)-electron energy loss spectroscopy (EELS), we investigate the interface between the HfO2 thin film and the Si. Although the interface of the as-synthesized sample is found to be atomically sharp between the oxide and the Si, an interfacial oxide layer is identified with high defect density of states. In addition, sample annealing in the oxygen environment introduce a rather thick SiOx layer in-between the high-K film and the Si substrate. We find that introducing Al to the HfO2 film not only passivates the interfacial defect density of states for the as-deposited sample, but also prevents the formation of the interfacial SiOx layer upon oxygen annealing, which mechanism is disclosed by an ab-intio calculation—the Al block the diffusion of O through the high-K film to reach the interface, and thus effectively prevent the reaction between the O and the Si and the formation of SiOx in the interfacial region. This work is supported by a grant of the Research Grant Council of HKSAR, under project No. 402105.


H5.2
Comparisons of Physical and Electrical Characteristics of Laser-MBE Fabricated HfSiO versus HfSiON Dielectrics Yuekang Lu¹, Weiguang Zhu¹ and R. Gopalkrishnan²; ¹School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Singapore; ²Institute of Microelectronics, Singapore, Singapore.

The HfSiO and HfSiON gate dielectric films were fabricated by the laser molecular beam epitaxy (Laser-MBE) technique. The concentration ratio of Hf in hafnium silicate has been properly adjusted in order to achieve the desirable electrical and dielectric properties. It is found that Hf0.23Si0.12O0.65 shows the best electrical and dielectric properties. Furthermore, based on Hf0.23Si0.12O0.65, nitrogen was incorporated in order to further enhance the gate property. HRTEM and AES have been used to investigate the interface growth and to illustrate the scaling limit of these gate oxides. The HRTEM results reveal that both of the films were kept in amorphous state after RTP at 950 oC in N2 for 30 seconds. However, a relatively thick interface has been observed for the 1.5-nm thick HfSiO. In comparison, the interface growth has been greatly inhibited for the 1.5-nm HfSiON. High quality HfSiON film has thus been obtained with an EOT value of about 0.95 nm as well as low leakage current density, 3 to 4 orders of magnitude lower than that of SiO2 with the same thickness.


H5.3
Electron-Stimulated Desorption of H / D from Silicon Surface with Homogeneous Electron Injection Toshiki Mori and Satoru Watanabe; Fujitsu Laboratories Ltd., Morinosato-Wakamiya, Atsugi, Kanagawa, Japan.

Isotope effects of hydrogen (H) and deuterium (D) at gate dielectrics/Si interfaces have attracted much attentions, concerning with the life time of MOSFETs[1,2]. In this work, we present observations of electron-stimulated desorption of H and D from silicon surface simulating that happens under operations in the FETs. Electrons produced in low-pressure plasma were used in order to provide homogeneous injection simulating currents flowing through the dielectrics such as SiO2, SiON, and high-k. Kinetic energies of injected electron were controlled with bias applied to the sample located in the plasma chamber. Samples with an ordered Si (111) 1x1 surface fully terminated by H or D were prepared using a wet chemistry. The desorption of H or D atoms under electron injection were monitored with observing thermal vibrations originated from Si-H and Si-D structures with highly sensitive infrared spectroscopic technique. Desorption rates of H and D for electron injection had a threshold energy at 6 eV, which corresponds to that was reported by the observation of STM[2], while our estimated desoption yield was quite larger[3]. Under the threshold energy, the desorption was attributed to Si-H and D bond breaking by multiple vibrational excitations so that the desorption yield was strongly affected by injection current density, while above the threshold those was attributed to electronic excitations.[2,4] But in our experimental configuration with homogeneous injection, the desorption rates had linearly dependence to current densities under the threshold, and we could not observe the reported large isotope effect[2] originates multiple vibrational excitation model. Models which lead to H and D desorption to explain our chemical, isotopic results while comparing with the results deduced with the STM will be discussed. [1] J. W. Lyding, K. Hess and I. C. Kizilyalli, Appl. Phys. Lett. 68 (1996) 2526. [2] T. -C. Shen, C. Wang, G. C. Abeln, J. R. Tucker, J. W. Lyding, Ph. Avouris and R. E. Walkup, Science 268 (1995) 1590. [3] T. Mori and S. Watanabe, Jpn. J. Appl. Phys. 44 (2005) L839. [4] C. G. Van de Walle and W. B. Jackson, Appl. Phys. Lett. , 69 (1996) 2441.


H5.4
Hydrogen Interaction with Point Defects in the Si-SiO2 System and its Influence on the Interface Properties. Daniel Kropman, Department of Materials Science, Tallinn University of Technology, Tallinn, Estonia.

It has been established by 1H NMR spectra measurements of the Si-SiO2 structure composed on the n- and p-type silicon samples, that the line width of the chemical shift of protons of the n-type samples is broader that of the p-type ones.The extent of this effect goes up with the extent to which the movement of adsorbed molecules is hindered. One possible reason for that can be the strength of the magnetic interaction with the paramagnetic impurities of the adsorbent. It has been proposed that this effect may be connected with the differences in the grown-in defects density in CZ and FZ grown wafers. In the present work set of experiments to investigate the effect is performed. Hydrogen content in Si-SiO2 system was varied by oxidation ambient composition and by SiH4 decomposition in NH3 ambient up to Si3N4 formation of SiO2. Hydrogen do not penetrate through Si3N4 and its provide his separation. It has been revealed, that after Si3N4 deposition the differences in hydrogen content between n- and p-type wafers increases. One possible reason, that explain the differences in hydrogen content in SiO2 on n- and p-type wafers may be it different separation. To evaluate the contribution of different hydrogen species and it distribution in SiO2 on n- and p-type wafers, the influence of the ions drift in SiO2 in electrical field (BT) on the charge value in SiO2 was investigated. It has been established that in MOS structure on p-type Si the BT treatment bring about increasing of the charge value, that is greater than in MOS structure on n-type samples and, hence the content of bonded and unbounded hydrogen in these samples is different.After the Si-SiO2 structure laser irradiation the influence of BT treatment on the Q value decreases.


H5.5
Comparative Study of Diffusion of Defects and Impurities in HfO2. Valerie Cuny¹, Nicolas Richard¹, Alain Esteve² and Mehdi Djafari Rouhani²; ¹CEA-DIF, Bruyères-le-Châtel, France; ²Laboratoire d'Analyse et d'Architecture des Systèmes, CNRS, Toulouse, France.

Continuous downscaling of transistor leads silicon dioxide constituting the gate in typical metal oxide semiconductor field effect (MOSFET) to its limits. One possibility is to replace SiO2 by a material of higher dielectric constant (high-k). Hafnium dioxide seems to be the most promising one. However, high-k transistor performances are often affected by the presence of defects creating charge traps or diffusion centers. In this paper, using a pseudopotential plane wave code in the density-functional total theory framework, we calculate in a monoclinic HfO2 supercell the structure, formation and ionisation energies, electron affinities and diffusion barriers of intrinsic defects (oxygen vacancy and interstitial, and hafnium vacancy) and extrinsic defects coming from dopants and impurities (Cl and F). We consider different charged states of these defects. The positions of defect levels with respect to the bottom of silicon conduction band are determined. Our results will be discussed and compared to literature data [1,2]. First results on HfSiON will also be presented. [1] J.L. Gavartin et al, J. Appl. Phys., 97, 053704 (2005) [2] A.S. Foster et al, Phys. Rev. B, 65, 174117 (2002)


H5.6
Design of Hafnium β-ketoiminato Precursors for the MOCVD of Hafnium Oxide Thin Films. Bradley Dean Fahlman and Anne Germeroth; Department of Chemistry, Central Michigan University, Mount Pleasant, Michigan.

Since the first CMOS field effect transistors were demonstrated, the gate length has steadily decreased to its current size of < 30 nm. For the current 65 nm technology node, this translates to a gate oxide on the order of 1.2 nm, or approximately 5 atomic layers! As one might imagine, such a thin insulating layer is prone to electron tunneling between the polysilicon gate and channel, leading to increased power consumption and heat buildup. A recent strategy to offset this problem is the use of high-k dielectric films rather than SiO2. These materials have a larger dielectric constant than SiO2, which allows one to use thicker oxide layers for an identical gate capacitance. Herein, we will report the synthesis/characterization of novel precursors for the chemical vapor deposition (CVD) of hafnium oxide (k = 25, relative to 3.82 for SiO2). The volatilities of the compounds were assessed using thermogravimetric analysis prior to CVD studies. The resultant films were characterized by SEM/EDS to assess the morphology, conformality, and chemical composition.


H5.7
Chemical Vapor Deposition of Hafnium and Zirconium Oxide Thin Films. Bradley Dean Fahlman and Jason C. Macdonald; Department of Chemistry, Central Michigan University, Mount Pleasant, Michigan.

As we continue the goal of increasing computational speed for miniaturized devices, the size of the transistor “workhorses” are fast approaching fundamental limits. Since integrated circuits (ICs) reached the market in the 1970’s, the number of transistors has grown from < 10 to now over 1 billion in the most recent dual-core Intel chips. For the current 65 nm technology node, this miniaturization translates to a gate oxide thickness on the order of 1.2 nm, or approximately 5 atomic layers! A recent strategy to offset the ensuing gate leakage problem is the use of high-k dielectric films rather than SiO2. These materials have a larger dielectric constant than SiO2, which allows one to use thicker oxide layers for an identical gate capacitance. Herein, we will describe the synthesis and characterization of Hf and Zr β-ketoiminato and β-diketiminato precursors for the MOCVD of HfO2 and ZrO2. The resultant films will be characterized by SEM/EDS to assess the morphology, conformality, and chemical composition.


H5.8
Observation of an Interfacial Transition Layer in a Nano-scale SiO₂ Layer on a Si Substrate by X-ray Reflectivity (XRR) Analysis. Chang-Soo Kim¹, Tae-Kyoung Koo^2,1, Ji-Yeon Yun^2,1, Byung-Sung Oh² and Young-Dae Choi³; ¹Div. Of Advanced Tech., Korea Research Institute of Standards and Science, Daejeon, South Korea; ²Department of Physics, Chungnam University, Daejeon, South Korea; ³Department of Optical and Electronic Physics, Mokwon University, Daejeon, South Korea.

Nanometer scale single SiO₂ layers of thicknesses of 2, 4, 8 and 10 nm were grown, respectively, on (100) Si substrates by thermal oxidation method. X-ray reflectivity (XRR) measurements were performed using a normal X-ray diffractometer equipped with an X-ray mirror. Since the amplitudes of the thickness fringes of a reflectivity curve for a SiO₂ layer on Si are very low due to the small difference in the electron densities between SiO₂ and Si, a measured reflectivity curve was normalized with a reference reflectivity curve for a Si substrate, and the normalized curve showed clearly the positions of the thickness fringes and the overall shape of the curve. The normalized reflectivity curve was analysed by fitting with the calculated reflectivity curve which was also normalized with the same reference curve. The positions of the thickness fringes for the measured reflectivity curve are identical with those for the average of two calculated curves, one is the best fit calculated for the SiO₂ single layer with a higher refractive index than that of Si substrate, and the other calculated for the SiO₂ single layer of a different thickness with a lower refractive index. The result suggests that the variation in the fringe positions is caused by the interference effect from the two oxide layers of different refractive indices and of different thicknesses with each other. The refinement of the simulation shows that between the SiO₂ overlayer and the Si substrate there exists a thin SiO₂ interfacial transition layer of a different refractive index from that of the SiO₂ overlayer, and the thickness of the transition layer is about 0.9 nm. For all of the samples examined in the study the XRR results show the interfacial transition layers of almost the same thicknesses. The mechanism for the formation of the interfacial transition layer will be discussed. In addition, the analytical method used in the study determines the thickness of an ultra-thin SiO₂ layer on Si with low uncertainty and the SiO₂ thicknesses of the samples by XRR analyses are compared with those by TEM, XPS and SE. X-ray reflectivity curve for a SiO₂ layer was influenced by surface contamination, and the effect of the surface contamination on the thicknesses of the overlayer and the interfacial transition layer will be also discussed.


H5.9
Synthesis and in situ Characterization of High-k Oxides by Remote Plasma ALD. Erwin Kessels¹, Hans Van Hemmen¹, Wytze Keuning¹, Erik Langereis¹, Stephan Heil¹, Johan Klootwijk², Fred Roozeboom³, Chris Hodson⁴ and Richard Van de Sanden¹; ¹Dept. of Applied Physics, Eindhoven Univ. of Technology, Eindhoven, Netherlands; ²Philips Research, Eindhoven, Netherlands; ³NXP Semiconductors Research, Eindhoven, Netherlands; ⁴Oxford Instruments Plasma Technology, Yatton, United Kingdom.

High quality oxides can be prepared at low temperatures by remote plasma atomic layer deposition (ALD) alternating metalorganic precursor dosing with O₂ plasma exposure. In this contribution we report on remote plasma ALD of several high-k oxides on 8” silicon wafers in the Oxford Instruments FlexAL reactor. The reactor is equipped with in situ UV-VIS spectroscopic ellipsometry (spectral range 1.2 - 6.5 eV) that is used to monitor the film growth process and to characterize the properties of the oxide film and oxide/semiconductor interface obtained. In situ experimental data will be reported on the following oxides: HfO₂ deposited from tetrakis(ethylmethylamino)hafnium (TEMAH); Al₂O₃ deposited from trimethylaluminium (TMA); Ta₂O₅ deposited from pentakis(dimethylamino)tantalum (PDMAT); and TiO₂ from titaniumisopropoxide (TIP). The deposition temperatures range from 25 - 350 °C. Additional ex situ characterization of the oxide films will be provided by transmission infrared spectroscopy, C-V and I-V measurements, and high-resolution SEM imaging of the oxides deposited in high-aspect ratio features such as blind via holes (aspect ratio = ~10).


H5.10
Effect of Oxidizer on Chemical Vapor Deposited Hafnium oxide-based Nanostructures and the Engineering of their Interfaces with Si(100). Manish K Singh¹, Gregory Jurisch² and Christos G Takoudis³; ¹Department of Chemical Engineering, University of Illinois at Chicago, Chicago, Illinois; ²American Air Liquide, Countryside, Illinois; ³Departments of Chemical Engineering and Bioengineering, University of Illinois at Chicago, Chicago, Illinois.

The silicon based complementary metal oxide semiconductor field effect transistor is the most important component in modern electronic devices. To meet the need for faster electronics and smaller devices, transistors have been continuously miniaturized over the past several decades. This scaling has allowed for more and more transistors to be fit on a single chip. But this scaling has led to the silicon dioxide layer reaching a limit below which the leakage current has become too large. A possible way identified to continue miniaturization is to replace the currently used silicon dioxide layer with a suitable gate dielectric material having a higher dielectric constant (κ). The new dielectric material has to meet several criteria most important of which are: (i) it should form a good interface with silicon, and (ii) it should be thermodynamically and kinetically stable during post deposition processing at temperatures up to 1000 °C. In contrast to silicon oxide, which can be thermally grown, the high κ dielectric material has to be deposited. Quality of deposited films depends on the method of deposition. Industrially, metal organic chemical vapor deposition (MOCVD) and its modified version, atomic layer deposition (ALD) are the two most widely used techniques for high-κ deposition. Choice of oxidizer for these techniques strongly influences the quality of deposited films and their interfaces with Si. Hafnium oxide (κ ~ 25) is currently one of the promising high-κ replacements. Several precursors have been studied including halide, alkoxide, and amide based ones. In this study, thin films of hafnium oxide are deposited using a metal amide precursor, tetrakis(diethylamino) hafnium along with two different oxidizers: (a) ozone/oxygen mixture, and (b) dry oxygen. Ozone being a strong oxidizer results in films with lower contamination from incomplete oxidation of precursor. On the other hand, the strong oxidizing nature of ozone also leads to more interfacial oxide formation during deposition process. These two factors have to be considered before choosing the oxidizer for MOCVD or ALD process. Fourier-Transform infra-red spectroscopy and x-ray photoelectron spectroscopy are used to investigate and compare the HfO₂/Si interface. The MOCVD hafnium oxide films are also compared to the ALD hafnium oxide films deposited using the same precursor and water. Effect of annealing in argon ambient is also studied to investigate the stability of HfO₂ film and the changes at the interface with Si(100) at temperatures up to 1000 °C.


H5.11
Electronic Structure and Thermal Stability of HfSiON Using a Direct Plasma Nitridation. Kwun Bum Chung¹, Chan Jung Lim^3,1, Moon Hyoung Jang^2,1, Dae-Hong Ko³ and M. -H. Cho²; ¹Advanced Analysis Group, Korea Research Institute of Standards and Science, Daejeon, South Korea; ²Institute of Physics and Applied Physics, Yonsei University, Seoul, South Korea; ³Ceramic Engineering, Yonsei University, Seoul, South Korea.

The thermal stability and electronic structure of nitrided xHfO₂(100-x)SiO₂ (HfSiO) (x = 30%, 55%, and 70%), prepared using a direct N plasma treatment, were investigated by various techniques. The N 1s spectra of nitrided Hf-silicate film indicate that complex chemical states are generated. In particular, the energy states with a high binding energy are stably maintained even after post-nitridation anneal. The quantity of N incorporated into the film is almost equal and is not related to the mole fraction of HfO₂ in the film, while the thermal stability of the N in the film is significantly influenced by the fraction of HfO₂ present. Some of the N bonded to HfO₂, but not to SiO₂, in an alloy film of HfO₂-SiO₂is very unstable, resulting in out-diffusion after the post nitridation anneal. The thermal stability of the N in the film critically affects the stoichiometry and thickness of the film: i.e, after the post-nitridation anneal, the thickness of the silicate film and the quantity of Hf and N are decreased, as the result of the dissociation of unstable Hf-N bonds.


H5.12
Electronic Structure and Defects in Al2O3 Gate Oxides. Dameng Liu, Koon-yiu Tse and John Robertson; Engineering, Cambridge University, Cambridge, United Kingdom.

High dielectric constant (K) oxides are needed to reduce gate leakage current in CMOS devices. Al2O3 is one of those considered. It has a very wide band gap, a moderate K value, and its great advantage is that it stays amorphous if annealed to high temperatures. The local structure of the amorphous phase is not like in corrundum, the average Al coordination is closer to 4 than 6. It also has a lower band gap of ~6.2 eV, compared to 8.8 eV. We find that the beta-Ga2O3 structure is a reasonable model of the amorphous Al2O3 phase, having a mixture of 4- and 6-fold Al sites. We have calculated the band gap of this phase to be 6.5 eV in the weighted density approximation, which gives the correct band gaps. This resolves the differences between the calculated and experimental band gaps and conduction band offsets found previously. We have calculated the electronic structure of defects in both the corundum and Ga2O3 structures. The vacancy levels lie near mid gap and the vacancy states are strongly localised. The Si-Al2O3 interface has also been studied, in order to understand the origin of its tendency to give PMOS pinning.


H5.13
IBA of Ordered Ultra-thin SiO2 Grown on (1x1) Si(100). Nicole Herbots¹, James Bradley¹, Robert J. Culbertson¹, Justin Shaw² and Vasu Atluri³; ¹Physics, Arizona State University, Tempe, Arizona; ²Magnetics Group, NIST, Boulder, Colorado; ³Intel Corp., Chandler, Arizona.

2 - 20 nm thick SiO2 films were grown on OH-passivated, ordered (1x1)Si(100) surfaces. The passivated (1x1)Si(100) surfaces are stable in ambient air and formed at room temperature by wet chemical cleaning [US Patent 6,613, 677, Herbots et al.]. The oxides are grown by Rapid Thermal Oxidation. Oxygen and silicon in the oxide are detected by Ion Beam Analysis (IBA) using a combination of ion channeling with the 3.05 MeV 16O(alpha,alpha)16O nuclear resonance. IBA yields Si surface peak areal densities (SP) lower than that of a disorder-free, bulk-terminated (1x1)Si(100) crystal calculated by the Monte-Carlo program 3-D string. This indicates that Si substrate atoms are shadowed by Si atoms within the oxide in the first 2 nm, after which the Si SP increases linearly with oxygen coverage. Beyond 2 nm, the oxide becomes amorphous. No unregistered Si is found at the SiO2/Si interface. Shadowing is detected in <100>, <110> and <111> direction. This is consistent with insertion of oxygen atoms close to a strained crystobalite-like phase. Alignment to Si(100) is also supported by 10 keV Reflection High Energy Electron Diffraction (RHEED). Comparative Infrared spectroscopy ordered oxides exhibit a constant, well-defined frequency of optical absorption across a 1 nm thickness in the interfacial region near Si. This is in contrast to a rapidly changing frequency in conventional oxides in the same region. Thus, IR supports the presence of a well defined bond-length and stoichiometry as detected by IBA and RHEED. Comparison between HRTEM and ellipsometry measurements show that the HRTEM thickness is significantly lower, by 30%, when compared to the thickness measured by ellipsometry. indicating a change in optical properties. TOF-SIMS shows that carbon concentrations in the ultra-thin ordered oxides is lower by several order of magnitudes when compared to conventional oxide.


H5.14
A New 3D Multistring Code to Identify Compound Oxide Nanophase With Ion Channeling. Nicole Herbots¹, James Bradley¹, Robert Culbertson¹, Justin Shaw² and Vasu Atluri³; ¹Physics, Arizona State University, Tempe, Arizona; ²Magnetics Group, NIST, Boulder, Colorado; ³Intel Corp., Chandler, Arizona.

A new computer code has been developed and tested to simulate channeling data of ordered Silicon Oxide nucleated on passivated (1x1) silicon formed via oxygen hydroxyl-like termination of silicon (100) in air at 300 K via the Herbots-Atluri clean as described in U.S. patent 6,613,677 (9/3/2003). Short range order within these new nanofilm phases has been investigated along the three major crystal directions of <100>, <110>, and <111> of the cubic diamond Si (100) substrate via ion channeling and blocking combined with the 3.05 MeV nuclear resonance analysis and comparison of ion scattering data with computer simulations of beta-cristobalite silicon dioxide 1-50 nm thick nanofilms on Si (100) as a function of oxygen coverage The new computer code, which we call "3D MultiSTRING", is derived from the original 3DSTRING program that originated at Bell Labs, NJ . When epitaxially ordered silicon oxide is modeled as _- cristobalite layered on (1x1) terminated cubic diamond silicon, the simulated ion channeling spectra confirm what is observed experimentally via Ion Beam Analysis (IBA) combining ion channeling and nuclear resonance analysis (NRA) with the 3.045 MeV 16O(alpha,alpha)16O interaction. A new, never previously identified ordered oxide interphase between the amorphous silicon oxide top films and the ordered Si (100) interface is discovered and exhibits a critical thickness measured at the (1x1) Si (100)/epitaxial silicon dioxide interface and the ordered/amorphous glass interphase.


H5.15
Abstract Withdrawn


H5.16
Chemistry and Electronics of CH₃-Ge(111). David Knapp and Nathan S. Lewis; Division of Chemistry and Chemical Engineering, California Institute of Technology, Pasadena, California.

One of the reasons Germanium has been outpaced by Silicon as an electronic device material, despite higher carrier mobilities, is the instability and higher electrical defect density of the Germanium oxide. This drawback disappears if the silicon dioxide is to be replaced with other dielectrics, provided the semiconductor surface can still be passivated. As with Silicon, the chemsitry of Germanium permits methyl termination of the (111) surface, which for Silicon has proven to be an effective method for passivating an oxide-free surface. Such a surface is obtained from an oxidized substrate in three steps: fluoride solution based hydrogen termination; radical halogenation; and methylation with methylmagnesium chloride. In addition, the solubility of GeO₂ allows for direct aqueous hydrochloric or hydrobromic acid based halogenation not possible for Si substrates. We address the applicability of the two- and three-step methylation reactions to producing passivated Ge surfaces. We compare electrical stability and defect density, as measured by surface conductance and surface recombination velocity, to chemical composition and stability, as measured by XPS and FTIR. A major impediment to obtaining methyl surfaces of the same quality as CH₃-Si(111) is the instability of the precursor H-Ge(111) and X-Ge(111). There is evidence that this is due in part to surface roughness.


H5.17
Structural Properties and Electrical Performance of La₂Hf₂O₇ on Si. Monica Sawkar-Mathur and Jane P Chang; Chemical Engineering, UCLA, Los Angeles, California.

The continuous down-scaling of microelectronic devices requires a replacement gate dielectric for future generation metal oxide semiconductor field effect transistors (MOSFETs). HfO₂ has been studied extensively and is promising in replacing SiO₂ because of its high dielectric constant and low leakage current. However, the interfacial issues arising from the amorphous HfO₂/crystalline Si interface limit the successful integration of HfO₂ in MOSFET devices. As a result, it may be beneficial to employ a crystalline oxide to achieve an atomically sharp interface between the gate dielectric and silicon, providing a low defect density. Furthermore, the use of a crystalline oxide may lower the leakage current and improve the reliability due to the lack of grain boundary formation upon post-deposition high temperature processing. An important criterion for the successful growth of crystalline oxides on silicon is a small lattice mismatch between silicon and the crystalline oxide. One crystalline oxide that has recently gained attention is La₂Hf₂0₇, which has a lattice parameter approximately two times that of silicon, resulting in a lattice mismatch of ~1% at room temperature and essentially zero at ~800°C, making it an excellent candidate for epitaxial growth on Si.* A comprehensive study of La₂Hf₂O₇ is performed, including detailed analysis of its bulk crystal structure, its interfacial properties, and its electrical performance. La₂Hf₂O₇ is deposited by atomic layer deposition (ALD) on Si using hafnium t-butoxide as the Hf precursor and La[N(SiMe₃)₂]₃ as the La precursor. The composition of the bulk film and at the interface is determined by X-ray photoelectron spectroscopy (XPS). Synchrotron X-ray diffraction (XRD) is used to determine the crystalline structure of La₂Hf₂O₇ film and its epitaxial relationship to the Si substrate. Macroscopic structure determined by synchrotron XRD is used in conjunction with cross-sectional high-resolution transmission electron microscopy (HRTEM) images and the local structure determined from extended x-ray absorption fine structure (EXAFS) to fully assess the structure of the La₂Hf₂O₇ films deposited. MOS capacitors fabricated on the films deposited are used to assess the electrical performance through leakage current density-voltage (J-V) and capacitance-voltage (C-V) analysis, which yield information about the leakage current density and barrier height across the La₂Hf₂O₇/Si interface, the dielectric constant, equivalent oxide thickness, and density of interface states. * Mereu, B. et. al. Applied Physics A 80, (2005).


H5.18
Abstract Withdrawn


H5.19
Material and Electrical Properties of HfRuN Gate Electrodes on HfO₂. Monica Sawkar-Mathur and Jane P Chang; Chemical Engineering, UCLA, Los Angeles, California.

Many alternative gate dielectric candidates for future generation MOSFET devices, including Hf based dielectrics, require the use of a metal gate, because of the instability issues, sheet resistance, gate depletion, and dopant penetration issues experienced with polysilicon gates. Hf based gate electrode materials may be promising candidates, because they are believed to reduce the charge transfer and subsequent dipole formation, as a result of the homo-nuclear bonds that form between the Hf in the metal gate and the Hf in the gate dielectric. It is important that the gate electrode material is thermodynamically stable with Hf based dielectrics, and no inter-diffusion occurs between the metal atoms in the gate electrode material and the metal atoms in the dielectric material. The bulk work function of Hf is ~4 eV, however, it is very reactive and unstable. As a result, it is necessary to reduce its reactivity by incorporating nitrogen and/or by alloying it with a less reactive higher work function metal. This paper discusses the material and electrical properties of sputter-deposited Hf-Ru and Hf-Ru-N gate electrodes atop atomic layer deposited HfO<su>2. X-ray photoemission spectroscopy (XPS) and X-ray diffraction (XRD) analyses determined the composition and crystalline phase of the films. The thermal stability of the films is assessed through the depth profiling of the gate stacks using both Secondary Ion Mass Spectrometry (SIMS) and XPS before and after rapid thermal annealing at 800oC. Capacitance-voltage (C-V) characteristics of fabricated metal-oxide-semiconductor (MOS) capacitors are used to determine the effective work functions (EWFs). The EWFs are determined as a function of alloy composition to determine the best composition for p-MOSFET devices. Pure Hf and pure Ru gate electrodes deposited on HfO₂ exhibited EWFs of 4.1eV and 5.3eV, respectively. HfRu alloys with EWFs ranging from 4.4 to 5.0eV have been deposited on HfO2. HfRuN (%N varying from 27-41%) films were synthesized to assess the effect of nitrogen incorporation on the work function. An EWF of a HfRuN film with a Hf:Ru:N ratio of 1:6:3 was determined to be ~5eV, a possible candidate for p-MOSFET devices.


H5.20
Evaluation of Plasma Nitridation (PN) with Low Electron Temperature for the DRAM application. Hyo-jung Kim, Woo-jun Lee, Sung-kwan Kang, Jae-young Park, Han-jin Lim, Seok-woo Nam, Tae-hyuk Ahn and Chang-lyong Song; NRD-PJT, Samsung electronics Co., Hwaseung-Si, South Korea.

Plasma nitridation can introduce high nitrogen concentration to block boron penetration and decrease leakage current through very thin oxide and realize small EOT without the increase of thickness. However, nitrogen incorporation by plasma nitridation with the high electron temperature (Te) at the poly Si/SiON can induce plasma damage, which results in the decrease of mobility and the increase of leakage current. Especially, the effect of plasma damage on the electrical property of CMOSFETS becomes more severe as the gate oxide scales down. In this paper, two types of plasma nitridation with low electron temperature (<1.5eV) was compared in terms of boron penetration and leakage current for the DRAM application. One is the microwave source (2.45GHz) type and the other is RF source (13.56MHz). For the basic test, N atom profile and total N contents in about 20Å gate oxide was obtained using AR-XPS and shallow probe. With the microwave source plasma nitridation process, the re-oxidation occured at the gate oxide/Si substrate could reduce leakage current and improve on current characteristics. For the comparison of electrical results, all process used in this experiment were based on the high density DRAM technology. The electrical results, such as boron penetration and leakage current, will be discussed.


H5.21
Abstract Withdrawn


H5.22
Gas Phase HF Etching of III-V Compound Semiconductors. Fee Li Lie and Anthony J. Muscat; Chemical and Environmental Engineering, University of Arizona, Tucson, Arizona.

III-V compound semiconductor materials are potential candidates for high speed, low power devices due to their significantly higher electron mobility and conductivity compared to classic Si-based devices. In order to integrate III-V semiconductor materials into high quality electronics, controlled removal of native oxide and passivation/activation of the surface are crucial. Various etching techniques to remove native oxide in III-V compounds such as liquid phase chemical etching, thermal desorption, and ion bombardment face issues of partial oxide removal, roughened surfaces and selective etching, which leads to a change in surface stoichiometry. Gas phase processing is emerging as a technique that not only addresses the issues of process repeatability and uniformity, but also minimizes ultra pure water usage and reduces the thermal budget. Si technology has long utilized HF in the liquid phase to etch SiO₂ producing surfaces passivated with H atoms, which could be readily desorbed by heating in a subsequent deposition step. This study investigated gas phase etching of GaAs, InP, and InAs using mixtures of anhydrous HF and water vapor at a total pressure below 100 Torr and temperatures from 20-40°C. In-situ X-ray photoelectron spectroscopy (XPS) was used to characterize oxide removal and fluorine coverage. Substrates exposed to gaseous mixtures of anhydrous HF and water vapor for 30 s at 100 Torr and 29°C showed that the balance of HF and water vapor fed to the reactor was important in oxide removal. The partial pressures of HF and water were varied from 3.6 to 14 Torr and 6.2 to 12 Torr , respectively. The results show that HF to water vapor ratios near 1 yielded the lowest F coverages, while preserving the stoichiometry between the group III and V atoms. Atomic force microscopy (AFM) showed that the HF/vapor processes did not roughen surfaces compared to the starting surface.


H5.23
Al-Oxynitride Buffer Layer Facilities for PrO_X/SiC Interfaces. Karsten Henkel, Rakesh Sohal, Carola Schwiertz, Yevgen Burkov and Dieter Schmeisser; Angewandte Physik-Sensorik, BTU Cottbus, Cottbus, Brandenburg, Germany.

The use of a buffer layer between PrO_X and SiC is necessary as we found destructive interactions like silicate and graphite formation between these materials. We focus on aluminum oxynitride (AlON) as a suitable buffer layer for this high-k/wide band gap system. Its permittivity value and a good lattice matching to SiC should act as benefits for good chemical and electrical properties of the interface. The AlON layers are prepared by sputtering an aluminum source with nitrogen ions. We report on results achieved by synchrotron Radiation Photoemission Spectroscopy (SRPES) and on results of electrical measurements, respectively. In our spectroscopic investigations we found a stable AlON/3C-SiC interface as well as no elemental carbon and silicate distributions in the core levels after thin PrO_X deposition and annealing up to 900°C. In electrical characterizations of PrO_X/AlON stacks on silicon we found already a strong improvement in the leakage current up to values of 10^-7 A/cm² at an EOT of 4nm. The interface state density could be reduced to mean values of 5*10¹¹/eVcm². Even first results of characterization on SiC will be presented.


H5.24
Metal Electrode Dependent Interface States of HfO2 Film on Si and Ge Substrates. In-Sung Park¹, Sunwoo Lee², Sang Seol Lee², Jungho Park² and JinHo Ahn²; ¹Information Display Research Institute, Hanyang Univeristy, Seoul, South Korea; ²Department of Materials Science and Engineering, Hanyang University, Seoul, South Korea.

As complementary metal-oxide-semiconductor (CMOS) devices continue to scale down for higher integration density and better performance, there is an enormous interest in developing strained substrate, high-k dielectric, and metal gate electrode to replace conventional Si substrate, SiO2, and poly-Si electrode, respectively. These replacements can enhance the performances of transistor including high mobility, low leakage current, and low threshold voltage. In this paper, we present gate electrode dependent interface states between HfO2 and Si or Ge substrate. The high-k HfO2 films were grown with atomic layer deposition technique on chemical-treated substrates. The MOS capacitors were fabricated with several electrodes with different work functions for nMOS and pMOS such as TaN, Ti, Al, Mo, Ru, and Pt. From the C-V measurements, it is clearly observed that the interfacial oxide thickness (EOT) and flat band voltage (Vfb) shifts depend on the metal electrodes. In addition, electrode-dependency of dielectric breakdown, interface trap, and reliability characteristics is also observed. For example for pMOS electrodes, Mo electrode exhibits a thinner and excellent interfacial state demonstrated by TEM results, which leads thinner EOT, lower interfacial trap generation, and longer expected lifetime than Ru and Pt electrodes.


H5.25
Surface Preparation of Germanium using Reactive Gas Phases Shariq Siddiqui and Anthony J. Muscat; Department of Chemical and Environmental Engineering, University of Arizona, Tucson, Arizona.

Germanium is a candidate to replace silicon in high performance devices because it has a higher carrier mobility and narrower band gap. Challenges must be overcome to use germanium in device manufacturing. For example, Ge oxides are not stable. Wet cleaning techniques to remove oxides and suboxides from Ge surfaces could be problematic, since GeO2 is soluble in water and could permit contamination to reach the Ge/GeO2 interface resulting in poor electrical properties. The lattice mismatch between Ge and GeO2 also produces an inhomogeneous oxide layer. The introduction of Ge consequently is an opportunity to use nonaqueous chemistries and deposit dielectric films needed for device fabrication directly on Ge surfaces. X-ray photoelectron spectroscopy (XPS) was used to study the removal of Ge oxides from Ge(100) with gas phase mixtures of HF and water vapor. Gas phase etching was performed at a total pressure of 100 Torr and a temperature of 29°C for 30 s exposures. The partial pressure ratio of HF and water vapor was varied from 0.3 to 2.3. The results were benchmarked with aqueous HF solutions at concentrations in the range of 1:100 to 1:10 (HF to ultra-pure water ratio by volume). Peak decomposition of the Ge 2p and 3d XPS traces showed how the oxidation state of Ge varied with the process fluid and conditions. The results show how to control the first step in developing a procedure to prepare clean Ge surfaces for the deposition of high dielectric constant films.


H5.26
Abstract Withdrawn


H5.27
Investigation of Local Coordination and Electronic Structure of Dielectric Thin Films from Theoretical Energy-loss Spectra. Manish K Singh¹, Javier Rosado², Ramarajesh R Katamreddy¹, Anand Deshpande¹ and Christos G Takoudis³; ¹Department of Chemical Engineering, University of Illinois at Chicago, Chicago, Illinois; ²Air Products and Chemicals, Inc., Allentown, Pennsylvania; ³Departments of Chemical Engineering and Bioengineering, University of Illinois at Chicago, Chicago, Illinois.

Electron energy-loss spectroscopy (EELS) is a powerful technique for thin film analysis with sub-nanometer spatial resolution. This technique is ideal for characterizing the interfaces and ultrathin layers in the high-κ dielectric stacks. EELS uses the characteristic spectrum of energy losses of transmitted electrons to obtain information about elemental composition, chemical bonding and electronic structure of thin films. The electron energy-loss spectrum can be separated into two regions, low energy-loss and high energy-loss. Valence EELS (VEELS) in the low energy-loss region (0-100 eV) directly reflects the valence and conduction band structures while energy-loss near edge structure (ELNES) present at edges in the high energy-loss region (typically > 100 eV) probes the unoccupied electronic states. EELS experiments combined with theoretical calculations can provide clarification on the electronic structures and bonding coordination of thin films and aid in interpreting the features of the energy-loss spectrum. In this study, we perform quantum mechanical simulations to calculate the VEELS for aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, silicon oxide and silicon systems using the full potential Linearized Augmented Plane Wave (LAPW) formalism within the Density Functional Theory (DFT) framework. To simulate the low-loss spectra (VEELS), the energy-loss function (ELF) is derived from the calculation of the complex dielectric tensor within the random phase approximation. The calculated spectra are compared with experimental scanning transmission electron microscope/EELS of atomic-layer deposited Al₂O₃ and HfO₂ on Si(100) to evaluate their use as a “fingerprint” method to distinguish between various polymorphs of Al₂O₃ and HfO₂ thin films and relate the fine structure to the electronic structure and local bonding environment. Calculated low-loss spectra are in excellent agreement with the experimental data. Also, the combination of such theoretical calculations and experimental data has been of key importance in our understanding of fundamental issues of these systems. Compared to ELNES or core energy-loss spectra, the ELF calculated for low-loss spectra is computationally less expensive and can prove useful for prompt analysis. The pDOS and joint DOS are also calculated to interpret the EELS features as well as determine the matrix element effects, a factor that weights the effect of selection rules on the calculated EELS.


H5.28
Structure and Diffusion of Excess Silicon in Amorphous Silica: First Principles Studies. Chin-lung Kuo, Sangheon Lee and Gyeong S Hwang; Chemical Engineering, The University of Texas at Austin, Austin, Texas.

Atomic-level understanding of the behavior and properties of defects in oxide layers and their interfaces is crucial in the evolution of silicon semiconductor technology. In particular, the behavior of excess silicon atoms in silica is of great interest as they can directly influence the fabrication and performance of silicon-based electronic and photonic devices, such as the synthesis and structure of oxide-embedded silicon nanocrystals and the evolution of dopant profiles in ultrashallow junction formation. In this presentation, we will show the structure, diffusion, and bonding mechanisms of single silicon atoms and silicon-oxygen molecules introduced in amorphous silica based on density functional theory calculations. Silicon diffusion in silica has been extensively studied both experimentally and theoretically, but the underlying diffusion mechanism is still unclear. Recent experiments have shown that silicon diffusion coefficients under equilibrium conditions are two orders of magnitude lower than those under nonequlibrium conditions (where silicon atoms are presented in excess.) Silicon diffusion (under equilibrium) in thermally grown amorphous silica has been described taking into account silicon-oxygen molecules generated at the silicon/silica interface, but yet ambiguous. Results from our extensive first principles calculations shed some light on the complex diffusion behavior of silicon in amorphous silica.


H5.29
Microstructure Evolution in Yttria-doped Zirconia Thin Films Grown on High-mobility Semiconductor Substrates. Masaru Tsuchiya¹, Andrew Minor² and Shriram Ramanathan¹; ¹Division of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts; ²National Center for Electron Microscopy, Lawrence Berkeley National Laboratory, Berkeley, California.

Doped-transition metal-oxides such as Y-doped ZrO₂, Gd-doped HfO₂ are considered promising high-dielectric constant materials to replace SiO₂ as the gate insulator for future nanoelectronic devices. Adding sufficient dopants such as yttria (Y₂O₃) to ZrO₂ stabilizes high temperature cubic phase (referred to as YSZ) down to room temperature and can lead to an increased dielectric constant. This is an elegant approach to improving the scaling of the dielectric constant of the gate oxide. Due to its technological importance, microstructure of bulk YSZ had been extensively studied both experimentally and theoretically for many years. However, there has been very little research to understand role of substrate in the resulting microstructure of YSZ thin films and their stability. Moreover, very little is known about structure and stability of such oxides on high-mobility semiconductors such as Ge, InAs etc. Here we report in-situ transmission electron microscopy (TEM) observation of structure evolution in YSZ films grown by electron beam evaporation. YSZ (8 % Yttria doped) were grown on Ge, InSb, InAs, and MgO substrates by electron beam evaporation technique at room temperature. Samples were annealed both in-situ inside the TEM using a heating holder and also ex-situ and the resulting structures were studied. Interestingly, as-grown doped-zirconia films on Ge (100) show amorphous structure, while those on InSb and InAs substrates show polycrystalline structure. During in-situ heating experiments, we observed amorphous doped-zirconia thin film on Ge nearly instantaneously crystallized into cubic phase near 520 °C. On the other hand, as-grown polycrystalline YSZ thin film on InSb and InAs appeared to transform into single crystalline film at only 300 °C. These results were also correlated to ex-situ air annealing experiments. The differences in microstructure of as-grown samples and the crystallization temperature indicate the role of substrate in altering free energy of nucleation in nanoscale YSZ films and we will discuss this aspect in detail in this talk.


H5.30
Rare-earth Based Pseudobinary High-k Dielectric. Peter Darmawan, Jin Shun Teh and Pooi See Lee; School of Materials Science and Engineering, Materials Technology, Nanyang Technological University, Singapore, Singapore.

The future high-performance devices was projected to require transistor gate stacks to have an equivalent oxide thickness (EOT) <1.0 nm for the 45 nm node, according to the International Technology Roadmap for Semiconductors (ITRS) [1]. The use of SiO2 based gate dielectric has approached its limit when scaled down to below 1.5 nm. The gate current increases rapidly due to the quantum mechanical tunneling. One approach to overcome this problem is with the introduction of high-k dielectrics. However, up to now, no material is found to meet all requirements imposed: the chemical and structural stability in contact with Si at high temperature, the large bandgap and conduction/valance band offsets to Si, high-k value and preservation of the amorphous morphology at the CMOS processing thermal budget. The use of Lu2O3 as a gate dielectric has been reported using various deposition methods such as Atomic Layer Deposition (ALD) [2], E-beam deposition [3], and Pulsed Laser Deposition (PLD) [4]. This work explores the possibility of improving further the properties of Lu2O3 as a high-k dielectric through the incorporation of SrTiO3 in various (Lu2O3 : SrTiO3) atomic percent ratios. SrTiO3 has been known to have a very high dielectric constant of ~300 at room temperature. Eisenbeiser et al has reported that an EOT of < 1 nm is achievable by using SrTiO3 as gate dielectric.[5] The (Lu2O3)x (SrTiO3)y was deposited on a p-type Si(100) substrate using PLD. The thickness of the film was estimated to be around 5 nm for a 2 minute deposition time. Atomic Force Microscopy (AFM) analysis revealed a surface roughness of about 0.345 nm and this is improved to 0.159 nm after subjecting it to rapid thermal annealing (RTA) at 400°C for 1 minute in nitrogen gas ambient. The Capacitance-Voltage (C-V) measurement revealed a well-shaped C-V curve with minimal trapped charges in the film. Low leakage current of 2.35 x 10-5 A/cm2 at -1 V bias is also obtained from the current density versus voltage (J-V) measurement. The electrical measurement results indicated an improvement in properties of Lu2O3 as a gate dielectric in term of its k-value (k > 15) and achieving a of low leakage current 2.35 x 10-5 A/cm2, making this pseudobinary system an attractive candidate worth pursuing. Further refinement in the processing conditions should bring about additional improvements to the properties of the (Lu2O3)x (SrTiO3)y thin film. <p> References: <p> [1] International Technology Roadmap for Semiconductors, (2005). <p>[2] G. Scarel, E. Bonera, C. Wiemer et al., Applied Physics Letter 85, 630 (2004). <p>[3] S. Ohmi, M. Takeda, H. Ishiwara et al., J. Electrochem. Soc. 151 (279) (2004) <p>[4] P. Darmawan, C. L. Yuan, P. S. Lee, Solid State Communications 138 (12), 571 (2006) <p>[5] K. Eisenbeiser, J. M. Finder, et al, Applied Physics Letter 76, 1324 (2000)


H5.31
Surface Reconstruction Dependence and Annealing of Amorphous Lanthanum Aluminate on GaAs. Donghun Choi¹, Maitri Warusawithana³, Chi On Chui², Niti Goel², Wilman Tsai², Darrell G. Schlom³ and James S. Harris¹; ¹Electrical Engineering, Stanford University, Stanford, California; ², Intel Corporation, Santa Clara, California; ³Materials Science and Engineering, Pennsylvania State University, University Park, Pennsylvania.

One of the approaches to realize low power and high-speed/frequency devices is using materials in which the mobility is much higher than Si, like GaAs. But the big issue for using these III-V materials is that they require good insulators to achieve low interface state densities (Dit) and avoid Fermi level pinning to enable realization of inversion mode devices. In this work, we investigated the use of molecular beam deposited (MBD) lanthanum aluminate (LaAlO3) for GaAs-based metal-oxide-semiconductor (MOS) device applications. Amorphous LaAlO3 films were ex-situ deposited on GaAs layers grown by molecular beam epitaxy (MBE) on p-type GaAs wafers. We used a thick Arsenic capping layer to protect the surface from oxidation and contamination during wafer transfer between MBE chambers. Thin (5 nm) LaAlO3 layers were deposited on three differently reconstructed GaAs surfaces, which were engineered by thermal Arsenic decapping at different temperatures: i) (2x4) As-rich surface, ii) c(4x4) As-rich surface, and iii) (1x1) surface due to insufficiently thick Arsenic cap layer, as evident from the RHEED patterns. Al gated MOS capacitors were subsequently fabricated to study the effects of various annealing treatment on the interface and dielectric properties and their dependences on different surface reconstructions. On the (2x4) samples, we performed post dielectric deposition rapid thermal anneal (RTA) at 450 °C for 2 min in N2, and/or post metal deposition RTA at 400 °C for 1 min in N2 followed by an optional forming gas anneal (4% hydrogen and 96% N2) at 350°C for 25 min. The C-V stretch out as well as the frequency dispersion decreased with annealing indicative of the reduction of interface states density and oxide defects generated during deposition. The current-voltage (I-V) measurements also showed a corresponding decrease in the leakage current. Depending on the annealing condition, the leakage current density ranged from 4*10-4 to 1*10-7 A/cm2 at the flat-band condition. The bi-directional C-V hysteresis decreased a little (50 mV) but still remained at around 250 mV after various anneals. In addition, we carried out the same annealing experiments on the c(4x4) and (1x1) samples. Prior to any anneals, there was no observable C-V characteristic from either of these samples. After appropriate annealing treatments, the C-V characteristics of the c(4x4) samples became steeper and were similar to those of the (2x4) samples. Post dielectric deposition RTA at 450 °C on the c(4x4) samples shrank the C-V hysteresis to ~0.1V at the flat-band condition, however, this was accompanied by a substantial frequency dependent flat-band voltage shift compared to the (2x4) samples. Finally, we observed some improvements in the C-V characteristics from the (1x1) samples after the anneals, but the C-V curves were still not clear at low frequency (~10Khz) and the I-V curve exhibited large leakage current, 7x10-4 A/cm2.


H5.32
Abstract Withdrawn


H5.33
Abstract Withdrawn


H5.34
Abstract Withdrawn


H5.35
Formation of Low-leakage-current Ultra-thin SiO2 Films Using Low-temperature Neutral Beam Oxidation Toru Ikoma¹, Seiichi Fukuda¹, Kazuhiko Endo², Heiji Watanabe³ and Seiji Samukawa¹; ¹Institute of Fluid Science, Tohoku University, Sendai, Miyagi, Japan; ²National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki, Japan; ³Graduate School of Engineering, Osaka University, Suita, Osaka, Japan.

Scaling down MOSFETs requires ultra-thin gate dielectric films that are less than 1.5-nm thick. At these thicknesses, it is difficult to use SiO2, a conventional dielectric material, because of high leakage currents. To solve this problem, many scientists have previously studied high-k materials, such as HfO2 and ZrO2, as new gate dielectric materials. It is also important to fabricate a very thin SiO2 underlayer between high-k films and Si substrates and to improve electrical characteristics. At the same time, high-quality thin SiO2 films need to be fabricated at low temperature for the replacement gate process. To fulfill these requirements, we formed an ultra-thin SiO2 film using an oxygen neutral beam at 300^oC. An oxygen neutral beam (<10 eV) was irradiated on a Si substrate, and the substrate was atomically oxidized without any radiation damage, even at 300^oC, lower than the temperature required for thermal oxidation. We believe that the low-energy oxygen neutral beam can be used to form low-temperature, high-quality ultra-thin (<1 nm) SiO2 films for future devices. We formed the SiO2 films using our neutral beam source, which consists of an inductively coupled plasma (ICP) source, a top graphite electrode, a bottom silicon electrode, and a process chamber. The bottom silicon electrode has many apertures. Oxygen ions generated in O2 plasma are neutralized by passing through the Si apertures. Then, oxygen neutral beams are irradiated on a silicon substrate in the process chamber. Since bombarding neutral particles with kinetic energy activates the Si surface, atomic layer oxidation easily progresses even at a low temperature. As a result, it is speculated that the interface structure in NBO film is drastically improved, as compared with that in thermally grown SiO2 film. The p-type Si (100) wafers were used to form the SiO2 films. Native oxide was removed by immersing the wafers in a 0.5% HF solution. The SiO2 films were then formed using neutral beam equipment at 0.14 Pa. The wafers were placed on a heated stage, and their surface temperatures were fixed at 300^oC. Conversely, the thermally grown SiO2 films were formed on the 8-inch-diameter substrate at 850^oC in O2 in the ULSI production line. To measure the electrical characteristics of the NBO films and the thermally grown SiO2 ones, we deposited Al electrodes on them and annealed them at 450^oC in 3% H2 (+N2) for 30 min. We then measured the C-V and I-V characteristics and derived the leakage currents of the films as functions of their equivalent oxide thicknesses (EOTs). The fabricated NBO films were of higher quality and had lower leakage currents than the thermally grown SiO2 ones. We believe this is due to structural differences (e.g., density, interface structure) in NBO and thermally grown SiO2 films.


H5.36
Study of Atomic Layer Deposited Gadolinium Oxide Thin Films on Silicon. Salvador Duenas¹, Helena Castan¹, Hector Garcia¹, Luis Bailon¹, Kaupo Kukli^2,3, Timo Hatanpaa³, Mikko Ritala³ and Markus Leskela³; ¹Electronica, Universidad De Valladolid, Valladolid, Valladolid, Spain; ²University of Tartu, Tartu, Estonia; ³Chemistry, University of Helsinki, Helsinki, Finland.

The progressive scaling of integrated-circuit technologies stimulates intense study of very thin dielectric layers on semiconductors, in order to increase the functionality of microelectronic devices. However, in conventional SiO₂-based technologies, as the effective gate oxide thickness scales towards 1 nm there is excessive leakage current due to direct tunnelling. On account of this limitation, SiO₂ must be replaced with a suitable high dielectric constant (k) material, the higher k allowing a thicker gate dielectric that reduces tunnelling while maintaining the electric fields necessary for controlling the channel current. In the search for proper candidates of alternative dielectrics, the rare-earth (RE) oxides are attractive based on thermodynamic considerations, i.e., RE metals are much more reactive with oxygen than other transition metals, and a high conduction band offset to silicon. In particular, gadolinium oxide Gd₂O₃ is an attractive material among the RE oxides because cubic Gd₂O₃ has one of the closest lattice matches to silicon. Thin films of Gd₂O₃ have been proposed for gate-dielectric applications because its dielectric constant (near 16), as well as its large band gap (5.3 eV), thermodynamic and chemical stability in contact with silicon. The present work deals with the electrical characterization of atomic layer deposited (ALD) gadolinium oxide films on silicon. Samples studied were Al/Gd₂O₃/n-Si/Al and Al/Gd₂O₃/SiO₂/n-Si/Al MOS capacitors. The effect of oxide thickness and thermal treatments on the electronic quality of the films has been studied. Capacitance-voltage (C-V), deep level transient spectroscopy (DLTS), and conductance transient (G-t) techniques provided defect density values. On the other hand, from current-voltage (I-V) and constant-capacitance flat-band transient (VFB - t) measurements, information about current mechanisms in the insulator was obtained. Interfacial state densities as low as 1-2 x 10¹¹ cm^-2eV^-1 have been obtained in 750 °C annealed 8.1 nm-thick films deposited on HF-etched silicon. Current density values of 2 x 10^-5 and 2.5 mA/cm² at electric field values of 0.25 and 1.25 MV/cm, respectively, have been measured in as-deposited 8.5 nm-thick films deposited on SiO₂/Si. The analysis of the recorded dependencies of current density on voltage and temperature allowed us to establish Poole-Frenkel conduction mechanism as dominating at low electric fields, whereas the phonon-assisted tunnelling explains the conduction at high electric fields.


H5.37
Impact of Additives on the Microstructure of Hafnium-based High-k Dielectrics. Richard B Gregory¹, Dina H. Triyoso², Rama I. Hegde², Jamie K. Schaeffer², Peter L. Fejes¹, Stefan Zollner², Z. Jimmy Yu¹ and Xiang-dong Wang¹; ¹Wireless and Packaging Systems Laboratory - Technology Solutions Organization, Freescale Semiconductor, Inc., Tempe, Arizona; ²Austin Silicon Technology Solutions - Technology Solutions Organization, Freescale Semiconductor, Inc., Austin, Texas.

Development of hafnium-based high-k dielectrics has evolved to include a variety of additive elements intended to improve performance of these materials in advanced CMOS platforms. Elements such as Ta, Ti, Si, or Zr are alloyed into pure hafnium dioxide (HfO2), altering the microstructure to overcome inherent deficiencies in its electrical properties. In this paper we report detailed physical characterization on the impact of Ta, Ti, Si and Zr on the microstructure of hafnium-based high-k dielectrics deposited using atomic layer deposition (ALD). Auger electron spectroscopy (AES), RBS, XRD, AFM, and TEM are used to investigate microstructural changes that occur in HfO2 as a result of these various additives. The analytical approach used typically starts with simpler spectroscopic methods such as RBS and XRD, then followed up with AFM, AES, and, if needed, TEM. Among the results to be presented are those highlighted as follows. AES analysis of HfTaOx shows that an upward trend in Ta:Hf ratio for ALD material correlates to increased k value. XRD of HfTaOx indicates crystallization following a 1000°C source/drain anneal to a mixture of tetragonal HfTaOx and monoclinic HfO2. A more promising system that uses Ti as the additive is more easily evaluated for content by RBS, which shows that ALD HfTiOx produced with a 2:1 Hf:Ti cycle ratio has 45% TiO2 and 55% HfO2. XRD analysis of the entire Hf:Ti cycle series shows that following simulated source/drain anneals, films approaching 45% TiO2 content show diffraction peaks corresponding to the orthorhombic HfTiO4 phase. However, some discussion has suggested that the XRD data alternatively show peaks for doubled tetragonal HfO2. Films with lower TiO2 content (12%) form the monoclinic HfO2 phase with smaller lattice constant due to some alloying with Ti. Surface roughness measured with AFM decreases as TiO2 content increases. A similar analytical approach is used to physically characterize the HfxZr1-xO2 system. RBS shows composition for ALD HfxZr1-xO2 measuring close to targeted values and remaining stable after a 1000°C anneal. XRD analysis of the ALD series indicates mixed tetragonal and monoclinic phases, with the desired tetragonal phase becoming more stabilized as the ratio of ZrO2:HfO2 is increased. In conclusion, detailed physical characterization reveals significant microstructural changes that occur in HfO2 by the addition of Ti, Ta, Si and Zr. These microstructure modifications result in better device performance.


SESSION H6: Complex and Crystalline Oxides
Chairs: E. Garfunkel and C. Musgrave
Thursday Morning, April 12, 2007
Room 3007 (Moscone West)
8:30 AM *H6.1
Atomic Scale Characterization of Complex Oxides on Silicon. David A. Muller¹, Lena Fitting Kourkoutis¹, C. Stephen Hellberg², V. Vaithyanathan³, Darrell G. Schlom³ and K. E. Andersen²; ¹School of Applied and EngineeringPhysics, Cornell University, Ithaca, New York; ²Center for Computational Materials Science, Naval Research Laboratory, Washington, District of Columbia; ³Dept. of Materials Science and Engineering, Penn State University, State College, Pennsylvania.

Perovskite oxides exhibit a wide range of electronic and magnetic properties with potential device applications. In particular, SrTiO3 could be used as a ferroelectric or buffer layer for the growth of more exotic perovskite oxide heterostructures on Si. This opens up possibilities for the incorporation of novel materials into existing Si-based technology. While the SrTiO₃/Si interface structure has been studied extensively, most experimental techniques rely on averaging and hamper the determination of the local interface structure. Scanning transmission electron microscopy (STEM) is a powerful technique for imaging buried structures, such as thin films and isolated vacancies in a crystal. Here, clear imaging of buried SrTiO₃ layers as thin as a single monolayer can be achieved in plan view STEM by exploiting electron channeling or in cross-section to allow atomic-scale measurements of interface electronic structure. We apply these methods to study how polarization, compensating interface charges and strain affect the growth, islanding and defects in thin epitaxial films. . This work was supported under the ONR EMMA MURI monitored by Colin Wood and by the Cornell NSF-MRSEC.


9:00 AM H6.2
Preparation and Characterization of MOSFETs with Gadolinium Scandate as Alternative Gate Dielectric. Martin Roeckerath, Joachim Knoch, Tassilo Heeg, Juergen Schubert and Siegfried Mantl; Institute of Bio- and Nanosystems (IBN 1), Research Centre Juelich, Juelich, NRW, Germany.

Rare earth scandates are a promising class of materials as alternative high-k gate dielectrics for future CMOS applications due to their promising morphological and electrical properties (D. G. Schlom et. al., MRS Bull. 27, 198 (2002)). In particular, gadolinium scandate has recently attracted an increasing attention since it exhibits a high thermal stability, a favorable k-value of ~23 and is in contrast to other rare earth oxides not hygroscopic. Furthermore, high quality GdScO₃ films were recently demonstrated employing atomic layer deposition, hence enabling in principle an introduction of this material into large scale industrial processes (K. H. Kim et. al., Appl. Phys. Lett. 89, 133512 (2006)). However, the integration of a rare earth scandate into a field effect transistor device has not been demonstrated yet. In this work long channel metal-oxide-semiconductor field-effect transistors (MOSFETs) on bulk-silicon have been prepared and investigated integrating gadolinium scandate as high-k gate dielectric in a gate first process. In particular, the investigation was focused on the impact of the high-k dielectric/silicon interface on the electrical characteristics. In order to do so it is necessary to be able to realize different interface conditions which in turn requires a SiOx-free deposition of the high-k dielectric. Therefore, the GdScO₃ films were deposited by electron beam evaporation from a stoichiometric ceramic target in high vacuum conditions in a conventional e-gun system (Leybold Univex 450). Recently, we demonstrated (M. Wagner et. al., Appl. Phys. Lett. 88, 172901 (2006)) that this deposition method allows to fabricate a SiOx-free interface between the high-k and the silicon. To vary the interface condition different preparations of the silicon substrates prior to the deposition and different post deposition treatments were applied. To be specific, a chemical silicon oxide or HF last surface on (100) silicon was used as the starting surface, respectively. Some of the samples were annealed in oxygen atmosphere after high-k deposition. Rutherford backscattering spectrometry (RBS) and X-ray reflectometry (XRR) were employed to investigate and verify the chemical composition as well as the thickness of the high-k film. Readily fabricated devices were electrically characterized by DC-measurements using an HP 4155B semiconductor parameter analyzer. The measurements reveal a significant influence of the oxygen annealing on both the on-state and off-state currents of the devices depending on the substrate preparation indicating a modification of the high-k dielectric/silicon interface due to the post-deposition oxygen treatment. A significant threshold voltage shift is observed which is likely to be associated with a compensation of oxygen vacancies in the high-k dielectric film. Furthermore, the influence of the interface condition on the charge carrier mobility will be discussed.


9:15 AM H6.3
Surprises in the Growth of SrTiO3 on Silicon: A Charged Interface and Polar Film. C. Stephen Hellberg¹, Kristopher E. Andersen¹, Joseph C. Woicik², P. Ryan³, Hao Li⁴, Lena Fitting⁵, David A. Muller⁵, V. Vaithyanathan⁶ and Darrell G. Schlom⁶; ¹Naval Research Lab, Washington, District of Columbia; ²NIST, Gaithersburg, Maryland; ³Ames Laboratory, Ames, Iowa; ⁴Motorola Labs, Tempe, Arizona; ⁵Cornell University, Ithaca, New York; ⁶Pennsylvania State University, University Park, Pennsylvania.

There has been great interest in growth of complex oxides on silicon for device applications. SrTiO3 has served as the prototypical system, but initial optimism has faded somewhat as well ordered epitaxial films have been difficult to achieve. Recently there have been several developments that have dramatically improved our understanding of these systems. Growth of coherent lattice-matched films has finally been achieved, and the measured expansion of the out-of-plane lattice constant exceeds the prediction of the bulk elastic constants of SrTiO3 by nearly 100%. Simultaneously, growth by a different process in thermodynamic equilibrium yields islands of SrTiO3. I will present first principles density functional calculations consistent with both experiments: The favored interface is electrically charged, and the film grows ferroelectrically polarized, with an accompanying out-of-plane expansion. Additionally, the calculations show the films are unstable to phase separation. Possible methods of substitutionally doping the interface to eliminate the charge are discussed.


9:30 AM H6.4
Interface Control in High-k stacks on Semiconductors Grown by Molecular Beam Epitaxy. Chiara Marchiori¹, Daniele Caimi¹, Roland Germann¹, Jean-Pierre Locquet¹, Bogdan Mereu¹, Christophe Rossel¹, Maryline Sousa¹, Axelle Tapponnier¹, Dave Webb¹, Maria Seo² and Jean Fompeyrine¹; ¹IBM Research Lab Zurich, Rueschlikon, Switzerland; ²IPMC, Ecole Polytechnique Fédérale de Lausanne, Ecublens, Switzerland.

Molecular beam epitaxy is a powerful technique for the deposition of high-k oxides on different semiconductor substrates. Its full capabilities can however be exploited only through a deep understanding of the oxide/semiconductor interface, as monitored in real time by reflection high energy electron diffraction (RHEED), or ex-situ by x-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM). First, we show that the possibility to work in UHV and to strictly control the amount of reactants provided to the surface -including oxidant species such as O2 or atomic O- are key factors in determining interface composition. XPS shows for instance that upon deposition of metallic Hf in low pO2 directly on a 2x1 Si surface, Hf-Si and SiOx readily form. Two alternative interface layers (IL) may be used in order to avoid Hf penetration into the Si substrate and silicide formation. Ultrathin layers of amorphous SiO2 can be prepared via RHEED-controlled, in-situ oxidation of the clean Si substrates by atomic O. Otherwise 2 monolayers (ML) of SrO can be deposited epitaxially on Si, following a layering sequence which minimizes Si-O bond formation (< 0.8ML of interfacial O). In this case, SiOx may grow during the subsequent HfO2 deposition at higher pO2, as product of the diffusion through the HfO2 and SrO layer. However, a careful process optimization based on RHEED and XPS allows HfO2 to be deposited without any additional SiOx formation on the preserved epitaxial SrO/Si interface and nevertheless to be completely oxidized. Electrical properties are strongly influenced by the interface composition. HfO2/HfSi-SiOx/Si capacitors are characterized by unacceptably high leakage current, > 1 A/cm2, probably due to the presence of HfSi filaments. On the other hand, due to the absence of any SiOx and the larger SrO dielectric constant (13,4), record EOT values, below 0.6 nm, and low leakage currents are obtained for 22A HfO2/2ML SrO/Si capacitors. However, the electron mobility in n-FET is rather low (50-60 cm2/Vs). As expected when the SiOx grows thicker at the interface the mobility can reach the high expected value for SiO2/Si transistor but at the cost of higher EOT. The deposition of epitaxial perovskites on Si is also discussed. We demonstrate that an additional key factor in determining the final interface composition is the thermal budget required to crystallize the amorphous layers. Indeed, amorphous SrTiO3 and SrHfO3 can be deposited on epitaxial BaxSr1-xO and SrO, respectively, without any SiOx formation. However, XPS data show that perovskite crystallization at 500-600 C in UHV leads to substrate oxidation and to a complete rearrangement of the initial epitaxial BSO and SrO interlayers.


9:45 AM *H6.5
Theory of Nonlinear Dielectric Response of Perovskite Superlattices and Interfaces. David Vanderbilt, Physics and Astronomy, Rutgers University, Piscataway, New Jersey.

At present there are strong motivations for developing improved first-principles methods to describe the nonlinear dielectric properties of dielectric and/or ferroelectric ultrathin films and superlattices. I will review some recent developments along these lines. In particular, I will discuss how it is possible to compute the total polarization of a given superlattice as a function of electric field or displacement field, how to extract layer-resolved polarizations using Wannier-based methods, and how this allows for the isolation of interface contributions. I will also show how such an analysis can be used to construct a first-principles-based model of the nonlinear dielectric (and piezoelectric) properties of a superlattice of arbitrary sequence. Although perovskite oxide superlattices will serve as the example systems in this talk, the methods should be applicable more generally.


10:30 AM *H6.6
Growth and Characterization of Epitaxial La_xLu_2-xO₃ Films on (111) Si. Darrell G Schlom¹, Wei Tian¹, Lisa F. Edge¹, D. O. Klenov², S. Stemmer², J. G. Wang³, M. J. Kim³, V. V. Afanas'ev⁴, S. Stesmans⁴, S. Shamuilia⁴, B. Hollaender⁵, J. Schubert⁵, M. E. Hawley⁶, S. Rivillon⁷ and Y. J. Chabal⁷; ¹Department of Materials Science and Engineering, Penn State University, University Park, Pennsylvania; ²Materials Department, University of California, Santa Barbara, California; ³Department of Electrical Engineering, University of Texas at Dallas, Richardson, Texas; ⁴Department of Physics, University of Leuven, Celestijnenlaan, Belgium; ⁵Institute of Thin Films and Interfaces and Center of Nanoelectronic Systems for Information Technology, Research Centre Jülich, Jülich, Germany; ⁶Materials Science & Technology Division, Los Alamos National Laboratory, Los Alamos, New Mexico; ⁷Departments of Chemistry and Chemical Biology,, Biomedical Engineering and Physics, Rutgers University, Piscataway, New Jersey.

Opportunities for alternative gate dielectrics in CMOS technologies include MOSFETs and FLASH. Among many criteria for choosing satisfactory alternative gate dielectrics are relatively high dielectric constant (high-K), thermodynamic stability in contact with Si and sufficient valence and conduction band offsets with respect to Si. Several of the rare-earth oxides possess these properties and grow epitaxially on (111) Si. In this work we have investigated the epitaxial growth of rare-earth oxides containing either empty (La₂O₃) or full (Lu₂O₃) f-shells, including solid solutions of these rare earth oxides: La_xLu_2-xO₃. The La_xLu_2-xO₃ thin films were grown on (111) Si using molecular-beam epitaxy to explore their applications for alternative high-K gate dielectrics. In addition to changing the electrical properties, solid solutions between these two end member binary oxides offer the opportunity to alter the crystal structure and lattice match with Si. In bulk, La₂O₃ is typically hexagonal, while Lu₂O₃ is typically cubic with the bixbyite structure. The polymorph, structural quality, epitaxial orientation relationships with respect to the Si substrate, and the interfaces were characterized by four-circle x-ray diffraction and transmission electron microscopy. Epitaxial La_xLu_2-xO₃ films with the bixbyite structure were grown on the (111) surface of Si with two orientation relationships: (111)[1-10]La_xLu_2-xO₃ || (111)[-110]Si (B-type) and (111)[1-10]La_xLu_2-xO₃ || (111)[1-10]Si (A-type). The presence of growth twins is a concern for alternative gate dielectric applications as the twin boundaries could lead to charge trapping. By controlling the surface roughness of the substrates, it was found possible to make the films nearly pure B-type growth variant (the volume fraction of the A-type growth variant was reduced to less than 0.3%). The full width at half maximum of the rocking curve of the 222 peak of the La_xLu_2-xO₃/Si films are as narrow as 0.0025° (9 arc sec), indicating a high degree of structural perfection. At higher x, La_xLu_2-xO₃ grows epitaxially on the (111) surface of silicon with a hexagonal structure and two orientations of (0001)[10-10] La_xLu_2-xO₃ || (111)[11-2]Si and (0001)[10-10]La_xLu_2-xO₃ || (111)[1-10]Si. High-resolution transmission electron microscopy and scanning transmission electron microscopy reveal abrupt and SiO₂-free interfaces between the oxide films and the Si substrates. The band alignments of epitaxial Lu₂O₃ (x=0) and LaLuO₃ (x=1) with respect to silicon were measured by internal photoemission and photoconductivity measurements. Epitaxial Lu₂O₃ and LaLuO₃ thin films were found to have conduction band offsets of 1.8 and 2.0 eV, respectively; the valence band offsets were measured to be 2.2 eV and 2.3 eV, respectively. These values are sufficiently large to suppress electron and hole tunneling and meet the criteria of the International Technology Roadmap for Semiconductors for silicon-based MOSFETs.


11:00 AM H6.7
Structual and Electrical Properties of Crystalline LaAlO₃ on Silicon (001) James W. Reiner¹, Agham Posadas¹, Miaomiao Wang², Tso-Ping Ma² and Charles Ahn¹; ¹Applied Physics, Yale University, New Haven, Connecticut; ²Electrical Engineering, Yale University, New Haven, Connecticut.

We have grown epitaxial LaAlO₃ (LAO) on silicon (001) surfaces by oxide molecular beam epitaxy using a 2 monolayer SrTiO₃ buffer layer. LAO is a promising gate oxide candidate for integration into future generations of silicon technology because of its relatively large dielectric constant (24) and band gap (5.5 eV). The structure of the epitaxial LAO films has been characterized by reflection high energy electron diffraction during and after growth, x-ray diffraction, and transmission electron microscopy (TEM). All of these techniques reveal a highly crystalline, epitaxial LAO/Si heterostructure. Cross-sectional TEM of samples shows no SiO₂ at the complex oxide-silicon interface. I-V and C-V measurements have been performed on MOS capacitor structures to characterize the leakage current and interface trap density. Samples have also been studied by inelastic electron tunneling spectroscopy, the results of which indicate an absence of SiO₂ at the complex oxide-silicon interface.


11:15 AM H6.8
Amorphous Lanthanum Lutetium oxide Thin Films as an Alternative High-κ gate Dielectric. Joao Marcelo Lopes¹, Martin Roeckerath¹, Tassilo Heeg¹, Jurgen Schubert¹, Uffe Littmark¹, Siegfried Mantl¹, Valeri V. Afanas'ev², Sheron Shamuilia², Andre Stesmans², Y. Jia³ and Darrel Schlom³; ¹Institute for Bio- und Nanosystems, Forschungszentrum Juelich GmbH, Juelich, Germany; ²Department of Physics, University of Leuven, Leuven, Belgium; ³Department of Materials Science and Engineering, Pennsylvania State University, Pennsylvania, Pennsylvania.

A large number of alternative materials is in discussion to replace SiO₂-based films as the gate dielectric in future MOSFET nanodevices. Ternary rare earth oxides are promising candidates and lanthanum lutetium oxide, as a member of this class of material, is predicted to have similar properties.¹ In this contribution we report results on LaLuO₃ thin films deposited on (100) Si substrates. The films were grown by pulsed laser deposition using a stoichiometric ceramic target. Rutherford backscattering spectrometry, transmission electron microscopy, atomic force microscopy, X-ray diffraction and X-ray reflectometry were employed to structurally investigate the samples. The results indicate the growth of stoichiometric, amorphous, and smooth LaLuO₃ films showing thermal stability up to 1000 °C. Internal photoemission and photoconductivity measurements show a band gap width of 5.2 ± 0.1 eV and symmetrical conduction and valence band offsets of 2.1 eV at the Si/high-κ interface. The electrical characterization also reveal promising results. C-V curves with small hysteresis and free of humps and irregularities were achieved, while I-V measurements indicate low leakage current density levels (60 μA/cm² for a 6 nm thick film). Additionally, a κ value of 32 was derived from a CET (capacitance equivalent thickness) plot. ¹ D.G. Schlom and J.H. Haeni, MRS Bull. 27, 198 (2002).


11:30 AM H6.9
Defects in La and Hf Gate Oxides. Koon-yiu Tse, Dameng Liu, Ka Xiong and John Robertson; Engineering, Cambridge University, Cambridge, United Kingdom.

HfO2 is presently the most researched high dielectric constant oxide to be used as a gate oxide in future CMOS devices. La2O3 and other lanthanides have a higher conduction band offset and lower leakage currents, but have generally been viewed with less interest because of their greater affinity for water. However, the largest unresolved problem for high K oxides is the inability to shift the Fermi level of metal gate electrodes to the band edge energies of Si. A number of groups have found that La-based oxide systems can resolve this problem [1-3], and so a detailed understanding of the electronic structure and defects is of great interest. Here we present the electronic structure of the bulk and the defects of La2O3 and La2Hf2O7, and compare it to HfO2. La2Hf2O7 is of interest as it has the pyrochlore structure, with 2 different oxygen sites, one (O1) surrounded only by La’s and the other (O2) by La and Hf, We find that an O vacancy at the O1 site (V1) has an unusual feature of its electron states being localised not on the nearest neighbor La sites, but on the next neighbor Hf sites. This is despite the vacancy wavefunction normally being localised within the vacancy. This feature allows the possibility of charge transfer and interface dipoles to be built up by vacancies, which could be a factor in the observed work function shifts. 1. X P Wang, et al, IEEE ED Letts 27 31 (2006) 2. V Narayanan, et al, VLSI symp (2006) 3. K Ohmori et al, SSDM (2006)


SESSION H7: High-k/Semiconductor Interfaces II, SiC, Electrical Characterization
Chairs: Dina Triyoso and Glen Wilk
Thursday Afternoon, April 12, 2007
Room 3007 (Moscone West)
1:30 PM *H7.1
Compositional and Band Alignment Characterization in CMOS Gate Stacks. L. Goncharova, S. Rangan, E. Bersch, O. Celik, T. Feng, S. Sayan, C. L. Hsueh, Y. Chabal, T. Gustafsson, R. Bartynski and E. Garfunkel; Rutgers University, Piscataway, New Jersey.

The properties of alternative dielectrics, metal electrodes and semiconductors are under intense scrutiny because of their potential to increase performance of nanoscale CMOS devices. To enable the rational selection of these new components, the ultrathin film and interface properties of adjoining materials must be understood at the atomic scale. There remain a variety of issues whose elucidation would greatly facilitate the integration of novel materials and structures. We will present selected results on structural, compositional, electrical, electronic band alignment and thermal stability properties of several classes of alternative (post-Si) materials. In the first part of the presentation we will review results primarily from medium energy ion scattering a high-resolution, low energy version of Rutherford backscattering. We will discuss the behavior of amorphous and polycrystalline films of materials such as HfO2, ZrO2, Y2O3, etc. We will present data on their thermal stability and their reactivity with adjoining semiconducting channel materials. We will next present isotopic labeling results to explore how oxygen reacts with and exchanges in the films, as oxygen chemistry appears critical to understanding defects in these systems. The third set of systems that we will discuss are metals electrodes deposited on dielectrics, focusing on their ability to add or remove oxygen from the dielectric layer(s). Finally, the stability of dielectrics on alternative channel materials (Ge and GaAs) will be presented. Proper band alignment at individual interfaces as well as across multilayer stacks is needed ensure proper device performance, including low leakage currents and appropriate threshold voltages. An understanding of the relevant energies, particularly the role played by interface dipoles, may enable the tuning of band offsets and effective work functions at interfaces. Band offset and DOS results of studies using direct, inverse and internal photoemission will be presented for a series of structures comprised of different metals (Ru, Al, Ti, Ni), dielectrics (HfO2, SiO2 and HfxSi1-xO2) and semiconductors (Si, Ge and GaAs). The band offsets we measure for the metal/oxide and oxide/semiconductor interfaces are, to first order, in agreement with a modified Schottky-Mott model. But as expected, the results reveal more complicated interfaces, and in particular strong chemical effects after metal deposition. Both Ru and Al induce an energy shift of the core, valence and conduction band levels of an adjoining material: Ru stays metallic upon deposition on the oxide, whereas interfacial Al is shown to become oxidized. NSF, SRC and MURI support are gratefully acknowledged. We also thank Sematech and several SRC member companies for very helpful collaborations.


2:00 PM H7.2
Characteristics of Hafnium-based Gate Dielectrics Depending on the Silicon Content. Sanghyun Woo, Seokhoon Kim, Hyungseok Hong, Hyungchul Kim and Hyeongtag Jeon; Materials Science and Engineering, Hanyang University, Seoul, South Korea.

High-k gate dielectrics have been widely studied for replacing conventional Silicon Oxynitride (SiON) gate dielectrics. Among the candidates of the high-k gate materials, hafnium oxide (HfO₂) and hafnium silicate (HfSi_xO_y) have been extensively studied due to their relatively larger band gap, reasonable permittivity and quite good thermal stability. In recent study, atomic layer deposition (ALD) is being studied for deposition method for high-k materials. However, several problems of conventional ALD such as high particle generation and corrosion of gas delivery lines were introduced. To solve these problems, remote plasma atomic layer deposition (RPALD) method was used for depositing HfO₂ and HfSi_xO_y films in this work. Rapid thermal annealing (RTA) was performed for all samples at 800°C for 30sec. To compare reliability of Hf-based high-k materials, time-dependent dielectric breakdown (TDDB) of HfO₂ and HfSixOy thin film has been investigated using metal-oxide-semiconductor (MOS) capacitors with platinum (Pt) electrodes. The TDDB of MOS capacitors were measured under -3.5V constant voltage stress (CVS) at room temperature. The TDDB lifetime for HfSi_xO_y samples were found to be longer than that for HfO₂ samples. This is believed to be due to the crystallization of dielectrics or decreased defects. High-resolution transmission electron microscopy (HRTEM) and X-ray diffractometry (XRD) shows that HfO₂ film is completely crystallized at 800°C. On the other hand, HfSi_xO_y remained amorphous at 800°C. Moreover, the crystallization temperature of dielectrics increased as the content of silicon atom in HfSi_xO_y thin films increased. Thus, these results suggest that the defect density can be effected by silicon atoms of HfSi_xO_y thin films.


2:15 PM H7.3
Roles of Oxygen and Water Vapor in the Oxidation of Halogen and Hydrogen Terminated Ge(111) Surfaces. Shiyu Sun^1,2, Yun Sun², Zhi Liu² and Piero Pianetta²; ¹Physics, Stanford University, Palo Alto, California; ²Stanford Synchrotron Radiation Laboratory, Menlo Park, California.

Germanium (Ge) has emerged as a promising material for high-performance devices due to its high intrinsic electron and hole mobilities. To fabricate devices on Ge, it is essential to clean and passivate its surface effectively. Although clean Ge surfaces can be achieved by wet chemical etching, the hydrogen and halogen passivation layers formed during etching are not stable in the air. Therefore, it is crucial to understand the mechanism of the initial oxidation of the treated Ge surfaces in the air. Since Ge(111) surfaces are structurally simple, Ge(111) surface can serve as a model system to investigate the oxidation mechanism, and help to understand the Ge(100) surface, which is technologically more important. In this work, we study the initial stage of the oxidation of Ge(111) surfaces treated by HF, HCl and HBr solutions using synchrotron radiation photoelectron spectroscopy (SR-PES) at Stanford Synchrotron Radiation Laboratory (SSRL). It is well known that the oxidation in the air is complicated, since oxygen, water vapor, trace oxidants such as ozone etc. and illumination conditions can all affect the oxidation process. Therefore, controlled experiments are performed to differentiate the effects of different oxidation factors. Experimental results show that water vapor and oxygen play different roles in oxidation. For Cl and Br terminated surfaces, water vapor effectively replaces the termination layers with the hydroxyl group (OH), but does not oxidize the surfaces further in dark conditions. In contrast, little oxidation is observed with dry oxygen alone, but with the help of water vapor, oxygen oxidizes the surface by breaking the Ge-Ge back bonds instead of changing the termination layer. For H terminated surfaces, water vapor behaves the same, but surface undergoes significant oxidation with dry oxygen dosing in dark conditions. The stability difference between halogen terminated surfaces and hydrogen terminated surfaces will be discussed. In addition, the effects of other oxidation factors such as the trace oxidant species in room air and the UV components of room light will be addressed.


2:30 PM H7.4
In-situ Infrared Absorption Monitoring of Atomic Layer Deposition of Metal Oxides on Functionalized Si and Ge Surfaces. Min Dai^2,1, Ming-Tsung Ho^2,1, Yu Wang^1,2, Sandrine Rivillon^3,1, Meng Li^2,1, Jinhee Kwon² and Yves Jean Chabal^1,3,2; ¹Laboratory for Surface Modification, Rutgers University, Piscataway, New Jersey; ²Department of Physics, Rutgers University, Piscataway, New Jersey; ³Department of Chemistry and Chemical Biology, Rutgers University, Piscataway, New Jersey.

The nature of the interface between Si and Ge substrates and high-k dielectrics often controls the performance of MOSFET devices. Precleaning and/or chemical functionalization of the surfaces can dramatically affect the formation of an interfacial layer. We have used in-situ IR spectroscopy to probe the relevant interfaces during ALD growth for a variety of surface treatments, including H- and Cl- termination, nitridation, and organic functionalization. This talk with focus on understanding the mechanisms for interfacial SiO2 (or GeOx) formation during HfO2 growth using mostly tetrakis-ethylmethylamidohafnium (TEMAH) as the metal precursor and water or ozone as the oxygen precursor. We find that impurities arising from incomplete ligand elimination during growth (e.g. OH for H2O processing and CO- and NO-containing species for O3 processing) are incorporated into the HfO2 film during growth. Upon annealing, most of these species react, but can also migrate to the interface. Nitridation and alkylation of Si and Ge surfaces will in general prevent SiO2 or GeOx formation but can also affect the growth rate.


2:45 PM H7.5
X-Ray Reflectometry Determination of Structural Information from Atomic Layer Deposition, Nanometer-scale, Hafnium Oxide Thin Films. Donald Windover¹, Nicholas Armstrong^1,2 and James P Cline¹; ¹Ceramics Division, NIST, Gaithersburg, Maryland; ²Department of Physics and Advanced Materials, UTS, Sydney, New South Wales, Australia.

Atomic Layer Deposition (ALD), hafnium oxide thin films illustrate the promising class of high-k candidate materials currently in development to replace the traditional gate oxide in the CMOS process. The clear device performance enhancement offered by these materials demands detailed deposition process optimization, lateral homogeneity studies, and film stability studies as first steps toward novel gate material adoption. Nanometer-scale film deposition optimization and stability studies present new challenges to the characterization community, because they require unprecedented accuracy in measuring structural information (eg., thickness, material density, surface and interface roughness). X-Ray Reflectometry (XRR) characterization provides theoretical, first-principles determination of thickness information and electron density gradient profiles for nanometer-to-micron-scale, smooth, high electron density contrast materials, such as hafnium compounds deposited on silicon. Both XRR data collection and inverse problem-laden analysis methods need standardization to achieve superlative accuracy in structure characterization. We present structural information from a series of hafnium oxide thin films, with 10 to 65 ALD deposition cycles, on silicon. The XRR structural information determination approach used is currently being studied at the National Institute of Standards and Technology (NIST) as part of developing a Standard Reference Material (SRM) for the calibration of commercial XRR instruments. The potential time stability and high electron density contrast ratio of hafnium oxide makes it of interest to NIST as a candidate material for a future XRR standard. Multiple structural models are tested for each XRR measurement and compared using Bayesian methods for determining the relative plausibility of the models. This structural determination approach eliminates bias caused by assuming a specific structural model for a sample prior to data analysis. Self-consistent structural information is filtered for the hafnium oxide film series and this information is used in deposition profiling for the ALD system. We conclude by discussing the limitations of the XRR method as applied in other nanometer-scale high-k gate material analyses.


3:30 PM H7.6
Atomic-scale Characterization of HF-treated 4H-SiC(0001)1×1 Surfaces by Scanning Tunneling Microscopy. Kenta Arima¹, Hideyuki Hara¹, Keita Yagi², Ryota Okamoto², Hidekazu Mimura¹, Akihisa Kubota³ and Kazuto Yamauchi¹; ¹Department of Precision Science and Technology, Osaka University, Suita, Osaka, Japan; ²Research Center for Ultra-Precision Science and Technology, Osaka University, Suita, Osaka, Japan; ³Department of Mechanical Engineering and Materials Science, Kumamoto University, Kumamoto, Kumamoto, Japan.

The purpose of this study is to elucidate passivated structures of 4H-SiC(0001) surfaces on the atomic scale after HF dipping. Hexagonal silicon carbide (4H-SiC(0001)) is a promising wide band gap semiconductor for electronic devices operated under extreme conditions, such as high power and high temperature. A preparation of clean, flat and well-ordered 4H-SiC(0001) surfaces is important for the fabrication of SiC-based devices with high performance. There are numerous attempts to remove native oxides and passivate hexagonal (4H or 6H) SiC(0001) surfaces by wet-chemical preparations. For Si surfaces, an HF treatment is a standard procedure to remove native oxides and terminate the surface with H atoms. Previous studies for SiC surfaces have pointed out that the HF dip removes silicate adlayers. However, it does not yield a perfect H-termination, and HF-treated SiC(0001) surfaces involve a considerable amount of oxygen as OH groups with varying amounts of excess carbon in the form of hydrocarbons and fluorine. But previous reports by spectroscopic methods such as AES and dynamical LEED merely provide information about average structural information of the surface. We investigate HF-treated 4H-SiC(0001) surfaces on the atomic scale by scanning tunneling microscopy (STM). In this study, on-axis n-type 4H-SiC(0001) wafers (0.02-0.03 Ωcm) were used. We removed disordered surface layers and flattened the 4H-SiC(0001) surface by an abrasive-free planarization method in HF solutions using a catalytic polishing pad made of Pt. After the planarization process, the SiC sample was wet-chemically treated as follows. The sample was first dipped into a solution of (sulfuric acid): (hydrogen peroxide)=4:1 for 10 min and subsequently rinsed with ultrapure water for 10 min. Then, it was dipped into a concentrated HF solution (50 wt. %) for 10 min, followed by a rinse with water for 1 min. Finally, the sample was blown dry with pure nitrogen gas. Atomic force microscopy observations revealed that the surface is composed of alternating wide and narrow terraces with single bilayer-height steps, and the mechanism is discussed based on the difference of lateral-etching rates in solutions between adjacent terraces. STM images show that a terrace is composed of bright dots regularly distributed along the [(-1)2(-1)0], [11(-2)0] and [2(-1)(-1)0] directions. The distance between neighboring bright dots is equal to 0.30-0.33 nm along the three directions. The crystallographic distance between neighboring outermost Si atoms on an unreconstructed 4H-SiC(0001) surface is 0.308 nm, which indicates that a 1×1 structure is formed on the HF-treated 4H-SiC(0001) surface. XPS and AES measurements demonstrate that the 1×1 phase represents OH-terminated Si atoms with a small amount of F-terminated Si atoms. We suggest that the OH- (or F-) termination of 4H-SiC(0001) surfaces by HF dipping is derived from the polarization of the underlying Si-C bonds.


3:45 PM H7.7
Investigation of 4H-SiC MIS Devices with AlON/SiO₂ Layered Structures. Makoto Harada, Yu Watanabe, Shgenari Okada, Takayoshi Shimura, Kiyoshi Yasutake and Heiji Watanabe; Osaka University, Suita-shi, Osaka, Japan.

Silicon carbide (SiC) is a promising semiconductor material for high-power and high-temperature devices because of its wide band gap, high breakdown field, and high thermal conductivity. It can also be oxidized to grow the SiO₂ insulator for fabrication of metal-insulator-semiconductor (MIS) structures. However, the major limiting factor in power electronic application is the poor characteristics of thermally grown oxides, especially for thick SiO₂ (50-100 nm) on SiC substrates. Recently, high-permittivity metal oxides (high-k gate dielectrics) have gained considerable attention as alternative gate dielectrics for advanced Si devices. Although excellent electrical properties have been reported for Hf-based high-k dielectrics, alternative high-k insulators with a wider band gap and superior thermal stability are required for SiC applications. Aluminum oxides (Al₂O₃) are candidate materials for SiC-MIS devices, but they have been reported to have a lot of negative fixed charges. In this study, we propose high-quality SiC-MIS devices with layered structures of aluminum oxynitrides and thin SiO₂ underlayers, in which the negative fixed charges of Al₂O₃ films are terminated by incorporation of nitrogen [1] and the interface property at SiO₂/SiC is improved by using thin SiO₂ layers. MIS capacitors were fabricated on Si-faced 4H-SiC(0001) wafers with n-type epitaxial layers. AlON insulators were deposited on thermally grown thin SiO₂ (less than 20 nm thick) by reactive sputtering using a N₂/O₂ gas mixture, and then, high-temperature post-deposition annealing was carried out to improve electrical properties. Our physical characterization showed that the nitrogen content of the typical AlON films was 14% and that its energy band gap was 6.9eV. We found that the amount of residual carbon within the SiO₂ layer and SiO₂/SiC interface increased as the oxide thickness increased, which suggests both thermal desorption of carbon oxides through the growing SiO₂ layer and use of thin SiO₂ underlayers. Capacitance-voltage measurement revealed that nitrogen incorporation into Al₂O₃ dramatically reduced the negative fixed charge by one order of magnitude and hysteresis by less than 20 mV. We also demonstrated that the SiC-MIS devices have a high breakdown field of over 15 MV/cm. Advantages of the AlON/SiO₂/SiC layered structure are discussed in detail. [1] K. Manabe et al., IEICE TRANS. ELECTRON, E87-C (2004) 30.


4:00 PM H7.8
Impact of Interfacial Nitridation of HfO2 High-k Gate Dielectric Stack on 4H-SiC Rajat Mahapatra¹, Amit K Chakraborty², Bing Miao¹, Alton B Horsfall¹, Sanatan Chattopadhyay¹, Nick G Wright¹ and Karl S Coleman²; ¹School of Electrical, Electronic and Computer Engineering, Newcastle University, Newcastle, United Kingdom; ²Department of Chemistry, University of Durham, Durham, United Kingdom.

Silicon carbide (SiC) is a potential semiconductor for high temperature, high-power and high-frequency devices because of its wide band gap, high breakdown field and high saturation velocity. The ability to grow thermal oxides on SiC also gives it significant advantages over other compound semiconductors. However, the low dielectric constant of SiO2, fundamentally restricts the maximum allowable electric field in SiC devices. Therefore, the application of high-k materials, such as HfO2, will reduce the field strength within the dielectric itself and thus allowing better exploitation of the properties of SiC. Still several challenges such as low band offset at the high-k/SiC interface limits its potential applications in SiC-based metal-insulator-semiconductor (MIS) devices. The deliberate incorporation of an oxide or oxynitride interfacial layer between SiC and high-k gate dielectrics attracts great attention because it allows the increase in band offsets at the high-k/SiC interfaces and an improvement of interface quality. In this regard, we have investigated the effect of interfacial nitridation of HfO2 high-k gate dielectric stacks on 4H-SiC. The high-k gate dielectric stacks on SiC were fabricated by thermally growing an initial oxide/oxynitride layer, followed by e-beam evaporation of hafnium and its subsequent oxidation. The X-ray photoelectron spectroscopy study of the HfO2/oxynitride/SiC gate stack confirms the formation of stoichiometric HfO2 film. No undesired hafnium-silicide formation is observed at the surface as well as in the interfacial layers. It is interesting to note that there is no significant amounts of carbon pile up at the interface. Electrical properties of the dielectric stacks have been studied using capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the MIS capacitors with Al top contact. It has been observed that the hysteresis behaviour for HfO2/SiOxNy dielectric stack is reduced in comparison to HfO2/SiO2, indicating the presence of fewer traps in the nitrided high-k gate dielectric stack. The interface state densities of the gate dielectric stacks are found to be ~7E11 and ~ 6E11 eV-1cm-2 @ Ec-Et = 0.2 eV in HfO2/SiO2 and HfO2/SiOxNy stacks, respectively. An improvement of gate leakage current density is also observed in HfO2/SiOxNy (~1E-8 A/cm2 @ E=1.5MV/cm) in comparison to HfO2/SiO2 stack (~1E-7 A/cm2 @ E=1.5MV/cm).


4:15 PM H7.9
Engineering of Epitaxial γ-Al₂O₃ (111) Gate Dielectrics on 4H-SiC (0001) Carey M. Tanner¹, Monica Sawkar-Mathur¹, Jun Lu², Hans-Olof Blom², Michael F. Toney³ and Jane P. Chang¹; ¹Chemical and Biomolecular Engineering, University of California Los Angeles, Los Angeles, California; ²Angstrom Laboratory, Uppsala University, Uppsala, Sweden; ³Stanford Synchrotron Radiation Laboratory, Stanford Linear Accelerator Center, Menlo Park, California.

The development of epitaxial high-k gate oxides has the potential to improve the performance of 4H-SiC power MOSFETs by improving the semiconductor/dielectric interface and enabling operation at a higher electric field. The selection of candidate materials is limited by the strict requirement for adequate band offsets imposed by the wide bandgap of 4H-SiC (E_g = 3.26 eV). Al₂O₃ (κ = 10) was selected for investigation due to its large bandgap (E_g = 7.0 eV) and demonstrated stability in several crystalline phases. <p>Al₂O₃ thin films were grown on n-type 4H-SiC (0001) by thermal ALD at 200°C using trimethylaluminum and water vapor. The films were stoichiometric with carbon incorporation below detection limits as evaluated by in-situ XPS. The as-deposited Al₂O₃ films were amorphous as determined by in-situ RHEED. Upon rapid thermal annealing in N₂ at 1100°C, the film crystallized to the γ-Al₂O₃ phase. The abrupt interface of the as-deposited Al₂O₃ film with the substrate was preserved during the crystallization process, as observed by cross-sectional HRTEM images. Selected area electron diffraction (SAED) indicated an epitaxial relationship between the film and the substrate, γ-Al₂O₃ (111) || 4H-SiC (0001) and γ-Al₂O₃ (-110) || 4H-SiC (-12-10). <p>More detailed analysis of the film crystallinity was performed by synchrotron X-ray scattering of γ-Al₂O₃ films of various thickness. For all films, the same epitaxial relationship as well as twinning around the [111] axis were observed. No peaks associated with other crystallite phases or orientations were observed in the specular scans. The FWHM of the (222) peak was 0.057° ± 0.02° for all film thicknesses, suggesting the high quality of the film. Strong interference fringes were seen for the γ-Al₂O₃ (222) reflection for films of ≤100 Å, indicating the parallelness of the atomic planes. No detectable misorientation in phi, chi, or θ was observed for the 25 Å films; however, an increase in the percentage of isotropically misoriented grains was observed for films of increasing thickness up to 200 Å. For thicker films, only partial crystallization was achieved under these processing conditions and mixed crystalline and amorphous regions were visible in the cross-sectional HRTEM images. <p>C-V and I-V measurements of 4H-SiC MOS capacitors fabricated with 200 Å thick Al₂O₃ dielectric films were performed to compare the dielectric constant, fixed charge, density of interface states, and breakdown field characteristics of epitaxial γ-Al₂O₃ films with respect to those of amorphous Al₂O₃ as well as state-of-the-art thermal oxides. A fairly symmetric band alignment was determined from synchrotron XPS spectra of Al₂O₃ thin films and the results were confirmed by the barrier height extracted from I-V measurements. Conductive AFM measurements provided nanoscale spatial resolution of the electrical properties of the films and elucidated the role of grain boundaries as leakage paths in the crystalline films.


4:30 PM H7.10
Controllability of Flatband Voltage in Metal/High-k Gate Stack Structures. Kenji Ohmori¹, Parhat Ahmet², Kuniyki Kakushima², Hideki Yoshikawa¹, Kenji Shiraishi³, Naoto Umezawa¹, Kiyomi Nakajima¹, Michiko Yoshitake¹, Keishuke Kobayashi¹, Kikuo Yamabe³, Heiji Watanabe⁴, Yasuo Nara⁵, Takashi Nakayama⁶, Martin L Green⁷, Hiroshi Iwai², Keisaku Yamada⁸ and Toyohiro Chikyow¹; ¹Advanced Electronic Materials Center, National Institute for Materials Science, Tsukuba, Ibaraki, Japan; ²Tokyo Institute of Technology, Yokohama, Japan; ³University of Tsukuba, Tsukuba, Japan; ⁴Osaka University, Osaka, Japan; ⁵Semiconductor Leading Edge Technologies, Tsukuba, Japan; ⁶Chiba University, Chiba, Japan; ⁷National Institute of Standards and Technology, Gaithersburg, Maryland; ⁸Waseda University, Shinjuku, Tokyo, Japan.

We have applied a combinatorial materials technique for investigating the controllability of flatband voltage in metal/high-k dielectric/Si stacking structures. Two kinds of high-k dielectric films, HfO2 and La2O3, were systematically compared under various annealing conditions. The Pt-W alloy films were used as metal electrodes so that the work function can be tuned continuously from 4.7 to 5.5 eV by changing the ratio of Pt to W. In the case of Pt-W/HfO2/SiO2/Si structures, the difference in flatband voltage from Pt and W electrodes are only 0.05 V after forming gas annealing (FGA) regardless of the work function difference of 0.8 eV. By an additional oxidizing gas annealing (OGA), the difference increases to 0.3 eV which is still smaller than the workfunction difference. This is attributed to Fermi level pinning which derives from an electric dipole at the metal/high-k interface because of oxygen vacancy formation. This change in effective work function is dominant for higher work function metals such as Pt. On the contrary, the La2O3 films exhibit great controllability in flatband voltage. We observed the difference in flatband voltages of 0.7 and 1.2 V after FGA and OGA, respectively. The magnitude of flatband voltage controllability is 3 times larger in La2O3 than in HfO2. Hard x-ray photoelectron spectroscopy at the SPring-8 synchrotron facility demonstrates the existence of a Si-rich layer between the HfO2 and metal films. This is consistent with the ultrathin reaction layer observed only in metal/HfO2 interfaces by transmission electron microscopy. We consider that the pile-up of Si at the metal/high-k interface significantly deteriorate the controllability in flatband voltage. From this viewpoint, we believe that the La2O3 film is one of the most promising high-k dielectric materials for future CMOS devices in 32nm-node and beyond.


4:45 PM H7.11
Electrical Characterization of High-k Dielectrics by Means of Flat-Band Voltage Transient Recording. Salvador Duenas¹, Helena Castan¹, Hector Garcia¹, Luis Bailon¹, Kaupo Kukli^2,3, Mikko Ritala³ and Markus Leskela³; ¹Electronica, Universidad De Valladolid, Valladolid, Valladolid, Spain; ²Institute of Experimental Physics and Technology, Univ. Tartu, Tartu, Estonia; ³Chemistry, Univ. Helsinki, Helsinki, Finland.

In the search for a replacement of silicon dioxide as gate dielectric in CMOS technologies, high permittivity (high-k) dielectric materials have gained a lot of attention. However, there are several material and process related issues to be overcome to realize the benefits of this replacement. In particular, high-k oxides have larger densities of charge traps and interface states than SiO2, causing more significant trap-related conductions. For this reason, much effort has currently been focused to the study of their microstructural, physical, and dielectric properties. In particular, the development of electrical characterization techniques which provide good knowledge of the very nature of these processes is an important issue in order to qualify both the dielectric materials themselves as well as the most adequate fabrication approaches. The present work deals with the investigation of thermally activated defect trapping and detrapping processes in order to determine the energy of soft-optical phonons in high-k dielectrics. We have carried out a comparison between flat-band transients displayed in metal-oxide-semiconductor (MOS) structures fabricated on several atomic layer deposited (ALD) high-k dielectric films: HfO₂, ZrO₂, Al₂O₃, Ta₂O₅, TiO₂, and Gd₂O₃. The gate voltage as a function of time is recorded while keeping constant the capacitance at the initial flat band condition (C_FB). Since samples are in darkness, under no electric fields and no charge-injection conditions, transients must be due to charge trapping of localized states produced by electrons (holes) coming from the semiconductor by tunnelling. The process is assisted by phonons and it is therefore thermally activated. The temperature-transient amplitude relation follows an Arrhenius plot which provides the thermal activation energy of soft-optical phonons. We have proved that the flat-band voltage transients are increasing or decreasing depending on the previous bias hystory (accumulation or inversion) and the hysteresis sign (clockwise or counter-clockwise) displayed by capacitance-voltage (C-V) characteristics of MOS structures. More details, including phonon energy values obtained for the studied materials will be presented during the conference.