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Symposium G: Extending Moore’s Law with Advanced Channel Materials

Chairs

Srini Chakravarthi TCAD, Silicon Technology Development Texas Instruments M/S 364 13121 TI Blvd. Dallas, TX 75243 972-995-2580		Reza Arghavani Applied Materials M/S 1266 P.O. Box 58039 Santa Clara, CA 95054 408-986-7328
Gerhard Klimeck Network for Computational Nanotechnology (NCN) Dept. of Electrical Engineering Purdue University W. Lafayette, IN 47907 765-494-9212

Symposium Support
Applied Materials, Inc.
Intel Corporation
Texas Instruments Incorporated


Proceedings to be published in both book form and online
(see Proceedings Library at www.mrs.org/publications_library)
as volume 995
of the Materials Research Society
Symposium Proceedings Series.

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* Invited paper

SESSION G1: Challenges / Directions of Current CMOS
Chairs: Reza Arghavani and Srini Chakravarthi
Tuesday Morning, April 10, 2007
Room 3005 (Moscone West)

8:00 AM *G1.1
Future Direction of Strained Si/channel MOSFETs for Advanced 90 to 22nm Logic Technologies Scott Thompson, Electrical & Computer Engineering, University of Florida, Gainesville, Florida.

Abstract—Experimental data along with a detailed theoretical picture is given for the physics of strain effects in semiconductors and Metal-Oxide-Semiconductor- Field-Effect-Transistors (MOSFETs). MOSFET piezoresistance coefficicents are measured on industrially fabricated 30-100nm gate length Si, SiGe and Ge channel MOSETs with SiO2 and HfO2 gate dielectrics. The data is interpreted considering energy band splitting and warping, subband alignment, effective mass change, and phonon scattering alteration. These effects are investigated by symmetry, tight-binding and kp methods for in-plane biaxial and longitudinal and transverse uniaxial stresses. From these data, we intreprete and project the past and future direction of strained Si for advance 90 to 22nm logic technologies.


8:30 AM *G1.2
Mobility Engineering in Si CMOS. Serge Biesemans, Peter Verheyen, Philippe Absil and Thomas Hoffmann; CMOSDR, IMEC, Leuven, Belgium.

We review and discuss the latest developments in strain engineering in Si CMOS devices. Transistor scaling has been the major driving force in the semiconductor industry for 40 years. The track has been one of many roadblocks and creative solutions. Strain engineering has been employed since the 90nm node and is generally accepted as a key enabler for scaling technology performance in subsequent nodes. Several strain techniques exist with different gains at circuit level. Do local strain techniques scale into 32nm node and beyond ? Or do engineers have to move to wafer level strain or new channel material options ? Can strain techniques be combined with other advanced options like laser anneal and high-k/metal gates ? Several details will be discussed like Stress Memorisation Technique (SMT) understanding on nFET and pFET, SiC S/D as the nFET equivalent of the SiGe S/D and its impact S/D silicidation.


9:00 AM G1.3
Strain-Transfer Structure Beneath the Transistor Channel for Increasing the Strain Effects of Lattice-Mismatched Source and Drain Stressors. Yee-Chia Yeo, Kah-Wee Ang, Jianqiang Lin and Chee Shing Lam; Electrical and Computer Engineering, National University of Singapore, Singapore, Singapore.

Strain-induced mobility enhancement is an attractive way to enhance the performance of metal-oxide-semiconductor field effect transistors. Lattice-mismatched source/drain (S/D) stressors such as silicon-germanium (SiGe) S/D for p-FET and silicon-carbon (Si:C) for n-FET has been investigated. In this paper, we introduce a new concept of incorporating an additional structure beneath the transistor channel region to increase the strain-transfer efficiency of the S/D stressors. The additional structure is lattice-mismatched with respect to the overlying Si-channel and/or with respect to the S/D stressors. For n-FET, a SiGe region integrated beneath the Si-channel enhances the magnitude of the tensile strain due to the Si:C S/D, and this leads to increased strain effects. For p-FET, a Si:C region beneath the Si-channel enhances the strain effect due to the SiGe S/D. This additional structure is called a strain-transfer structure. Extensive numerical simulations were performed using the finite element method to explain how the new strain-transfer structure works. Profiles of the various strain components in the transistor channel were obtained. Dependence of the strain effect on geometrical features of the new transistor structure will also be reported. Experimental realization of the device structures will also be reported. Electrical results from nanoscale transistors confirm the strain enhancement effects due to the strain-transfer structure.


9:15 AM G1.4
A Theoretical Investigation of Selected Silicides and Germanides. Alex Demkov, Manish Niranjan and Leonard Kleinman; Physics, The University of Texas, Austin, Texas.

A germanium channel field effect transistor is being considered for the next generation CMOS technology. New materials system requires re-development of most elements of the device. Among other elements low resistance contacts compatible with a self aligned process have to be developed based on metal germanides. Germanides with low n- and p-type Schottky barriers (for the use in NMOS and PMOS devices) to germanium channel need to be identified. We report a comprehensive theoretical study within the framework of density functional theory of several germanides (NiGe, PtGe, YGe, Y5Ge3, HfGe and HfGe2) and compare them with monosilicides of Pt and Ni. We report bulk electronic structure and elastic properties. However, we focus on the surface properties important to thin films such as surface energy, work function and Schottky barrier height. We are able to identify thermodynamic stability fields for surface terminations resulting in work functions consistent with the low Schottky barrier requirement. Several interface structure were also considered which afford a direct evaluation of the barrier height. Germanides have complex phase diagrams, and we find ab-initio calculations extremely useful in providing fundamental understanding of the structure-property relations between the crystal structure, chemical composition and atomic structure of the alloy/semiconductor interface on one hand and the Schottky barrier height on the other hand.


9:30 AM *G1.5
Design Guidelines for High Mobility Channel Bulk n-MOSFETs Lee Smith¹, Makoto Fujiwara^2,3, Krishna Saraswat², Yoshio Nishi² and Dipu Pramanik¹; ¹Synopsys, Inc., Mountain View, California; ²Stanford University, Stanford, California; ³Toshiba Corporation, Yokohama, Kanagawa, Japan.

Because of high electron mobility, Ge and III-V channel n-MOSFETs have attracted considerable interest as possible replacements for Si channel devices. From a manufacturing and economic point of view, planar bulk devices will continue to be employed where possible, and the integration of high mobility materials with Si substrates will be essential. For this reason Ge and GaAs are particularly attractive since Ge can be grown on Si via SiGe interlayers, and GaAs is closely lattice-matched to Ge. In this work, we use device simulation to evaluate Ge and GaAs bulk n-MOSFETs in order to establish guidelines for achieving superior performance relative to strained Si. In contrast to previous simulation studies, we explicitly consider the impact of the relatively low active donor concentrations attainable in Ge and GaAs on extension resistance as well as the impact of Fermi-level pinning in Ge and GaAs on contact resistance. Doped and metal source/drain devices are also compared. For Ge, we find that high parasitic resistance at practical doping levels severely degrades Ion at even moderate contact barrier heights. While this can be improved with metal source/drain, Ge displays intolerably high tunnel leakage from the metal drain. In GaAs, low parasitic resistance and high channel velocity enable improved performance at low contact barrier height, but high contact resistance at the known, pinned Fermi-level position limits the achievable Ion.

9:45 AM *G1.6
Simplified Surface Preparation for GaAs Passivation Using Atomic-layer-deposited High-k dielectrics. Peide (Peter) Ye, Yi Xuan and Han-Chung Lin; School of ECE, Purdue University, West Lafayette, Indiana.

Atomic layer deposition (ALD) provides a unique opportunity to integrate high-quality gate dielectrics on III-V compound semiconductors. The physics and chemistry of III-V compound semiconductor surface or interface is such a complex problem that the understanding is still very limited after three-decade research. We report on a simplified surface preparation process using ammonium hydroxide to remove the native oxide and have hydroxylated GaAs surface ready for ALD surface chemistry reaction with tri-methyl-aluminum. The effectiveness of GaAs passivation with ALD Al2O3 is demonstrated with small hysteresis, 1-2% frequency dispersion per decade at accumulation capacitance, and mid-bandgap Dit of 8x10_11/cm_2-eV to 1x10_12/cm_2-eV determined by Terman method. The results from ammonium sulfide, hydro-fluoride, hydro-chloride treated surfaces and surface with native oxide are also presented to compare with the results from ammonium hydroxide treated surface. It provides conclusive experimental evidence that ALD oxides can unpin the Fermi level in GaAs with appropriate surface preparation and material choice. This conclusion is further confirmed and can make it more general to III-V compound semiconductors with the newly fabricated devices, showing the drain current of 250 mA/mm in inversion-mode InGaAs MOSFETs and 60 mA/mm in inversion-mode InP MOSFETs using ALD Al2O3 as gate dielectrics.

SESSION G2: Prospective Materials for CMOS Channels
Chairs: Reza Arghavani and Srini Chakravarthi
Tuesday Morning, April 10, 2007
Room 3005 (Moscone West)
10:30 AM *G2.1
New Channel Materials and the Ultimate MOSFET Mark Lundstrom, School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana.

Silicon CMOS transistors continue to be pushed to smaller and smaller dimensions, but the end of silicon scaling is in sight. The original choice of silicon was driven by the properties of its native oxide, SiO2. With the development of high-k gate dielectrics, the use of different substrate materials for the channel of a MOSFET is worth considering. This raises some questions. What are the desired properties of a semiconductor to produce a high performance MOSFET with the smallest possible dimensions? Of the available semiconductors, which one(s) have the best properties for a MOSFET? What is the maximum benefit in device performance metrics that could result, and what would be the corresponding improvement in circuit performance? This talk will address the question: if we could solve the materials and fabrication challenges and build a high-quality MOSFET with any channel material we choose, which material would we select and how much would we benefit?


11:00 AM G2.2
Metal-Oxide-Semiconductor Field Effect Transistors with InGaAs and GaAs/InGaAs Channels and High-k Gate Dielectric. Sergei Viktor Koveshnikov^1,2, Serge Oktyabrsky², Vadim Tokranov², Michael Yakimov², Richard Moore², Feng Zhu³, Wilman Tsai¹ and Jack Lee³; ¹Intel Corporation, Santa Clara, California; ²College of Nanoscale Science and Engineering, University at Albany-SUNY, Albany, New York; ³Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas.

In this work we study the correlations of the III-V-High-k dielectric interface structure and its chemistry with the formation/passivation of interface states and demonstrate good electrical characteristics of InGaAs and GaAs/InGaAs channel MOSFETs. To avoid Fermi level pinning we employed an amorphous arsenic-doped Si interface passivation layer (α-Si IPL) in-situ deposited on top of III-V channels grown by molecular beam epitaxy. High-k gate stack was further fabricated either in-situ using e-beam evaporation of metallic Hf in reduced vacuum (10-6 to 10-5 Torr) without exposure to air, or ex-situ using physical vapor deposition of HfO2. Transmission electron microscopy revealed high quality atomically clean III-V-Si interface which was stable up to 800 °C; the Si layer remained amorphous. Exposure of the III-V wafers with an α-Si layer to air led to its partial or complete oxidation as revealed by TEM/EDX and x-ray photoelectron spectroscopy. Full oxidation of the Si layer resulted in Fermi level pinning as demonstrated by the frequency dependent capacitance-voltage measurements of the TaN-gated MOS capacitors revealing large stretch-out and frequency dispersion of C-V characteristics. A non-pinned Fermi level was demonstrated on both p-type and n-type InGaAs and GaAs/InGaAs wafers when the α-Si IPL was partially oxidized thus preventing excess of oxygen at the III-V surface. The minimum thickness of the α-Si IPL required to prevent Fermi level pinning was ~0.2 nm and ~1.5 nm for in-situ and ex-situ HfO2 deposition, respectively. Good thermal stability of the III-V-α-Si IPL interface was demonstrated for both in-situ and ex-situ gate stacks making it appropriate for Si implant activation within MOSFET technology. Both depletion mode and enhancement mode (inversion channel) N-MOSFETs were demonstrated with transconductance above 100 mS/mm and mobility up to 1500 cm2/Vs.


11:15 AM G2.3
Electronic Structure of Si/InAs Composite Channels. Marta Prada^1,2, Neerav Kharche¹ and Gerhard Klimeck¹; ¹School of Electrical and Computer Engineering, Network for Computational Nanotechnology Purdue University, W Lafayette, Indiana; ²Physics, University of Wisconsin-Madison, Madison, Wisconsin.

Although pure InAs has a lighter effective mass and higher mobility than Si, an ultra-scaled Si device may still perform better than an ultra-small InAs device [1]. The co-integration of InAs on top of a thin Si body may provide improved device performance [2]. This work models the electronic structure of such composite channels for three different growth directions: (100), (110), (112). The (110) and (112) growth directions are the technically most relevant, since they balance surface charge dipoles. The calculations are performed with NEMO 3-D [3]. Atoms are represented explicitly in the Valence Force Field (VFF) method [4] to minimize the strain and in the sp3d5s* tight-binding model. The bulk material parameters have been calibrated to match the band-offsets according to Van de Walle’s model solid theory [5]. NEMO 3-D enables the calculation of localized states in the quantum well and their dispersion in the quantum well plane. From this dispersion, the bandgap, its direct or indirect character, and the associated effective masses of the valence and conduction band can be determined. Such composite bandstructure calculations are demonstrated here for the first time. The calculations can then be included in empirical device models [1] to estimate device performance. Concretely this work considers a total constant quantum well thickness of 8nm composed of $Si_{1-x}(InAs)_x$ where x is 0,1,2,3,8nm. The data on the three different lattice orientations in terms of direct/indirect gap, gap energy, electron and hole effective masses are summarized in the associated tables. For samples grown along the (001) direction, Si is a direct bandgap material, and deposition of InAs thin layers reduces only slightly the light-hole effective mass, also decreasing the magnitude of the gap. Pure InAs QW appears to be a direct bandgap material, with a relatively small gap and effective masses of about one order of magnitude smaller than for pure Si QW of equivalent thickness. In contrast, along the (110) and (112)-growth direction, a thin layer of InAs (x>=2nm) causes the new material to be direct-bandgap, decreasing significantly the electronic effective mass and increasing the gap. [1] A Rahman, G Klimeck, and M Lundstrom, 2005 IEEE IEDM, 2005 [2] private communication, Dr. Alan Seabaugh, Notre Dame. [3] G Klimeck, et al, Computer Modeling in Engineering and Science 3, 601-642 (2002). [4] P N Keating, Phys. Rev. 145, 637-645 (1966). [5] C G Van de Walle, Phys. Rev. B 39, 1871-1883 (1989)


11:30 AM *G2.4
Building a CMOS technology with Non-Traditional Materials to Satisfy Digital Requirements. Douglas William Barlage¹, Mark A. L. Johnson², David William Braddock³, Yawei Jin¹ and Lei Ma¹; ¹Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina; ²Material Science and Engineering, North Carolina State University, Raleigh, North Carolina; ³OSEMI, Cannon Falls, Minnesota.

The CMOS architecture has largely dominated massive scaled electronic systems because of the incomparable leakage management that it affords. The creation of the minimum dimension (<10nm) devices using non-Si III-V materials is investigated with simulation and experimental techniques. A standard benchmark is proposed to allow the comparison of an array of semiconductor materials using the bulk properties of the semiconductor materials. This benchmark is verified with simulations. Of considerable note from this work is that distinctly different material properties are required for the source and the drain than the channel of the device to exceed the performance of silicon based devices. The source drain requires a high-mobility with relatively low band gap while the channel material requires a wider band gap to successfully manage the leakage that is unavoidable as the gate length continues to shrink. This is expanded in detail and the heterogeneous-source-drain MOSFET, such as already demonstrated in PMOS manufacturing, is extended to include III-V based materials for N and P type MOSFETs. Based on the preliminary assessment this approach is a logical choice for CMOS extension. Simulation data of this device for an array of III-V materials will be presented. In addition to the materials issues in the channel and source drain, a suitable oxide must be created to allow for successful scaling. Building on knowledge from the high-k on silicon work, materials compatibility for oxides on non-Silicon material is explored. Hetero-structure gate stacks are compared with oxides on non-traditional materials and the oxide compatibility is evaluated for III-V compounds. The findings highlight the underlying challenges associated with creating suitable unpinned interfaces in non-silicon materials. Finally, experimental data is presented for MOS devices created in the III-Nitride based system. As part of the analysis in this work, the mobility evaluation for a given III-V gate stack is presented. This mobility analysis will focus on the calculation for the correct field and charge associated with the gate stack when the material changes as well as the underlying mechanisms that govern charge transport in a typical enhancement mode MOS device. Furthermore the relationship between low field mobility and the impact on current-voltage characteristics is presented. These considerations are critical when choosing a channel material to carry the large amount of charge demanded by the high-performance logic circuits to be manufactured beyond 2015.


SESSION G3: Advanced Channel Materials I: (110) Si, Ge
Chairs: Srini Chakravarthi and Gerhard Klimeck
Tuesday Afternoon, April 10, 2007
Room 3005 (Moscone West)
1:30 PM *G3.1
Future Channel Materials and Processes for High Performance CMOS Devendra Sadana¹, S. W Bedell¹, J. P Souza¹, A. Reznicek¹, S. J Koester¹, Yanning Sun¹, E. Kiewra¹, J. Ott¹, K. Fogel¹, D. J Webb², J. Fompeyrine², J. -P Locquet², M. Sousa² and R. Germann²; ¹Advanced Substrate Research, IBM, Yorktown Heights, New York; ²IBM Zurich Research Laboratory, Säumerstrasse 4 / Postfach, Rüschlikon, CH-8803, Switzerland.

CMOS scaling is facing a formidable challenge because of a number of factors including increasing gate leakage current, rising active power due to non-scaled voltage, band-to-band tunneling at high body doping levels, and insufficient source-drain doping for series resistance reduction. Meeting performance targets of 32 nm CMOS and beyond will require innovation at all levels, including system architecture, circuit design, integration, device design and new channel materials. This work is focused to address present and future CMOS performance challenges via advanced materials and processes. Some of the options under consideration include (i) local and global strain, (ii) Si surface orientation, and (iii) non-Si materials including Ge and III-Vs. Challenges associated with each of these options will be examined both at fundamental level as well as at manufacturing level. Key fundamental challenges include relaxation of strain in locally and globally strained Si during processing, surface passivation of III-V materials, and high defectivity in Ge and III-V films grown on Si. Key manufacturing challenges include incompatibility of processes integration between Si and non-Si materials, and lack of infrastructure readiness for non-Si materials. A perspective on performance driven scaling will be presented.


2:00 PM G3.2
Bonded Layer Thickness Optimization for DSB-HOT. Angelo Pinto¹, Sachin Joshi², Y. T. Huang³, Rick Wise¹, Rinn Cleavelin¹, Mike Seacrist⁴, Mike Ries⁴, Manfred Ramin², Melissa Freeman⁵, Billy Nguyen⁵, Kenneth Matthews⁵, Bruce Wilks⁵, Mike Ma³, C. T. Lin³ and Sanjay Banerjee²; ¹External Research, SiTD, Texas Instruments Inc., Austin, Texas; ²Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas; ³United Microelectronics Corporation Inc., Hsinchu, Taiwan; ⁴MEMC Electronic Materials Inc., St. Peters, Missouri; ⁵Advanced Technology Development Facility Inc., Austin, Texas.

The use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (110) Si layer bonded to a bulk Si (100) wafer provides opportunities for migration of bulk CMOS designs to higher performance materials: namely (110) Si for PMOSFETs for higher hole mobility. This has been demonstrated using Silicon-on-Insulator (SOI) substrates with either one or both types of devices on an insulating layer. However, this requires complex selective epitaxial growth. Also, in order to easily reuse bulk CMOS libraries, a “bulk-like” technology is interesting. A 2X performance improvement in the Ion-Ioff behavior for short channel (85 nm) PMOS devices fabricated using a standard polysilicon / nitrided silicon dioxide process was observed on DSB wafers. Performance of NMOS devices fabricated on recrystallized (100) active areas of the wafer was comparable to bulk (100) Si. This report discusses layer thickness optimization necessary to minimize off-state leakage for DSB-HOT. Ultra-thin (110) layers would be ideal for the scheme of amorphization and templated recrystallization (ATR) before shallow trench isolation (STI) proposed by Saenger et al. in order to minimize the triangular morphology observed at the border of the epitaxially regrown region. The morphology results due to competing solid phase (SPE) epitaxial regrowth processes from the bottom (100) and sidewall surface of the (110) layer. The presence of this region near the junction of a device would increase off-state NMOS leakage. It is necessary to minimize this morphology near the device and consume the triangular region by STI in order for the technology to be applicable to SRAM cells at the 45/32 nm nodes. However, there are interesting tradeoffs associated with very thin Si (110) layers. Significant dopant segregation is observed from SIMS profiles after device fabrication at the bond interface between the (110) Si layer and the (100) substrate. This leads to a large source-to-drain leakage for short channel devices with very thin DSB layers. Long channel MOSFETs as well as short channel MOSFETs fabricated on thicker DSB layers show a much lower off-state leakage. IV data indicates that DSB layer thicknesses of 200 nm and higher demonstrate a significant reduction in S-D leakage while thicknesses lower than 100 nm result in electrical shorts between the S/D regions for short channel devices. The corresponding triangular epitaxial regrowth morphology for a 100 nm thick DSB layer was observed to be as large as 110 nm. This presents a significant roadblock for this technology in SRAM cells at the 45/32 nm nodes. Process techniques to reduce the morphology for NMOS devices as well as junction engineering to minimize leakage at the bond interface have been investigated. One order of magnitude improvement in the PMOS DSB junction leakage was demonstrated by optimizing the implant conditions which could enable thinner DSB layers.


2:15 PM G3.3
Understanding Facet Formation During Solid Phase Epitaxy of Patterned Amorphized Regions in (001) and (011) Silicon: Observations and Model. Katherine L. Saenger¹, Haizhou Yin², Keith E. Fogel¹, John A. Ott¹, Joel P. de Souza¹ and Devendra K. Sadana¹; ¹IBM Semiconductor Research and Development Center, IBM T.J. Watson Research Center, Yorktown Heights, New York; ²IBM Semiconductor Research and Development Center, IBM Microelectronics, Hopewell Junction, New York.

The strongly anisotropic effect of strain on the performance of Si-based field effect transistors has led to increased interest in both alternative channel alignments and wafer surface orientations. Consequently it is becoming increasingly important to understand how differences in crystal orientation can affect the defectivity and growth patterns of patterned amorphized material recrystallized by SPE. After a brief survey of the mask-edge/trench-edge defects and faceted recrystallization behaviors we have seen in (001) and (011) Si (in both single-orientation and hybrid-orientation direct-silicon-bonded wafers) we will describe a simple model that appears to explain nearly all of the observed phenomena.


2:30 PM G3.4
Sub 50nm Strained n-FETs formed on Silicon-Germanium-on-Insulator Substrates and the Integration of Silicon Source/Drain Stressors Huiqi Grace Wang^1,2, Eng-Huat Toh^1,2, Keat Mun Hoe², S. Tripathy³, Subramanian Balakumar², Guo-Qiang Lo², Ganesh Samudra¹ and Yee-Chia Yeo¹; ¹National University of Singapore, Singapore, Singapore; ²Institutue of Microelectronics, Singapore, Singapore; ³Institutue of Materials Research and Engineering, Singapore, Singapore.

Group-IV high-mobility semiconductors such as Ge [1] and SiGe [2] have received considerable attention as potential materials for further extension of transistor performance. Exploitation of strained-Ge and SiGe channels would lead to further reduction in carrier effective mass and improve mobility enhancement, paving the way for high mobility transistors with superior speed performance. Existing works on SiGe channel show marginal enhancement in NMOS [3], possibly due to the compressive stress in thin SiGe channel structures. By adopting silicon-germanium-on-insulator (SGOI) substrates fabricated by a novel Ge condensation technique [4], the lateral compressive strain normally present in SGOI substrates can be reduced, enabling n-FET fabrication with excellent performance. We found that the magnitude of the compressive strain can be relaxed by up to 0.7%, according to Raman spectroscopy measurements. In this work, we also report the experimental demonstration of uniaxial tensile strained thin-body silicon-germanium-on-insulator (SGOI) n-FETs with silicon (Si) source and drain (S/D) regions. The selectively grown Si S/D induces uniaxial tensile strain in the SiGe channel, leading to enhancement in electron mobility. The stress distribution in n-FETs formed with Si S/D and Si_0.75Ge_0.25 or Si_0.60Ge_0.40 channel region was investigated using numerical simulation. The simulated stress profile shows lateral compression of the SiGe lattice underneath the Si S/D stressors, and lateral tensile stress S_xx induced in the SiGe channel. The tensile stress generated near the channel center increases from 1.2GPa to 1.7GPa, as the Ge content in the channel increased from Si_0.75Ge_0.25 to Si_0.60Ge_0.40. Tensile stress developed in the SiGe channel is the key for electron mobility enhancement. Devices with gate length L_G down to 50 nm were fabricated. The Si S/D gives rise to 39% higher saturation drive current I_Dsat for transistors fabricated on Si_0.60Ge_0.40-on-insulator substrates. For n-FETs fabricated on Si_0.75Ge_0.25-on-insulator substrates, a 27% I_Dsat enhancement was observed. Dependence of the transistor performance on channel orientation and device dimensions, e.g. gate length and width, are explored. Appreciable I_Dsat enhancement was observed. Transistors employing group-IV high mobility channel materials could be promising for realizing very high performance levels. REFERENCES [1]H. Shang et. al., IEDM Tech. Dig., pp. 157, 2004 [2]H. C.-H. Wang et al, IEDM Tech. Dig., pp. 161,2004. [3]T. Irisawa et. al., Appl. Phys. Lett. 81, pp.847,2002. [4]G. H. Wang et. al. Appl. Phys. Lett., 89, no.5, pp.3109, 2006.


2:45 PM G3.5
Characterization of a Multidirectional Condensation Ge Process for Co-integrated SOI/GeOI Substrate Fabrication. Benjamin Vincent, Jean-Francois Damlencourt, Denis Rouchon, Pierrette Rivallin and Laurent Clavelier; , CEA-DRT-LETI-CEA/GRE, Grenoble, France.

Germanium seems to be one of the most adapted substitutes of Silicon for ultimate device scaling due to higher carriers mobilities. Its use for fabrication of pMOSFET has already been judged as really efficient whereas its application for nMOSFET is still discussed. Ge MOSFET having important leakage currents due to a narrow band gap, the presence of a buried oxide is necessary for devices fabrication on this semiconductor: it permits to limit the diode leakage current and to take profit of the advantages of “On Insulator” technologies. Then, co-integrated SOI (Silicon On Insulator) and GeOI (Germanium On Insulator) structures on the same wafer for respectively n and pMOSFETs are investigated for advanced Complementary MOS fabrication. The most adapted technique for SOI/GeOI lateral co-integration is the Ge condensation technique. This process involves a Si selective oxidation of a SiGe layer epitaxially grown on an initial SOI wafer. The basics of the technique are the Si consumption by the oxidation, the Ge diffusion through the remaining SiGe layer and then the replacement of the Si of the initial SOI substrate by the Ge. Experimental and simulation results of this technique have already been presented for fabrication of full sheet SGOI or GeOI substrates. In order to carry out SOI/GeOI co-integration, oxidations of mesa islands of SiGe on SOI have been studied. By this experiment, we observed a lateral condensation phenomenon due to a multidirectional oxidation. An enrichment gradient on the oxidized mesas has been characterized by intensities ratio calculation, IGe-Ge, ISi-Ge and ISi-Si, obtained by Raman spectroscopy. The Raman peaks intensity is only related to the Ge concentration and do not take into account the strain states differences of the layers. The highest concentrations values have been obtained at the mesas corners due to a three directional oxidation (from the top and two lateral sides); then, lower enrichments are obtained at the mesas edges due to a two directional oxidation (from the top and one lateral sides); the lowest enrichment values are obtained at the mesa centers due to the one directional oxidation from the top side. A global study of the multidirectional condensation has been performed by measurements of the relative gradient values and gradients widths for different mesas centers concentrations and different mesas shapes and sizes. These results permit firstly to define new design rules for localized Ge condensation process for GeOI/SOI co-integration and to calibrate secondly a simulation tool for multidirectional condensation. Simulations of one dimensional Ge condensation process have already been carried out by a TCAD tool and an analytical model. The TCAD tool is now adapted for more complex condensation studies due to this lateral condensation process calibration.


SESSION G4: Advanced Channel Materials II
Chairs: Reza Arghavani and Gerhard Klimeck
Tuesday Afternoon, April 10, 2007
Room 3005 (Moscone West)
3:30 PM *G4.1
Strained Si-Ge Heterostructure Channel Materials for Bulk and Ultra-thin Body MOSFETs. Judy L Hoyt, Cait Ni Chleirigh, Leonardo Gomez, Ingvar Aberg and Guangrui Xia; Microsystems Technology Laboratories, MIT, Cambridge, Massachusetts.

The materials and device technology of MOSFETs utilizing Si-Ge heterostructure channels are reviewed. Strained Si-strained Ge heterostructures offer the potential for both electron and hole mobility enhancement using Si-compatible gate dielectrics. In strained (100) Ge in particular, the measured hole mobility enhancement is 10x higher than in unstrained Si p-MOSFETs. Strain relaxation limits the SiGe layer thickness to less than 10 nm for high-Ge-content strained SiGe grown on Si, while hole mobility drops for SiGe layer thicknesses in this regime, due to confinement effects. These considerations suggest a design space for the layer composition, thicknesses and strain, which impacts the hole mobility as well as off-state leakage and thermal budget constraints. The combination of these enhanced mobility materials with alternate device architectures, including ultra-thin body and double-gate devices, is of interest for device scaling as a means of improving electrostatics, and progress in heterostructure on insulator materials will be discussed.


4:00 PM *G4.2
High-κ Material Selection for Realization of High Effective Hole Mobility Ge p-MOSFETs. Yoshiki Kamata, Tsunehiro Ino, Masato Koyama and Akira Nishiyama; TOSHIBA CORPORATION, Yokohama, Japan.

High-κ/Ge gate stacks have recently attracted much attention due to their potential for offering high channel mobility and small EOT simultaneously. In particular, p-channel Ge FET is promising since bulk hole mobility of Ge is four times as high as that of Si and it can be further enhanced by strain. High-κ materials studied in Si technology, such as ZrO₂ and HfO₂, have been widely investigated on Ge substrate. However, it was revealed that Ge diffusion into the high-κ dielectrics during the annealing process, which was widely observed in the case of ZrO₂ and HfO₂, leads to the degradation of Ge MOSFET characteristics. In order to avoid this Ge diffusion, a thermally stable surface passivation layer is required. Surface passivation techniques using NH₃, SiH₄ and PH₃ before high-k deposition have already been reported, and some of these studies succeeded in suppressing the Ge diffusion, resulting in good device characteristics. We review our different approach for high-κ/Ge p-MOSFETs without an intentional interfacial layer. Using amorphous Zr silicate directly on Ge substrate, Ge diffusion and large CV hysteresis are suppressed and higher effective hole mobility than Si universal curve is accomplished.


4:30 PM G4.3
Interfacial Composition and Electrical Properties of Hf Oxide Dielectric Films Grown on In_xGa_1-xAs. Lyudmila Goncharova¹, Ozgur Celik¹, Eric Garfunkel¹, Torgny Gustafsson¹, Niti Goel², Safak Sayan² and Wilman Tsai²; ¹Physics, and Chemistry and Chemical Biology, Rutgers University, Piscataway, New Jersey; ²Intel Corp., Santa Clara, California.

MOSFETs incorporating In_xGa_1-xAs channels are an attractive option to further increase complementary MOS logic performance, since In-rich GaAs alloys offer electron mobilities significantly higher than Si. The poor electrical quality and low chemical stability of native oxides, leading to Fermi level pinning and high defect densities, has so far prevented the fabrication of competitive In_xGa_1-xAs based devices, and made integration of In_xGa_1-xAs with ultra-thin high-κ dielectric films a viable option. We have used atomic layer deposition to grow ultra-thin HfO₂ gate dielectrics on In_0.13Ga_0.87As wafers with and without sulfide passivation and investigated their interfacial and electrical characteristics. HfO₂ was either left unannealed or post-deposition annealed in a nitrogen ambient followed by deposition of an Al gate metal. Results from medium energy ion scattering, x-ray photoemission, high-resolution transmission electron microscopy and electrical measurement were compared. Structures with very thin or no interfacial oxide layer were achieved, as measured both by medium energy ion scattering and by x-ray photoemission spectroscopy. Surprisingly S-passivated samples revealed that the S-containing layer does not stay at the InGaAs/HfO₂ interface but floats on top of the Hf oxide layer during dielectric deposition. The Al gate layer becomes oxidized on the top surface and forms a sub-oxide layer at the Al/HfO₂ interface. Al/HfO₂ interdiffusion and interface roughness may also occur. Additional interfacial layer formation or Hf diffusion into the substrate was observed after PDA treatment of un-passivated InGaAs devices. Electrical measurements reveal no significant change of capacitance equivalent thickness after the HfO₂ stack is annealed, although a decrease in C-V stretch out as well as in hysteresis for un-passivated capacitors is observed. The smaller relative change in flat band voltage with increase in measurement frequency for sulfide treated devices compared to un-annealed or annealed but non-sulfide treated capacitors suggests reasonable passivation of interface trap states. Work at Rutgers was supported by SRC and NSF.


4:45 PM G4.4
Enhancement-Mode (with Channel Inversion) and Depletion-Mode MOSFETs with Ga₂O₃(Gd₂O₃)/Si₃N₄ Dual-Layer Gate Dielectrics on In_0.2Ga_0.8As Jun-Fei Zheng¹, Wilman Tsai¹, Tsung-Da Lin², Chih-Ping Chen², Minghwei Hong², Raynien Kwo³, Sharon Cui⁴ and Tso-Ping Ma⁴; ¹Strategic Technology/External Program, Intel Corporation, Santa Clara, California; ²Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu, Taiwan; ³Department of Physics, National Tsing Hua University, Hsinchu, Taiwan; ⁴Department of Electrical Engineering, Yale University, New Haven, Connecticut.

In this paper, we report a Ga₂O₃(Gd₂O₃)/Si₃N₄ dual-layer gate dielectric approach for enhancement-mode (with channel inversion) and depletion-mode MOSFETs on In_0.2Ga_0.8As. The dual-layer dielectric is formed by first depositing an nm-thick Ga₂O₃(Gd₂O₃) layer in-situ on In_0.2Ga_0.8As/GaAs. This unpins the In_0.2Ga_0.8As surface Fermi-level. Then an nm-thick Jet-Vapor-Deposited (JVD) Si₃N₄ is ex-situ deposited on Ga₂O₃(Gd₂O₃), which not only serves to protect Ga₂O₃(Gd₂O₃) from moisture during air-exposure and device processing, but also significantly reduces the gate leakage current. We fabricated and characterized n-channel enhancement-mode MOSFETs (with surface channel inversion) and n-channel depletion-mode MOSFETs on In_0.2Ga_0.8As, with a total dual-layer gate dielectric effective oxide thickness (EOT) of ~5 nm. Enhancement- mode MOSFET with a ring gate of L=10 μm shows excellent electrical characteristics with Id of ~ 0.22 mA/mm at Vds=1V and Vg=4.5V. Depletion-mode MOSFET with a ring gate of L=10 μm and large S/D to gate separation of 12.5 μm exhibits Id of 19.3mA/mm at Vds=4V and Vg=4V. We will discuss the process integration as well as process related device optimization.


SESSION G5: Poster Session
Chairs: Reza Arghavani, Srini Chakravarthi and Gerhard Klimeck
Tuesday Evening, April 10, 2007
8:00 PM
Salon Level (Marriott)
G5.1
Growth and Material Characteristics of Ga₂O₃(Gd₂O₃)/Si₃N₄ Dual-Layer Gate Dielectric for Inversion-Channel and Depletion Mode GaAs-based MOSFET. T. D. Lin¹, C. P. Chen¹, M. Hong¹, J. Kwo², J. F. Zheng³, W. Tsai³, S. Cui⁴ and T. P. Ma⁴; ¹Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu, Taiwan; ²Department of Physics, National Tsing Hua University, Hsinchu, Taiwan; ³Intel Corporation, Santa Clara, California; ⁴Department of Electrical Engineering, Yale University, New Haven, Connecticut.

Alternative channel materials are urgently required to drive the transistor scaling beyond 22nm node. III-V compound semiconductors, which possess much higher mobilities than that of Si, are candidates for the new channels. The interface pinning and/or gate insulator leakage, which has hindered the development of the III-V MOSFETs over the past four decades, have now been solved with the first demonstration of the GaAs surface unpinning using Ga₂O₃(Gd₂O₃) in-situ deposited on GaAs [1]. The discovery has led to the first inversion-channel GaAs MOSFETs in both n- and p-configurations [2]. Nonetheless, the strong affinity of the oxide to moisture [3] has posted difficulty in device processing. In this paper, growth and materials characterization of a dual gate dielectric approach using a nano thick Ga₂O₃(Gd₂O₃) as the initial dielectric layer in-situ deposited on In_0.2Ga_0.8As/GaAs and then a Jet Vapor Deposit Si₃N₄ as the second dielectric layer ex-situ deposited on Ga₂O₃(Gd₂O₃) is reported. The initial Ga₂O₃(Gd₂O₃) plays an important role in unpinning GaAs. The thermodynamic stability of Ga₂O₃(Gd₂O₃)/GaAs up to 780°C [4] allows the subsequent deposition of Si₃N₄, which serves as a protective layer for Ga₂O₃(Gd₂O₃) during air-exposure and device processing. Device structures of Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As/GaAs were grown in a multi-functional and multi-chamber UHV system, including GaAs-based and oxide molecular beam epitaxy (MBE) chambers [1].Depletion-mode In_0.2Ga_0.8As-channel MOSFETs with the dual gate dielectric were fabricated and characterized. Transistors with a 10 μm ring gate exhibit a large drain current density of 19.3 mA/mm at V_G of 4V with a large distance of S/D to gate (=12.5 μm). Inversion-channel devices also showed excellent electrical characteristics. The growth of semiconductor channels, in-situ deposited Ga₂O₃(Gd₂O₃) and ex-situ deposited Si₃N₄ will be discussed. The material characteristics using x-ray reflectivity, high-resolution transmission electron microscopy, and medium energy ion scattering will be presented. [1] M. Hong, et al, J. Vac. Sci. Technol. B, 14, 2297, 1996. [2] F. Ren, et al, Solid-State Electron. 41, 1751, 1997. [3] M. Hong, et al, Appl. Phys. Lett. 76, 312, 2000. [4] Y. L. Huang, et al, Appl. Phys. Lett. 86, 191905, 2005.


G5.2
Formation and Characterization of Pt-Germanide Thin Films on Ge(001) for Schottky Source/Drain Application in Ge pMOSFETs Haibiao Yao¹, Dongzhi Chi¹, Rui Li^2,1 and Sungjoo Lee²; ¹Institute of materials research & engineering, Singapore, Singapore; ²SNDL, Dept. of ECE, National University of Singapore, Singapore, Singapore.

The lack of a stable native germanium oxide has been the main obstacle for the use of Ge in complementary metal oxide-semiconductor devices. However, recent development of next generation deposited high-k gate dielectrics for Si also allows for the fabrication of high performance Ge-based metal-oxide-semiconductor field effect transistors (MOSFETs). For the formation of electrical contacts on Ge-based MOSFETs, transition metal germanides, such as Ni and Pt germanides, appear to be suitable candidates due to their low resistivity, low formation temperatures (as low as 250 °C), and ability to form in self-aligning manner. In this work, we have characterized the material and electrical properties of platinum germanide films which were formed on Ge(001) through solid-state reaction between Pt and Ge(001) via rapid thermal annealing. Formation of sequential phases of PtGe, Pt2Ge3, and PtGe2 with increasing annealing temperature was confirmed by X-ray diffraction measurement: PtGe at 300 oC, Pt2Ge3 at 400 oC and PtGe2 at 500 oC. A minimum resistivity value of ~36 ohm.cm was obtained for PtGe2, while the corresponding values for PtGe and Pt2Ge3 were found to be 52 and 71 ohm.cm, respectively. Scanning electron microscopy revealed that Pt-germanide films exhibit better morphological stability than NiGe, particularly for ultra-thin films. Almost identical effective barrier heights of ~ 0.619-0.626 eV were obtained for PtGe/n-Ge(001), Pt2Ge3/n-Ge(001), and PtGe2/n-Ge(001) Schottky contacts from current-voltage measurements. From the effective barrier height values, actual barrier heights of ~0.653 - 0.663 eV were determined by taking into account image force induced barrier lowering in the presence of strong inversion layers at the interfaces. The actual barrier height values obtained were further validated by the good agreement between experimental and simulation results for capacitance - voltage characterization. The observation of barrier heights of ~0.653 - 0.663 eV on n-Ge(001) means that Pt-germanides have near zero barrier for hole injection into inverted p-channel, thus ideal for the application as Schottky S/D in Ge pMOSFETs.


G5.3
Impact of Interfacial Layer Control in high-K Gate Dielectrics on GaAs for Advanced CMOS Devices. Goutam Kumar Dalapati¹, Yi Tong¹, Wei Yip Loh² and Byung Jin Cho¹; ¹Dept. of Electrical & Computer Engineering,, National University of Singapore, Singapore, Singapore; ²Institute of Microelectronics,, Singapore, Singapore.

The six times higher electron mobility of GaAs compared to that of Si makes GaAs an attractive candidate for future CMOS devices. However, there is a critical obstacle to GaAs MOS devices, which is the lack of stable and high quality insulators on GaAs that can match the performance of SiO2 on Si. The HfO2 based gate dielectric shown the promising results on Si and GaAs. However, there is still lack of study on the integration of high-K gate dielectric on GaAs. In this work, electrical and interfacial properties of high-K dielectric (Al2O3, HfO2 and HfAlO by atomic layer deposition (ALD), HfO2 and HfGdO gate dielectrics by physical vapor deposition (PVD)) on GaAs substrate will be investigated. The improved interfacial property of HfO2/Gd2O3/GaAs will be discussed in details. MOS capacitors were fabricated on Zn doped p-GaAs (100) wafer. The samples in this work have used HCl cleaning for 30 sec for the removal of surface oxide, followed by (NH4)2S last cleaning for 1 min for S-passivation of GaAs surface. The 6 nm thick high-K dielectric layers were deposited by ALD at a temperature of 300oC. Trimethyl aluminum (TMA, Al(CH)3)3 for Al2O3, hafnium tetrachloride (HfCl4) for HfO2, and water (H2O) were used as precursors, and nitrogen was employed as carrier gas during ALD processes. The HfAlO composite films were formed by alternative cyclic depositions of HfO2 and Al2O3. The 7 nm thick HfO2 and HfGdO dielectric layers were deposited by physical vapor deposition. Thin layer of Gd2O3 (2 nm) was deposited for Gd2O3/HfO2 stack using PVD. Post deposition annealing (PDA) was carried out in a N2 ambient at 500oC-600oC for 1 min by rapid thermal annealing (RTA). TaN gate electrode was formed by sputtering. The HfAlO on p-type GaAs has good electrical properties such as small frequency dispersion, low interface state densities, and lower leakage current compared to single ALD HfO2 or Al2O3. It is also found that the formation of GaxOy at the interface is the key to determine the electrical properties of high-K dielectrics on GaAs substrate. The leakage current of HfAlO on p-type GaAs is a comparable or lower than that of SiO2 on Si for the same EOT. The frequency dispersion of PVD HfO2 can be improved by using the Gd2O3 passivation layer between HfO2 and GaAs. The HfO2/Gd2O3 stack has lower hysteresis voltage and interface trap density compared with single PVD HfO2. The HfGdO gate dielectric can also improve the interface quality and gate dielectric property. In conclusion, ALD high-K gate dielectrics and PVD HfGdO and HfO2 with Gd2O3 passivation on GaAs are demonstrated for gate dielectrics application. TaN/HfAlO/p-GaAs stack shows good electrical properties and better thermal stability. Thin layer of Gd2O3 on GaAs also improves the C-V-shape for HfO2. The low frequency dispersion, interface trap density, and hysteresis voltage have been obtained for Gd2O3/HfO2 stack.


G5.4
Current-Voltage Measurements and Photoconductance Spectroscopy of Ultrathin InAs Grown on (211) Si. Bin Wu¹, Dane Wheeler¹, Qin Zhang¹, Patrick Fay¹, Alan Seabaugh¹, Changhyun Yi², Inho Yoon², April Brown² and T. F. Kuech³; ¹Electrical Engineering, University of Notre Dame, Notre Dame, Indiana; ²Electrical and Computer Engineering, Duke University, Durham, North Carolina; ³Chemical and Biological Engineering, University of Wisconsin-Madison, Madison, Wisconsin.

An approach for forming InAs-channel MOSFETs is being explored in which sub-10-nm thick InAs is grown directly on submicron (211) silicon-on-insulator (SOI) islands. These thin channels are capped with a high-k dielectric consisting of aluminum or hafnium oxide. The (211) orientation is selected to provide a charge neutral growth plane and circumvent the formation of antiphase domains. Since the growth is highly mismatched (11.6 %), submicron device mesas or islands are formed to provide edges to terminate dislocations. The growth is by molecular beam epitaxy (MBE) using growth temperatures under 300 C to suppress islanding. Post-growth annealing is being explored to improve the crystallinity. Gated van der Pauw and FET structures have been designed to explore transport in InAs on Si channels. Current-voltage measurements of Au/Ti/10 nm InAs/p-Si heterostructures show diode characteristics, consistent with the formation of n-InAs/p-Si junctions. Scanning electron microscopy of these first films reveal the formation of islands with an island size ranging from 5 to 25 nm in extent. Current-voltage measurements in the plane of the film show hysteresis and sweep time dependence not present in the vertical transport measurements. Photoconductance spectroscopy measurements at fixed bias and over the spectral range from approximately 1 to 5 microns (1.2 - 0.25 eV) are being used to unravel the transport in these films.


G5.5 TRANSFERRED TO G1.6

G5.6
High-performance Inversion-mode InGaAs/InP MOSFETs Using ALD Al2O3 as Gate Dielectrics. Yi Xuan, Han-Chung Lin and Peide (Peter) Ye; School of ECE, Purdue University, West Lafayette, Indiana.

Atomic layer deposition (ALD) provides a unique opportunity to integrate high-quality gate dielectrics on III-V compound semiconductors. ALD Al2O3 is a high-quality gate dielectric on III-V compound semiconductor with low defect density, low gate leakage, and high thermal stability. The high-quality of Al2O3/InGaAs interface surviving from high temperature annealing is verified by good CV curves showing sharp transition from depletion to accumulation with small hysteresis and frequency dispersion at accumulation capacitance. An inversion-mode n-channel In0.53Ga0.47As/InP MOSFET is demonstrated for the first time by forming the true inversion channel at Al2O3/InGaAs interface. The p-InGaAs was epitaxially grown and doped to 2x10_17/cm_3 with Be. The source and drain regions were selectively implanted with Si and high-temperature activated to produce low resistance ohmic contacts. The drain current of 250 mA/mm is obtained on a 0.75 μm-gate-length device with a strong potential to further increase by optimizing the fabrication process. The threshold voltage, VT, is 0.3-0.5 V and the device shows low gate leakage current. The results from small-signal RF and large-signal RF measurements on this type of devices will also be presented.


G5.7
Material and Electrical Characterization of Nickel Silicide-Carbon as Contact Metal to Silicon-Carbon Source and Drain Stressors Rinus Tek Po Lee¹, Litao Yang¹, Kah-Wee Ang¹, Tsung-Yang Liow¹, Kian-Ming Tan¹, Andrew See Weng Wong², Ganesh S. Samudra¹, Dong-Zhi Chi² and Yee-Chia Yeo¹; ¹Silicon Nano Device Lab, Electrical and Computer Engineering, National University of Singapore, Singapore, Singapore; ²Institute of Materials Research and Engineering, Agency of Science Technology and Research, Singapore, Singapore.

Lattice-mismatched source and drain (S/D) stressors is being actively pursued to enhance carrier mobility and drive current performance of nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). For p-channel MOSFETs, the use of silicon-germanium (SiGe) S/D stressor introduces uniaxial compressive strain in the channel and improves the drive current significantly. Conversely, silicon-carbon (SiC) S/D stressor introduces uniaxial tensile strain in the channel beneficial for n-channel MOSFET drive current enhancement. In order to reap the full benefits of channel strain engineering, it will be imperative to integrate the new materials (i.e. SiGe and SiC) with low resistance silicide technology. Nickel-germanosilicide (NiSiGe) is compatible with SiGe technology and adopted as the contact metal for strained p-channel MOSFETs in high-volume manufacturing. However, literature on the material and electrical characteristics of nickel silicide-carbon (NiSi:C) as contact metal to SiC is currently lacking. In this paper, we present phase analysis of NiSi:C films and electrical characterization of NiSi:C contacts to n⁺/p SiC junctions formed by selective epitaxy of SiC and ex-situ ion implantation. NiSi:C films investigated in this work were formed by rapid thermal annealing in nitrogen ambient for 60 seconds. The incorporation of carbon shows an increase in sheet resistivity for NiSi:C compared to NiSi films for the temperature range of 200 - 600 ^oC. However, sheet resistivity is degraded at elevated temperatures (> 650 ^oC) for NiSi films but suppressed effectively for NiSi:C films. We speculate that carbon segregates into the grain boundaries of NiSi and stabilizes the film morphology/phase. The stabilized NiSi:C film increases the maximum processing temperature available for NiSi by ~ 150 ^oC. X-ray diffraction analysis further revealed that NiSi:C films are textured with a preferred orientation. Current-voltage measurements of NiSi and NiSi:C n⁺/p junctions show similar cumulative distribution for the junction leakage, which implies the incorporation of carbon has a negligible impact on the junction integrity of a MOSFET. Our results suggest that NiSi:C is a suitable self-aligned contact metal to n-channel MOSFETs with SiC S/D stressors in a similar manner to the way in which NiSiGe is used for p-channel MOSFETs with SiGe S/D stressors.


G5.8
A Combinatorial Materials Science Approach to the Ge/HfO2/metal Gate Stack. Nabil D Bassim¹, Kao-Shuo Chang¹, Sandrine Rivillon², Min Dai², Peter K. Schenck¹, Martin Green¹ and Yves Chabal²; ¹National Institute of Standards & Technology, Gaithersburg, Maryland; ²Rutgers University, Piscataway, New Jersey.

Although Ge has the advantages of higher electron and hole mobilities than Si, it has an unstable native oxide (GeO2). Control of the Ge/high-k interface is therefore crucial for proper electrical performance as an alternative channel material. In addition, matching the Ge channel (substrate) with metals of appropriate work-function will be a critical task for the development of Ge-based CMOS. In our study, we build on our experience with Ge-cleaning prior to ALD growth of HfO2 (S. Rivillon, et. al, Appl. Phys Lett, 87,253101 2005) in order to study the effects of Ge substrate pretreatments such as H, S and Si termination (prior to HfO2 growth) on the chemical and electrical properties of the Ge-based gate stack. We use combinatorial methods to optimize the thickness of a Si passivation layer. Using infrared absorption spectroscopy (IRAS) in conjunction with capacitance-voltage and current-voltage measurements, we have studied the structure of the Ge-HfO2 interface, and optimized the resultant electrical properties. Finally, we have applied combinatorial growth methods to study binary (TaN-AlN) and ternary (eg. Ni-Pt-Ti) metal gate systems and measure flatband voltage shifts as a function of metal gate composition.


G5.9
Nanoanalytical Electron Microscope Investigations of Etching Processes for III-V MOSFET Devices. Paolo Longo¹, Jamie Scott¹, Alan James Craven¹, Richard Hill² and Iain Thayne²; ¹Department of Physics and Astronomy, University of Glasgow, Glasgow, United Kingdom; ²Department of Electronics & Electrical Engineering, University of Glasgow, Glasgow, United Kingdom.

Planar Si MOSFET technology, using Si(ON) is rapidly approaching its theoretical limit and the search for new material is essential. n-type GaAs has a mobility 5 times higher than Si. This makes it a suitable candidate for MOSFETs devices. So far, GaAs has not been used for practical MOSFETs because of the difficulties of making a good dielectric oxide layer in terms of leakage current and unpinned Fermi Level [1]. Using processes pioneered by Passlack et al [2], dielectric gate stacks consisting of a template layer of amorphous Ga2O3 followed by GdGaO have been grown on GaAs substrates. The introduction of Gd is important in order to decrease the leakage of current. To produce viable GaAs-based MOSFET devices requires not only high quality gate dielectric stacks but also suitable etching techniques to define the gate and source/drain contacts. Spectrum Imaging (SI) in a scanning transmission electron microscopy (STEM) and Energy Filtering Transmission Electron Microscopy (EFTEM) carried out in a nano-analytical microscope have been shown to be excellent methods to characterise GaAs/Ga2O3/GdGaO materials after processing. Both techniques involve the electrons which have lost part of their initial energy after going through the specimen. This energy is directly related to the chemical structure. SI combines energy electron loss spectroscopy (EELS) with a STEM imaging. In this way is possible to scan the beam across a particular area of the material and get an EELS spectrum for each point in the area. EFTEM consists in the use of a spectromether which has the capability to filter the electron energy. EFTEM complements SI by offering rapid elemental mapping of elemental distributions where the elements are inhomogeneusly distributed. In this way areas for more detailed analysis can also be identified. We are currently investigating a number etching processes on Ga2O3/GdGaO dielectric stack layers. All these samples were prepared in the Department of Electrical and Electronic Engineering in the University of Glasgow (UK). During a dry etching process extra layer can form due to both amorphisation and the redeposition of elements. To know the nature and the elemental composition of these modified layers gives us a big advantage in understanding the outcome of an etching process for the fabrication of MOSFET devices. The combination of SI and EFTEM techniques has allowed us to study in deep the effects of different etching processes on Ga2O3/GdGaO dielectric stack layers. The paper will compare the results obtained from different etching processes. [1] Passlack M., Abrokwah J. K., Droopad R., Sexton J, Kummel A. C., IEEE 23, 508, 2002 [2] Passlack M., Medendorp N., Gregory R. and Braddock, Appl. Phys. Lett., 83, 5262, 2003


G5.10
Strained Si/Si1-xGex/Relaxed Si1-yGey (x>y) Structures: Identifying Roughness Due to Compressed SiGe and Its Impact on High Mobility MOSFETs. Enrique Escobedo-Cousin¹, Sarah H. Olsen¹, Anthony G. O'Neill¹, Olayiwola Alatise¹, Rouzet M.B. Agaiby¹, Peter Dobrosz¹, Glyn Braithwaite², Alan Cuthbertson², Tim Grasby³ and Evan H.C. Parker³; ¹Newcastle University, Newcastle upon Tyne, United Kingdom; ²Atmel North Tyneside, Newcastle upon Tyne, United Kingdom; ³University of Warwick, Coventry, United Kingdom.

Full exploitation of dual channel virtual substrate (VS) MOSFETs requires progress in several technological areas. Ge out-diffusion from the buried strained SiGe layer induces both mobility loss and degraded gate oxide quality. This can be partially alleviated by using a tensile strained Si layer below the strained SiGe since Ge diffusion is retarded in tensile strained Si. A further issue is small-scale roughness due to compressed SiGe. We have recently shown that this roughness severely impacts gate leakage, gate oxide interface trap density and carrier mobility. Surface nMOSFETs are also affected because undulations originating below the surface are transferred to the overlying strained Si electron channel. Until now the effect of the undulations has primarily been evaluated through electrical characterisation. Physical analysis of these undulations is challenging since roughness wavelengths and amplitudes are smaller than those due to VS relaxation. Consequently critical small-scale roughness is often unidentified. In this work we present an efficient and non-destructive technique to extract meaningful roughness data in single channel, dual channel and ‘trilayer’ structures (comprising an additional buried strained Si layer) from AFM measurements using detailed spectral frequency analysis. The extracted roughness parameters correlate well with electrical data from n- and p-MOSFETs in which variations in mobility enhancement, drive current and gate oxide quality result from strain-induced undulations in the buried SiGe. By acquiring very small scale AFM data (1 um2) and implementing wavelength filtering, roughness analysis at lateral scales down to ~20 nm is possible. For the first time AFM is used to show that incorporating a compressively strained SiGe layer below the tensile strained Si surface layer induces roughness with correlation lengths and amplitudes relating to carrier mobility. By studying a matrix of structures we show that roughness in dual and trilayer structures is dominated by compressive strain in the SiGe as opposed to the actual Ge content in either the VS or the compressed SiGe. For structures having identical surface Si strain (0.6%), the rms roughness of wavelength components < 750 nm increases from 0.2 to 2.7 nm for an increase of 0.4% strain in the buried SiGe layer (35% Ge compared with 25% Ge, on a 15% Ge VS). There is a corresponding change of 20% in electron mobility at high fields, where surface roughness scattering dominates. Single channel structures with equivalent strain yield filtered rms roughness < 0.04 nm. The filtered roughness correlation lengths and amplitudes are also found to be highly dependent on compressive strain; in strained Si0.65Ge0.35 the correlation length and amplitude are 200 nm and 12 nm, respectively. Roughness data are confirmed by TEM. Multiple batch runs demonstrate that the results are repeatable and should be considered in the design of high-speed CMOS architectures using SiGe.


G5.11
Embedded SiGe Source/Drains and Buried SiGe channels: A Successful Combination to Increase Drive Current and to Adjust Threshold Voltage in High k pMOS Devices. Roger Loo¹, Haruyuki Sorada², Akira Inoue², Masaaki Niwa², Aude Rothschild¹, Peter Verheyen¹ and Matty Caymax¹; ¹IMEC, Leuven, Belgium; ²assigned to IMEC, Matsushita Electric Industrial Co., Osaka, Japan.

The main problems of Hf-based gate dielectrics with poly-Si gate in p-type Metal Oxide Semiconductor (pMOS) devices are the reduced channel mobility linked with enhanced phonon or charge scattering and the uncontrollable high threshold voltage (VT) that comes from “Fermi level pinning”. It has been shown that these issues can be tackled by using Selective Epitaxial SiGe Growth. Embedded strained SiGe grown in the recessed Source/Drain areas is a generally accepted method to improve device performance. The embedded SiGe results in uniaxial strain in the Si channel which leads to an enhanced hole mobility. Besides, it results in a reduction of the contact resistance which also contributes to the drive current enhancement. The presence of a buried SiGe channel underneath the gate is another way to compensate the mobility loss induced by the high k gate. The main purpose of implementing buried SiGe channels in pMOS devices is to adjust the threshold voltage to the desired value. The combination of both schemes is a logic next step in this development. In this presentation we discuss the requirements on the epitaxial growth process to successfully combine both integration schemes. Conventional epitaxial growth by Chemical Vapor Deposition is used for both epi steps. During the second deposition step, SiGe re-growth on the recessed Source/Drain areas, epitaxial layers are grown on both Si and SiGe surfaces. We will describe the important parameters that can effect the quality of the buried SiGe channel during the second epi step. Device results demonstrate the feasibility to combine buried SiGe channels with embedded SiGe in the Source/Drain areas. The improvement in drive current is mainly attributed to the embedded SiGe in the Source/Drain areas, while the buried SiGe channels simultaneously allow to adjust the threshold voltage to the desired value.


G5.12
Electrical and Physical Characterization of ALD-grown HfO2 Gate Dielectrics on GaAs (100) Substates with Sulfur Passivation. Eunji Kim¹, Joseph Chen¹, Donghun Choi², Niti Goel³, Chi On Chui³, Wilman Tsai³, James Harris², Yoshio Nishi², Krishna Saraswat² and Paul C. McIntyre¹; ¹Materials Science and Engineering, Stanford University, Stanford, California; ²Electrical Engineering, Stanford University, Stanford, California; ³Intel Corporation, Santa Clara, California.

IIIV semiconductor-based field effect transistors are receiving increased attention among research groups due to their potential for very high electron mobility and low power dissipation. However, achieving IIIV-based metal-oxide-semiconductor devices remains very challenging in part because deposition of high-quality gate dielectrics on the channel may produce subcutaneous oxidation of the IIIV material, leading to a high density of interface defects which are difficult to passivate. We have investigated the electrical and physical properties of W/HfO2/p GaAs MOS capacitors with and without sulfur passivation prior to HfO2 deposition. ALD-grown HfO2 on non-treated epitaxial GaAs shows very promising CV characteristics, including an apparent dielectric constant of 15 (which includes the effects of an interface layer) and low leakage current density. After performing a rapid thermal anneal at 450 degrees for 2mins in N2 ambient, the HfO2 film showed improved film properties, such as reduction in CV hysteresis, recovery of a near-ideal flat band voltage and an increase in gate capacitance density. ALD-HfO2 deposited on S-passivated GaAs showed a decrease in CV hysteresis relative to non-treated GaAs, without sacrificing capacitance. Physical properties of the film such as surface roughness, film thickness, and density were also studied by AFM, XRR, and XPS. The mechanisms for improvements in MOS electrical properties as a result of pre-deposition and S treatment and post-deposition anneals will be discussed.


G5.13
Abstract Withdrawn


G5.14
Abstract Withdrawn


G5.15
Ni-germanide Contacts on Ge: Phase Formation and Electrical Characterization. Karl Opsomer^1,2, Eddy Simoen¹, Christophe Detavernier³, Anne Lauwers¹, Christian Lavoie⁴, Roland Vanmeirhaeghe³ and Karen Maex^1,2; ¹IMEC, Leuven, Belgium; ²Electrical Engineering Department (ESAT), Katholieke Universiteit Leuven, Leuven, Belgium; ³Solid-State Sciences Department, Universiteit Gent, Gent, Belgium; ⁴IBM T.J. Watson Research Center, Yorktown Heights, New York.

The interest in using germanium (Ge) as an alternative substrate for ultimate CMOS transistors has been a strong motivation for the recent research activities on germanide formation.[1-3] In particular, Ni germanides are likely put forward as candidates to contact the Ge devices at source, drain and gate, similarly as is done with silicides on Si based devices. In addition, although a considerable understanding on solid-state phase formation and phase stability is relatively well established, still some aspects are less well understood, such as the initial phase formation (selection of the first phase), the influence of texture in the growing film, the evolution of stress during film growth. Therefore studying metal-Ge reactions might contribute to the further understanding of compound formation. In a first part, we present the results on the solid-state reactions between Ni and Ge substrates, studied by a variety of complementary in-situ and ex-situ characterization techniques. In-situ techniques as XRD, sheet resistance, substrate curvature and diffuse light scattering are carried out during the reaction of Ni layers with different thickness, on different Ge-substrates: Ni layers of 10, 30, 90, and 500 nm and Ge substrates of different crystallinity (Ge(100), Ge(111), p-Ge and a-Ge) are investigated. The combination of complementary techniques in our results, show some subtle aspects when compared to ex-situ alternatives. Our results are reflected on the current understanding of both Ni germanide phase formation and stress evolution during solid-state reactions. The relation between initial phase formation and stress development in particular will be addressed. In a second part, and in relation with our findings based on pure materials studies aspects, our results on the use of Ni germanides on devices are discussed for selected stages in the reaction. DLTS and current-voltage (I-V) characteristics of Ni-germanide/n-Ge contacts are studied.[3] Our results reveal that a particular behavior is present, dependent on the measurement temperature (78K - 298K). These results are discussed in the scope of the known I-V-characteristics. [1] S. Gaudet, C. Detavernier, A. J. Kellock, P. Desjardins, and C. Lavoie, J. Vac. Sc. Technol. A 24 (3), 474 (2006). [2] F. Nemouchi, D. Mangelinck, C. Bergman, G. Clugnet, P. Gas, and J. L. Labar, Appl. Phys. Lett. 89 (13), 131920 (2006). [3] E. Simoen, K. Opsomer, C. Detavernier, R.L. Van Meirhaeghe, K. Maex, and P. Clauws, Appl. Phys. Lett. 88 (18), 183506 (2006)


G5.16
Gate-all-around (GAA) Fully Depleted (FD) Cantilever Channel MOSFET with high-κ Dielectric and Metal Gate. Sagnik Dey¹, Sachin V Joshi², Se-Hoon Lee³, Prashant Majhi⁴ and Sanjay K Banerjee⁵; ¹Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas; ²Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas; ³Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas; ⁴Intel Assignee, Sematech, Austin, Texas; ⁵Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas.

A MOSFET formed by a Si cantilever channel suspended between source/drain “anchors” wrapped all-around by high-κ dielectric and metal gate is demonstrated. The device shows excellent subthreshold characteristics and low leakage currents due to the fully depleted body and the gate-all-around architecture. At the same time this also allows a high drive current due to mobility enhancements arising from volume inversion of the cantilever channel such that a large I_ON/I_OFF is achieved. As devices are scaled down below the 45nm nodes, controlling 2D parasitic effects in transistors and subthreshold leakages would require such thin gate-dielectrics even for novel architecture devices that conventional SiO2 would need to be replaced by high-κ dielectrics from both manufacturability and gate-oxide-integrity point of view. However, one of the major issues for integrating a high-κ gate-dielectric is reduced mobility arising out of higher surface scattering. In this paper we propose a thin body cantilever channel MOSFET architecture surrounded by a high-κ dielectric and metal gate formed by atomic layer deposition (ALD) that is able to address all these issues and provide an attractive alternative for performance enhancements as devices are scaled down. The GAA architecture of the device leads to excellent suppression of subthreshold leakages and short channel effects due to better gate control and thin body while use of high-κ dielectric replacing conventional SiO₂ helps to lower gate leakage for the required effective-oxide-thickness. The thin body GAA channel leads to overlap of the inversion charge densities from the all-around gate in such a way that the entire body of the channel is inverted. As a result, the inversion charge centroid shifts from the surfaces towards the bulk of the channel such that surface scattering is significantly reduced leading to mobilities higher than the universal electron mobility even using a high-κ dielectric. The proposed integration of high-κ dielectric this way in such a device architecture might be an attractive solution to mitigate the high-κ/Si interface problems and sustain scaling beyond 45nm nodes. The Si cantilever channel devices (~100nm thick) were fabricated from silicon-on-insulator wafers by selectively etching off the buried oxide layer underneath the channels which remains suspended as a cantilever between the source and drain. HfO₂ and TaN were then used as the gate stack to wrap around this cantilever by a ALD process. To the best of our knowledge this is the first instance of ALD high-κ and metal gate being used in such GAA architecture. The fabricated n-MOSFETs show low off-state leakage currents (<10nA/μm at V_D=1.2V,V_G=0V), high drive currents (~1.4mA/μm at V_D=1.2V) and near-ideal subthreshold characteristics (~65mV/dec). In conclusion, the proposed device can be an attractive alternative to integrate high-κ dielectric with novel 3D MOSFET architecture to enhance performance beyond 45nm nodes.


G5.17
Sub-30 nm FinFETs with Schottky-Barrier Source/Drain Featuring Complementary Metal Silicides and Fully-Silicided Gate for P-FinFETs Rinus Tek Po Lee¹, Kian Ming Tan¹, Tsung-Yang Liow¹, Andy Eu-Jin Lim¹, Guo-Qiang Lo², Ganesh S. Samudra¹, Dong-Zhi Chi³ and Yee-Chia Yeo¹; ¹Silicon Nano Device Lab, Electrical and Computer Engineering, National University of Singapore, Singapore, Singapore; ²Institute of Microelectronics, Agency of Science Technology and Research, Singapore, Singapore; ³Institute of Materials Research and Engineering, Agency of Science Technology and Research, Singapore, Singapore.

Dimensional scaling has been the main driver for complementary metal-oxide-semiconductor (CMOS) technology and has provided significant improvements in integrated circuit density and device performance. However, continual dimensional scaling into the nanoscale regime has led to immense technological challenges; therefore non-classical transistor structures, e.g. double-gate or triple-gate transistors, are needed to further extend the limits of device performance. In addition, various ‘technology boosters’ such as metal gate electrodes and metallic source/drain regions (e.g. metal silicides) could be implemented in these device structures. In this paper, fin field-effect transistors (FinFETs) with gate-lengths down to 25 nm integrated with Schottky-barrier source/drain were fabricated. Complementary low barrier self-aligned ytterbium and platinum silicides were used to reduce the contact and series resistances. Due to the low electronegativity parameter of ytterbium, a low temperature silicidation process was developed to avoid the reaction of ytterbium with the isolation regions (i.e. SiO₂ and SiN). The fabricated minimum gate-length transistors with gate oxide thickness of 30 Å exhibits N-FinFET |I_DSAT|= 241 μA/μm and P-FinFET |I_DSAT| = 211 μA/μm at V_DS = |V_GS - V_T| = 1V and I_on/I_off > 10⁴. The integration of fully-silicided (FUSI) metal gate into P-FinFETs was also explored in this work. A novel silicidation process that integrates simultaneously two different phases of platinum silicide with the appropriate work function values for gate electrode and source/drain application was demonstrated. Compared to poly-Si gate P-FinFETs, platinum-rich FUSI gate P-FinFETs exhibit significantly higher I_DSAT due to the elimination of poly-Si gate depletion effects.


G5.18
Abstract Withdrawn

G5.19 TRANSFERRED TO G1.5

G5.20
Abstract Withdrawn


G5.21
Fermi Level Position at YbGe/Ge(001) Interface and Schottky Barrier Height Determined by X-ray Photoelectron Spectroscopy Cheng-Cheh Dennis Tan, Haibiao Yao, Jian Wei Chai, Jisheng Pan and Dongzhi Chi; Institute of Materials Research & Engineering, Singapore, Singapore.

Rare-earth metal silicides, for example ErSi2 and YbSi2, have been shown to have low contact resistance for n-Si due to its low schottky barrier. It was therefore perceived that rare-earth germanides would also be good candidates as contact materials for Ge nMOSFETs. However, recent studies have shown that it is not the case. For example, though having its Fermi level almost perfectly aligned with the conduction band edge Ec of Ge[1], a relatively high Schottky barrier height has been observed for Er-germanide fromed on n-Ge(001). Expecting a similar behavior with Yb-germanide, in this work, we performed XPS characterization of Yb-germanide formed on Ge(001) in order to extract its Schottky barrier height. For the XPS measurement, we first collected the valence band spectra of pure Ge. Next, using an e-beam evaporator and a heating chuck mounted to the UHV preparation chamber of the XPS, we measured the XPS spectra of YbGe/Ge(001), which was formed by evaporating a thin layer (~6nm) of Yb on Ge(001) followed by annealing at 350°C for 60s. Using Ge3d core-level as reference to correct charge effects, we determined the Fermi-level Ef of YbGe relative to the valence band edge Ev of Ge at YbGe/Ge interface. The XPS result shows that Fermi-level of YbGe is virtually pinned to Ev with Ef - Ev ~ -0.10 eV, which appears to be in agreement with the result of I-V characterization of YbGe/n-Ge(001) diode where an effective barrier height of ~ 0.62 eV was obtained. This surprising finding suggests that, though it is not a suitable contact material for Ge nMOSFETs, YbGe appears to be a good candidate for the use as contact material in Ge pMOSFETs, due to its near zero (or even negative) barrier height to inverted p-channel and also considering its low resistivity which is comparable to that of NiGe. [1] Yoshinori Tsuchiya, Masato Koyama, Junji Koga, and Akira Nishiyama, Extended Abstracts of 2005 International Conference on Solid State Devices and Materials (SSDM), pp.844-845, Sep. 2005, Kobe, Japan


G5.22
Implications to Work Function Modulation from Metal-Oxide Interface Configurations: Case of Study HfO2 and SiO2. Blanka Magyari-Kope¹, Yoshio Nishi¹, Luigi Colombo² and Kyeongjae Cho³; ¹Electrical Engineering, Stanford University, Stanford, California; ²Texas Instruments Inc., Dallas, Texas; ³Physics and Electrical Engineering, University of Texas, Dallas, Texas.

A number of metal electrode materials are currently being investigated to identify the suitable candidate for the next generation of MOSFETs. The specific metal electrode’s behavior on high-k gate dielectric oxide films is influenced by the interface chemical reactions and defects. In this study, ab initio calculations are employed to investigate and analyze a number of possible interface structures between gate dielectric oxides, HfO2 and SiO2, and metal electrodes. In addition, model interface systems of metal bi-layers are constructed based on structural and compositional heterogeneity and are used as input configurations in the quantum mechanical calculations. The structural stability and electronic structure of the interfaces with implications to metal work functions are discussed. In particular, we find that the work function of metals on oxide is significantly influenced by the interface configurations and by the particular bonding pattern at the interface, yielding evidence for strong structure-composition-property correlations. It is also found that one or two atomic layers of the underlying metal shift the work function of double-layers to that of underlying metal.