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Symposium B: Materials and Devices for “Beyond CMOS” Scaling

Symposium B: Materials and Devices for “Beyond CMOS” Scaling Image

The continuation of evolutionary scaling of complementary metal-oxide semiconductor (CMOS) transistor devices becomes increasingly problematic owing to short channel effects and excessive power dissipation. Revolutionary device concepts–disruptive approaches–based on noncharge logic variables, are therefore extremely important for enabling “beyond CMOS” scaling in about 15-20 years from now. Potential advantages include low-power dissipation at extremely high switching speeds and scalability down to one-to-a-few nanometer length scales and highly integrated functionalities that are not possible with conventional field-effect transistors.

This symposium will focus on materials and device technologies that can enable realization of novel information processing technologies of relevance in the time frame after 2019. Examples include, but are not limited to, phase transitions among multiple local phase states, biological neural networks, spin-orbit interactions in complex oxides, etc. The symposium will emphasize revolutionary concepts incorporating functional materials that are of relevance to nanoscale logic and memory technologies. Theoretical approaches of novel devices incorporating nanoscale materials are also of interest.

This one-day symposium will be composed of invited talks and contributed posters.

Abstracts are solicited in, but not limited to, the following areas:

  • Phase transitions
  • Neural networks
  • Low-power-device approaches
  • Noncharge-based switching approaches
  • Spin-based devices
  • Complex oxide devices
  • Biologically inspired computing
  • Molecular-CMOS hybrids

Invited speakers include (partial list): R. Cavin (SRC: Semiconductor Research Corporation), R. Cowburn (Imperial College London, United Kingdom), G. de Micheli (Swiss Federal Inst., Lausanne, Switzerland), P. Gargini (Intel Corp.), M. Kawasaki (Tohoku Univ., Japan), A. Khitun (Univ. of California-Los Angeles), A. Kis (Univ. of California-Berkeley), and J. Tour (Rice Univ.).

Symposium Organizers

Shriram Ramanathan
Harvard University, School of Engineering and Applied Sciences, 29 Oxford St., Cambridge, MA 02138
Tel 617-496-0358, Fax 617-495-9837, shriram@deas.harvard.edu

George Bourianoff
Intel Corporation, MS PTL, 1501 S. MOPAC Expwy., Austin, TX 78703
Tel 512-732-3947, george.i.bourianoff@intel.com

Adrian Ionescu
Swiss Federal Institute of Technology, Ecole Polytechnique Fédérale de Lausanne, Micro & Nanoelectronics Laboratory of Micro/Nanoelectronic Devices (LEG2), Rm. ELB 335, Station 11, CH-1015 Lausanne, Switzerland
Tel 41-21-693-3978, Fax 41-21-693-3640, adrian.ionescu@epfl.ch



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