1:30 pm – 2:45 pm

Part I: Peide Ye
Dielectric Engineering for III-V 3D MOS Technology

High mobility materials offer distinct advantages over Si in achieving high performance at low supply voltages, thus reducing power consumptions and enabling a high performance “green” IC technology. Many encouraging results on these new channel materials such as III-V and III-N using high k dielectrics have been obtained lately, but stringent demands in terms of electrical performance, oxide thickness scaling, variability and reliability are still needed for manufacturing technology. We will review the significant progress in the past decade on dielectric research on III-V and III-N by atomic layer deposition and provide some insights to make III-V and III-N 3D MOS viable for future high-speed low-power logic and RF power applications.   

2:45 pm – 3:15 pm   BREAK

3:15 pm – 4:30 pm

Part II: Asif Khan
Negative Capacitance FETs—Physics, Materials and Devices

Future scaling of FETs demands a reduction in power dissipation and a sharpening of the ON/OFF switching characteristic of the FET. Negative capacitance FET (NCFET) is one of the options. This novel device technology promises an enormous reduction in power dissipation that is achieved by replacing the gate dielectric of a MOSFET by a negative capacitance material, which leads to two important effects in the transistor characteristics: sub-60 mV/decade switching and a high on-current. This tutorial will give an overview of the exciting developments in the field of negative capacitance over the past nine years starting from the theoretical prediction in 2008 to the clean experimental demonstration of this phenomenon in ferroelectric materials and transistors recently. All three aspects of this technology: physics, materials and devices will be discussed.

4:30 pm – 5:00 pm

Panel Discussion on III-V 3D MOS and NCFET

Instructors

• Peide Ye, Purdue University
• Asif Khan, Georgia Institute of Technology