Symposium Organizers
Geraud Dubois IBM Almaden Research Center
Mikhail Baklanov IMEC
Christian Dussarrat Air Liquide
Terukazu Kokubo JSR Tsukuba Research Laboratories
Shinichi Ogawa National Institute of Advanced Industrial Science and Technology
Symposium Support
Air Liquide
Air Products
Applied Materials Inc
GLOBALFOUNDRIES
IBM Almaden Research Center
JSR Micro Inc
Tokyo Electron America
O1: Low-k Materials I
Session Chairs
Griselda Bonilla
Geraud Dubois
Tuesday PM, April 26, 2011
Room 3000 (Moscone West)
9:15 AM - **O1.1
Development of Ultralow-k pSiCOH Dielectrics and Implementation in Interconnect Technology.
Alfred Grill 1 , Stephen Gates 1 , E.Todd Ryan 2
1 , IBM -T.J. Watson Research Center, Yorktown Heights, New York, United States, 2 , GLOBALFOUNDRIES, Albany, New York, United States
Show AbstractThe first low-k PECVD SiCOH dielectrics were introduced in the interconnects of VLSI chips at the 90 nm technology node. The need to maintain or even reduce the interconnect capacitance at the decreasing dimensions of later technology nodes led to the development of porous ultralow-k pSiCOH. The first generation of pSiCOH dielectrics with k=2.4 has been successfully integrated by IBM in 45 nm products, such as the Power 7 chip. Material extendibility of pSiCOH has been demonstrated to k values as low as 2.0. However, the reduction of the dielectric constant is achieved for a given chemistry by increasing porosity in the films, which causes a decrease of mechanical properties and degraded integrability of the dielectric, and potentially reduced reliability of the interconnect.Several chemistries used for the deposition of pSiCOH have been investigated for improving the properties of the films and their integration compatibility. The original chemistry produced the V1 pSiCOH films with a skeleton of O-Si-O bonds, with nanometer sized pores stabilized by Si-CH3 groups. These films are prone to plasma damage during the integration process and the degree of damage increases with decreasing k and decreasing pattern dimensions. To alleviate such problems we developed pSiCOH films using precursors containing Si-CH2-Si bonds. These chemistries enabled the fabrication of V2 and V3 type films whose skeleton comprises Si-CH2-Si bonds in addition to the Si-O-Si bonds and the terminal Si-CH3 groups. The V2, V3, high-carbon pSiCOH films have improved pore structures, higher resistance to plasma damage and provide improved dimension control during integration compared to V1 pSiCOH of identical k values. The talk will discuss the fabrication of the different dielectrics, the effects of the chemistries on the porosity structure of the different flavors of pSiCOH, their mechanical properties and the behavior under integration processing.This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.
9:45 AM - **O1.2
Ultra Low-k Materials Based on Self-assembled Organic Polymers.
Marianna Pantouvaki 1 , Larry Zhao 2 , Craig Huffman 1 , Kris Vanstreels 1 , Patrick Verdonck 1 , Yukiharu Ono 3 , Michio Nakajima 3 , Koji Nakatani 3 , Gerald Beyer 1 , Mikhail Baklanov 1
1 , Imec, Leuven Belgium, 2 , Intel, Leuven Belgium, 3 , Sumitomo Bakelite Co, Ltd, Yokohama Japan
Show AbstractInterconnect scaling requires low-k materials with dielectric constant < 2.5 for the 22 nm technology node and beyond. Typical low-k materials that are being studied for interconnect applications are variations of porous carbon-doped silicon dioxide. The incorporation of porosity in such SiOCH materials is done by introducing a porogen that is later removed by thermal treatment. The hybrid nature of such materials makes possible to increase porosity and consequently reduce the k-value, however it is accompanied by large pore size, hydrophilization upon exposure to certain plasmas or porogen residues, which can result in increased k-value and leakage current after integration. Organic polymers on the other hand are mono-component materials with virtually no polar bonds and, as such, they can be made with smaller pore size and more resistive to hydrophilization and plasma damage. Recently, we demonstrated successful integration of an advanced organic polymer to spacing varying from 80 nm to 20 nm. In this paper we discuss the key material properties that enabled these results. Electrical characterization of the impact of etch, PVD barrier process and surface treatment, is done using a planar capacitor test vehicle. By variation of the polymer consistency, the material properties can change. A comparison of the electrical properties of two versions of organic polymers is also presented in this study. The two polymers vary in terms of different functional groups that each of them contains and they also have different degrees of open porosity, as measured by toluene-based elipsometric porosimetry. Larger open porosity is found to be accompanied by higher leakage current. This implies a correlation of porosity/pore connectivity with the leakage mechanism in such materials. Higher leakage current however was not linked to faster dielectric breakdown, which suggests that the breakdown mechanism is related to the core material structure.
10:15 AM - O1.3
Molecularly Reinforced Sol-gel Glasses with Improved Pore-size Distribution.
Willi Volksen 1 , Geraud Dubois 1 , Theo Frot 1 , Teddie Magbitang 1 , Phil Rice 1 , Leslie Krupp 1 , Sebastian Engelmann 2 , Robert Bruce 2 , Sampath Purushothaman 2 , Hisashi Nakagawa 3 , Manabu Sekiguchi 3 , Terukazu Kokubo 3
1 , IBM Almaden Research Center, San Jose, California, United States, 2 , IBM T.J., Watson Research Center, Yorktown Heights, New York, United States, 3 , JSR Tsukuba Research Labs, Tsukuba, Ibaraki, Japan
Show AbstractWe have previously reported on the reinforcement of sol-gel glasses via carbon-bridging units between silicon atoms to yield organosilicate network structures with improved fracture energy and Young’s modulus [1,2,3,4]. This led to the development of a first generation, k = 2.0 organosilicate resin formulation, LKD 6504, which could be prepared on a large scale and met all the material requirements for integration, e.g. solution stability, low metal-ion contamination and excellent processability. However, high pore interconnectivity coupled with high levels of mesoporosity appeared to be responsible for severe strip and cap-open plasma damage. This plasma damage in the form of pitting, line-bottom roughness and microtrenching made it virtually impossible to integrate this material.As a result, a second-generation molecularly reinforced sol-gel glass was developed with the goal to minimize the mesoporous character at the higher porosities, without significantly impacting the mechanical properties. In this presentation we will describe the performance of new, improved molecularly reinforced sol-gel glasses at dielectric constants ranging from 2.4 to 1.8, with particular emphasis on mechanical properties and plasma resistance.[1] G. Dubois, W. Volksen, T. Magbitang, R.D. Miller, D. Gage, R. Dauskardt, Adv. Materials, 2007, 19 (22), 3989-3994.[2] G. Dubois, W. Volksen, T. Magbitang, M. Sherwood, R.D. Miller, D. Gage, R. Dauskardt, J. Sol-Gel Sci. & Techn., 2008, 48 (1-2), 187-193.[3] G. Dubois, W. Volksen, R.D. Miller, Dielectric Films for Advanced Microelectronics, M. Baklanov, K. Maex, M. Green (Editors), Wiley, 2007, Chapter 2.[4] W. Volksen, R.D. Miller , G. Dubois, Low-K Dielectric Materials, Chemical Reviews, 2010, 110 (1), 56-110
10:30 AM - O1.4
New Designs of Hydrophobic and Mesostructured Ultra Low k Materials with Isolated Mesopores.
Anthony Grunenwald 1 , André Ayral 1 , Pierre Antoine Albouy 2 , Vincent Rouessac 1 , Patrice Gergaud 4 , Christophe Licitra 4 , David Jauffres 3 , Marc Verdier 3 , Aziz Zenasni 4 , Vincent Jousseaume 4
1 , European Membrane Institute, Montpellier France, 2 , Laboratoire de Physique des Solides, Orsay France, 4 , CEA-LETI-MINATEC Campus, grenoble France, 3 , SIMAP-INPG, Grenoble France
Show AbstractFor advanced technology nodes, integration of highly porous dielectrics into microelectronic interconnection is required to reach dielectric constant values lower than k = 2.5 (ultra low k ULK). However, such porous materials exhibit low mechanical strength and potential loss of electrical performances due to impurity migration through open and interconnected porosity, particularly water diffusion. Consequently, typical amorphous porous materials have to face integration steps damage. At a given porosity level, mechanical models predict that ordering porosity induces an improvement of the mechanical strength and a minimal interconnection between pores. Whereas PECVD could only provide amorphous interconnected porous materials, spin-coating deposition opens a wide process window to tailor structure and porosity features. In this way, new designs of ULK materials with closed, ordered porosity, hydrophobic walls and appropriate mechanical properties could be suitable for interconnected applications. Nevertheless, the preparation of such materials still remains a big challenge. In this work, hydrophobic mesostructured organosilica thin films, exhibiting isolated mesopores (3-5 nm), have been successfully deposited by spin-coating using different polystyrene-block-polyethylene oxide copolymers (PS-PEO) as structure-directing agents and methyltriethoxysilane (MTES) as organosilica precursor. Different ordered mesostructures (Face Centered Cubic, 2D Hexagonal and Body Centered Cubic) can be achieved by controlling different synthesis parameters. X-Ray Diffraction (1D and 2D) techniques were used to investigate the mesostructure evolution through thermal and UV treatments. Swelling and shrinkage were, successively, evidenced by in-situ XRD and X-Ray Reflectivity measurements during the thermal removal of the meso-templates. Infrared spectroscopy, 29Si NMR and X-ray Photoelectron Spectroscopy were additionally used to investigate the microstructure evolution. The film porosity was estimated thanks to ellipsometry porosimetry. Isotherms with broad hysteresis loops were observed due to isolated mesopores only interconnected by the wall ultramicroporosity. Their shape was found to be dependent of the chemical affinity between the organosilica matrix and the adsorbate used. The wall ultramicroporosity was specifically analyzed by gas permeation measurements through films deposited on porous substrates. Correlation between mechanical properties through nanoindentation measurements and the mesostructure ordering will be discussed as well as assessments of the dielectric constant k by mercury contact probe.
10:45 AM - O1.5
Spin-on-dielectric Process for Nanoscale High Aspect Ratio Trenches for Device Isolation.
Suresh Regonda 1 , Eungjae Park 2 , Lisa Spurgin 1 , Wenchuang Hu 1 , Hyunjin Kim 2 , Jaehyun Kim 2 , Moon Kim 1 , Jiyoung Kim 1
1 Electrical Engineering, University of Texas at Dallas, Richardson, Texas, United States, 2 , Dongjin Semichem , Hwaseong-SI, Gyeonggi-Do, Korea (the Republic of)
Show AbstractThe growing aspect ratio (AR) of shallow trench isolation structures (STI) to meet future technologies at 32nm node and beyond, has forced research to turn to alternative methods and materials for void free gap filling. According to ITRS front-end roadmap [1] spin-on-dielectric coating (SOD) will be a promising material to meet the requirements. SOD features excellent surface planarity and conversion to dense SiO2 at low curing temperatures with lower processing cost making it an ideal candidate for void free gap filling with high aspect ratio STIs.In this work, high aspect ratio nano trenches (AR>20, trench width <25nm) were fabricated in silicon by e-beam lithography and plasma etching. Polysilazane based material SOD with an average molecular weight of 10K Da developed by Dongjin Semichem, Korea, was used to demonstrate excellent gap filling throughout the nanoscale trenches [2]. SEM analysis was performed for visual confirmation of the fill quality and dimensions of interest. To ensure desirable electrical performance and structural integrity of the resulting device, the samples were implanted with arsenic ions with shallow junction depths (<50 nm) followed by depositing metal contacts for electrical characterization (I-V, C-V characteristics). In the paper, we will present results of physical, chemical properties of SOD before and after curing, and also electrical properties such as low k dielectric constant, low leakage current and higher breakdown voltage in the filled nano-trenches that simulates STI for 32 nm and 22 nm node MOSFET devices.[1] ITRS Front-End Roadmap, (2009).[2] Krutarth Trivedi, et al., J. Vac. Sci. Technol. B. 27(6), pp. 3145-3148, (2009).
11:30 AM - **O1.6
Molecular Structure and Design of Ultra-low-k Hybrid Glasses.
Reinhold Dauskardt 1 , Mark Oliver 1 , Geraud Dubois 2
1 , Stanford University, Stanford, California, United States, 2 , IBM Almaden, Almaden, California, United States
Show AbstractHybrid organic-inorganic glass films processed from small organosilane precursors exhibit unique electro-optical properties while maintaining excellent thermal stability. Processed using either sol-gel or plasma-enhanced chemical vapor deposition they have application in emerging CMOS, nanoscience and energy technologies. A fundamental challenge for their integration, however, remains their inherently mechanically fragile nature that derives from the oxide component of the hybrid network and the presence of terminal hydroxyl and organic groups that reduce network connectivity. Also, to achieve ultra-low dielectric properties (i.e k < 2.4) nanoporous forms of the hybrid films are required which further reduce mechanical properties. We describe the development of computational methods to address the fundamental relationship between molecular structure and resulting mechanical and fracture properties of organosilicate glasses. Using molecular dynamics and a simulated annealing approach, large distortion-free hybrid glass networks with well-controlled network connectivity can be generated. With this capability along with a novel fracture model and molecular dynamics simulations of elastic deformation, we elucidate the critical effect of network connectivity and nanoporosity on mechanical properties. The accuracy of our computational tools is confirmed through comparison to synthesized hybrid films where the molecular structure, connectivity and nanoporosity is carefully controlled. Having predictive models for how molecular structure affects mechanical properties offers the opportunity for computational design of new glasses and provides a quantitatively accurate rationale for guiding precursor selection. Thus in addition to the fundamental insights gained regarding structure-mechanical property relationships, we will present our efforts to apply these tools to design new neat and nanoporous glasses with exceptional mechanical properties and low density.
12:00 PM - O1.7
Atomic-scale Modeling of the Mechanical Behavior of Ultra-low-dielectric-constant Mesoporous Amorphous Silicate Films.
Rauf Gungor 1 , James Watkins 2 , Dimitrios Maroudas 1
1 Chemical Engineering, University of Massachusetts, Amherst, Massachusetts, United States, 2 Polymer Science and Engineering, University of Massachusetts, Amherst, Massachusetts, United States
Show AbstractModern semiconductor devices require ultra-low-dielectric-constant (ULK) dielectric materials to eliminate the capacitive coupling between closely spaced interconnect lines. The mechanical strength of ULK dielectric materials is particularly important for the structural integrity and overall reliability of the microelectronic devices under the severe thermomechanical loading conditions characteristic of semiconductor manufacturing processes, chip packaging, and device service. Among materials that are being developed for ULK applications, porous amorphous silicate films are considered primarily due to their compatibility with current semiconductor manufacturing technologies. In this presentation, we report results of molecular-dynamics (MD) simulations of the mechanical response to various mechanical loading conditions of film structures of mesoporous amorphous silica with pore diameters of a few nanometers, as well as predictions of their mechanical properties. The MD simulations employ a validated classical potential that includes two-body and three-body interatomic interactions. The normal-density amorphous silica structures are prepared through MD, starting from a beta-cristobalite crystalline structure and following a thermal processing sequence that includes melting, rapid quenching, and a thermal annealing schedule. We have generated regular mesoporous structures through the introduction of various geometric arrangements of spherical or cylindrical pores by removal of atoms from the normal-density amorphous silica matrix and subsequent thermal annealing at the temperature of interest to ensure proper structural relaxation. We present a systematic analysis of the mechanical response of these regular mesoporous amorphous silica structures under applied strains within the elastic limit near room temperature; the analysis employs large-size computational supercells and is based on MD simulations of dynamic straining followed by isostrain MD simulations. We have computed the elastic moduli of mesoporous structures with spherical pores arranged in simple cubic lattices and with cylindrical pores in square and hexagonal lattice arrangements. We have analyzed the stability of these structures under tensile and compressive straining as a function of density, pore diameter, and, for cylindrical pore arrangements, pore orientation with respect to the direction of loading. Furthermore, we have analyzed the effects of high-temperature thermal treatment of the mesoporous amorphous structures on their structural stability and mechanical strength in correlation with the underlying microstructural evolution.
12:15 PM - O1.8
Molecular Design of High-stiffness ULK Glasses for Mechanically Robust Interconnects.
Mark Oliver 1 , Geraud Dubois 2 1 , Theo Frot 2 , Mark Sherwood 2 , Reinhold Dauskardt 1
1 , Stanford University, Stanford, California, United States, 2 , IBM Almaden Research Center, San Jose, California, United States
Show AbstractThere is a critical need for materials design methods for optimizing the molecular and pore structures of the increasing number of nanoporous ULK (k < 2.4) layers which make the BEOL thermo-mechanically weak. This is becoming ever more important with increases in die size, the development of 3D integration schemes, and the use of Pb-free solders which all result in higher mechanical constraint and stress. In order to design mechanically robust ULK materials at the molecular level, we have been developing a modeling approach that uses molecular dynamics to assemble large molecular models from any combination of organosilane precursors. These models can then be used to simulate elastic stiffness via molecular dynamics simulations and fracture properties using our minimum-cut fracture model. In this presentation, we will demonstrate how a synergistic use of these computational modeling methods along with chemical synthesis and experimental characterization can lead to discovery of novel strategies for enhancing ULK mechanical properties. Specifically, we will discuss the discovery of the exceptional elastic properties of glasses processed from 1,3,5 triethoxysilyl benzene which exhibit twice the elastic modulus of ethane-bridged glasses at a given connectivity. Glasses processed from this precursor were first predicted by molecular modeling to exhibit exceptionally high stiffness for their density. Based upon these predictions, the precursor 1,3,5 triethoxysilyl benzene was synthesis and sol-gel glass films prepared. Solid-state 29Si NMR of the synthesized glasses revealed a small degree of precursor fragmentation during processing. This structural information was then fed back into the molecular model to generate highly accurate models of the synthesized glasses. This enabled us to make direct comparison between the model and experimental data, confirming the quantitative accuracy of the model prediction and the exceptional properties of 1,3,5-benzene glasses.
12:30 PM - O1.9
High Toughness and Moisture-insensitive Hydrogenated Amorphous Silicon Carbide Dielectric Films.
Yusuke Matsuda 1 , Sean King 2 , Jeff Biefield 2 , Reinhold Dauskardt 1
1 , Stanford University, Stanford, California, United States, 2 , Intel Corporation, Hillsboro, Oregon, United States
Show AbstractHydrogenated amorphous silicon carbide (a-SiC:H) are attractive candidates for a number of nanoscience applications including CMOS and MEMS/NEMS technologies due to their widely tunable materials properties and chemical inertness. In the present study, we investigated the fracture of a-SiC:H dielectric thin films with widely varying materials properties. The fracture energy of flms with stoichiometric composition decreased linearly with decreasing average bond coordination number. However, a-SiC:H films with non-stoichiometric composition (excess carbon content) exhibited a surprisingly high fracture energy which was attributed to crack tip plasticity. Solid state 13C NMR revealed the existence of organic carbon chains responsible for the plastic behavior. We show that the amount of plasticity increased with increasing organic carbon chain content. All of the a-SiC:H films exhibited a low sensitivity to moisture-assisted cracking in moist environment ranging from dry nitrogen to 90RH% air environment. The low sensitivity is marked contrast to silica-based glasses, which are highly susceptible to moisture-assisted cracking. We present a model to describe the low sensitivity to moisture-assisted cracking.
Symposium Organizers
Geraud Dubois IBM Almaden Research Center
Mikhail Baklanov IMEC
Christian Dussarrat Air Liquide
Terukazu Kokubo JSR Tsukuba Research Laboratories
Shinichi Ogawa National Institute of Advanced Industrial Science and Technology
O5: Reliability
Session Chairs
Wednesday AM, April 27, 2011
Room 3000 (Moscone West)
11:30 AM - **O5.1
Impact of Dielectric Materials on Semiconductor BEOL Reliability.
Griselda Bonilla 1 , Thomas Shaw 1 , Xiao Liu 1 , Chao-Kun Hu 1 , Eric Liniger 1 , Stephan Cohen 1 , Hosadurga Shobha 2 , Christopher Penny 2
1 , IBM TJ Watson Research Center, Yorktown Heights, New York, United States, 2 , IBM at Albany Nanotech- Center for Semiconductor Research, Albany, New York, United States
Show AbstractLow-k SiCOH materials have replaced silicon dioxide in high volume production as an ILD of most high performance digital logic devices. The introduction of ULK materials with dielectric constant of k ≤ 2.5, however, comes at a significant increase in integration complexity and reliability challenges due to the degraded thermo-mechanical properties of the dielectric. Time dependent dielectric breakdown (TDDB) is commonly considered as an important reliability issue because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO2 dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. In addition, ULK dielectric materials are sensitive to all aspects of integration and tend to be easily damaged during processing, leading to increased integrated k-value, and re-entrant feature profiles that are hard to fill with defect-free metallization. The defects degrade yield and pose challenges to electromigration (EM) reliability. Lastly, the reduction in the elastic modulus and cohesive strength of the dielectrics has resulted in an increased susceptibility of these structures to cracking and delamination during processing and packaging of chips, especially for applications using large die (≥ 200 mm2) and lead-free C4 bonding.This talk will highlight the various failures that may occur related to the mechanical, chemical, and electrical properties of ultra low-k dielectrics during integration and packaging. The desirable material properties that will further enable ULK incorporation in highly reliable future CMOS technology will also be reviewed. This work was performed by the Research Alliance Teams at various IBM Research and Development facilities.
12:00 PM - O5.2
Interface Adhesion and Related Device Properties of Ultra-thin Cu Diffusion Barrier and High-k / Metal Gate Films.
Ryan Birringer 1 , Reinhold Dauskardt 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States
Show AbstractThe integration of new materials at both the interconnect and device levels in CMOS technologies has introduced a range of ultra-thin films and interfaces with largely unknown adhesive and cohesive properties. A quantitative understanding of these adhesive and cohesive properties is essential to ensure long-term reliability and maximize yield during manufacturing. Additionally, these fracture properties often correlate with other properties such as electromigration performance of diffusion barrier materials used in Cu metallization, stress relaxation in passivated Cu films, susceptibility to chemical mechanical polishing damage in low-k materials, and the work function of metal bilayer gate electrodes. In this study, we quantify the adhesive properties of a number of emerging CMOS materials, including SiC, SiN, BN, TaN and MnO barrier materials used in Cu interconnect technologies, which are processed using ALD, PVD, and CVD methods. In addition, we consider ultra-thin high-k / metal bilayer gate materials used at the device level. We demonstrate how these adhesive properties correlate with other pertinent properties, such as electromigration performance or metal gate electrode work function. Lastly, we use characterization methods such as angle-resolved X-ray photoelectron spectroscopy and secondary ion mass spectrometry depth profiling to model and explain the effects of interface chemistry and composition on the aforementioned properties. A brief overview of the methods used to quantify adhesive and cohesive properties will also be given.
12:15 PM - O5.3
The Effect of Thermal Stress on Cu-migration-induced Inter-metal-dielectric Breakdown.
Sung-Yup Jung 1 , Han-Wool Yeon 1 , Yoo-Yong Lee 1 , Jungwoo Pyun 2 , Young-Chang Joo 1
1 Department of Materials Science and Enginnering, Seoul National University, Seoul Korea (the Republic of), 2 Product Quality Assurance Team, Memory Division, Samsung Electronics Co., Hwasung-City, Gyeonggi-Do, Korea (the Republic of)
Show AbstractAs scaling down interconnect dimension in microelectronic devices, Cu interconnect is lay on harsh stress condition during operating such as high electric field on inter-metal-dielectric (IMD), high current through interconnect line and thermo-mechanical stress under high temperature. Theses stresses lead to the significant reliability issues in Cu metallization. High electric field leads to time dependent dielectric breakdown (TDDB), high current density leads to electromigration (EM) failure, and high thermo-mechanical leads to stress migration (SM). These are most well-known failure mechanisms for advance Cu metallization. SM has been studied by many research groups to analyze the influence of thermo-mechanical stress on EM behavior. However, the influence of thermo-mechanical stress on TDDB is important because the thermo-mechanical stress affects on not only EM but also breakdown of dielectric or its passivation. Cu-migration-induced dielectric breakdown is the most significant TDDB. The Cu migrates fast through IMD or interface between line and capping layer. It is expected that the dielectric which is degraded by thermo-mechanical stress is vulnerable to Cu migration. In order to investigate the mechanical stress effect on TDDB reliability, TDDB test was conducted before and after thermal cycle stress in this study. Damascene patterned comb/serpentine structure was prepared using conventional Cu metallization process. Cu line has Ta based diffusion barrier, SiO2 is used as IMD. Pattern is passivated by SiNx based capping layer. The samples were applied thermo-mechanical stress by thermal cycle with the -80°C to 150°C cycling temperature, 30 minutes of duration time, and 200cycles. After thermal cycle, the TDDB test which is the test method to obtaining time-to-failure (TTF) by monitoring leakage current through IMD under constant electric field was conducted. The leakage current during TDDB test increased and TTFs were distributed bimodally, after thermal cycle. Activation energy of Cu ion migration and electric field acceleration factor were calculated from temperature and electric field dependence of TTFs, respectively. Activation energy decreased and electric field acceleration factor increased after thermal cycle. This indicates that thermal stress changed the mechanism of Cu-induced dielectric breakdown. The thermo-mechanical stress effect on Cu migration will be discussed.
12:30 PM - O5.4
Reliability Characterization of Copper Vias in Silicon by Thermal Imaging Technique.
Shila Alavi 2 , Kazuaki Yazawa 2 , Glenn Alers 2 , James Christofferson 2 , Bjorn Vermeersch 2 , Ali Shakouri 2
2 Electrical Engineering, UCSC, Santa Cruz, California, United States
Show AbstractWith every new generation of integrated circuits, the interconnects are placed under more extreme conditions, supplying higher current densities, higher temperatures due to the higher heat flux dissipation from the chip and larger mechanical stresses. High temperature processing of copper dual damascene structure leaves a residual tensile stress in the copper via due to mismatch in coefficient of thermal expansion. This phenomenon is accelerated by the tensile stress at room temperature and leads to the formation of voids and ultimately open circuit failures. It is natural to assume the diffusion theory to dominate the intensity of void creation which is depends on the baking time. The understanding of this mechanical stress induced diffusion failure mechanism will be critical for the reliability of dual damascene copper interconnects. In this study the thermal imaging technique is used for presenting the thermal behavior of copper via chains under temperature stress tests for reliability. The CCD-based thermoreflectance microscopy as a high resolution, non-contact imaging technique is applied for thermal profiling and reliability analysis of 500nm diameter copper interconnects. This thermography technique is based on measuring the relative change in reflectivity of the device surface as a function of change in temperature. As the temperature of the sample changes, the refractive index, and therefore the reflectivity, varies. This initial thermal profile potentially indicates the location of the failure and the time-to-failure of the local via in a chain. In this frame work, we performed a systematic thermal characterization of different chains contain 10 & 100 vias respectively. The high resolution thermal images using thermoreflectance technique are obtained. Taking advantage from the full-field imaging capability of the thermoreflectance technique, we quantified the change in local temperature in 500nm vias under biasing condition and thermal process. These information are helpful to qualified the device in terms of reliability undre stress migration conditions. The interconnect resistance change was predicted by initial (time=0) thermal imformation with applying current bias. Thermoreflectance imaging could be useful to predict the potential falire of the local innterconnects with certain time for reliability without running long time oven tests. The significant increase in local temperature rise as a function of aging and its non-monotonic behavior is an indication of local void formation and large changes in the local heat dissipation profile.
O6: Metallization I
Session Chairs
Geraud Dubois
Christian Dussarrat
Wednesday PM, April 27, 2011
Room 3000 (Moscone West)
2:30 PM - **O6.1
Possibilities of CVD Mn Oxide as a Diffusion Barrier Layer for Advanced LSI Interconnections.
Junichi Koike 1
1 Dept. of Materials Science, Tohoku University, Sendai, Miyagi, Japan
Show AbstractIn Cu interconnection structures, a diffusion barrier layer plays a key role in device performance and reliability. The barrier layer should be thinner than 3 nm so as to occupy least possible volume of trenches and vias without compromising diffusion barrier property. It should also have a good adhesion with Cu so as to minimize electromigration failure. In this aspect, we have shown the effectiveness of a self-forming barrier (SFB) layer using a PVD Cu-Mn seed layer. However, the PVD method will encounter scaling challenges because of its poor coverage in the advanced technology node beyond 32 nm. To offer a solution for the advanced node, we have proposed the CVD formation of the Mn oxide barrier layer and investigated deposition behavior and barrier property.Precursor was bisethylcyclopentadienyl manganese, (EtCp)2Mn. Substrates were blanket TEOS-SiO2, dense SiOCH, Cu, and TEOS-SiO2/Si wafers having contact holes formed in the SiO2 layer. Some blanket samples were further deposited with Cu to investigate the diffusion barrier property using MOS structures. Samples were analyzed with TEM, XRF, Raman, XPS, and SIMS. CVD deposition was performed at substrate temperatures from 100 to 500 oC. Carrier gas was either H2 or Ar at a deposition pressure of 1 Torr at a precursor temperature of 85 oC.Metallic Mn islands were formed on TEOS-SiO2 at a substrate temperature of 500 oC, whereas a Mn oxide layer was formed below 400 oC, indicating a pyrolysis temperature of about 500 oC. The layer deposited above 300 oC contained a substantial amount of carbon that was originated from precursor fragments. This caused poor adhesion with the Cu overlayer. The layer deposited below 300 oC contained negligible amount of carbon, leading to a good adhesion with Cu. The deposited layer on TEOS-SiO2 was either the monolayer of amorphous oxide or the double layers of crystalline oxide and amorphous oxide, depending on substrate conditions. The amorphous oxide contained Si and, thus, was likely to be Mn silicate. Capacitance-voltage measurement after thermal annealing and bias-temperature annealing showed negligible shift of flat band voltage, indicating a good diffusion barrier properties of the deposited layer. In the case of contact hole structure, a good step coverage was observed with a uniform thickness of 2 to 3 nm. For the SiOCH substrates, surface treatment was necessary to deposit the barrier layer. For the Cu substrates, Mn was dissolved in Cu to form a solid solution.
3:00 PM - O6.2
32nm Node Highly Reliable Cu/Low-k Integration Technology with CuMn Doped Seed.
Shaoning Yao 1 , Vincent Mcgahay 1 , Matthew Angyal 1 , Andrew Simon 1 , Cathryn Christiansen 2 , Baozhen Li 2 , Tom Lee 2 , Fen Chen 2 , Paul McLaughlin 1 , Oluwafemi Ogunsola 1 , Stephan Grunow 1
1 , IBM, Hopewell junction, New York, United States, 2 , IBM Micorelectronics Division, Essex Junction, Vermont, United States
Show AbstractThis paper introduces a highly reliable Cu interconnect technology of the 32 nm node, 100 nm pitch wiring level with CuMn doped seed. A CuMn doped liner seed process has been developed to enhance reliability performance. The integration processes are briefly described. A Ta-based barrier liner is deposited onto open trenches and vias, followed by the doped CuMn seed layer. Mn dopant will diffuse and segregate on top of Cu wires, self-forming a Mn oxide cap layer during further process steps. This self-formed Mn oxide cap layer slows down electron migration at the cap interface because of good adhesion between Mn oxide and Cu. Lifetime of electromigration is enhanced by at least 10 times with CuMn doped seed as compared to pure Cu seed. TDDB performance with CuMn doped seed is comparable to that with pure Cu seed. However, a voiding issue was observed at plate structures under single vias during stress migration. A hypothesis that oxygen source from ILD during liner etch back process affects Mn segregation is discussed. Several liner processes including etch-back and non-etch-back schemes followed by CuMn seed are evaluated. Non-etch-back liner integrated with CuMn seed significantly reduces such void occurrance during stress migration testing. In addition, yield performance and resistivity of Cu wires with CuMn doped seed is being discussed in this paper.
3:15 PM - O6.3
Amorphous Ta-N as a Diffusion Barrier for Cu Metallization.
Neda Dalili 1 , Qi Liu 1 , Douglas Ivey 1
1 Chemical and Materials Engineering, University of Alberta, Edmonton, Alberta, Canada
Show AbstractCopper has replaced Al as the interconnect material in microelectronics due to its lower bulk resistivity and improved resistance to failure by electromigration and stress voiding. This material shift to Cu, however, has the inherent problem of Cu reaction with Si, as well as Cu diffusion/drift in Si and SiO2 followed by early device failure. Development of a reliable diffusion barrier material has been the subject of extensive research. In the current Cu interconnect technology, Ta-N compounds serve satisfactorily up to about 650-700°C and have been studied extensively. However, the failure mechanism of this barrier depends on several factors such as deposition condition, thickness, impurity content and microstructure and is not well known. Diffusion in thin films mainly occurs via high diffusivity paths such as grain boundaries and dislocations propagating through the barrier thickness. An amorphous structure, therefore, may provide a better alternative by eliminating short circuit paths. In this study, Ta-N layers with an amorphous structure have been examined as a diffusion barrier material. The thickness of these barriers continues to decrease with each generation of integrated circuits. In this respect various thicknesses of Ta-N film (10, 50 and 100 nm) were deposited on Si substrates by DC magnetron sputtering in an Ar/N2 atmosphere followed by deposition of Cu. Barrier performance was studied after annealing in forming gas (N2/H2) by employing resistivity measurements, glancing angle x-ray diffraction analysis, elemental depth profiling by secondary ion mass spectroscopy (SIMS), and electron microscopy. Crystallization of the amorphous film at elevated temperatures is accompanied by interdiffusion and reaction between layers, ultimately leading to barrier failure. The failure mechanisms of these barriers will be useful in improving their microstructure also in selecting new barrier materials in the future.
3:30 PM - O6.4
Structural and Barrier Properties of a Manganese Oxide Layer Formed by Chemical Vapor Deposition.
Nguyen Mai Phuong 1 , Kenji Matsumoto 2 , Kaoru Maekawa 2 , Junichi Koike 1
1 Material Science, Tohoku University, Sendai, Miyagi, Japan, 2 Technology Development Center, Tokyo Electron Ltd., Nirasaki Japan
Show AbstractWith the continuous scaling down of the interconnect dimensions, interconnect reliability becomes a major challenge for advanced integrated circuits (ICs). Although several advantageous properties of Cu make it a competent interconnect metal for IC such as low electric resistance and good anti-EM performance, it is well known that Cu diffuses readily into SiO2 and Si causing the degradation of electric properties. Therefore, it is necessary to insert a diffusion barrier between the Cu and the SiO2 substrate. Recently, a manganese oxide layer formed by chemical vapor deposition (CVD) has been reported to be a good candidate for the diffusion barrier in the future technology node. The present work reports the structural and diffusion barrier properties of the manganese oxide layers formed by thermal CVD.Substrates were p-type Si wafers having a plasma TEOS-SiO2 layer of 50 nm in thickness. A manganese oxide layer was deposited by thermal CVD at 300 oC using bisethylcyclopentadienyl manganese, (EtCp)¬2 Mn, as a metal organic precursor and H2 as a carrier gas. After the deposition of the manganese oxide layer, the sample was transferred to a load- lock chamber without breaking vacuum to deposit a Cu overlayer using a DC sputtering system at room temperature. To evaluate barrier property, Cu/MnOx/SiO2/Si/Al structures were annealed at 400 oC for 1, 2 and 4 h using a RTA system in vacuum. Then, capacitance- voltage (C-V) measurement was performed at room temperature. The microstructure of the post annealed samples was observed by a transmission electron microscope (TEM). The chemical bonding states of the manganese oxide layer were examined by angle-resolved X-ray photoelectron spectroscopy (XPS).TEM observation and XPS analysis revealed that the deposited layer was composed of two-stack layers of crystal MnO and amorphous MnSiO3 phases. The C-V curves of the samples after annealing at 400 oC for 4 h showed negligible shift of flatland voltage, indicating a good diffusion barrier property. The dielectric constant of the two-stack barrier layer was 12.08 and 13.40 before and after annealing. Additional results will be presented in detail at the conference with an emphasis on the dependence of the process conditions.
3:45 PM - O6.5
Bottom-up Filling of Surfactant Catalyzed Chemical Vapor Deposition (CVD) of Copper and Copper-manganese Alloy in Narrow Trenches.
Yeung Au 1 , Youbo Lin 1 , Roy Gordon 1
1 Department of Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States
Show AbstractWe present a process for the bottom-up filling of copper or copper manganese alloy with a CVD method in sub-20 nm trenches using manganese nitride as an underlayer and iodine as a surfactant catalyst. Conformally deposited manganese nitride films show barrier properties against copper diffusion and enhance adhesion between copper and dielectric insulators. Release of adsorbed iodine atoms from the surface of manganese nitride films allows iodine to act as a surfactant catalyst floating on the surface of a growing copper layer. As a result, void-free bottom-up filling of CVD of pure copper or copper-manganese alloy has been achieved in trenches narrower than 20 nm with aspect ratios over 9:1. Copper in these trenches forms a “bamboo structure” that is very resistant to electromigration. Upon post-annealing, manganese in the alloy diffuses out from copper through the grain boundaries and forms a self-aligned layer to further improve adhesion and barrier properties at the copper/insulator interface. Using this bottom-up filling technique, narrow trenches can be completely filled with copper and wider trenches can be coated by a conformal copper-manganese seed layer for electroplating. This process should facilitate the fabrication of future generations of nanoscale microelectronic devices with faster and more robust interconnections.
4:30 PM - **O6.6
Microstructure-based Statistical Model on Cap Layer Effects for Electromigration in Cu Interconnects Beyond the 45nm Node.
Lijuan Zhang 1 , Linjun Cao 1 , Paul Ho 1 , Oliver Aubel 2 , Christian Hennesthal 2
1 Laboratory for Interconnect and Packaging, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas, United States, 2 Dresden Module One LLC & Co., GLOBALFOUNDRIES, Dresden Germany
Show AbstractThis paper will first summarize the results of a recent study on the cap layer and the grain size effects on Cu electromigration (EM) reliability for the 45 nm technology node. With the standard SiCN cap, the EM lifetime was found to increase by 2x by changing from small to large grain structures. With the CoWP cap, the effect became more significant with the EM lifetime exceeding that of the SiCN cap by 24x for the small grain structures and ~160x for the large grain structures. A microstructure-based statistical model was formulated to analyze the grain size and cap layer effects for Cu interconnects. This model takes into account the statistical distribution of the grain structure and the interface and grain boundary contributions to mass transport in inducing void formation and EM damage. The grain structure of the Cu interconnect is examined by TEM, yielding grain size distributions which are used to extract the statistics of the bamboo and grain cluster distributions. The weakest-link model is applied to calculate the EM lifetime and statistics based on the measured bamboo and grain cluster distributions. After verifying with the measured EM results, the model is applied to examine the scaling effects on EM lifetime and statistics for Cu interconnects beyond the 45nm technology nodes. The results will be discussed.
5:00 PM - O6.7
Atomic Layer Deposition of Novel RuAlO Thin Films for Seedless Copper Electroplating Applications.
Taehoon Cheon 1 , Sang-Hyeok Choi 1 , Soo-Hyun Kim 1 , Sunjung Kim 2 , Kye-Sun Park 2
1 School of Materials Science and Engineering, Yeungnam University, Gyeongsan-si, Gyeongsangbuk-do, Korea (the Republic of), 2 School of Materials Science and Engineering, University of Ulsan, Ulsan Korea (the Republic of)
Show AbstractAs semiconductor devices are scaled down for better performance and more functionality, copper (Cu)-based interconnects suffer from an unwanted increase in the resistivity of the Cu wires due to the size effect on the resistivity of the metal film. One of the solutions to address it is to increase the volume of electroplated-Cu filled into the trench. One can increase the volume of EP-Cu filled into the trench using a thinner but conformal diffusion barrier and seed layer. The portion of Cu in the interconnects structure can be increased further using a direct plating because the electroplating of Cu can be achieved on a diffusion barrier without a seed layer. Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu. However, previous studies showed that Ru itself is not a suitable diffusion barrier for Cu metallization due mainly to its poor microstructure with polycrystalline columnar grains. This study developed a Ru-based multi-component thin film, RuAlO, which is compatible with the direct plating of Cu, using a thermal atomic layer deposition (ALD) process. AlOx was incorporated into the Ru by combining the Ru and AlOx ALD cycles, and a ternary thin film, RuAlO, was fabricated at 225 oC. The step coverage of ALD-RuAlO was perfect at contact holes with an aspect ratio of ~ 25 (top-opening diameter: ~ 85 nm). XRD and TEM results indicate that ALD-Ru film prepared without AlOx ALD cycle forms a polycrystalline structure with columnar grains. But, with incorporating the AlOx cycles, RuAlO films were formed with non-columnar grains and nano-crystalline microstructure consisting of Ru nano-crystals separated by amorphous AlOx matrix. XRD analysis showed that the structure of Cu (100 nm)/ RuAlO (8 nm)/ Si was stable after annealing at 600 oC for 30 minute while Cu (100 nm)/ Ru (15 nm)/ Si structure was failed after annealing at 450 oC. It was also shown that the electroplating of Cu was directly achieved on a very thin (~10-nm-thick) RuAlO film. * E-mail:
[email protected], Tel: +82-53-810-2472, Fax: +82-53-810-4628
5:15 PM - O6.8
Atomic Layer Deposition (ALD) of Ru Thin Films using a Novel Zero Metal Valent Ru(0) Metallorganic Precursor and Application to the Seed Layer for Cu Electroplating.
Sanghyuk Choi 1 , Taehoon Cheon 1 , Kwang Deok Lee 2 , Jung Woo Park 2 , Soo-Hyun Kim 1
1 Materials Science and Engineering, Yeongnam Univ., Gyeongsan-si, Gyeongbuk, Korea (the Republic of), 2 Thin Film Material Team, Hansol Chemical, Seoul Korea (the Republic of)
Show AbstractRuthenium (Ru) thin films have been investigated throughout the last decade for semiconductor microelectronic devices applications, such as a gate for MOS transistor, an electrode for the capacitor in DRAM and a seed layer for Cu metallization due to its advantages including low resistivity (7.1 micro Ω-cm for bulk), large work function (4.7 eV), thermal, chemical stability, and feasibility for the dry etch process. Recently, the application of Ru has been extended to nano-scale emerging devices in the form of nano-dots, nano-tubes and nanocomposites, such as nonvolatile memory devices, catalysts and supercapacitors. For these applications, the Ru films need to be deposited uniformly and fill high aspect ratio (AR) structures with a conformal thickness. In addition, a deposition technique with high process controllability that can provide large-area uniformity is essential as the demand for shrinking dimensions is increased. In these respects, atomic layer deposition (ALD) is a viable solution because ALD employs a self-limiting film growth mode through surface-saturated reactions, which enables atomic-scale control of the film thickness with excellent step coverage. But, the previous results of Ru ALD showed that the uses of Ru(II) or Ru(III) metallorganic precursors have a relatively long incubation cycle with a lower film growth rate at the initial stages of film deposition, which is related to the delayed nucleation of the film material. This results in a film with a rough morphology, which is unsuitable for conformal film deposition on high aspect-ratio structures. In this study, we investigated ALD-Ru process using a sequential supply of a novel zero metal valent precursor, (EthylBenzen) (EthylCycloHexadienyl) Ru(0) (EBECHRu, C16H22Ru) and molecular oxygen (O2) at substrate temperatures ranging from 185 to 310 oC. A high growth rate of 0.08 nm/cycle and negligible incubation cycles of ~ 9 were obtained at ALD temperature window, indicating the rapid nucleation of Ru. This was clearly compared to the results with Ru(II) or Ru(III) metalloganic precursors. The film deposited at 270 oC showed a minimum resistivity of ~ 37 micro Ω-cm. However, at 310 oC, the growth rate increased significantly to 0.15 nm/cycle due to partial decomposition of the precursor. The step coverage of the ALD-Ru film was excellent at a high-aspect ratio contact hole (top opening diameter: 85 nm and aspect ratio of ~ 25), the step coverage was excellent. ALD-Ru film investigated in this study was used successfully as a seed layer for Cu electroplating.* E-mail:
[email protected], Tel: 82-53-810-2472, Fax: 82-53-810-4628
Symposium Organizers
Geraud Dubois IBM Almaden Research Center
Mikhail Baklanov IMEC
Christian Dussarrat Air Liquide
Terukazu Kokubo JSR Tsukuba Research Laboratories
Shinichi Ogawa National Institute of Advanced Industrial Science and Technology
O8: 3D Packaging
Session Chairs
Thursday PM, April 28, 2011
Room 3000 (Moscone West)
2:30 PM - **O8.1
Sub-micron Scale Local Strength Evaluation for LSI Interconnect Structures.
Shoji Kamiya 1 5 , Nobuyuki Shishido 1 5 , Hisashi Sato 1 5 , Masahiro Nishida 1 5 , Chen Chuangton 1 , Masaki Omiya 2 5 , Tomoji Nakamura 3 , Takashi Suzuki 3 , Takeshi Nokuo 4 5 , Tadahiro Nagasawa 4 5
1 , Nagoya Institute of Technology, Nagoya, Aichi, Japan, 5 , JST CREST, Chiyoda-ku, Tokyo, Japan, 2 , Keio University, Yokohama, Kanagawa, Japan, 3 , Fujitsu Laboratories Limited, Atsugi, Kanagawa, Japan, 4 , JEOL Limited, Akishima, Tokyo, Japan
Show AbstractA new technique to enable sub-micron scale local strength evaluation for small-scale 3D structures is developed, in the framework of the newly launched project to compose a platform for the study of microscopic strength distribution in LSIs aiming at the establishment of a systematic design scheme from the view point of mechanical engineering.Mechanical fracture of small scale structures in LSIs has become a serious issue, especially since 3D integration of many different structure levels of chips and interconnects with various shapes is quickly developed for complex functions in a compact package. Introduction of multiple interfaces in such structures has spread many potential weak points from the view point of mechanical engineering. Evaluation and prediction of reliability of such complicated devices definitely requires a new experimental technique for the measurement of local interface strength in the scale of real structures where the fracture initiates. Interfaces patterned into micron-size may not have the same local strength as that evaluated with mm-scale blanket interfaces.Strength evaluation in the scale of LSI interconnect structures, i.e., down to even smaller than 1 μm, is realized with the currently developed technique by fabricating specimens of this scale at specified places in the structures and performing the experiment of this resolution in a multi-beam imaging and milling system (scanning electron microscope, SEM combined with focused ion beam, FIB) which is also equipped with an analyzer for electron-backscatter diffraction (EBSD) and a nano-indenter. The EBSD system is utilized for residual stress measurement and the nano-indenter for mechanical fracture test as well as measurement of local elastic-plastic properties. All the experiment is performed under SEM observation, so that it is possible to apply the same experimental procedure performed recently for the evaluation of interface toughness in a scale of 10 μm under optical microscope observation[1]. This technique uses small blocks fabricated on the stacking structure as specimens subjected to fracture test. Interface bonding energy is evaluated through the simulation of crack extension in the specimen to take the effect of specimen size into account and also to separate the energy dissipated by plastic deformation. Therefore the evaluation result is in principle independent of specimens used for the experiment, even down to sub-micron scale.The information obtained with the platform developed in this project provide not only a map of local strength distribution but also a possibility toward a systematic design scheme on the basis of mechanical engineering brought into LSI interconnect structures.[1] S. Kamiya, H. Shimomura, M. Omiya, T. Suzuki, Journal of Materials Research, in press.
3:00 PM - O8.2
Probing the Mechanics and Reliability of Multilayer Microelectronic Interconnect Structures.
Alexander Hsing 1 , Andrew Kearney 2 , Vivian Ryan 3 , Reinhold Dauskardt 1
1 , Stanford University, Stanford, California, United States, 2 , Cisco Systems, San Jose, California, United States, 3 , GLOBALFOUNDRIES, Inc., Albany, California, United States
Show AbstractThe focus of our research is to characterize fundamental materials, mechanics and failure mechanisms of heterogeneous multilayer interconnect structures to allow for the reliable packaging of complex interconnect structures. This challenge is exacerbated with scaling, as dielectrics become more brittle and contain multi-layers of ULK films, the industry-wide use of Pb-free solders with higher stiffness and reflow temperatures, and increasing levels of mechanical stresses on dies during packaging. We demonstrate a microprobe test metrology based on a micron-scale diameter stiff probe to directly measure a range of mechanical properties of multilayer thin-film structures in back-end microelectronics. These measurements are made at the relatively unexplored length scale between the nanoscale and conventional mechanical testing. Compressive, tensile and shear loading capabilities coupled with precise temperature control replicate various types of stresses experienced by dies during the packaging process as well as operation. Salient mechanical properties like stack compliance, strength characteristics, fracture behavior, and fatigue resistance are probed. We further elucidate the effects of solder bump support geometry, bump pad size, features surrounding the bump, under-bump metallization (UBM), and variations in metal density and film thickness. The typical deformation, defect evolution and ultimate failure mechanisms due to localized contact stresses that are critical for reliable device packaging are discussed.
3:15 PM - O8.3
Mechanical Stress Measurements in Cu Through-silicon via (TSV) Samples Using In Situ Synchrotron X-ray Microdiffraction for 3-D Integration.
Arief Budiman 1 , Hae-A-Seul Shin 2 , Byoung-Joon Kim 2 , Sung-Hwan Hwang 2 , H. Son 3 , M. Suh 3 , Q. Chung 3 , K. Byun 3 , Nobumichi Tamura 4 , Martin Kunz 4 , Young-Chang Joo 2
1 Center for Integrated Nanotechnologies (CINT), Los Alamos National Laboratory (LANL), Los Alamos, New Mexico, United States, 2 Department of Materials Science and Engineering, Seoul National University (SNU), Seoul Korea (the Republic of), 3 PKG Development Group, R&D Division, Hynix Semiconductor, Inc., Seoul Korea (the Republic of), 4 Advanced Light Source (ALS), Lawrence Berkeley Nationa Laboratory(LBNL), Berkeley, California, United States
Show AbstractThere is much interest recently in the 3-D interconnects using through-silicon via (TSV) technology in the microelectronics industry due to their potentials for vast improvements in the performance of microelectronics devices as well as their promises in enabling advanced multi-level chips integrating diverse CMOS technologies with each other as well as with emerging technologies such as MEMS and bio-chips. One of the key enablers for the successful implementation of 3-D interconnects using TSV is the control of the mechanical stresses in the Cu TSV itself as well as in the surrounding silicon substrate. Stresses induced intrinsically by thermal treatment in the TSV interconnect schemes, as well as stresses induced extrinsically, for example due to silicon wafer thinning or chip-package interactions, introduce new reliability challenges for through-silicon via (TSV) technology, while stresses in the silicon substrate surrounding the copper-filled TSV can affect electron mobility in the transistors and thus determine the keep-away zone for Front-End Of Line (FEOL)/chip design. In an effort to shed lights on these topics, experiments using synchrotron-based X-ray microdiffraction technique (developed at the Beamline 12.3.2 at the Advanced Light Source (ALS), Berkeley Lab) to measure crystal orientations and stresses in Cu TSV samples in the as-fabricated state, during annealing (in situ) as well as after annealing (post mortem) were conducted. As the high-brilliance synchrotron-sourced X-rays can penetrate and easily distinguish signals of the metallic structures from that of other materials in their surroundings, strain measurements can be done in our samples while the copper-filled TSV is still buried inside the silicon substrate. This allows strain measurements that are as close as possible to conditions in the real operations of the device. Using this approach, we studied Cu TSV samples and found the general stress state in as-fabricated Cu TSV is tensile but during the annealing process, it relaxes significantly and upon brought back to room temperature, it goes back up to tensile state. The annealing also causes residual stresses in Si surrounding the Cu TSV and from our measurements we determined the keep-away zone. Our findings further underline the importance of both measuring and controlling the stresses and especially how they could lead to degradation of the device in the technology development and process integration, as well as reliability improvement of the 3-D interconnect schemes.
3:30 PM - O8.4
Evolution of Damage during Thermal Cycling and Relation between Mechanical Stress and Microstructure in through Silicon via for 3D Integration.
Hae-A-Seul Shin 1 , Arief Budiman 2 , Byoung-Joon Kim 1 , Sung-Hwan Hwang 1 , Ho-Young Son 3 , Min-Suk Suh 3 , Qwan-Ho Chung 3 , Kwang-Yoo Byun 3 , Nobumichi Tamura 4 , Martin Kunz 4 , Young-Chang Joo 1
1 Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 Center for Integrated Nanotechnologies , Los Alamos National Laboratory, Los Alamos , New Mexico, United States, 3 Research & Development Division, Hynix Semiconductor Inc., Icheon Korea (the Republic of), 4 Advanced Light Source (ALS), Lawrence Berkeley National Laboratory, Berkeley, California, United States
Show AbstractThrough-silicon-via (TSV) technology becomes widely applied for 3-dimensional integration due to its excellent electrical properties such as high conductivity and low RC delay. However, the difference in thermal expansion coefficient between copper and silicon induce thermal stress during manufacturing process. Thermal stress develops cracking or copper extrusion in TSV, debonding at the interface of copper and silicon. Because these mechanical failures of copper affect the performance of TSV and stress of silicon, understanding of microstructure evolution and stress variation in copper is important. Cu TSV sample that has 20 μm diameter and 90 μm height with 90 μm pitch and sample that has 10 μm diameter and 50 μm height TSVs with 50 μm pitch were prepared. Stress measurement with 20 μm diameter was performed before increasing temperature, during annealing at 200 ℃ for 1 hour and after cooling down. Stress measurement was conducted by synchrotron x-ray diffraction (XRD). Synchrotron XRD uses white beam and monochromatic beam. All components of deviatoric stress are gained from white beam and hydrostatic stress also measured from the monochromatic beam. Furthermore, measurement of local stress from small grains with submicron size beam is the advantage of synchrotron XRD.Before heat treatment, hydrostatic stress of copper was tensile stress with small grains. Stress changed to compressive stress at 200℃, because of the volume expansion of copper and grains of copper grew in high temperature. After thermal heating, stress value went back to tensile, but it was tensile stress which was smaller than before annealed sample. Because total area of grain boundary was reduced with grain growth, stress of copper moved to tensile side. In addition, thermal stress was induced by volume shrinkage of copper with decreasing temperature. These stress variations caused the formation of voids and cracks in TSVs and stress level of copper was smaller than non-annealed sample with relaxation. In other point, deviatoric stress components had higher stress and large deviation in non-annealed TSV but after annealing, deviatoric stresses were lowered with smaller deviation due to relaxation. The decrease of deviatoric stress also indicates the reduction of stress is due to the formation of damage. Texture of TSV samples are measured by EBSD (electron backscattered diffraction) analysis. From the EBSD observation of non-annealed sample, copper had small grains at the top and side of TSVs and a little bit bigger grains in center with random orientation. After annealing, grains were larger in every region of TSVs due to grain growth. The relationship between texture and mechanical stress as well as effect of TSV size will be discussed.
3:45 PM - O8.5
Micro-bump Impact on Reliability and Performance in Through-silicon Via Stacks.
Aditya Karmarkar 1 , Xiaopeng Xu 2
1 , Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh, India, 2 , Synopsys, Inc., Mountain View, California, United States
Show AbstractThree dimensional (3D) integration using through-silicon via (TSV) technology provides high integration densities, heterogeneous integration and enhanced system performance. Micro-bumps are employed to connect vertically stacked silicon chips. The 3D chip stack with macro-bumps forms an intricate geometry with materials that have widely varying thermo-mechanical properties. The micro-bumping and stacking operations introduce mechanical stresses that depend on the process cycle, micro-bump and underfill materials, geometry, and layout. These stresses alter the carrier mobility in the active regions of the underlying silicon chip and consequently affect the device performance. They may also act as a damage driving force for interface debonding and/or cracking and result in mechanical and electrical failures in the 3D chip stack system. The mechanical stress evolution during micro-bumping process and 3D integration assembly is assessed in this study. An advanced FEM-based 3D process simulator that accounts for various stress sources is employed to generate realistic 3D structures, trace stress history, and analyze performance and reliability impact due to micro-bumping. The effects of process sequence, micro-bump geometry, layout, and materials on the mechanical stress, and hence the device performance and structural reliability, are examined. The results show that stress impact on device performance and structural reliability depends on carrier type, crystal and channel orientation, and magnitudes of various stress components. For a [001] wafer with [110] channel orientation, the NMOS devices in the active regions adjacent to the micro-bumps show the most significant performance variation due to the large vertical stress component in the region. These results are in contrast to the effects of a TSV. The magnitudes of stress components can be modulated by the micro-bump and under-fill materials. It is also observed that the regions with the largest device performance variation are different from the regions where the reliability of the structure is at risk. These results are used to develop stress management strategies to minimize reliability and performance impact in the 3D chip stack with micro bumps.
4:30 PM - O8.6
Out-of-Plane Catalyst Rotation in Metal-assisted Chemical Etching for Complex 3D Nano-scale to Micron-scale Manufacturing.
Owen Hildreth 1 , C. Wong 1
1 , Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractOur group recently developed a novel method to etch 2D and 3D nanostructures such as sloping channels, cycloids and spiral shapes in silicon with smooth walls and with relatively high aspect ratios ranging from 10:1 to 50:1 using metal-assisted chemical etching (MaCE) of silicon in conjunction with shaped catalysts. Building upon this previous work we have now developed a method to induced out-of-plane rotation of the catalyst in which the catalyst rotates both into and out of the silicon substrate to fabricate scooping channels, swinging structures and more. In MaCE a metal catalyst is used to generate a local galvanic cell across the catalyst that locally increase the dissolution rate of silicon in an etchant solution of hydrofluoric (HF) acid and hydrogen peroxide (H2O2). Unlike other etching techniques were a pattern of material remains on the top surface acting as a mask, in MaCE the metal catalyst moves into the substrate at the silicon around and beneath the catalyst dissolves. Because the catalyst can travel in 3 dimensions while continuing to etch it is possible to create 3D patterns in the silicon with straight, curved, helical, and random, etching paths reported for Pt, Au and Ag nanoparticles and colloids. More recently, our group has reported on the effects of catalyst shape on etching direction and showed that cycloids, spirals, sloping channels, “S” shaped channels and more can be fabricated by controlling catalyst shape to create complex, 2D and 3D nanostructures with extremely smooth walls. This presentation will detail the methodology utilized to fabricate 2D and 3D nanostructures using out-of-plane rotation during MaCE.
4:45 PM - O8.7
Cu-contamination-induced Degradation of nMOSFET Characteristics in 3D-Integrated Device under Thermal and Electric Field Stress.
Han-Wool Yeon 1 , Sung-Yup Jung 1 , Jungwoo Pyun 2 , Hyungwook Kim 2 , Dohyun Baek 2 , Young-Chang Joo 1
1 Department of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 Product Quality Assurance Team, Memory Division, Samsung Electronics Co., Hwasung City, Gyeonggi-Do, Korea (the Republic of)
Show Abstract3-D Integration process with through silicon via (TSV) has become widely used in high density integrated circuits. During the wafer thinning process, TSV material is exposed outside and contaminates Si. Cu, the most promising candidate for TSV material, migrates to active area of device and causes the reliability problem. Moreover, the gettering layer is eliminated by thinning process and it is hard to prevent the Cu contamination during following Cu-related processes. The effect of Cu contamination on the Si device characteristics has been researched intensively, through thermal diffusion into the active layer of device. However, on actual device operating condition, the devices are stressed by not only thermal stress but applied electric field. Because Cu exists as positive ion in Si, it is expected that Cu migration behavior in device is affected by electric field. In this study, the effect of Cu contamination on Si device characteristics considering both thermal and electric field stress was investigated. Backside of wafer which contains nMOSFET was thinned to eliminate gettering layer, and Cu was deposited by DC sputtering. In order to prevent Cu silicidation at interface between Cu and Si, SiO2 was deposited by PECVD before Cu deposition. Samples were thermal-stressed under 400 °C for 7 hours in vacuum. The changes of electric properties such as pn+ junction leakage current (Ileak), and series resistance (Rs) of pn+ diode were measured at room temperature by using an Agilent 4156C Analyzer. After thermal annealing, Ileak for sample with SiO2 and sample without SiO2 increased. The increment of Ileak for sample with SiO2 (8.2 × 10-8 A) is larger than that of sample without SiO2 (5.1 × 10-11 A). SiO2 layer helps Cu diffusion into Si preventing Cu silicidation, results in degree of Cu contamination for sample with SiO2 is more severe than sample without SiO2. Cu-TSV has a diffusion barrier and SiO2 layer as a dielectric. If diffusion barrier is broken, Cu diffusion to Si enhanced by SiO2 layer. Sample with SiO2 were stressed electric field in the channel (10 kV/cm) under 300 °C simultaneously for 3 hours. Rs of bulk-source diode increased from 234 Ω to 559 Ω, whereas that of bulk-drain diode was not changed. Cu drifts to source region due to electric field in the channel, Cu accumulation occurred at the interface between metal silicide contact and n+Si. When accumulated Cu at interface is supersaturated, Cu should be precipitated as Cu silicide. This precipitate increased contact resistance between metal silicide contact and n+Si. It is expected that switching performance of the transistor can be degraded because of decreasing on-current. The change of Rs for bulk-source diode according to the stressing time will be also discussed.
5:15 PM - O8.9
Tailoring the Crystallographic Texture and Electrical Properties of Inkjet-printed Interconnects for Use in Microelectronics.
Romain Cauchois 1 2 , Mohamed Saadaoui 2 , Karim Inal 2 , Beatrice Dubois-Bonvalot 1 , Jean-Christophe Fidalgo 1
1 Innovation and Manufacturing Technologies Department, Gemalto, Gemenos France, 2 Microelectronics Center of Provence, Ecole Nationale Supérieure des Mines de Saint-Etienne, Gardanne France
Show AbstractAdditive printing technologies have gained tremendous interest as a pathway to large area and flexible electronics. Among several printing methods, drop-on-demand inkjet printing is a non contact and digital technique that allows fast prototyping without any waste. This technology can thus be advantageously adapted for the realization of interconnects on silicon ICs for low cost electronics packaging. Those interconnects are patterned by jetting a colloidal suspension of metal nanoparticles whose thermodynamic size effect is exploited to reduce the sintering temperature. Printed features should exhibit a low electrical resistivity and high mechanical properties for being compatible with subsequent wire bonding step. Tuning those physical properties are particularly challenging since an optimization of microstructure through a solid-state sintering is required. Hence, a proper IC compatible post-process using a well-timed temperature profile has to be properly adjusted.In this paper, inkjet printed interconnects are studied for future applications in smart-card packaging. Silver nanoparticles with mean diameter of 30 nm are used. The combined effects of the substrate crystalline orientation and the sintering condition have been demonstrated to have a significant impact on microstructures. Silver nanoparticles were printed on (100) silicon substrate coated with either amorphous silicon nitride or with strongly textured (111) Ti / Au (50 nm / 200 nm) deposited by evaporation. Sintering temperature (200°C to 500°C) using different ramp (0.1°C/s to 50°C/s) resulted in 400 nm thick silver film. The crystallographic texture and grain size of those printed films have been investigated using Electron Back-Scattered Diffraction (EBSD) in a FEG-SEM. The result shows that the normal grain growth during coalescence of nanoparticles is in the same order of magnitude whatever the underlying film. However, a {111} fiber texture is developed above 200°C in printed silver only if the underlying film exhibits a preferential orientation, i.e. gold in this study. This texture transfer is interpreted by the out-of-plane diffusion occurring between evaporated gold and printed silver which arises simultaneously with the coalescence of nanoparticles. Impact of crystallographic texture of sintered silver has been further analyzed by ink-jetting interconnection lines and bond pads. Electrical resistivity shows no dependency on texture since it is mainly affected by grain size. An optimal value of 3.4 µΩ.cm is achieved at 300°C using a fast sintering ramp of 10°C/s under N2 atmosphere. On the contrary, only the {111}-textured silver pads above 200°C provides perfect gold-wire bondability with a high bonding strength through the increase of both interfacial adhesion and hardness. Inkjet-printed interconnects shows a prospective potential compared to conventional subtractive technique and offers new opportunities for low cost metallization in electronics packaging.
Symposium Organizers
Geraud Dubois IBM Almaden Research Center
Mikhail Baklanov IMEC
Christian Dussarrat Air Liquide
Terukazu Kokubo JSR Tsukuba Research Laboratories
Shinichi Ogawa National Institute of Advanced Industrial Science and Technology
O10: Emerging Technologies
Session Chairs
Friday AM, April 29, 2011
Room 3000 (Moscone West)
9:45 AM - **O10.1
Optical Interconnect Technologies Based on Silicon Photonics.
Wim Bogaerts 1 , Dries Van Thourhout 1 , Philippe Absil 2 , Shankar Kumar Selvaraja 1 , Pieter Dumon 1 , Hui Yu 1 , Joris Van Campenhout 2 , Thijs Spuessens 1 , Roel Baets 1
1 Information Technology, imec - Ghent University, Gent Belgium, 2 Process Technology, imec v.z.w., Leuven Belgium
Show AbstractOptical communication is becoming widespread since the introduction of the optical fiber. Optical fibers (or waveguides) can transport huge quantities of data with low attenuation: A laser source generates a high-frequency (~200THz) carrier wave on which data is modulated at very high bit rates, and multiple wavelengths can be transported on the same waveguide (Wavelength Division Multiplexing, or WDM).Optical links were first introduced in long-haul communication networks. With the increasing demand for bandwidth, they have penetrated metro networks, access networks, and even interconnects in datacenters. With optical links connecting electronic ‘boxes’, the definition of ‘box’ is shrinking. With the advent of multi-core processing, and the logic-to-memory interconnect bottleneck, optical interconnects are being considered even for on-chip communication. For this, silicon photonics could be a very attractive technology. A typical optical link consists of a transmitter, a waveguide medium, and a receiver. When WDM is used, wavelength multiplexers and demultiplexers are needed. Optical waveguides confine light in core with a high refractive index, surrounded by a low index cladding. The core size is determined by the index contrast. In silicon photonics, the core is made of silicon, which is transparent beyond 1100nm wavelengths. Silicon has a much higher refractive index than silicon dioxide, and therefore very compact waveguides are possible. Such ‘photonic wires’ have submicron cores, which allows integration of many photonic components on a single chip. Fabrication can be done with the same advanced tools used for electronics manufacturing, opening up large volume markets. For receivers, compact photodetectors are required. Because silicon is transparent, germanium is the most obvious material, as it can be epitaxially grown on silicon, and is already used in existing CMOS processes. On the transmitter side, we discern two key components: A laser to provide the carrier, and a modulator to impose an electrical signal. Modulators operate by changing the refractive index of a waveguide, and thus inducing a phase change. Typically, this is achieved by manipulating the carrier density, e.g. by embedding a diode or capacitor in the waveguide.The largest difficulty is the light source, and the simplest solution is to use an external light source as an optical ‘power supply’. Alternatively, the source could be integrated on the chip, but efficient laser sources typically need high-quality III-V epitaxial layers. A promising approach is heterogeneous integration: bonding III-V materials on the silicon photonic circuit, and subsequently processing them into lasers.While all these building blocks have already been demonstrated, bringing them together in a robust optical interconnect is still an ongoing challenge. We will discuss the requirements, and possible technological implementations based on silicon photonics.
10:15 AM - O10.2
Vertically Aligned Carbon Nanotubes as Flip Chip Interconnects.
Dunlin Tan 1 , Beng Kang Tay 1
1 School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore Singapore
Show AbstractWith the downscaling trends in electronic devices, integrated circuits packaging technology has evolved to 2 and 3 dimensional stacking, depending on the market drivers be it miniaturization, performance, and or reliability. Current solutions to limited chip area include increasing the aspect ratios of electronic interconnections. However, scaling copper interconnects can no longer satisfy performance requirements with substantial increase in electrical resistivity and incapability to carry high current density. A long term solution has to be steered away from traditional scaling and material modifications.Carbon nanotubes have excellent electrical, thermal and mechanical properties. They can also carry extreme current density and are less sensitive to electro-migration. Carbon nanotubes are probably the most promising materials to achieve the challenging aims of smaller feature sizes and high stress demands. Recently it has been shown that nanotubes interconnects have high ballistic transport. In this regard, they have been considered as future building block materials for both active and passive components in electronic devices. However integration into such devices has been futile. In this work, we demonstrate flip-chip bonded multi-walled carbon nanotubes connection in a daisy chain. Vertically aligned multi-walled carbon nanotubes are grown using the plasma enhanced chemical vapour deposition technique. The catalyst would be patterned on the metal trace with suitable barrier layers for a complete metallization system for electrical characterization. The electrical conductivity of the carbon nanotubes would be measured from point to point on a daisy chain layout and four-point measurements. Persistent issues pertaining to the metal/nanotube interfaces and quality nanotube growth would be discussed. Such interconnects could also be extended to other possibilities like optical, radio frequency applications.
10:30 AM - O10.3
Silicide Materials for Aligned Carbon Nanotube Synthesis in Interconnect Applications.
Can Zhang 1 , Feng Yan 1 , Guofang Zhong 1 , Bernhard Bayer 1 , Bingan Chen 1 , Stephan Hofmann 1 , John Robertson 1
1 , University of Cambridge, Cambridge United Kingdom
Show AbstractSilides are CMOS compatible materials and are electrically conductive. They also have significantly lower surface energy compared to most single element metals (e.g. Mo, W, Ta) which have been used as conductive substrate for Carbon Nanotube (CNT) synthesis; a low surface energy substrate material is beneficial for the catalyst thin films (e.g. Fe) to de-wet and form nanoparticles on top of it prior to the Chemical Vapor Deposition (CVD) step. In our study, cobalt silicide was found to be a thermally and chemically stable material under CVD conditions, including high temperature treatment at 650 oC and exposure to gas mixtures containing H2 and C2H2. Vertically aligned and high density Multi-walled CNTs (MWNTs) can be grown on CoSi2 using Fe as the catalyst, with a carbon shell density approaching 1012/cm2.We also found that, with a proper Reactive Ion Etch (RIE) process and a reduction step in H2 at the CVD temperature, even without a separate step of catalyst deposition, both cobalt and nickel silicides were able to catalyze CNT growth in a purely thermal CVD process. We also present X-ray Photoelectron Spectroscopy (XPS) data to understand the mechanism of catalyst formation in this process flow. This finding is very important in integrating CNTs in via/interconnect structures as catalyst patterning in small via holes and/or on vertical surfaces is extremely challenging. Using the techniques presented here, a horizontal CNT interconnect structure is fabricated by growing arrays of horizontal CNTs from a CoSi2 layer patterned on a vertical surface of the electrodes. Electrical measurements on these devices show an Ohmic contact between CoSi2 and as-grown CNTs, with resistance per tube/contact in the order of tens of kΩ. This value is comparable to the state-of-the-art values for contact between CNTs and metals (e.g. Pd, Cr) fabricated through a lithography step after CNT growth, which is not a CMOS compatible process flow.
10:45 AM - O10.4
Comparison of Electrical Characteristics of Multilayer Graphene and Multiwalled Carbon Nanotubes for Interconnect Applications.
Neha Kulshrestha 1 , Abhishek Misra 2 , Reeti Bajpai 1 , Kiran Hazra 1 , Soumyendu Roy 1 , Devi Shankar Misra 1
1 Physics, Indian Institute Of Technology Bombay, Mumbai, 400076, India, 2 Electrical Engineering, Indian Institute Of Technology Bombay, Mumbai, Maharashtra, India
Show AbstractGraphene and Carbon Nanotubes are the two most promising candidates for the interconnect applications for future nanoscale ICs. We here present a comparison of I-V characteristics of multilayer graphene (MLG) obtained by the pyrolysis of graphite and multiwalled carbon nanotubes (MWNTs) grown by thermal CVD. These MWNTs and MLG sheets were characterized by SEM, HRTEM and Raman spectroscopy. Towards the device fabrication approach, we have developed a 100% reliable technique to ensure the correct location of the tube and MLG for repeated ex-situ I-V measurements. Square metal (Au) pads of dimensions 100μm and separation of 3μ between them were prepared in countable number of rows and columns by direct writing using electron beam lithography on Si wafer having 150 nm SiO2 and 200 nm Cr/Au. The MWNTs and MNG have been dispersed on the as prepared Au electrodes. Identification of exact location is based on counting of the number of the row and the column of interest (where the MWNT or MLG bridges the gap between two pads). The current was found to increase linearly for both the MWNTs and MLG sheets at low voltages, while at high voltages (around 2 V), the nonlinear behavior becomes clearly visible. This nonlinearity in current suggests the diffusive conduction in both the MWNTs and MLG sheets. In general, the MLG sheet has been found to have higher currents at the same voltages compared to the MWNTs. The statistically obtained data on different devices suggest rapid joule heating and hence lower breakdown voltages (1-4 V) for MLG sheets as compared to the MWNT (2-10 V). Breakdown of the MWNT and MLG devices has been confirmed by SEM imaging. Based on these results and handling issues, we predict that the MWNTs are more promising for interconnect applications than MLG.
11:30 AM - O10.5
Emerging Materials for Nanoscale Interconnects.
Cengiz Ozkan 1 , Ali Guvenc 1 , Jian Lin 1 , Miro Penchev 1 , Jiebin Zhong 1 , Mihri Ozkan 1
1 Mechanical Engineering, University of California at Riverside, Riverside, California, United States
Show AbstractI will describe our recent work on emerging interconnect technologies based on graphene layers and semiconductor nanowires and elaborate on the materials processing challenges for large scale applications. Graphene exhibits exceptional physical, thermal and electronic properties, and is offering new avenues of applications in nanoelectronics, sensors and energy storage. Interconnects fabricated from graphene layers could serve as a future replacement for metal interconnects and overcome their limitations in data transmission performance. An attractive aspect of using graphene interconnects is the potential dual-functionality where they could also serve as thermal spreaders given their excellent thermal conductivity characteristics. In the first part of my talk, I will present our results on digital data transmission performance of graphene based interconnects grown by chemical vapor deposition. Initial studies demonstrated that the synthesized graphene based interconnects can sustain data rates up to 90 megabits per second. Graphene based interconnects behave as RLC lines and the bandwidth is inversely proportional to resistance caused by defects in the synthesized graphene layers and the inductance and capacitance of the interconnect lines. In the second part of my talk, I will describe the data transmission performance of indium antimonide nanowire based interconnects grown by chemical vapor deposition. Data transmission performance of nanowires suffer from low mobility due to scattering and crystal defects. Our results indicate these nanowires can sustain data rates up to 10 megabits per second without any impedance matching and de-embedding of the parasitic parameters. We are continuously improving on the quality of the CVD grown graphene layers and semiconductor nanowires to improve the bandwidth of transmission beyond the gigabits per second level.
11:45 AM - O10.6
Stretchable Silicon Integrated Circuits with Graphene Interconnects.
Won Ho Lee 1
1 Material Science and Engineering, Sungkyunkwan University, Suwon Korea (the Republic of)
Show AbstractIt have been developed that stretchable devices adding wavy patterns in the interconnect parts between devices and pre-strain to these parts or wrinkles on whole area of substrate by pre-strain, it showed limitation of the stretchable characteristics in the strains same to pre-strain level. So materials having high electrical conductivity and stretchable characteristic are needed in stretchable device systems. In this letter, we demonstrate stretchable single crystal silicon thin film transistors and logic gates which are electrically connected by graphene interconnect on a rubber substrate. These devices protected by polymer were transferred to the rubber substrates from elastomeric stamps by dry transfer method that controlled the bonding forces between top and bottom contact areas. Degradation of electrical properties of devices, especially active layers in high strain level is serious problem in the stretchable device system. So structures and layouts were designed that the applied strain should be concentrated in the interconnect part between devices to minimize the strains in active layers. Stretching test was done by a stretching machine and computer programs to control exact strain values. Single crystal silicon TFT showed high performances with graphene electrodes and the logic gates that were inverters interconnected by graphene also showed good electrical properties. These devices were also stable electrically and mechanically in high strain level. This method suggests significant possibilities in fields of stretchable electronics.
12:00 PM - O10.7
E-beam Deposited Tungsten Contacts for Nanocarbon Interconnect Test Devices.
Nobuhiko Kanzaki 1 , Shusaku Maeda 1 , Patrick Whilhite 1 , Toshishige Yamada 1 , Cary Yang 1
1 , Santa Clara Univ., Santa Clara, California, United States
Show AbstractCarbon nanostructures in their various forms are promising on-chip interconnect materials for next-generation integrated circuits. Previously, we prepared carbon nanofiber (CNF) interconnect test devices, where tungsten electrode contacts were formed using focused ion beam (FIB) [1]. Total resistance became smaller than that for the pre-W-deposited device by a factor of about 1000. However, as a chip fabrication process step, FIB has a potential risk of damaging the on-chip devices because of its high beam energy, and the gallium ion as the beam source could result in unacceptable device contamination. To address these issues, we have developed an alternative technique for W deposition using a well-controlled electron beam in a variable-pressure scanning electron microscope (VP-SEM). In this technique, the source gas is delivered via a specially designed gas injection system (GIS) [2] and guided by the focused electron beam to yield deposition on a selected target at a lower energy than the FIB. This technique is also more cost-effective as the GIS can be one of the modules in an existing SEM, which allows for in situ imaging and elemental analysis before, during, and after deposition. We have compared the resistances of CNF test devices formed by W deposition using FIB and e-beam deposition techniques. We also examine the improvements in resistance made by the e-beam deposited W contacts. As in our previous study for FIB-deposited W contacts, we have investigated the electron transport in the CNF test device at elevated temperatures by conducting high stressing current through the device [3]. Similar results to those with FIB-deposited contacts are found. In conclusion, W contacts are successfully formed by e-beam deposition after optimizing the GIS parameters in the SEM chamber and high-quality contacts comparable to those formed by FIB are obtained.[1] T. Saito, T. Yamada, D. Fabris, H. Kitsuki, P. Wilhite, M. Suzuki, and C. Y. Yang, Appl. Phys. Lett., 93, 102108 (2008).[2] D. C. Joy and P. D. Rack, Microscopy and Microanalysis, NY, 11, 816 (2005).[3] T. Yamada, H. Yabutani, T. Saito, and C. Y. Yang, Nanotechnology 21, 265707 (2010).
12:15 PM - O10.8
A Simple Patterning Method of Solution-Processed ZnO Thin Film for the Flexible Transparent Thin Film Transistor.
Kyongjun Kim 1 , Si Yoon Park 1 , Seung-Chul Yew 1 , Ji hyun Lee 1 , Sungyun Chung 1 , Hanju Jo 1 , Youn Sang Kim 1
1 Department of Nano Science and Technology, Graduate School of Convergence Science and Technology, Seoul National University, Suwon-si, Gyeonggi-do Korea (the Republic of)
Show AbstractTransparent thin film transistors (TTFTs) have emerged as next-generation transistors because they are applicable in transparent electronic devices. The transparent device has a great ripple effect for the whole industry, it has been spotlighted in response to changing markets and technological demands. From a technology standpoint, the advance of transparent devices increases the beam transmittance to enhance aperture ratio. It means higher transmittance of the thin film transistor (TFT) prevents the block penetration of back light and improves power consumption efficiency. Especially, the major driving force of solution-processed zinc oxide research is its prospective use toward printing electronics. Since the fabrication of TTFTs employs the complicated photolithography, the needs of sophisticated skills and high-cost are unavoidable. Moreover, there are two limitations in the patterning of ZnO-based thin films. First, the stripping photoresist passes throughout the thin film in wet etching because the thin films of affiliated ZnO have a porous structure. Therefore, it causes loss in the film’s performance and interface between the active layer and the gate insulator. Second, soft materials of the device are damaged by plasma in dry etching. For these reasons, we have developed a new patterning method, which is used by pre-patterned substrate. To achieve this, we completed a novel patterning method for use as direct patterning of solution processed ZnO, which has the potential to control the ZnO thin film patterns without the complicated photolithographic process in the TTFTs. Also, we fabricated the patterned flexible TTFT on the polymer dielectric layer because we believe that our proposed patterning method has excellent potential to fabricate the future transparent electronic devices.