Symposium Organizers
Byung-ki Cheong Korea Institute of Science and Technology
Paul Fons National Institute for Advanced Industrial Science and Technology
BartJ. Kooi University of Groningen
Bong-sub Lee Tessera Inc.
Rong Zhao Data Storage Institute
R4/Q3: Joint Session: Phase Change Memories
Session Chairs
Byung-ki Cheong
Yoshihisa Fujisaki
Wednesday PM, April 27, 2011
Room 3002 (Moscone West)
9:00 AM - **R4.1/Q3.1
Status of Advanced Non-Volatile Memory Technology Development.
Roberto Bez 1 , Andrea Redaelli 1
1 , Numonyx, Milan Italy
Show AbstractThe fast development of the digital consumer electronic has been sustained by the availability of suitable and powerfull Non-Volatile Memory (NVM) technologies. The key driver has been the Flash memories, both in NOR and NAND architecture, which are the enabling technologies for code and data storage application in mobile systems. The needs for superior performance and larger density memory will continuously rise, driven by the convergence of the many different portable systems. In this contest, the industrial interest in exploring new technologies, which must be able to provide an attractive NVM roadmap, is increasing. The presentation will give an overview of the innovative NVM technologies, which have been recently presented, with a special focus on the phase change memory technology based on chalcogenide material.
9:30 AM - R4.2/Q3.2
Interface Characterization of Metals and Metal-nitrides to Phase Change Materials.
Deepu Roy 1 , Rob Wolters 1 2
1 Central R&D, NXP Semiconductors, Eindhoven Netherlands, 2 MESA+ Institute for Nanotechnology, University of Twente, Enschede Netherlands
Show AbstractWe have investigated the interfacial properties of doped-Sb2Te phase change materials (PCM) to different CMOS compatible electrode materials. The interface of doped-Sb2Te both in the amorphous and in the crystalline state to W, TiW, Ta, TaN and TiN is studied. The nature of the interface is characterized by electrical measurements, it is expressed in terms of specific contact resistance (ρc). These measurements are performed using four-terminal Kelvin Resistor test structures.In the amorphous state, a lower electrical interfacial resistance is observed for metal-nitrides to doped-Sb2Te (ρc ≈ 10-4 Ω.cm2) as compared to the metal electrodes (ρc ≈ 10-3 Ω.cm2). In the case of pure metal electrodes, a chemical reaction is expected at the metal-PCM interface which leads to a better defined and clean interface. In general, a clean interface results in a lower interfacial resistance (ρc). In the case of metal-nitrides, less chemical reaction is expected. But the higher measured electrical interfacial resistance of metal to PCM suggests that the electronic conduction at the interface is determined by the metal-PCM barrier height and not the chemical reaction. The work function of metals is larger than the corresponding nitrides, therefore the measured electrical interfacial resistance is higher.In the crystalline state, the electrical interfacial resistance of both metals and metal-nitrides to doped Sb2Te is in the same range (ρc ≈ 10-7 Ω.cm2). In this state doped-Sb2Te acts like a semiconducting material with a high carrier concentration of 2×1021 /cm3, where tunneling dominates the electronic conduction mechanism at the contact interface. ρc shows no dependence with the work function of the electrode material and the slightly lower ρc in the case of pure metals to doped Sb2Te is attributed to the chemical reaction at the interface.
9:45 AM - R4.3/Q3.3
Controlled Recrystallization for Low-current RESET Programming Characteristics of Phase Change Memory with Ge-doped SbTe.
Zhe Wu 1 2 , Gang Zhang 1 3 , Young-Wook Park 1 4 , HyungKwang Lim 1 4 , Dongmin Kang 5 , Ho-ki Lyeo 5 , Doo Seok Jeong 1 , Jeung-hyun Jeong 1 , Kwangsoo No 2 , Byung-ki Cheong 1
1 Electronic Material Research Center, Korea Institute of Sceince and Technology, Seoul Korea (the Republic of), 2 Department of Material Sicience and Engineering, Korea Advanced Institute of Science and Technology, Daejeon Korea (the Republic of), 3 SKKU Advanced Institute of Nano-Technology, Sungkyunkwan University, Suwon Korea (the Republic of), 4 Department of Material Sicience and Engineering, Seoul National University, Seoul Korea (the Republic of), 5 Nano and Quantum Science Center, Korea Research Institute of Standards and Science, Daejeon Korea (the Republic of)
Show AbstractThe phase change memory (PCM) based on Ge2Sb2Te5 (GST) chalcogenide material has been recently commercialized, being positioned as the best candidate for replacing the present flash memory technology and serving as a low-cost, high-performance non-volatile memory in the next decade. Despite many promising attributes of the GST-based PCM, it has some challenging problems to be overcome so as to become a competitive high-performance non-volatile memory. One of them is its sluggish writing speed that would limit its range of application as a storage class memory. Writing speed of a PCM is determined essentially by the speed of SET-programming that involves crystallization of a RESET-programmed amorphous phase change material, and research has been carried out to look for phase change materials with fast crystallization characteristics. Ge-doped SbTe (GeST) is a very promising material in that regard and a PCM device with GeST of a high Sb-to-Te ratio was indeed shown to render much faster SET speed than GST-based device [1]. Despite its attractive high-speed SET programming characteristics, PCM with GeST of a high Sb-to-Te has an apparent drawback of a relatively high RESET programming current and this is a primary focus of the present study. By examining relevant material properties like electrical, thermal conductivities and growth rate of crystallization measured for the three selected GeSTs of varying Sb-to-Te ratio from 1.8 to 3.82, we advance a postulate that the growth rate of crystallization, diminishing strongly with decreasing Sb-to-Te ratio, may play a critical role in determining RESET current by way of altering the degree of recrystallization during melt quenching. Electrical characterization of PCM devices with the pore-type cell structure indeed has shown RESET current to decrease markedly with decreasing Sb-to-Te ratio. In the case of GeST of the lowest Sb-to-Te ratio studied (1.8) in particular, programming characteristics are shown to change drastically with increasing falling edge of a RESET pulse, manifesting not only the important role of recrystallization but also the possibility of multi-level cell operation according to a conventional programming scheme. As for SET programming characteristics, it is shown that SET time increases with lowering Sb-to-Te ratio, mostly due to increasing crystallization time. Because of direct scaling of crystallization time of GeST with the size of a programming region, however, SET speed of a smaller device could possibly be maintained as fast even with GeST of a low Sb-to-Te ratio. Consequently, GeST of a low Sb-to-Te ratio is a promising candidate for a high-speed, low-power PCM device. [1] Suyoun Lee et al., J. Electrochem. Soc. 156, H612(2009) Keywords: phase change memory, RESET current, Sb/Te ratio
10:00 AM - R4.4/Q3.4
Polyamorphous Compounds for New Fast Non-volatile Memory: Concept and Initial Experimental Results.
Semyon Savransky 1
1 , The TRIZ Experts, Newark, California, United States
Show AbstractInitial goal of phase change memory (PCM) and some other resistive memories to be unified memory for Flash, DRAM and SRAM memories replacement is still not reach after dozen years of extensive research. We briefly discuss fundamental limits and constrains of phase-change alloys (such as long crystallization time and/or high programming energy) that make this goal probably unachievable using known materials because of constrains similar to generic limits described in Ref. 1.
The governing physics of allotropy, polyamorphism and ergodicity together with requirements from semiconductor industry leads to a new concept [2] for unified memory based on polyamorphous compounds (PACs). Some PACs are relaxation semiconductors [3] that combine properties of phase change alloys and chalcogenide threshold switching glasses [4].
TRIZ approach for materials design is outlined and some designed and investigated PACs are described. The Deborah number is used to estimate PAC data retention and glass transition temperatures is used to estimate power consumption of memory from PACs.
Analytical memory devices from few PACs were produced using 10um semiconductor fabrication process. The experimental results obtained on analytical devices shows read window above 2X, non-volatility and no cycling degradation. Programming current for memory devices from some quaternary PACs is 3X-4X smaller than in typical PCM.
The memory from PAC has high speed and cycling ability while required significantly lower energy than PCM and DRAM during operation. The memory from PAC can be scalable to single nm mode and can be produce using modern semiconductor technology.
PACs also have unique properties that allow expand their applications beyond high-capacity, low-cost, fast, non-volatile memory field for new logic and optoelectronic devices as well as memristive systems.
References:
[1] H. Schroeder, V.V. Zhirnov, R.K Cavin, and R. Waser; Voltage-time dilemma of pure electronic mechanisms in resistive switching memory cells. Journal of Applied Physics, 107 (2010) 054517.
[2] S. D. Savransky; US Patent Application 2010/0090189 and other patent pending applications.
[3] W. van Roosbroeck and H. C. Casey, Jr; Transport in Relaxation Semiconductors. Physical Review B 5 (1972) 2154.
[4] S. R. Ovshinsky; U.S. Patent No. 3271591 and Reversible Electrical Switching Phenomena in Disordered Structures. Phys. Rev. Lett., 21 (1968) 1450.
10:15 AM - **R4.5/Q3.5
Scaling Studies of Phase Change Memory.
H.-S. Philip Wong 1 , Sangbum Kim 1 , Marissa Caldwell 2 , Jiale Liang 1 , Rakesh Jeyasingh 1
1 Department of Electrical Engineering, Stanford University, Stanford , California, United States, 2 Department of Chemistry, Stanford University, Stanford , California, United States
Show AbstractPhase-change memory (PCM) has emerged as a leading candidate for next-generation non-volatile electronic memory. As a candidate for future applications, one of the key characteristics is PCM’s potential to scale further than competing technologies. In this work, we investigate the scaling implications of several key PCM device parameters. Aggressive scaling scenarios result in faster scaling for cell-to-cell distances which leads to larger temperature rises in adjacent cells during programming. Using a PCM cell with a built in micro-thermal stage, we investigate the effect of thermal disturbance on both threshold voltage (Vth) and high resistance state (RRESET) drift. We show that thermal disturbances can cause at least 25% variation in RRESET and 100% in Vth. Current projections of PCM scaling also promises reductions in both programming current and power dissipation. By comparing a variety of PCM cell structures previously described, we calculated the effective contact area of each cell geometry and found a linear decrease in programming current with effective contact area, implying a constant current density for programming of ~10 - 40MA/cm2. Additionally, we investigated the relative number of low frequency noise (LFN) generators by measuring the power spectra density (PSD) of current fluctuations in Ge-Sb-Te alloy films of varying thicknesses. The normalized PSD values increased as the GST film thickness decreased, which is consistent with a decrease in the number of LFN generators. Finally, we report our recent success in building PCM cells using novel techniques, including the fabrication of a low temperature memory cell selection device.
11:15 AM - **R4.6/Q3.6
Recent Progrss and Prospect of Phase Change Memory.
Hongsik Jeong 1
1 Semiconductor Devision, Samsung Electronics, Yongin-City, Gyeonggi-Do, Korea (the Republic of)
Show AbstractIt was not surprising to search for next-generation non-volatile memory age since NAND- and NOR-type memories have shown some limitations in terms of programming/read speed and power consumption though they have superior device characteristics of non-volatility and high-density for mobile applications. Phase change memory is one of the most promising device which can replace conventional flash memories. Finally, PCM has been introduced in commercial stage which is incorporated into a cellular phone. This success comes from low melting temperature and high speed phase change materials which can be available by developing GeTe-Sb2Te3 pseudobinary alloys. Moreover, nano-size patterning techniques significantly reduce the operation current far below to make possible more reliable memory switching operations above 10E7 cycles. Being the first runner in the race of next-generation non-volatile memory is attributed to three advantages of phase change memory; Firstly, it can be easily scalable than other memories. Scalability represents the sustainability of a semiconductor device over several technology generations. It is demonstrated by theoretical and experimental studies that phase change memory is scalable below 10nm. In addition, it is relatively free from the burden of scaling down power consumption since an operation current spontaneously decreases with the same ratio of contact area scaling enough to maintain a required current density (Joule heating) for write operation. Secondly, intrinsic cell reliabilities are superior and more controllable to conventional flash memory. Temperature for data retention is higher and cycles for endurance is better than those of flash memories. Finally, the cell structure of phase change memory is simple and the process is compatible with Si processing, which means that it has more advantageous to directly use many well-established process techniques and facilities from a conventional memory device fabrication.In this presentation, recent progress and prospect of PCM device will be reviewed.
11:45 AM - R4.7/Q3.7
Investigation on Phase Change Behaviors of Si-Sb-Te Alloy: The Effect of Tellurium Segregation.
Xilin Zhou 1 , Liangcai Wu 1 , Zhitang Song 1 , Feng Rao 1 , Kun Ren 1 , Bo Liu 1 , Songlin Feng 1 , Bomy Chen 2
1 State Key Laboratory of Functional Materials for Informatics and Laboratory of Nano-technology, Shanghai Institute of Microsystem and Information Technology (SIMIT), Chinese Academy of Sciences (CAS), Shanghai China, 2 , Silicon Storage Technology, Inc., Sunnyvale, California, United States
Show Abstract Phase-change memory (PCM) emerged in recent years has been regarded as one of the most promising solutions to replace standard floating-gate devices for the next generation nonvolatile memory due to its excellent features, such as long data retention, fast write/read speed, good cyclability, high scalability, low power consumption and good compalibility with complementary metal-oxide-semiconductor (CMOS) technologies. The rapid reversible phase transition (thermally-assisted) between the amorphous (RESET state with high resistance) and crystalline (SET state with low resistance) states is exploited for information storage, which represent the logic state ‘1’ and ‘0’, respectively. With the challenge for consumer applications, however, chalcogenide films with various compositions have been widely investigated for better data retention as well as lower RESET voltages. In this study, novel Si2Sb2Te6 phase-change material was investigated in detail for the applications of phase-change memory using isothemal resistance measurement, X-ray photoelectron spectroscopy (XPS), and transmission electron microscopy (TEM). It was found that the thermal stability of film was improved and maximum temperature for a 10 year data lifetime was estimated to be 406 K, which revealed better data retention than traditional Ge2Sb2Te5 film. The phenomenon that Te diffuses to the film surface during phase switching and successively evaporates has been confirmed. Resembling to Ge2Sb2Te5, a nucleation-dominated crystallization behavior was also observed. PCM device employing Si2Sb2Te6 was successfully fabricated and programmed with a RESET switching at 1.85 V with 100 ns duration. Furthermore, a data endurance of 500000 cycles was achieved with a resistance ratio of 100, failing with a reset-stuck mode, mainly attributing to the migration of Tellurium constituent.
12:00 PM - R4.8/Q3.8
Nanofabrication of Stacked Type TiN/Ge2Sb2Te5/TiN Array for Low-power Consumption PRAM by Block Copolymer.
Jong Moon Yoon 1 , Hu Young Jeong 2 , Sung Hoon Hong 3 , Hyoung Seok Moon 1 , Seong-Jun Jeong 4 , Junhee Han 1 , Yong In Kim 1 , Yong Tae Kim 5 , Heon Lee 3 , Sang Ouk Kim 1 , Jeong Yong Lee 1
1 Materials Science & Engineering, KAIST, Daejeon Korea (the Republic of), 2 Graduate School of EEWS, KAIST, Daejeon Korea (the Republic of), 3 Materials Science and Engineering, Korea University, Seoul Korea (the Republic of), 4 Materials Science and Engineering, University of California, Berkeley, Berkeley, California, United States, 5 Semiconductor Materials and Devices Laboratory, Korea Institute of Science and Technology, Seoul Korea (the Republic of)
Show AbstractPhase change random access memory (PRAM) is a promising non-volatile memory device demonstrating high operation speed, low energy consumption, endurance to cycling and so on.[1-4] In a PRAM device, data storage/erase is accomplished by reversible thermal phase changes between the high resistive amorphous state and the low resistive polycrystalline state.[2,5] To achieve low power consumption and high-density PRAM devices, it is inevitable to reduce the size of the PRAM cells down to nanoscale.[6] Block copolymer lithography is a promising technology that may generate highly dense sub-10-nm scale features.[7] In this work, we fabricated ultra-high density (207 Gb/inch2) TiN (top electrode) /Ge2Sb2Te5(GST) /TiN (bottom electrode) trilayer PRAM cell array using block copolymer lithography and sequential two-step etching. This outcome is epoch-making considering that recently reported data-storage capacity of commercialized PRAM is 512Mb.[8] First of all, TiN (top electrode) /GST /TiN (bottom electrode) thin film is sequentially deposited on Si substrate with 100nm SiO2 by radio frequency (RF) magnetron co-sputtering method. After surface modification with PS-r-PMMA, a modified PS-b-PMMA block copolymer thin film was spin-coated. Cylinder component was selectively wet-etched to produce nanotemplates with hexagonally packed cylindrical nanopores. Cr was selectively deposited by e-beam evaporation owing to remaining PS template. Cr nano-dots were left behind subsequent to lifted-off. TiN/GST/TiN trilayers were accomplished by two-step etching process with the gas mixtures of Ar(45)/Cl2(5) and Ar(45)/CF4 (5). The electrical characteristics of single trilayer cell was measured by conductive atomic force microscopy (C-AFM). Phase change memory switching was realized in trilayer PRAM with a threshold voltage of 1.1 V. Reset state and set state were successfully accomplished by reset voltage (1.8 V, pulse width: 100 ns, pulse trailing: 2.5 ns) and set voltage (1.2 V, pulse width: 100 ns, pulse trailing: 100 ns), respectively.AcknowledgementThis work was supported by Priority Research Centers Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2009-0094040) and Samsung Electronics and the National Research Project for Phase-change Random Access Memory Development, which is sponsored by the Korean Ministry of Knowledge Economy (MKE).References[1] Wuttig, M.; Yamada, N. Nat. Mater. (2007) 6, 824-832[2] Wuttig, M. Nat. Mater. (2005) 4, 265-266[3] Kolobov, A. V. et al., Nat. Mater. (2004) 3, (10), 703-708.[4] Ahn, J.-K. et al., Nano Lett. (2009) 10, 472-477.[5] Hegedus, J. et al., Elliott, S. R. Nat. Mater. (2008) 7, 399-405.[6] Pirovano, A. et al., Tech. Dig.-Int. Electron Devices Meet. (2003) 3, 699-702[7] Kim, S. O. et al., Nature (2003) 424, 411-414.[8] Oh, J. H. et al., Tech. Dig.-Int. Electron Devices Meet. (2006) 1-4.
12:15 PM - R4.9/Q3.9
Multi-level Storage in Lateral Multi-layer and Single Layer Phase-change Memory.
You Yin 1 , Sumio Hosaka 1
1 Department of Production Science & Technology, Gunma University, Kiryu, Gunma, Japan
Show AbstractThere is a growing demand for memory nowadays. One of the most effective approaches to increase the memory capacity is the multi-level storage (MLS), by which much more information can be stored without increasing memory size [1-3]. In the past few years, researchers have demonstrated three- and four-level storage based on the layer-by-layer crystallization of chalcogenide films in vertical phase-change memory (PCM) [1]. However, there is a lack of literatures on MLS in lateral PCMs although lateral PCMs were demonstrated to have many advantages. Here, we report MLS in both a multi-layer lateral PCM and a single-layer lateral PCM with a top heater.The phase-change layer of SbTeN is adopted in these devices. SbTeN shows a gradual resistivity drop and good phase stability with increasing annealing temperature, a characteristic which makes it suitable for MLS applications. The active medium in the multi-layer devices is a top 30-nm TiN/180-nm SbTeN /20-nm TiN/bottom 120-nm SbTeN stacked structure. Three stable and distinct resistance levels are demonstrated in both static and dynamic switching characteristics of the multi-layer devices. Analysis reveals that two separate crystallization processes causing the two resistance drops could sequentially occur at the steps from the bottom thin 120-nm SbTeN layer to the top thick 180-nm STN layer due to the electric field confinement at the steps. The active layers of a single-layer PCM device consist of 150-nm-thick SbTeN layer with an additional top 50-nm-thick TiN layer. Experimental results exhibit a number of levels up to 16 are distinct and stable, which are induced by electric currents. The multi-level storage results mainly from the gradual nanoscale enlargement of crystalline region between electrodes by Joule heating according to our analysis. These levels also exhibited good thermal stability. [1]J. Feng, Y. F. Lai, B. W. Qiao, B. C. Cai, Y.Y. Lin, T. A. Tang, and B. Chen, Jpn. J. Appl. Phys. 46, 5724 (2007).[2]Y. Yin, H. Sone, and S. Hosaka, Microelectron. Eng. 84, 2901 (2007).[3]Y. Yin, N. Higano, H. Sone, and S. Hosaka, Appl. Phys. Lett. 92, 163509 (2008).
12:30 PM - R4.10/Q3.10
Void Formation and Analysis of the GeSbTe Thin Film Deposited by DC Sputtering for PRAM.
JeongHee Park 1 , JinHo Oh 1 , JungHwan Park 1 , SungLae Cho 1 , Hideki Horii 1 , DongHo Ahn 1 , ManSug Kang 1 , SugWoo Nam 1
1 Process Development Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd., Kyungki-Do,Hwasung-City, Banwol-Dong, Korea (the Republic of)
Show Abstract Phase-Change Random Access Memory [PRAM] has been widely studied by a lot of research groups for its remarkable properties as a solid state memory. Recently, its research field has been spread out to the post DRAM applications due to its good scalability and low power consumption [1]. For DRAM and NVM applications where endurance characteristic is very important, the quality of GeSbTe [GST] film plays a critical role in realization of a high performance PRAM. For examples, GST integrity is closely related to various reliability issues such as voiding, phase separation and interface delamination. In this study, we focused on the void formation mechanism. To understand the void generation and growth, TEM analysis was carried out with a DC sputtered GST thin film which was annealed under an extreme condition to intentionally generate voids in it. From the temperature study of the void growth, it was found that the amount of the Ar incorporation in a GST film during deposition decided the probability of void generation. That means void in GST thin film can be easily controlled by thin film deposition conditions. Also, we found the etch chemistry was another source for voiding. For this study, ellipsometry was introduced to analyze the density of GST film which is closely linked to the void in GST film. A long wave optical pulse was used to measure GST n, k value due to its high transmittancy into GST film. Furthermore, computational simulation could successfully reproduce the experimental data including a portion of the void in GST film. Throughout our study for void formation and analysis, the void in our GST thin film could be well controlled and properly monitored.[1] I.S. KIM et al, Symposium on VLSI technology, p.203-204, 2010
12:45 PM - R4.11/Q3.11
Crystallization Study of GeTe `Melt Quench' for Phase Change Memory Applications.
Audrey Bastard 1 2 4 , Jean-Claude Bastien 1 3 , Sandrine Lhostis 2 , Bérangère Hyot 1 , Caroline Bonafos 4 , Jacques Crestou 4 , Cathy Crestou 4 , Germain Servanton 2 , Frédéric Lorut 2 , Andréa Fantini 1 , Luca Perniola 1 , Emmanuel Gourvest 1 2 , Sylvain Maitrejean 1 , Anne Roule 1 , Véronique Sousa 1
1 , CEA - Leti Minatec, Grenoble France, 2 , ST Microelectronics, Crolles France, 4 , CEMES, Toulouse France, 3 , Laboratoire Verres et Céramiques, Rennes France
Show AbstractPhase Change Random Access Memories (PCRAM) are promising candidate for next generation of non-volatile memories. Among the materials showing phase change properties, GeSbTe (GST) alloys are the most studied. However, retention at high temperature is required for embedded purpose and GeTe alloys show promising performances due to its higher crystallization speed and stability of the amorphous phase [1]. Phase Change Materials can crystallize following two different mechanisms either by nucleation or by growth. According to Shih and al., the growth component of the phase change material has to be decreased to get high data retention with few cell failures [2]. Moreover, previous works have highlighted a difference of behaviour between the first and the second amorphous states [3, 4, 5]. However, most of the studies are focused on the crystallization process of the as-deposited material. To our knowledge, neither comparison between first and second amorphous state of stoechiometric GeTe nor the integrated material state behaviour after several cycles have been investigated.In this paper, we focus our attention on the differences of crystallization of the as deposited and ‘melt-quench’ GeTe thin films. The second amorphization is obtained on a crystalline GeTe material using a blue laser static tester, with power and time control. A small array of melt quench GeTe spots is thus obtained. Transmission Electronic Microscopy (TEM) observations are performed to determine the type of crystallization process i.e., to distinguish between nucleation and growth and to identify the crystalline phases of the written array. Differences on the crystallization mechanism between as deposited and ‘melt quench’ materials have been observed. These observations have been correlated to reflectometer and static tester measurements. Then, we investigate if a change of crystallization behaviour with cycling can be evidenced in basic GeTe integrated cells. The second amorphization state of the GeTe PCRAM cell is investigated by STEM-EDX and compared to a cell that has been cycled 107 times. This study allows a deep understanding about cell performance and reliability.First results concerning doped GeTe will also be presented in order to compare the change on crystallization behaviour and the effect of doping on recrystallization time, retention and endurance.[1] G. Bruns et al, Appl. Phys. Lett. 95, 043108, 2009.[2] Y.H. Shih et al., Proc. IEDM 2008[3] S. Raoux et al., Proc. of the EPCOS Symposium 2008.[4] P. K. Khulbe et al., J. Appl. Phys., 88, 3926–3933, 2000.[5] G. F. Zhou et al., Proc. SPIE 4090, 108, 2000.