The “pad-in-a-bottle” (PIB) approach to planarization is a non-traditional chemical mechanical polishing (CMP) process in which a slurry containing polymer beads is used instead of a conventional polishing pad. The approach is hypothesized to be able to perform polishing by mixing polymer beads with similar chemical and mechanical properties as pad asperities into the slurry to provide force application and polishing contacts, so that a traditional CMP pad is not needed. Pad-in-a-bottle could provide predictable and controllable mechanical contacts through bead size control, which could substantially reduce process variability. Pad-in-a-bottle also has the potential to reduce the CMP consumable cost. In this work, we propose a physical model to understand the behavior of the pad-in-a-bottle approach and estimate the relationship of applied pressure and material removal rate in this variant of CMP. Two specific cases of polymer bead formation are considered in our modeling work, bead packing and bead stacking. In the bead packing case, monosized polymer beads are uniformly dispersed. In the bead stacking case, polymer beads are randomly aggregated. Model prediction shows that the two bead formation cases generate distinctly different polishing mechanisms: material removal is applied pressure driven in bead packing, but contact event driven in bead stacking. The physical model suggests that in future experiments or applications of pad-in-a-bottle, a polymer bead size distribution or shape variation may be needed to achieve efficient material removal.

Systematic defects caused by processing play a major role in the yield of wafers at advanced nodes. Chemical mechanical polishing (CMP) is a manufacturing process that removes or planarizes overburden material on each of the layers on the wafer. An emphasis has been placed on CMP due to its inherent effect on lithography and electrical performance degradation due to dishing, erosion, and pooling. Introducing accurate CMP models into the design flow would lead to higher yield, shorter process maturation times, and more relevant virtual simulations analyzing the effects of custom designs. However, traditional model-based CMP checks are only performed opportunistically at the top level of the design.
There have been many models presented on modeling CMP at a variety of scales such as the pattern density models and higher fidelity physics-based models, which leverage rigorous treatments of surface parameters and interfacial fluid physics to predict the polishing process. The current work aims to show how a high-fidelity CMP feature scale wear model is coupled alongside a wafer-scale elasto-hydrodynamic lubrication (EHL) model in order to predict the material removal at each layer over time. In addition to simulating the evolution of topography due to CMP, first-order process models are used to simulate lithography, deposition and etching. Results could be used for addressing problem areas in a chip&’s design or tuning the manufacturing process, namely CMP, to certain layout designs.

Fabrication of integrated circuit is a multi-step process that involves chemical mechanical polishing (CMP) for planarizing the deposited layers. Most CMP researchers assume that the polishing occurs in the mixed-lubrication regime, where the applied load on the wafer is supported by the hydrodynamic slurry pressure and the contact stress generated during the pad-wafer contact. The particle augmented mixed lubrication (PAML) approach has been employed by Terrell and Higgs (2009) as a high-fidelity asperity-scale mixed-lubrication CMP model. The current work introduces a more computationally efficient wafer-scale PAML model, called PAML-lite, which employs a two-dimensional average flow Reynold's Equation incorporating spatial dependence of entrainment velocities to model the hydrodynamic pressure. The contact mechanics are modeled using a Winkler elastic foundation in cylindrical polar coordinates. The resulting slurry hydrodynamic pressure distribution and contact stress are used to determine the equilibrium configuration of the system in the form of a nominal clearance and rolling and pitch angles. Local and wafer scale material removal rate (MRR) is predicted by assuming a uniform distribution of particle sizes. The prediction of PAML-lite were then benchmarked against experimental results. Upon verification, parametric studies were conducted to understand the effect of some unexplored CMP parameters.

Most chemical mechanical polishing (CMP) researchers assume that the polishing occurs in the mixed-lubrication regime, where the applied load on the wafer is supported by the hydrodynamic slurry pressure and the contact stress generated during the pad-wafer contact. Consequently, the particle augmented mixed lubrication (PAML) approach has been employed as an extremely high-fidelity micro-scale mixed-lubrication CMP model in the past. Recently, a more computationally efficient PAML approach, PAML-lite, which considers the slurry&’s fluid and particle dynamics, the pad/wafer contact mechanics, and the resulting material removal, was introduced. The current work presents the PAML-lite framework with the isothermal assumption relaxed. As a result, interfacial temperatures during CMP can be predicted by considering asperity heating and dissipation of the heat into the solid and fluid media in the sliding contact.

Semiconductor technology is the key point of the information society. However, as technology developing, the traditional semiconductor material such as silicon (Si) could not meet the demand of the society. Therefore, the next generation semiconductor material silicon carbide (SiC) is widely concerned. Compared to Si, SiC has some superior physical and chemical properties. On the other hand, it is difficult to polish SiC wafers due to the chemical, mechanical, and thermal stability.
To achieve high-efficient CMP processing of SiC substrates, oxygen gas was introduced which might increase removal rates. MnO2 slurry was selected instead of silica slurry and strong oxidant KMnO4 was used to improve SiC-CMP process as an additive. In this paper, the effect of oxidant was inspected first. Meanwhile, we carried out the CMP experiment with the new type CMP machine to control the processing atmospheres including types of gases and gas pressures.
As conclusions, oxygen and high atmospheric pressure can increase the removal rate in MnO2 slurry. KMnO4 additive has a great effect on increase of the removal rate. One of additional interesting results is that there seems to be the optimum mixture ratio of N2 and O2 gases to achieve a higher removal rate of SiC wafer.

Gallium nitride (GaN) and its related alloys are some of the most promising materials for next generation optoelectronic applications and high-power, high-frequency devices. GaN substrate is expected as the most suitable substrate to grow these device films, however, it is difficult to apply conventional chemical mechanical polishing (CMP) to the Ga-face of GaN substrates due to their chemical inertness and mechanical hardness; the reported removal rate is as low as around 17 nm/h. Therefore, development of an advanced CMP technique for GaN substrate is highly desired.
As a background of this study, we found that removal rate of GaN in conventional CMP obeys Prestonian behavior (RR=KPV, where RR, K, P, and V is removal rate, system dependent parameter, applied downward pressure, and relative polishing speed, respectively). This indicates that the higher applied pressure condition with the larger machine is one of the most reasonable and easiest ideas to obtain a higher removal rate. Actually, the removal rate of GaN substrate reached over 1 µm/h when we demonstrated the CMP process under a higher applied pressure (6.6 kg/cm2) with the larger polishing machine (600 mm in platen diameter). However, this presents us with stringent polishing conditions. In other words, precise control of the machine motion to suppress unexpected scratches and/or the effective management of the heat generated by the friction between the pad and substrate etc. are required for the polishing machine design and its operations. Therefore, it is much more essential to improve the system dependent parameter (K) rather than the parameters P and V. It has been reported that GaN is polished by the surface oxidation mechanism of Ga2O3 formation followed by the dissolution of the Ga2O3 into the chemical solution. Therefore, the enhancement of the surface oxidation reaction improves the parameter K.
In this study, the optimization of CMP of Ga-faced GaN substrates using a colloidal silica slurry was studied by focusing the improvement of the surface oxidation reactions. Three advanced approaches have been introduced and discussed: pre-annealing by an air environment before CMP, ultraviolet (UV)-assisted CMP, and atmosphere-controlled CMP with closed bell-jar CMP machine. Details of the results for these new approaches will be presented in detail and comprehensive discussion will be done to understand the removal mechanisms of GaN by the colloidal silica CMP.

The motivation of this study is to provide answers to questions rising with the 3 dimensional stacking of microelectronic chips. This includes the development and validation of concepts for 1) TSV formation, 2) metal layer build-up, 3) various types of assembly and packaging concepts and methods, as well as 4) process characterization.
The investigations discussed here have been conducted on test wafer (ASSID-TC 2.0) developed by Fraunhofer IZM. This design contains dedicated test structures which have been implemented to enable different unit processes and allow easy physical analysis. One of those test structures has been used to study the impact of the TSV density on the stress generation after TSV fill, anneal and CMP including copper protrusion and planarization behaviour. First results of the interaction between different TSV plating bath chemicals, anneal procedures and wafer bow obtained with the test wafer ASSID-TC1.0 were already presented during ICPT 2011.
The process flow applied in this investigation was (1) TSV filling by electro-plating, (2) anneal, and (3) CMP. Physical analysis has been conducted between all process steps. The TSV diameter used in this study was 10µm and the aspect ratios applied were 10 to 12.
The test wafers processed were divided into two groups according to the utilized copper plating bath chemistries. The copper TSV metallization was carried out by electro-chemical deposition in plating bath chemicals from two different suppliers. These electrolytes included three organic additives in two different additive compositions for each plating bath. The additives, a suppressor, an accelerator and a leveller, are necessary to enable a bottom-up fill mechanism which allows acceleration of copper plating at the via bottom and suppression of plating near the top. The current density applied during electro-plating has been varied from 1 mA/cm2 up to the maximum of 5mA/cm2. The test wafers were rotated during processing and an additional paddle agitation close to the wafer surface was applied to optimize the transport of copper and additives in the electrolyte. Microscope inspection was done for surface analysis. After TSV filling the copper surface shows protrusion on top of the TSVs and ring-shaped non-uniformities around the filled TSV holes which can be described as “dip”-shapes. The “dip”-shapes were analysed after each step of the process flow.
An anneal process was conducted after TSV plating and key process parameters like temperature and gas composition were studied. The annealing temperature was varied to investigate its influence on the material properties (protrusion) and the dip behaviour. The experiments were accomplished at 250 degree Celsius and above.
Afterwards all test samples were processed by CMP with different selective slurries. First aim was the removal of the copper overburden followed by the clearance of the barrier layer. The polish process was stopped within the isolation layer. After the CMP process the planarization was measured with AFM and optical methods.
Bow and warpage measurements of the test wafers taken after each process step have been analysed. Our investigation has demonstrated the influence of the additives on the different behaviour of the plating bath chemistries during temperature treatment (copper recrystallization) and therefore also the planarization behaviour after CMP.

The semiconductor industry is currently developing many products that utilize advanced packaging technologies based on thru silicon vias (TSV&’s) or similar architectures in alternative substrate materials. Most of these package integrations are intended to accomplish one or more of several design goals, including provide additional routing flexibility, reduce parasitic losses, and shrink final form factors. For many CMOS manufacturers, this represents an alternative to continued 2D device shrinks which are often viewed as both expensive and high risk except for the largest of existing manufacturers.
In the current project, the desired final device structure includes an array of Cu posts (roughly 10 micron in height and 10 um diameter) that are surrounded by a smooth, planarized polymer layer. The top of the polymer surface should roughly coplanar with the top of the exposed Cu posts. Several options were explored for fabricating these types of structures, and the following sequence was chosen.
Deposit and pattern thick photoresist to define areas where vias are desired
Electroplate Cu through patterned openings
Strip photoresist
Spin on thick polymer coating (a few microns thicker than height of Cu posts)
Cure polymer layer thoroughly (lengthy bake at 190 deg C)
CMP to planarize polymer and expose tops of Cu posts and features
Achieving the intended surface required the development of a unique CMP process. Screening experiments were conducted to determine if all of the following criteria could be met simultaneously: blanket film polymer removal rate >0.5 µm/min, good planarization (>95% planarization efficiency), no scratching, and no evidence of Cu corrosion or attack on posts once exposed. Slurries were chosen based on previous experience at Entrepix. The results after one round of tests confirmed that all of the required criteria were met. Subsequent experiments confirmed that the device structures were acceptable for later steps in the process flow (not discussed here). Future optimization steps will include characterization of batch to batch repeatability and increasing throughput.

Aluminum (Al) gate fill has been implemented in Replacement Metal Gate (RMG) due to its low resistivity. Titanium (Ti) has been widely used as wetting layer for Al to fill the gates. For low resistance gate fill in structures with small feature size and high aspect ratio Ti-Al metal fill becomes increasingly more challenging as we move from 20nm into 14nm FinFet and 3D type structures.
Cobalt (Co) also provides a good wetting characteristic for Al with better fill performance and lower resistance than Ti-Al based process. However, due to the difference in corrosion potential between Al & Co, Chemical Mechanical Planarization (CMP) creates pitting type defects on Al-Co film that increases resistance variability across pattern density. CMP induced corrosion is separated in two parts; first is the static Co corrosion happened in the acidic chemical environment in Al CMP. Second is the galvanic corrosion from Co-Al metal boundary due to high metal electrical potential. Static corrosion can be resolved by adding a Co corrosion inhibitor in the slurry formulation. Galvanic corrosion can be minimized by controlling Co thickness deposition and formation of complete intermetallic phase. By controlling the removal rate with respect to corrosion rate we were able to suppress corrosion significantly.
Furthermore, we looked into compositions where the corrosion potential (Ecorr) gap between Al and Co is reduced to #61603;10mV leading to reduced galvanic currents. Stabilization of the corrosion currents in both Al and Co was observed using potentiodynamic scans. The effect of pH, several oxidizers and additives on the open circuit potentials (Eoc) of Al and Co was investigated and it was found that solutions of KMnO4, saccharides and sulfonate group containing compounds help reduce the Ecorr gap in between Al and Co to ~10 mV
Controlling the Al gate height across pattern densities and gate lengths to within few nm is another challenge for Al CMP. The industry widely used approach is to clear all Al using a slurry with high selectivity to dielectric, followed by a CMP step using a non-selective Al-to-oxide slurry. Both polishing steps need to be optimized in parallel in order to remove the incoming spacer SiN divot, minimize Al loss on gates with high pattern density or long gate length, minimize oxide loss on large open areas while maintaining low defectivity.
In this paper we are presenting an innovate Al CMP process for defect-free Co-Al fill process that demonstrated low gate resistance with tight distribution up to 80% pattern density and throughout the range of Lgate evaluated . This work has been supported by the independent Bulk CMOS and SOI technology development projects at the IBM Microelectronics Division Semiconductor Research & Development Center, Hopewell Junction , NY 12533.

The unabated drive to continue Moore&’s law has dominated technology advancement in the semiconductor industry. For more than 40 years, scaling of transistor level devices has led to the successful shrinking of device structures and performance improvements. In order to continue this drive for advancement, however, new materials and integration schemes for the transistor level have recently been introduced. Two main paths to integrate high-k metal gates for continuous performance scaling have been explored by the industry. The so-called gate-first (Metal Inserted Poly-Si) and gate-last (Replacement Metal-Gate) approaches have both pros and cons for realizing the final gate structure. For low power applications (which do not require aggressive EOT and ultra low VT), gate-first is arguably the most appropriate choice. The benefits of the gate-last approach, in terms of extra strain and overall work function control, however, make gate last the best option for both high-performance and low-power applications.
Intel Corporation&’s announcement of a replacement and non-planar build strategy for high-k metal gate structures has led design approaches for the sub-32 nm node. In order to enable this technology advancement, new polishing steps and slurries are needed to meet the stringent planarity and defect requirements for device performance. This talk will describe several of these slurry technologies in detail, including poly-open polish, gate capping, aluminum, tungsten, and germanium CMP. The keys to these technologies are outlined and polishing performance will be given. The critical mechanisms involved in the material polishing for each of these steps will be discussed. All of these new technologies are needed in order to build successful transistor architectures for advanced node integration via a replacement gate build strategy.

With the ever decreasing scaling of devices, semiconductor industry will face critical issues in the development of the 14-nm technology node and beyond. In particular, due to the increasing number of process steps and the more and more stringent specifications involved in the fabrication of new devices, new challenges are posed to the chemical mechanical polishing (CMP). Today the topography is characterized either at the gate scale (asymp;20 nm) or at the test box scale (asymp;100 µm). Nevertheless after CMP, the surface morphology depends, among other parameters, on the pattern density and size. As CMP metrology has reached its limit, new metrological methods/tools capable of measuring, at the die-scale, nanometric topographical variations with micrometric lateral resolution are highly desirable.
In this context, thanks to the new developments and improvements in interferometric microscopy, this technique can play a key role. Indeed a topographic image at the die-scale is now possible, in just a few minutes, with nanometric vertical resolution and micrometric lateral resolution. The aim of this work is to show how CMP process can benefit from topography measurement done at the die-scale.
We report on die-scale characterization of the topography induced by CMP process of the front end of line such as: shallow trench isolation (STI), primary metal dielectric (PMD) or replacement metal gate (RMG) and contact for advanced technology node. Topographic variations obtained using interferometric microscopy on one or several dies distributed all over the wafer are compared with those obtained usually at the gate scale and test box scale (by mechanical profilometry, AFM...). The pattern density dependence on the topography at the die-scale is characterized and correlated with pattern density cartographies. The impact of critical pattern density on the neighbouring areas is analysed and quantified. Finally, we analyse the impact of the different CMP steps on the front-end of line topography.
This work shows that the CMP process can benefit from topography measurement done at the die-scale. Indeed the surface morphology characterization at the die-scale with a nanometric vertical resolution and a micrometric lateral resolution provides several new inputs that could be used to monitor the CMP process. Furthermore it could be valuable for a thorough understanding of the CMP mechanism this will allow easier specifications respect.

CMP-induced topography is systematic largely in three different lateral scales: wafer
scale, die scale, and feature scale. Wafer-scale topography variation is from the radial
dependency of the CMP process. Die-scale variation is from the effective pattern density effect across a chip, which is the domain of design for manufacturing (DFM). Feature-scale
topography is individual line width-, line space-, or feature shape-dependent variation. Wafer and chip-scale variation can be compensated for in the lithography scanner through focus-level adjustment by measuring wafer surface heights before each exposure. Today, optical or mechanical detection of long-range wafer surface height variation and focus adjustment is possible in most advanced lithography systems. However, feature-scale topography cannot be compensated for in the lithography step since it is within an individual exposure field. Hence, topography non-uniformity in feature scale is most critical for CMP process development from a lithography perspective. In addition, local topography is important since it can cause ‘puddle&’ defects in subsequent layers. If local erosion is too great, the CMP process in the next layer cannot remove metals in the recessed area, causing residual metal and short problems. Thus reducing feature scale post- CMP non-uniformity in advanced technology nodes becomes extremely important. In this paper, a novel set of macros with line/space width from 128nm/128nm, 64nm/64nm to 32nm/32nm was designed and installed on 20nm technology-node hardware. The pitch-dependent dishing and erosion post Cu CMP was studied by atomic-force microscopy (AFM) and transmission electron microscopy (TEM) quantitatively on this macro. A new scheme of partial Cu plating process followed by SiCNH insulator deposition and then CMP was used to reduce the pitch- and density-induced CMP non-uniformity greatly.
Acknowledgments: This work was performed at the IBM Microelectronics, Div. Semiconductor Research & Development Center, Hopewell Junction, NY 12533.

Ruthenium (Ru) CMP slurry is required to enable next generation integration schemes such as directly plated Cu interconnects and Ru bottom electrodes. For selected applications, high Ru removal rate and selectivity to oxide is desired. Alumina particles were evaluated as a function of morphology, size and phase. The results indicate these parameters can be used to optimize both Ru removal rate and Ru/TEOS selectivity. A mechanism for interaction between alumina particles and the ruthenium and silica films is proposed.

New CMP steps are required to define the structures for new integration schemes for high-k metal gate and FinFET. The performance and yield of these new devices directly depend on CMP control of film thickness variation. As a consequence, CMP requirements are becoming increasingly stringent. This paper highlights the new process control technologies which enable efficient and cost-effective solutions for the new CMP steps, including FullVision® endpoint & in situ profile control (ISPC) for dielectric and poly CMP, and real-time profile control (RTPC) for aluminum, tungsten, and copper CMP.

As feature dimensions continue their inexorable decrease, new barrier materials are attracting attention. These include Ru, Co, Mn, Al/Co and other alloy materials among others. These films have mechanical and electrochemical characteristics that are very different from those of Cu and underlying dielectric films. Hence, their polishing slurry compositions must have appropriate removal rate selectivity over Cu and the dielectric films while at the same time defectivity and contamination and galvanic corrosion with respect to Cu are controlled and minimized. After investigating a large number of compositions, it was found that periodate and permanganate based aqueous solutions containing various other additives like sucrose, BTA, ascorbic acid and using silica abrasives can meet the requisite performance criteria. The results of these investigations will be described in this presentation with an emphasis on the fundamental aspects of various chemical and electrochemical interactions between these films and the relevant slurry constituents, both in the presence and absence of Cu.

CMP performance has to be controlled by the design of effective slurry composition including the chemical content and the abrasive particle selection. The chemical nature of the slurry is critical since it controls the material removal rates, slurry particle stability as well as the selectivity during CMP [1]. Slurry stability is necessary to prevent unacceptable levels of surface roughness and defects which are known to be caused by particle aggregates, where as surface friction is needed for material removal and planarization. Previously, we have established that alkyl quarternary amine mediated silica nanoparticle dispersions are able to meet the stringent stability criteria necessary in critical CMP operations, however, the presence of strongly adsorbed surfactant structures at the solid-liquid interface has also been shown to lead to negligible material removal. Adjustment of pH and ionic strength were adopted to initiate appreciable friction and material removal rates in silica polishing systems containing dodecyl trimethylammonium bromide (C12TAB) based dispersants [2].
In this study, slurry formulations in the presence of self-assembled surfactants were investigated for Ge/SiO2 CMP in the absence and presence of oxidizers. Both anionic (sodium dodecyl sulfate-SDS) and cationic (cetyl trimethyl ammonium bromide-CTAB) micelles were used in the slurry formulations as a function of pH and oxidizer concentration. CMP performances of Ge and SiO2 wafers were evaluated in terms of material removal rates, selectivity and surface quality. The material removal rate responses were also assessed through AFM wear tests to obtain a faster response, which corresponded to the material removal rates of the CMP tests very well. The surfactant adsorption characteristics were studied through contact angle and FTIR analyses. It was determined that the self-assembled surfactant structures can help obtain selectivity of the silica/germanium system and good defectivity control with a sufficient material removal rate values.
References:
1.Basim G.B., Engineered Particulate Systems for Chemical Mechanical Planarization, Lambert Academic Publishing, ISBN 978-3-8433-6346-4, 2011.
2.Vakarelski I. U., Brown, S.C, Basim G.B, Rabinovich, Y. I., and Moudgil B.M., "Tailoring Silica Nanotribology for CMP Slurry Optimization: Ca2+ Cation Competition in C12TAB Mediated Lubrication", ACS Applied Materials & Interfaces, Vol. 2, No 4, pp. 1228-1235, 2010.

The interactions of Poly(acrylic acid) with silicon nitride surfaces were investigated using CMP removal rates. In the presence of Poly(acrylic acid) a protective film is formed on the nitride surface and this influences the removal rates. The variation of the removal rates as a function of experimental parameters was used to probe the surface kinetic processes involved. The CMP removal rates exhibit abrupt transitions from high to low when the concentration of Poly(acrylic acid) is increased. These transitions are dependent on the experimental parameters such as abrasive loading and the downforce. Observations on the influence of the Poly(acrylic acid) film on the interactions of the silica abrasive particles and the nitride surface will also be presented.

Chemical-Mechanical Planarization (CMP) involves complex molecular interactions occurring among the polishing pad, the slurry components, and the wafer surface. Many studies have described macroscopic interactions occurring between the polishing pad and wafer surface during CMP, but a comprehensive molecular understanding of specific chemical interactions driving CMP processes is lacking. This paper focuses on the characterization of one of these specific interactions - adsorption of slurry additives onto the dispersed abrasive particles in a CMP slurry. The characterization technique used in this study was fluorescence correlation spectroscopy (FCS), a single-molecule spectroscopic method.
FCS employs a confocal fluorescence microscope to both excite and collect the fluorescence emission from a fluorophore either dissolved or dispersed in solution. Application of FCS to CMP slurries entails the analysis of competitive adsorption between a fluorophore and CMP slurry additives at an abrasive particle&’s surface. Because FCS measures the diffusion coefficient of the fluorophore, abrasive-bound fluorophores yield a distinctly smaller diffusion coefficient than do unbound (free) fluorophores in solution. If slurry additives interact with a fluorophore-bound abrasive particle and de-sorb the fluorophore, FCS-measured diffusion coefficients will indicate an increasing concentration of the free fluorophore in solution as the concentration of slurry additives increases.
FCS results for the adsorption of slurry additives, such as benzotriazole (BTA) and glycine, to model slurries based on colloidal silica abrasives at low pH are described. The fluorophore used in these studies, Alexa fluor 546, exhibits a pH-dependent adsorption to colloidal silica. The concentration of colloidal silica abrasive in the slurries ranged from 0.5 to 30 wt%. As expected, adsorption of Alexa fluor 546 to silica increased as the abrasive concentration increased. The addition of 0.1 wt% BTA produced dramatic de-sorption of Alexa fluor 546 over this range of abrasive concentrations. By contrast, glycine addition to the slurry enhanced Alex fluor 546 adsorption to dispersed colloidal silica particles.
Additional applications of the FCS technique to the study of molecular adsorption at the surface CMP abrasives and the variability in slurry additive adsorption behavior in response to the surface chemistry of abrasive particles are discussed.

Metal CMP applications necessitate the formation of a protective oxide film in the presence of surface active agents, oxidizers, pH regulators etc&’ to achieve global planarization. Formation and mechanical properties of the chemically modified metal oxide thin films in CMP determine the stresses develop at the interfaces delineating the stability and protective nature of the chemically altered films on the surface of the metal wafer. The balance between the stresses built in the film structure versus the mechanical actions provided during the process can be used to optimize the process variables and furthermore help define new planarization techniques for the next generation microelectronic device manufacturing.
The preliminary studies and modeling efforts were concentrated on the very well established tungsten CMP applications. It is known that the oxidation of tungsten results in formation of a mixture of WO2 and WO3 films. In order to conduct a stress-free, damage-free, atomically smooth and planar surfaces through CMP, it is necessary to understand the composition and the protective nature of these chemically modified films. The protective nature of the tungsten oxide films forming during CMP were characterized extensively through XRF analyses in addition to AFM surface morphology, FTIR and wettability tests through contact angle measurements. It was observed that the oxidation results in a nano-scale pure oxide formation on the very top which is unstable, followed by partially oxidized layers with a chemically protective nature. Furthermore, the surface roughness and wettability analyses also detected the physical changes in the nature of the formed oxide films. The thin film analyses conducted through XRD, XRR and FTIR characterization were compared to the theoretical calculations for the modeling simulations as a function of the oxidizer concentrations. A similar study was also conducted on copper CMP for the purposes of CMP optimization as well as preventing the CMP corrosion post cleaning.

The result of CMP (Chemical Mechanical Polishing) process can be realized as an integrated performance of various phenomena which are caused by many factors determined by a variety of polishing parameters. Polishing parameters are such as down force, platen rotation, visco-elesticity of polishing pad, slurry pH, abrasive particle concentration, slurry flow and so on. However, even if all the parameters are properly set, it is not always possible to obtain consistent result at each wafer. The possible reason for this inconsistency may be come from the complexity of three body system consisting of wafer, pad and slurry, which makes difficult to understand the polishing process. Various research works have been done so far to understand the polishing process analytically. We are also doing some research works to understand the polishing process through the research of polishing pad. Especially we are interested in the surface asperity and pore structure of polishing pad as well as the development of the intelligent pad in order to analyze polishing condition more actively. The pad surface asperity influences the contact area between wafer and pad. Because of the topography generated by conditioning, only the peaks of surface asperity can contact with wafer surface. Then the actual contact area turns out to be only a few % of the total pad surface area. Even if the contact area is small, when the number of contact point increases, the increase of contact frequency results in the effective polishing result. The three dimensional observation using X ray CT scanner helped to analyze the pore size distribution in the bulk of pad and the topography of surface asperity. It was also applied for analyzing the clogging of pad surface, by being visualized in depth. Those results can be used for the optimal pad design. By the newly designed sensor-embedded polishing pad, it becomes available to in-situ monitor the polishing pressure and temperature. The sensor module consists of pressure and temperature sensors interconnected with circuit board with memory, CPU and transmitter. The experimental result showed that we could successfully detect the pressure distribution over the wafer. And the distribution was proved to correlate with the NU of the wafer. This is still a prototype, but the concept of the sensor embedded pad was verified to work. This result showed that the sensor embedded pad turns out to be quite a unique intelligent pad, with which we can analyze the polishing process more actively. So far the pad has been considered as a passive tool which can be controlled by the polishing machine. But thanks to the intelligent pad, the in-process monitoring of polishing condition can be possible and we might be able to create an integrated polishing system with the polishing machine.

In this study, a 3M A3700 diamond disc was used to condition a Cabot Microelectronics Corporation D100 pad for a total of 30 hours. Its aggressive diamonds and the furrow surface area evolution were analyzed on a pad substitute material (i.e. polycarbonate sheets).
Results showed that the top 20 aggressive diamonds identified during the 30-hour polishing tests accounted for more than 75% of the total furrow surface area, confirming that they are the dominant working diamonds in pad conditioning. Results also showed that the original top 20 aggressive diamonds identified before wafer polishing experienced wear after the first 15 hours of polishing, indicated by the significant decrease (47%) in their furrow surface area. Seven new aggressive diamonds were born and they made a significant contribution (34% and 26% for Orientation 1 and 7, respectively) to the total furrow surface area. On the other hand, the furrow surface area generated by the new top 20 aggressive diamonds identified after the first 15-hour polishing was significantly lower (by 20%) than the original top 20 aggressive diamonds, leading to the loss of disc aggressiveness. In comparison, the disc aggressiveness was maintained after the second 15-hour wafer polishing as the furrow surface area of these new top 20 aggressive diamonds did not change significantly.
The above results showed a general trend for a conventional diamond disc during its early life: the disc initially loses its aggressiveness due to wear of its original aggressive diamonds; as the original aggressive diamonds wear out, new aggressive diamonds are born, but these new aggressive diamonds are less aggressive than the original aggressive diamonds; the disc aggressiveness can be maintained if these new aggressive diamonds withstand further wear.

For most commercial polishers, slurry is applied near the pad center where platen rotation and grooves help transport it to the pad-wafer interface. As the pad rotates, fresh slurry may flow directly off the surface due to bow wave formation and inertial forces without ever entering the pad-wafer interface, resulting in very low slurry utilization. On the other hand, some slurry that has passed under the wafer stays on the pad, mixes with fresh slurry, and re-enters the pad-wafer interface. This used slurry contains polishing by-products as well as pad debris due to conditioning that may cause wafer-level defects. Furthermore, large amounts of DI water are used to rinse off the debris and by-products between wafers; appreciable DI water may stay on the pad surface and inside the grooves. When fresh slurry is introduced to polish the next wafer, it mixes with the residual water and is diluted, resulting in lower material removal for most types of slurries. As such, the current slurry application method does not provide efficient slurry utilization and leaves significant room to improve polish performance.
In contrast, a novel slurry injection system (SIS-100) developed by Araca Incorporated delivers fresh slurry more efficiently to the pad-wafer interface. SIS-100 conformally rides on the pad surface during polishing and delivers a thin slurry film to the wafer. Used slurry and residual water are partially separated from new slurry by the device. Patterning on the injector bottom surface is used for residence time management and for thermal management of the recirculating slurry. Through more efficient slurry delivery, reduced slurry mixing and dilution, and residence time and thermal management, SIS-100 can achieve higher material removal rates and the same or fewer polishing defects with significantly lower slurry consumption. As slurry consumption is reduced, less waste slurry is generated thus making the SIS-100 suitable for low COO processes that are also environmentally benign.
The present study reports on the successful installation and performance of the SIS-100 device on a Speedfam-IPEC 472 ® polisher. Blanket 200-mm oxide wafers were polished at 5 PSI on a Dow IC1000 K-groove pad with Cabot Microelectronics Corporation Semi-SperseTM 25 slurry. The platen rotated at 38 RPM and the wafer carrier at 42 RPM. Oxide removal rates and wafer-level defects were measured as a function of slurry flow rate ranging from 50 to 150 ml/min. Data from this experiment show that SIS-100 generated consistently higher oxide removal rates (ranging from 6.2% to 11.5%) than the standard slurry applicator at different slurry flow rates. This indicated that either a lower flow rate or a shorter polishing time (and therefore less slurry usage) could be adopted for removing the same amount of material. For example, with a slurry flow rate of 67 ml/min, SIS-100 could achieve the same oxide removal rate as the standard slurry applicator at the slurry flow rate of 150 ml/min, resulting in 55% less slurry consumption.