Symposium EM11 : Wide-Bandgap Materials for Energy Efficiency—Power Electronics and Solid-State Lighting

As the demand for more energy efficient electronics increases, GaN has emerged as an attractive candidate material for high-voltage power management applications. The most promising device structure at the moment is that of a metal-insulator-semiconductor high-electron mobility transistor (MIS-HEMT) in which a gate oxide is placed between the gate metal and the AlGaN/GaN heterostructure of a HEMT. This is an attractive device architecture because of its high current, high breakdown voltage and low gate leakage current, all desirable attributes for power transistors. A concern with this new device technology is reliability and instability under prolonged high-field and high-temperature conditions. In particular, issues associated with the gate oxide have not been studied in the better established GaN HEMTs and bring in new concerns. Understanding sources of instability and reliability associated with the gate oxide is the goal of the present research.

The physical mechanisms responsible for bias stress instability (BTI) in GaN MIS-HEMTs are poorly understood. This is because of their complex gate stack structure with multiple interfaces and many trapping sites. In order to isolate the role of the gate oxide and its interface in BTI, we are studying a simpler GaN MOSFET structure in which the gate oxide is placed directly on top of the GaN channel. Even in this case, GaN substrate trapping complicates the interpretation of the results. Our research reveals the importance of electron trapping and detrapping inside the oxide as well as trap state generation at or near the oxide/semiconductor interface. Separately, we are studying time-dependent dielectric breakdown (TDDB) in GaN MIS-HEMTs, a catastrophic condition that arises after prolonged high-voltage gate bias stress. We have developed an experimental methodology to characterize TDDB through time-dependent current-voltage and capacitance-voltage measurements. Our techniques isolate different roles of threshold voltage shift, oxide trap formation and trapping, interface state generation, stress-induced leakage current (SILC), and eventual oxide breakdown. Out of this research, a classical signature for TDDB in GaN MIS-HEMTs emerges with evidence of progressive breakdown that supports the percolation model of defects.

These studies should be instrumental in understanding the complex instability and reliability issues of GaN MIS-HEMTs for power electronics applications.

This paper reviews the most relevant dielectric-related trapping mechanisms in GaN-based transistors with MIS-type and p-GaN type gate. Metal-insulator-semiconductor (MIS) devices with partially-recessed gate have been submitted to pulsed and constant voltage stress, with the aim of evaluating the impact of charge trapping processes on the dynamic properties of the devices and on the negative-bias threshold instabilities (NBTI) induced by negative gate bias. Three different dielectrics were considered for this investigation: SiN deposited by rapid thermal chemical vapour deposition (RTCVD), SiN deposited by plasma enhanced atomic layer deposition (PE-ALD), and Al₂O₃ deposited by atomic layer deposition (ALD). In addition, we investigate the failure processes of GaN-based HEMTs with p-type gate submitted to long-term stress tests. The results obtained within this paper are critically compared to previous literature reports, to provide a more complete view of the state-of-the-art.

GaN has been employed for high temperature, high power, high voltage and high frequency devices due to its wide band gap, excellent electron mobility and high breakdown electric field[1]. But achieving a dielectric with low interfacial defect density on GaN, high permittivity and low leakage current still remains challenging. Previously, we have shown that a defect-free interface can be achieved by growing lattice matched epitaxial lanthanum oxide (La₂O₃) on GaAs (111) using atomic layer deposition (ALD)[2]. However, there is no binary metal oxide has a suitable lattice constant, band gap, and conduction band offset for passivating the GaN(0001) surface and serving as an effective dielectric.
In this work, we demonstrate for the first time that an epitaxial Mg_xCa_1-xO film can be deposited on GaN by ALD. By adjusting the ratio between the Mg and Ca concentrations in the film, a lattice matched Mg_xCa_1-xO/GaN(0001) interface can be achieved with low interfacial defect density. High resolution XRD has shown that the lattice parameter of this ternary oxide obeys Vegard’s Law. Cross-sectional TEM shows an atomically sharp interface, confirming the high quality of the epitaxy. The valence band offset between Mg_xCa_1-xO and GaN was measured to be ~1 eV and thus the conduction band offset is ~3eV assuming the oxide band gap is ~7.4eV. Therefore both the band gap and band offset of Mg_xCa_1-xO are suitable as gate dielectric for GaN device applications. High temperature capacitance-voltage characterization shows that the film with composition Mg_0.25Ca_0.75O has the lowest density of interfacial defects. With this optimal oxide composition, a Mg_0.25Ca_0.75O/AlGaN/GaN MOS-HEMT device was fabricated. An ultra-high on/off ratio of 10¹¹ and a near ideal subthreshold swing of 62 mV/dec were achieved with this device. Thus we believe epitaxial Mg_xCa_1-xO films on GaN can be applied for the future high-power and high-frequency applications.


[1] S. Dimitrijev, J. Han, H. A. Moghadam, and A. Aminbeidokhti, “Power-switching applications beyond silicon: Status and future prospects of SiC and GaN devices,” MRS Bull., vol. 40, no. 05, pp. 399–405, 2015.
[2] X. Wang, L. Dong, J. Zhang, Y. Liu, P. D. Ye, and R. G. Gordon, “Heteroepitaxy of La2O3 and La2−xYxO3 on GaAs (111)A by Atomic Layer Deposition: Achieving Low Interface Trap Density,” Nano Lett., no. 111, 2013.

Understanding degradation of AlGaN/GaN high electron mobility transistors (HEMTs) is critical for enabling optimal performance and reliability of these devices. Mechanical strain is believed to be a critical degradation mechanism based on finite element simulations and experimental observations of cracks and pitting in the devices. However, there is a lack of experimental techniques capable of measuring mechanical strains in AlGaN/GaN HEMTs. In this work, we present atomic force microscope (AFM) measurements of thermomechanical and inverse-piezoelectric (IPE) deformation in periodically biased AlGaN/GaN HEMTs. Periodic applied bias induces periodic Joule heating and an associated periodic thermomechanical surface deformation, which the AFM cantilever tracks with sub-picometer precision. Periodic applied bias also induces measurable periodic IPE deformation. This technique is able to measure deformation in regions of the device with sub-micron features, including near the metallic gate, which is inaccessible by Raman microscopy. We investigate devices with a range of operating conditions: drain-source voltage, V_DS, of 0 to 50 V, gate-source voltage, V_GS, of -10 to 1 V, drain-source power of 0 to 6 W/mm, and frequency of 30 – 400 kHz. To study thermomechanical behavior, we open the channel and apply periodic V_DS. As V_DS increases, deformation decreases, especially near the gate and on the source side of the channel. We present an electro-thermo-mechanical finite element model which agrees well with and aids interpretation of the measurements. The model reveals that as V_DS increases, the hotspot moves away from the gate and toward the drain, leading to decreased gate temperature rise and decreased thermomechanical deformation, especially near the gate and source. The model also reveals that tensile thermal stress develops in the AlGaN layer near the drain-side edge of the gate due to a large mismatch of thermal expansion coefficients between the metallic gate and the AlGaN layer. This is important because the total stress is a combination of IPE, intrinsic, and thermal stresses. IPE and intrinsic stress in the AlGaN layer are both believed to be tensile. Therefore, tensile thermal stress will increase the total stress and may accelerate device degradation. This indicates that the gate temperature (and associated thermal strain mismatch with the AlGaN layer) is more important for thermal stress than the maximum device temperature. As the hotspot moves away from the gate for increasing V_DS, the gate temperature decreases, leading to 55% greater tensile thermal stress for V_DS = 10 V than for V_DS = 48 V for the same device power. To study IPE deformation, we set V_DS = 0 V to prevent heating and apply periodic V_GS. The measurements indicate that IPE deformation above the gate is 1.5 pm/V above pinch-off voltage and < 0.5 pm/V below pinch-off voltage. We conclude with a discussion of the implications of our experimental results on device degradation.

Recently, GaN-based transistors have been expected to be used in the low voltage applications such as DC/DC converters. For the switching devices, normally-off operation is strongly required from the viewpoint of safety. In order to obtain the normally-off characteristic, on-resistance (R_on) has been sacrificed and normally-off GaN HFETs show higher R_on. Thus, decreasing R_on, especially decreasing contact resistance (R_c) is a critical issue for these devices.
We have proposed a normally-off GaN HFET with p-type NiO gate for reduction of R_on by decreasing device dimensions [1]. The p-type NiO gate is successfully fabricated and normally-off operation is also realized with a threshold voltage (V_th) of 0.8 V. Although R_on is reduced by downscaling with introducing NiO gate, R_c becomes the main part of R_on in the limitation of downscaling. Then, we introduce a novel fabrication technique for source and drain electrodes to reduce R_c. In this technique, a heavily doped n⁺⁺-GaN layer regrown by MOCVD is introduced using Ge as a dopant [2]. A carrier concentration of up to 1 x 10²⁰ cm^-3 is achieved. Using this layer for source and drain electrodes, the total R_c is markedly reduced to 0.25 Ωmm. From these novel techniques, the fabricated GaN HFET with the 350 nm NiO gate exhibits a low R_on of 0.95 Ωmm, a maximum drain current of 1.1 A/mm, and a peak transconductance of 490 mS/mm, maintaining normally-off operation. These excellent results will contribute to the marked increase of conversion efficiency in switching devices.

[1] A. Suzuki, Y. Yamada, H. Tanaka, H. Ueno, N. Otsuka, Y. Anda, T. Ueda, T. Tanaka, and D.Ueda, Proc. Workshop on Compound Semiconductor Device and ICs, 2013, p. 77.

[2] A. Suzuki, S. Choe, Y. Yamada, S. Nagai, M. Hiraiwa, N. Otsuka, and D. Ueda, IEDM Tech. Dig., 2014, p. 275.

With the emergence of novel high power applications such as the automotive market, the development of a new generation of power devices operating well above 1 kV with high efficiencies is needed. Alternatives to existing Silicon (Si) technology have to be found since Si power devices are thermally limited and show high specific on-resistance at those operating voltages. GaN’s wide band-gap semiconductor properties and the compatibility with silicon technology lead to high expectations in low-cost power electronics with breakthrough performance, especially for high voltage DC-DC converters. However, this technology still suffers from the limitation of the silicon substrate since the breakdown occurs when the electric field reaches the silicon for large gate to drain spacing. In order to overcome this limitation, we have developed a process in which the Si substrate is locally removed near the high electric field region. This allowed us to achieve state-of-the-art 3-terminal lateral breakdown voltage GaN-on-Si transistors above 3000 V while delivering low specific on-resistance. These devices still shows lateral breakdown voltages well-above 2 kV at 600 K.
In order to make this approach viable for high power applications, high thermal dissipation has to be ensured and the substrate needs to be grounded. An integrated thermal management based on thick PVD AlN is being implemented into the trenches, which is expected to maintain the outstanding breakdown voltage properties. In this presentation, first results corresponding to the development of this technology will be depicted.

Even though the majority of development efforts for high power and high frequency applications have focused on
AlGaN/GaN High Electron Mobility Transistors, InxAl1-xN shows promise as a candidate material for the gate
barrier and polarization charge-inducing layer because of its wide bandgap, high spontaneous polarization charge,
and lattice-matching to GaN [1]. The advances in epitaxial growth of HEMTs on silicon substrates have enabled
both improved economic efficiencies and technical functionalities. However, the growth of InAlN by MOCVD is
challenging as the optimal conditions for AlN and InN growth are substantially different, and potential incorporation
of Ga into the film compromises the sharp interfaces required in HEMT structures encompassing AlInN. It has been
reported that both 2DEG density and mobility degrade as a result of the parasitic formation of a GaN layer at the
InAlN/AlN interface [2].
This paper reports on InAlN films and InAlN/GaN HEMT structures epitaxially grown on 150 mm <111> Si, using
Veeco’s Propel� single wafer MOCVD system. The TurbodiscÒ, vertical rotating disk reactor encompasses the
core reaction and high velocity laminar flow characteristics of its predecessor batch systems, thus enabling stable,
repeatable operation, long PM cycles, and direct, model-based process scale up. Moreover, it incorporates advanced
features for alkyl/hydride flow distribution and temperature uniformity, which translate into excellent uniformity in
epitaxial layer thickness, alloy composition, and doping profile across the wafer. [3]
Material quality was studied by growing InAlN films, 100 nm thick, with indium content of 17% on Si substrates
using a simplified stress compliance AlN/GaN buffer structure. Smooth surfaces with root mean square (rms)
roughness of 0.68 nm were observed in a 5x5 μm2 AFM scan. X-ray Diffraction analysis shows well defined layer
peaks and fringes, indicating good structural quality and abrupt layer interfaces. Thickness uniformity of InAlN is
0.87% for a 7-point XRD measurement across the 150 mm wafer. SIMS analysis confirms the uniform In depth
profile and the presence of abrupt layer interfaces. Negligible Ga (< 100 ppm, atomic) incorporation was detected in
the InAlN bulk film. Film sheet resistance of 230�/�, charge of 2.1×1013/cm2, and mobility of 1270 cm2/V.s were
measured on a prototypical InAlN/GaN HEMT structure comprising a 10 nm-thick, 17% In, InAlN barrier.
References
[1] J. Kuzmik, IEEE Electron Device Lett. Vol. 22, No. 11, pp. 510 (2001);
[2] Lin Zhou, et al, Phys. Status Solidi C 7, No. 10, 2436-2439 (2010);
[3] Jie Su, et al, Phys. Status Solidi A 213, No. 4, 856–860 (2016).

Today, 40% of the energy in the United States is consumed as electric energy. Power electronics, which are used to efficiently convert, control, and process the flow of electric power, play a significant and growing role in the delivery of this electricity. It has been estimated that as much as 80% of electricity could pass through power electronics between generation and consumption by 2030 [1]. Therefore, advances in power electronics promise enormous energy efficiency gains. A key element of any power electronic system is the semiconductor power switching device which determines the frequencies and power levels at which a power electronic system may operate. A Significant portion of the power losses in power electronic converters is dissipated in their power semiconductor devices. Silicon (Si) has been the semiconductor material of choice for power devices for quite some time, due to cost, ease of processing, and the vast amount of information available about its material properties. Si devices are, however, reaching their operational limits in blocking voltage capability, operation temperature, and switching frequency due to the intrinsic material properties of Si. Wide bandgap (WBG) power semiconductors, such as gallium nitride (GaN), silicon carbide (SiC), and diamond, are an attractive emerging alternative to Si in many applications. Power converters based on WBG devices can achieve both higher efficiency and higher gravimetric and volumetric power conversion densities. However, high cost and challenging fabrication of practical devices remain important barriers to the widespread adoption of WBG devices. In 2014, ARPA-E launched a program entitled SWITCHES (Strategies for Wide Bandgap, Inexpensive Transistors for Controlling High-Efficiency Systems) to catalyze the development of WBG devices using new fabrication innovations and/or new device architectures. This paper gives an overview of the technical progress to date in the SWITCHES program. The performance of various high voltage and high current rectifiers and transistors in the GaN, SiC, and diamond material systems is discussed. Material and processing challenges and reliability concerns for wide-bandgap power devices are also described. A glimpse into the future trends in device development and commercialization is offered.

It is undeniable that wide badgap materials will be the face of next generation electronics offering solutions never thought of before. The roadmap beyond Si in power electronics, introduced by Silicon carbide and Gallium nitride, is now expanding further with wider bandgap materials like Gallium Oxide [1], Aluminum (Gallium) Nitride [2] and Diamond [3] technologies gaining maturity. Higher blocking electric field definitely sets up wider bandgap semiconductors for operations between tens of kilowatts to megawatts rage. Medium power GaN HEMTs supporting applications up to 10KW have shown the pathway to commercialization. While GaN based diodes have already established the capability to block multiple KVs[4], transistors still fall short of delivering blocking voltages as predicted by GaN’s materials limit and reliable normally off single chip solutions. Although reducing the overall cost of the chip continue to impede market penetration, one can surely rely on the examples set by lateral GaN devices, to extend the roadmap using vertical GaN and ultimately diamond based devices.
Our recent success achieved with vertical GaN devices, viz. CAVETs[5], demonstrating over 500V blocking capability (complying with the drift layer design) suggests that with improvement in bulk GaN substrates these vertical devices will be competitive with SiC devices. Our predictive models [6] based on experimentally calibrated simulation tools, clearly show the manifestation of higher electron mobility [7] in bulk GaN in lower power losses in switches compared to its SiC counterparts. For example a 1.2KV GaN vertical JFET incurs significantly less switching loss compared to its SiC equivalent since the gate charge is reduced by 50%.
A very important feature of the GaN based power devices is realized when these devices are run ‘hotter’, thereby simplifying or eliminating cumbersome cooling techniques at the system level. Our recent study on contact metallurgy [8] creates a very promising landscape where the contacts are experimentally proven to sustain temperatures over 400^oC.
Finally, the promise of the ultimate power electronics lies in diamond. The outstanding material properties in diamonds are best utilized in devices designed to support over 1KV, at the very least. Some of our recent results present an encouraging future of diamond power electronics demonstrating bipolar action and high blocking voltages suitable for KV operations.
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For fabricating n-channel power-switching MOSFETs as well as high breakdown voltage junction diodes based on GaN, the site-controlled fabrication of p-type GaN of controlled hole concentrations is indispensable. For this purpose, Mg ion-implantation with subsequent annealing is an attractive process, because Mg concentration ([Mg]) and its depth profile can be controlled by the multiple-energy implantation method. However, there have been few reported results on p-type conductivity of Mg-implanted GaN, and the relation between the point defects generated by the implantation and photoluminescence (PL) spectra is scarcely known [1]. In this presentation, the defect species detected using the positron annihilation method [1] and PL spectra are correlated for ion-implanted and epitaxial Mg-doped GaN.

Mg⁺-ions were implanted into 4-μm-thick unintentionally doped (UID) GaN epilayers, creating box profiles of [Mg] at 1×10¹⁷, 1×10¹⁸, and 1×10¹⁹ cm^-3. For comparison, 1-µm-thick Mg-doped epilayers of similar [Mg] being 5×10¹⁷, 2×10¹⁸, and 4×10¹⁹ cm^-3 were grown on the 4-µm-thick UID GaN by MOVPE. For all samples, c-plane freestanding GaN substrates grown by HVPE was used as a substrate, in order to get rid of extrinsic effects originating from threading dislocations. All the samples were annealed at 1300 °C for 5 minutes with N₂ gas atmosphere at 1 atm. The static and temporal PL measurements were carried out between 10 and 300 K.

A broad ultraviolet luminescence (UVL) band with the peak at 3.28 eV was observed in all ion-implanted and epitaxial Mg-doped GaN at 10 K. As it originates from the radiative transition of electrons in the conduction band or shallow donors to Mg acceptors, the result implies the presence of Mg acceptors on Ga sites. The result is consistent with the fact that PL spectra at 10 K of low [Mg] samples exhibited a peak originating from the recombination of excitons bound to a neutral acceptor.

It should be noted that Mg-implanted GaN commonly exhibited a broad green luminescence (GL) band at 2.35 eV, which was almost unseen in epitaxial Mg-doped GaN. Moreover, overall PL intensity at 10 K of Mg-implanted GaN was more than an order of magnitude lower than that of epitaxial Mg-doped GaN, indicating higher concentration of nonradiative recombination centers (NRCs) in the Mg-implanted samples. As Uedono et al. have shown [1] that high temperature annealing increased the size of vacancy complexes composed of Ga vacancies (V_Ga) and N vacancies (V_N) and Chichibu et al. [2] have clarified the origin of NRCs in GaN as V_Ga-complexes like V_Ga(V_N)_n, additional introduction of V_N by Mg-implantation is likely. Accordingly, GL band is most likely originating from V_N. We will discuss the PL dynamics at the meeting.
This work has been supported in part by NEDO-SIP and MEXT programs (Research Alliance and Grant-in Aids of Scientific Research), Japan.
[1] Uedono et al., PSS B 252, 2794 (2015). [2] Chichibu et al., APL 86, 021914 (2005).

Due to the high-speed switching and high-voltage blocking capabilities, GaN power transistors can enable high-efficiency, compact and low-cost power converters. This presentation provides an overview of the development of GaN power switching device technology at HRL, for both lateral and vertical device structures. For GaN-on-Si lateral transistors, we have tackled key challenges in normally-off gate structure and dynamic on-resistance, resulting in KW-level power switching with ~ns switching time. For GaN-on-GaN vertical didoes and transistors, we addressed issues in carbon impurity, Schottky junction design, trench gate structure, and P-body contact, leading to 600V class Schottky barrier diodes and normally-off transistors.

GaN HEMTs for power switching are being actively developed by major power electronics companies due to their superior combination of low on-resistance and high off-state voltage capability. However the on-state resistance after switching from off-state (dynamic R_ON) is often found to be dramatically higher than the static resistance resulting in unacceptable switching losses. This problem now results largely from transient charge trapping in the semi-insulating carbon doped layer situated below the 2DEG. Here we will show that good performance not only requires good control of doping but also, rather surprisingly, control of the vertical leakage from the 2DEG to the GaN:C layer.
Recent calculations have placed the carbon acceptor level in the lower half of the GaN bandgap making the material slightly p-type. We will demonstrate using simulation and experiment the consequences that follow for device operation, since the GaN:C layer is isolated from the 2DEG by a reverse biased P-N junction under normal operational bias. This floating buffer can easily charge resulting in the dynamic R_ON dispersion, so suppression requires a leakage path to prevent the undesirable charging.
Using an innovative silicon substrate ramp technique we show that leakage between layers and charge storage in the key parts of the GaN epitaxial stack does indeed exist in epitaxy displaying low dynamic R_ON dispersion. It will be demonstrated that good performance of devices requires a blocking barrier below the 2DEG and a vertical leakage path allowing positive charging of the GaN:C, presumably along active dislocations.

This work was funded by the UK EPSRC PowerGaN project.

β-Ga₂O₃ is a promising candidate for future high-power device applications because of its extremely large band gap of about 4.5 eV and associated high breakdown electric field. Recently, we demonstrated a record breakdown voltage of over 750 V for Ga₂O₃ MOSFETs with a channel layer grown by molecular beam epitaxy (MBE) [1]. There have been several reports on homoepitaxial growth of Ga₂O₃ thin films on Ga₂O₃ (100) and (010) substrates. However, Ga₂O₃ MBE growth on Ga₂O₃ (001) substrates has received little investigation. In this work, we performed systematic studies on ozone MBE growth of Ga₂O₃ thin films on Ga₂O₃ (001) substrates.
Ga₂O₃ thin films were grown on β-Ga₂O₃ (001) substrates by MBE using Ga metal source and ozone gas. We investigated their structural features as a function of growth temperature by using reflection high energy electron diffraction (RHEED) and atomic force microscopy (AFM).
The growth rate of a Ga₂O₃ thin film on a Ga₂O₃ (001) substrate strongly depended on the growth temperature. At 600°C, the growth rate was as high as about 0.6 μm/h, which was almost the same as that of Ga₂O₃ thin films grown on Ga₂O₃ (010) substrates. However, the growth rate of Ga₂O₃ (001) monotonically decreased with increasing growth temperature and reached a very small value of less than 10 nm/h at 750°C. Note that the growth rate of Ga₂O₃ (010) thin films grown under similar conditions is almost constant at 0.5-0.6 μm/h in the wide temperature range of 550-750°C [2]. The surface AFM image of a Ga₂O₃ (001) thin film grown at 600°C revealed a wire-like-shaped morphology running in the [010] direction with a periodicity of about 20 nm, which was consistent with the [010] azimuthal RHEED patterns that had implied the formation of micro-facets. The average surface roughnesses (R_a) of Ga₂O₃ (001) films grown at 600°C and 650°C were 1~2 nm and three to four times larger than those of MBE-grown Ga₂O₃ (010) surfaces. In contrast, straight and ordered steps were observed on a Ga₂O₃ (001) surface grown at 700°C, and the absence of two-dimensional islands on the surface grown at 750°C suggested the transition of growth mode from two-dimensional nucleation to step flow at around 700°C. The meandering step-edges running in the [010] direction observed on Ga₂O₃ (001) surfaces grown above 700°C indicated that Ga adatoms were incorporated only at the (010) step-edges. These results suggested that the substrate off-cut angle (i.e. step density) and direction could be important parameters for the high-speed growth of atomically-flat Ga₂O₃ thin films on Ga₂O₃ (001) substrates.
This work was partially supported by Council for Science, Technology, and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), "Next-generation power electronics" (funding agency: NEDO).

[1] M. H. Wong et al., IEEE Electron Device Lett. 37, 212 (2016), [2] K. Sasaki et al., J. Cryst. Growth 392, 30 (2014).

Gallium oxides are promising materials. There are 5 known polymorphs[1], the α-, β-, γ-, δ-, ε-Ga₂O₃. Especially the thermodynamically stable phase β-Ga₂O₃ has attracted interest as a material for high power devices[2]. The other metastable polymorphs are moving into focus as well. Oshima et al. have grown ε-Ga₂O₃ thin films by MOCVD[3] and Orita et al. used PLD to grow ε-Ga₂O₃. Basic material properties of ε-Ga₂O₃, such as the size of the band gap are comparable to those of β-Ga₂O₃, but it is also expected to exhibit a high spontaneous polarization, possibly allowing the realization of two dimensional electron gases with high sheet carrier densities[4] when used in heterostructures. α-Ga₂O₃ was grown homoepitaxially on c-plane sapphire by mist CVD[5]. Schewski et al. observed pseudomorphic films on c-plane sapphire with a thickness of 3 monolayers independent from growth technique[6].
In our work we concentrate on the metastable phases ε-Ga₂O₃ and α-Ga₂O₃. We present the growth of ε-Ga₂O₃ and of thicker α-Ga₂O₃ layers by plasma assisted molecular beam epitaxy (PAMBE). ε-Ga₂O₃ thin films were grown in a tin-assisted process on c-plane sapphire. Usually, in Ga-rich conditions the growth of gallium oxide is attenuated by an etching of the growing film due to Ga₂O formation, which re-evaporates at growth temperature[7]. With the addition of a small tin flux this etching is shown to be suppressed, hence allowing the formation of ε-Ga₂O₃ in metal-rich conditions. α-Ga₂O₃ thin films with thickness of up to 200 nm are grown pseudomorphically on r-plane sapphire. However, the film thickness is still limited as nucleation of β-Ga₂O₃ can occur on the c-plane facets of the growing layers. The influence of different growth parameters on the phase formation and properties of the thin films is analyzed with HRXRD, AFM, and optical reflection measurements.


[1] Roy et al. J. Am. Chem. Soc. (1952)

[2] M. Higashiwaki et al. Phys. Status Solidi A 211 (2014)

[3] Y. Oshima et al. J. Appl. Phys. 118 (2015)

[4] M. B. Maccioni and V. Fiorentini Appl. Phys. Express 9 (2016)

[5] D. Shinohara and S. Fujita Jap. J. Appl. Phys. 9 (2008)

[6] Schewski et al. Appl. Phys Express 8 (2015)

[7] P. Vogt and O. Bierwagen Appl. Phys. Lett. 108 (2016)

Gallium oxide (Ga₂O₃) is a wide-bandgap semiconductor with attractive properties being exploited for the development of a range of electronic and electro-optic applications. In this work, we report on the growth of epitaxial Ga₂O₃ thin films on various substrates using metal organic chemical vapor deposition (MOCVD) method. Triethylgallium (TEGa) and trimethylgallium (TMGa) were used as precursors for gallium to grow Ga₂O₃ thin films at chamber pressures of 40 Torr, 65 Torr, 90 Torr and 120 Torr using 1800 sccm of pure oxygen. As the chamber pressure increases, the growth rate of the films was observed to decrease. Moreover, the films grown from the TEGa source were generally thinner than those grown from the TMGa source, despite identical growth conditions. The crystal structure and surface quality of the films were assessed by XRD, Raman spectroscopy, and atomic force microscopy (AFM). The film grown using TEGa at 65 Torr yielded a single phase epitaxial (-201) oriented β-Ga₂O₃ material with a surface roughness of ~ 4.0 nm. However, the films grown using the TMGa source were polycrystalline. Although, the reaction path between TEGa or TMGa and O₂ to form Ga₂O₃ by MOCVD is unknown, the fact that the TEGa pyrolyzes at lower temperature than the TMGa indicates greater susceptibility of the TEGa source to gas phase parasitic reactions than the TMGa source. This suggests that the TEGa source is highly depleted before it reaches the substrates surface, leading to a slow growth rate and, hence, a thinner epitaxial film. The UV-visible transmission spectra for films grown from both Ga sources had a band gap of~4.9 eV. Cathodoluminescence (CL) spectroscopy measurements presented a broad blue emission band, regardless of the Ga source used for the film growth, suggesting the presence of donor-acceptor-pair (DAP) processes. Ga₂O₃ thin film growth with water vapor as an oxidant was also studied and will be discussed.

Vertical n-Ga₂O₃ power devices require insulating or p-type materials for current blocking layers (CBLs), guard rings, or inversion-mode channels. Mg-ion (Mg⁺⁺) implanted Ga₂O₃ was investigated in this work as a CBL in light of semi-insulating Ga₂O₃ obtained by Mg compensation doping of n-type bulk crystals. Systematic thermal anneals and electrical measurements presented evidence of implant activation and illustrated a pathway for forming Mg⁺⁺-implanted CBLs in Ga₂O₃ devices.

Two-terminal electrical test structures comprising n-Ga₂O₃/Ga₂O₃:Mg(CBL)/n-Ga₂O₃ were fabricated on 7-μm-thick Si-doped (n~10¹⁶ cm^-3) β-Ga₂O₃ (001) epilayers grown by halide vapor phase epitaxy on Sn-doped (n~3×10¹⁸ cm^-3) substrates. Their design resembled typical transistor structures with a thick n^- drift layer. Mg⁺⁺ implantation was performed at 560 keV and a dose of 4×10¹³ cm^-2 with a peak concentration of 1×10¹⁸ cm^-3 at ~600 nm below the surface. Capless thermal anneals were carried out at 800°C, 900°C, and 1000°C for 30 min in N₂ to attempt Mg⁺⁺ activation and implantation damage recovery. A 100-nm-thick n⁺ top contact layer was formed by Si ion implantation, followed by activation annealing at 800°C for 30 min in N₂. Patterned-top and blanket-bottom Ti/Au ohmic electrodes were subsequently deposited. Current-voltage measurements were performed to assess vertical conduction through the Mg⁺⁺-implanted CBL by grounding the top electrode and applying positive substrate bias.

Ga₂O₃ as-implanted with Mg⁺⁺ was highly resistive owing to extensive lattice damage. Annealing at increasing temperatures was expected to result in progressive damage recovery and hence reduced current blocking by the implanted region. Leakage through the CBL annealed at 800°C remained low (<1 mA/cm² at 200 V) as only limited damage reversal had taken place. A higher annealing temperature of 900°C led to significantly increased conduction through the CBL (1 mA/cm² at 60–90 V) consistent with improved crystal quality. However, the effect of damage recovery saturated beyond 900°C and only slight degradation in current blocking capability (1 mA/cm² at 40–80 V) was observed with 1000°C annealing. The similar blocking characteristics between structures annealed at 900°C and 1000°C suggested that the barrier was no longer dominated by lattice defects; instead, a distinct mechanism that could be unambiguously ascribed to Mg⁺⁺ activation as compensating acceptors in the host material had given rise to a new barrier in the current path. These results established Mg⁺⁺-implantation with an activation temperature beyond 900°C as a feasible CBL technology in vertical Ga₂O₃ transistors, for which the implantation and annealing conditions could be further optimized to realize effective electron barriers.

This work was partially supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: NEDO).

Ga₂O₃ has recently generated significant interest and high quality growth (both thin-film and bulk) has been achieved with several techniques. Its distinctive feature compared to other transparent semiconducting oxides is the high transparency all the way to UV thanks to a wide 4.9 eV band gap. Hence this material has potential applications in future UV devices and high power electronics. n-type doping is achieved with Sn and Si, and highly resistive material can be produced by doping with Fe and Mg. p-type doping is yet to be achieved. Ga vacancies have been shown to act as efficient compensating centers in n-type material [1]. In order use Ga₂O₃ as a semiconductor in electronics, detailed understanding and control of defects and doping are required.

In this work, we analyze the formation mechanisms of Ga vacancies with positron annihilation spectroscopy [2] in Ga₂O₃ thin films grown by metal-organic chemical vapor deposition [3]. To this end, we studied samples grown on different substrates (Al₂O₃, Ga₂O₃), with different doping impurities (Si, Sn) and using different precursors for Ga (TMGa, TEGa) and O (H₂O, O₂). In addition, post-growth thermal annealings were performed to manipulate the defect balance in the films. We show that the choice of substrate, precursor and n-type dopant all have a dramatic effect on the efficiency of Ga vacancy formation and hence on the electrical properties of thin-film Ga₂O₃.

[1] E. Korhonen et al., Appl. Phys. Lett. 106, 242103 (2015).
[2] F. Tuomisto and I. Makkonen, Rev. Mod. Phys. 85, 1583 (2013).
[3] G. Wagner et al., phys. status solidi (a) 211, 27 (2014).

Solar-blind photodetectors have great potentials for numerous applications including flame sensors, radiation detectors, and analysis in chemical, environmental, and biological fields. Various material can be used for solar-blind photodetectors such as In₂Ge₂O₇, InAlN, AlGaN, GaN, MgZnO diamond and so on. However, these materials have still several problems to be solved such as difficulty of film growth with high quality, chemical instability, difficulty of handling the substrate due to intrinsic properties, high cost and so on. Therefore, the development of novel materials and designs of devices with 5S (high stability, high speed, high signal-to-noise, high sensitivity, high selectivity) is necessary in deep-UV detectors research field. β-Ga₂O₃ is a promising candidate for deep-UV photodetectors due to its desirable electrical and optical properties such as ~4.9 eV of direct band gap, and excellent chemical and thermal stabilities. Because it also has intrinsic solar-blindness, blinding the light with wavelength over 280 nm, β-Ga₂O₃ based solar-blind photodetectors need not the additive filters. The solar-blind photodetectors were fabricated using two-dimensional β-Ga₂O₃ micro-flakes, which are mechanically exfoliated from bulk sample. The exfoliated flakes were transferred to as-prepared SiO₂/p-Si/back gate metal (Ti/Au) structure and then the Cr/Au contact electrodes were formed via photolithography and electron-beam evaporators technique. The crystal structure and quality of the exfoliated flakes were confirmed by using transmission electron microscope, selected area electron diffraction pattern and micro-Raman spectroscopy. The photoresponse properties of device were investigated using the semiconductor parameter analyzer and the UV lamp with wavelengths of 254 nm and 365 nm. The devices have back-gate field-effect transistor structure. Therefore, dark currents were effectively reduced and the photoresponse properties were enhanced by applying the negative gate voltage. In this study, we demonstrated the solar-blind photodetectors using exfoliated β-Ga₂O₃ micro-flakes for the first time and investigated the output characteristics and photoresponse properties. The fabricated devices exhibited the highest responsivity among the reported literatures. We believe that these excellent results resulted from the following two reasons; the decrease of dark current and the high surface-to-volume ratio of 2-dimensional β-Ga₂O₃ flakes. The details of the results will be presented at the conference.

Atomic-layer-deposition (ALD) Al₂O₃ films are the most promising solution to gate insulation and surface passivation for non-Si, non-SiC semiconductor devices because of their high thermal stability, relatively high dielectric constant (~ 9), and large bandgap (~ 7 eV) together with high conformity, uniformity, and reproducibility due to the self-limiting process of ALD.[1] The reliability of the Al₂O₃ films as gate insulators needs to be assessed based on the right understanding of current conduction process in the films. To meet this requirement, we recently proposed a model, called space-charge-controlled field emission (SCC-FE) model, and successfully reproduced quantitatively experimental current-voltage (I–V) characteristics of Al₂O₃ films.[2] The SCC-FE analysis revealed that the negative- and positive-bias leakage currents of Al₂O₃ films are enhanced by a sheet of virtual dipoles near the gate and a sheet of positive charge near the substrate, respectively.
To reduce the leakage currents, this study investigated the effect of temperature, a key condition of ALD, on the current conduction in Al₂O₃ films, formed on Si substrates using H₂O oxidant, and obtained the following results. First, from a practical viewpoint, I–V characteristics of insulators need to be compared at the same equivalent oxide field (EOF). In terms of the EOF, the negative-bias leakage current of Al₂O₃ films is approximately independent of ALD temperature above 150°C, because of the compensation of two competing effects of increasing electron affinity and increasing permittivity of Al₂O₃. On the other hand, the positive-bias leakage current increases with increasing ALD temperature above 210°C, due to the increasing sheet of charge near the substrate. Intriguingly, we observed an oscillatory change of leakage current with increasing ALD temperature from 125°C to 210°C, and attributed it to an oscillatory change of dipoles located at the Al₂O₃/underlying chemical SiO₂ interface. Hence, 125°C- or 175°C-grown Al₂O₃ films have the minimal leakage current under positive bias. Considering, however, that these films cause the so-called blisters problem when heated above 400°C,[3] a 450°C ALD process is presently the most promising technology for growth of high-reliability Al₂O₃ film, because of the absence of blistering. It is open to further investigations to develop technologies for reducing charges and dipoles near and at the Al₂O₃/underlying insulator interface, thus suppressing leakage current under positive bias.

[1] A. Hiraiwa, et al., J. Appl. Phys. 117, 215304 (2015); doi: 10.1063/1.4921824
[2] A. Hiraiwa, et al., J. Appl. Phys. 119, 064505 (2016); doi: 10.1063/1.4941547
[2] O. Beldarrain, et al., J. Vac. Sci. Technol. A 31, 01A128 (2013); doi: 10.1116/1.4768170

An alloy system of corundum-structured oxide semiconductors constituted with α-Al₂O₃, α-Ga₂O₃, and α-In₂O₃ offers novel opportunity for wide-bandgap heterostructure oxide semiconductor devices. Marked evolution of α-Ga₂O₃[1], recently, has launched Schottky barrier diodes with record-low on-resistance and high-breakdown voltage[2]. One of other promising materials is α-In₂O₃, whose bandgap is as high as 3.7 eV and electron mobility seems to be higher compared to that of α-Ga₂O₃. We have reported the preliminary operation of α-In₂O₃ MOSFETs[3], and in this presentation we show the recent advancement of crystal growth, conductivity control, and device performance.
We have used the mist CVD technology, which is a safe and cost-effective technology suitable for oxide materials, for the crystal growth on c-plane substrates. As a buffer layer in order to relax the lattice mismatch between α-In₂O₃ and sapphire (∼15%), we used α-Fe₂O₃, α-Ga₂O₃, or α-(Al,Ga)₂O₃. The w-scan x-ray diffraction FWHM of α-In₂O₃ was as small as 110 arcsec. UID α-In₂O₃ showed n-type conductivity with electron concentration and Hall mobility at room temperature of, for example, 3.1×10¹⁸ cm^-3 and 143 cm²/Vs, respectively. More doping of Zn or Mg systematically reduced the electron concentration, suggesting that they acted as compensating acceptors. This means that p-type conductivity might be expected by reducing unintentionally-doped donors.
MOSFETs were fabricated using amouphous Al₂O₃ as a gate insulating layer and Au as gate and source electrodes. The device showed saturated drain current characteristics and clear pinch-off with subthreshold swing of 1.83 V/dec, field-effect mobility of 187 cm²/Vs, and effective mobility of 240 cm²/Vs. The relatively high mobility values are attractive for future evolution.
[1] D. Shinohara and S. Fujita, Jpn. J. Appl. Phys. 47, 7311 (2008)..
[2] M. Oda et al., Appl. Phys. Express 9, 021101 (2016).
[3] K. Kaneko et al., Appl. Phys. Express 8, 095503 (2015).

Transparent conducting oxides (TCOs) and transparent semiconducting oxides (TSOs) have received extensive interests and demands for the application of current optoelectronic devices. Alkaline earth stannates have recently attracted much attention as an excellent TCOs and TSOs. In particular, La-doped BaSnO₃ (LBSO) has excellent room-temperature (RT) carrier (electron) mobility (μ_e ~ 320 cm²V^-1s^-1 at n = 8.0 × 10¹⁹ cm^-3 in a single crystal) and higher electrical conductivity than previously-reported TCOs. Despite the great potential of LBSO for use in Indium-free TCOs and TOSs, epitaxial LBSO films were reported to have much lower μ_e than single crystals. This difference has been attributed to the high density of extended defects in the films, i.e., threading dislocations, which are considered as scattering centers for carriers.
In this presentation, we show significant increase in the room-temperature electron mobility of LBSO by post-annealing under N₂ at higher temperature than the growth temperature. Regardless of pre-annealing growth temperature, simple annealing under N₂ consistently doubled the RT μ_e of LBSO films on STO substrates and could achieve the maximum electron mobility of 78 cm²V^-1s^-1 at n = 3.0 × 10²⁰ cm^-3, which is comparable to the best mobility of PLD-grown LBSO films on STO substrates. The enhancement of room-temperature mobility by post-annealing is attributed to the annihilation of extended defects, along with compressive strain induced by the difference in the thermal expansion coefficients of substrates and LBSO films. Our finding suggests that the thermal strain induced by high-T annealing can be exploited to reduce the density of extended defects in LBSO films to boost their room-temperature mobility.

Gallium oxide (Ga₂O₃) has attracted great interest because of its potential for the next-generation of power electronics for its ultra wide band gap of 4.8 eV, a higher breakdown field of 8 MV/cm and potential low-cost mass production of native substrates. In this paper, we study the integration of GaN film on Ga₂O₃ by MOCVD epitaxy. We used (0 1 0) β-Ga₂O₃ substrates compared to those with other orientation like (-2 0 1), (1 0 0), (1 0 1), etc, where c-plane GaN epitaxy has been performed.
A closed coupled showerhead reactor was used for GaN epitaxy on 10 x 15 mm² Ga₂O₃ substrates. It was found that the Ga₂O₃ substrate started to decompose below 600 °C under H₂ ambient. By introducing ~5 slm NH₃, the decomposition stopped and the substrate surface stayed stable until the temperature reached ~880 °C. By using a thin low-temperature (LT) AlGaN nucleation layer (NL), the top 1.36 μm GaN layer was grown at ~1000 °C. Selected area diffraction patterns taken by TEM confirmed the GaN film was grown along the [1 1 -2 0] direction. In Ga₂O₃’s (0 1 0) plane, the GaN’s c-axis was rotated 8.7° away from Ga₂O₃’s [1 0 2] direction towards the [2 0 7] direction. Ω-2θ scan by X-ray diffraction measurement showed the crystal peaks of (1 1 -2 0) GaN and (0 2 0) Ga₂O₃ with the Ω separation of ~1.5°. All these results indicate that single-crystal a-plane GaN film was grown on the (0 1 0) Ga₂O₃ substrate. To our knowledge, this is the first time that non-polar GaN epitaxy on Ga₂O₃ has been reported. Such non-polar film may have broad application in both electronic and optoelectronic devices.
Further growth optimization indicated the GaN layer preferred low V/III molar ratio and low growth pressure. Compared to using thick NL, thin AlGaN NL helped remove pits in the surface and reduced the root mean square roughness to 0.98 nm for 1 x 1 μm² scan and 3.15 nm for 10 x 10 μm² scan respectively. This result is comparable to those achieved from GaN homoepitaxy on a-plane GaN bulk substrates.
Oxygen was found to be one of the major impurities in the GaN film, with ~10²⁰ cm^-3 in the LT NL and stabilized at ~10¹⁹ cm^-3 in the top GaN. Coating the backside of substrates by sputtered AlN helped reduce the oxygen concentration by 5X in the LT NL, but did not improve the top GaN layer grown at high temperature. A comparative study showed the growth window of c-plane GaN on (-2 0 1) Ga₂O₃ substrates was much wider. By optimizing the growth conditions, the oxygen concentration was reduced and stabilized at ~4x10¹⁷ cm^-3 in the 3 μm c-plane GaN grown. Additional effort is undergoing to further reduce the oxygen concentration in the GaN film grown on (0 1 0) Ga₂O₃ substrates.

The key to the efficient transmission and conversion of low-carbon electrical energy is the improvement of power electronic devices. Diamond is considered to be the ultimate wide bandgap semiconductor material for applications in high power electronics due to its exceptional thermal and electronic properties. Two recent developments - the emergence of commercially available electronic grade single crystals and a scientific breakthrough in creating a MOS channel in diamond technology, have now opened new opportunities for the fabrication and commercialisation of diamond power transistors.
These will result in substantial improvements in the performance of power electronic systems by offering higher blocking voltages, improved efficiency and reliability, as well as reduced thermal requirements thus opening the door to more efficient green electronic systems.
The current research carried out mainly in Japan and Europe will be presented, with the various device architectures explored, including MOSFET, MESFET, JFET and rectifiers. Results obtained in the framework of the first European research collaboration on diamond devices, aiming at fabricating the first HVDC diamond based converter will also be presented.

AlGaN/GaN-on-diamond microwave devices have demonstrated at least three times higher power density than devices grown on SiC substrates. We demonstrate the benefit of optimized seeding of the diamond growth on achieving defect free GaN-on-diamond wafers, high mechanical stability and homogenous thermal properties for use in ultra-high power microwave electronic devices. These material structures benefit from the high electron mobility of the AlGaN/GaN device layer and the high thermal conductivity of the diamond, however, the rather large coefficient of thermal lattice expansion (CTE) between the diamond and the GaN pose challenges.

In situ focused ion beam cross-sectioning was used to study GaN-on-diamond wafers, fabricated at Element-Six, seeded with different size nano/microsize particles to gain insight on the microstructure-properties relationship. Voids can form at the GaN-diamond interface if an inappropriate seeding scheme is used; physical mechanisms for the occurrence of these defects will be discussed. Using an optimized seeding approach, we demonstrate that GaN-on-Diamond wafers with no macroscopic defects can be fabricated. For the investigation of the mechanical strength of the GaN-diamond interface, a novel micro-mechanical testing approach was employed. Micro-size pillars were fabricated containing GaN, diamond and the interface between the two layers; a mechanical load was then applied onto the GaN layer to ‘pull’ it away from the diamond layer to test the strength of the interface. We find that stress in excess of 3 GPa is required to break the ‘bond’ between GaN and the diamond. This has demonstrated high interface mechanical stability, which is essential for real-life deployment of this novel material structure in device applications. To correlate the local microstructure with the thermal properties of the GaN-on-Diamond wafers, mapping of the thermal properties using a transient reflectance technique was applied. The results showed a high homogeneity of the thermal properties for defect free wafers and this provides an excellent basis for achieving high performance ultra-high power electronic devices in a manufacturing environment. The most recent advances and challenges in these areas will be presented and discussed.

This work is in part supported by DARPA under Contract No: FA8650-15-C-7517 monitored by Dr. Avram Bar Cohen, supported by Dr. John Blevins, Dr. Joseph Maurer and Dr. Abirami Sivananthan.

We fabricated hydrogen-terminated (C-H) diamond MOSFETs using the two-dimensional hole gas (2DHG) induced by coating the C-H diamond surface with Al₂O₃ insulator by high temperature atomic layer deposition (ALD) method. We have reported high breakdown voltage (>1600 V) characteristics [1] and wide temperature (10 K-673 K) operations [2, 3]. Generally, the transport properties of C-H diamond MOSFETs shows normally-on because 2DHG is induced even when applying no bias. Normally-off characteristics are required for power devices for safety operations. The normally-off type Diamond FETs have reported by using partially oxidized diamond MISFET [4], HfO₂-gated diamond FETs [5] and JFETs with narrow channel widths [6]. In this paper, we fabricated C-H Diamond MOSFETs aim at gate threshold voltage (V_th) by partial oxidation (partial C-O) and nitrogen-doped to C-H channel. V_th can be controlled by changing the level of valence band maximum. As a result, normally-off operation, high breakdown voltage and high current density characteristics were obtained.
The fabrication process was as follows. First, undoped CVD layer was deposited on Ib (001) diamond substrate and Ti/Au source/drain were deposited. Second, the diamond surface was C-H by remote plasma. Third, the channel region was partial C-O channel or nitrogen-doped. To form partial C-O channel, UV irradiation in oxygen atmosphere. And the dose of nitrogen doping was varied to 10¹⁸–10¹⁹ cm^-3. The sheet resistance of partial C-O and N-doped surface was 10⁵–10⁶ Ωsq, which is one or two orders of magnitude higher than that of typical C-H diamond. Then, Al₂O₃ passivation layer was deposited to cover partial C-O channel by ALD. Finally, Al gate was deposited.
V_th of C-H diamond MOSFETs with partial C-O channel was -3.0 V (@RT) which is high enough for power device application. V_th control and normally-off operation were achieved. The maximum drain current density of -20 mA/mm (V_DS = -50 V) was obtained, which is compatible to C-H diamond MOSFETs with no partial C-O channel. Here, the sizes of the device were L_SG = 4 μm, L_G = 15 μm and L_GD = 21 μm, respectively.The breakdown voltage of a partial C-O channel C-H diamond MOSFET was obtained 1790 V (L_GD = 21 μm, @RT). In addition, the highest breakdown voltage was obtained to 2021 V (L_GD = 24 μm, @RT) with V_th = -3.5 V. The breakdown voltage of >2 kV is the highest for diamond FETs ever reported. Threshold shift characteristics of C-H diamond MOSFETs with N doping will be exhibited on site.

[1] H. Kawarada et al., IEEE IEDM 14933800, pp.279 -282 (2014) and ISPSD pp483-486 (2016).
[2] A. Hiraiwa, H. Kawarada, et al., J. Appl. Phys. 112 (2012) 124504.
[3] H. Kawarada et al., Appl. Phys. Lett. 105 (2014) 013510.
[4] H. Umezawa, H. Kawarada, et al., J. Appl. Phys. Vol. 44, No. 11, pp.7789 -7794 (2005).
[5] J. W. Liu, Y. Koide, et al., Appl. Phys. Lett. 103 (2013) 092905.
[6] T. Suwa, M. Hatano, et al., IEEE Electron Device Lett. Vol. 37, No. 2, pp. 209 -211 (2016).

Gallium Nitiride (GaN) and diamond are two important materials in next generation power electronics and LEDs. Specifically, GaN-based transistors have high breakdown voltages and high carrier densities resulting in low resistance and high efficiency. However, as the gate size of GaN-based transistors decreases to achieve higher operating frequency, heat dissipation worsens due to boundary scattering and growth defects. It is important to limit the temperature rise in these devices because an increase in temperature will reduce electron mobility and degrade the lifetime of the device. Currently, the thermal properties of size-constrained GaN is not well characterized. In this work, we measure the thickness dependent thermal conductivity of a 15-1000nm thick GaN film heteroepitaxially grown on 4H-SiC using a unique pump-probe thermal imaging technique. Additionally, diamond grown on GaN has been proposed as a near-junction heat sink for GaN based devices. However, the thermal conductivity of these thin diamond films is difficult to measure. In this work, we also measure the anisotropic thickness dependent thermal conductivity of 1-100μm thick diamond films grown on silicon.

Diamond as a semiconductor material for electronics has potential due to its material properties including high thermal conductivity, high electric field breakdown strength, and high carrier mobilities. In this paper we will report on the diamond based power electronics work at the MSU/Fraunhofer Center for Coatings and Diamond Technologies (CCD). We will present our work to improve the quality of bulk and epitaxial mono-crystalline diamond material and its use in making vertical diamond diodes for power electronics. The desired diode characteristics in this project includes a reverse bias breakdown voltage exceeding 1000 V and a forward current exceeding 10 A. Work will be described that improves the quality of the bulk substrates by reducing the line defect (dislocation) density. Boron doped epitaxial layers are then grown on the cut substrates with conditions and processes to minimize the generation of new dislocation defects. Diode architectures being studied include a Schottky vertical diode, a Schottky quasi-vertical diode and these same structures with field plates of Al₂O₃. To make the diamond diodes, a heavily-doped p-type layer and a lightly-doped p-type layer are deposited in microwave plasma-assisted CVD reactors using boron as the dopant. Efforts are made during the lightly boron doped deposition to minimize the unwanted nitrogen and other impurity incorporation.

Diodes have been fabricated with both small Schottky contact areas of 150 micrometer diameter and larger Schottky contact areas of 2 mm². Various types of Schottky contacts have been used including gold, platinum and molybdenum. Diodes with the smaller contacts have been fabricated with breakdown voltages of over 1000 V and forward current flow densities of 500 A/cm². Diodes with the larger contacts have been fabricated with current flows up to 18 A and a current density of 900 A/cm². Diode characteristics are measured in the temperature range from 300-600 K and comparisons are made to device simulations using the MEDICI and Sentaurus TCAD semiconductor device simulators. In particular, simulation studies to better understand the reverse bias breakdown voltage and the forward on resistance will be discussed.

The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DE-AR0000455.

Based on Baliga’s FOM, GaN, AlN, and AlGaN-based Schottky diodes are expected to be superior to SiC by a factor of 6 to 200. Advances in native substrates have led to the possibility of vertical devices with low dislocation densities, thus approaching the materials’ ultimate performance. After effectively removing dislocations, new material challenges become apparent: epitaxy morphology on native substrates, point defect control, and surface manipulation. These influence the development of these switches as they determine: thickness and composition, carrier concentrations and mobility at the contact and drift layers, and Schottky barrier and passivation/isolation. Surface morphology was found to strongly depend on the substrate miscut with characteristic differences between AlN and GaN, as determined by surface kinetics. These differences become significant for AlGaN, determining composition and lateral uniformity. Point defect control leads to the achievement of the necessary high carrier concentrations in the back contacts while allowing for controllable low carrier concentrations in the drift layers; a carrier concentration of 2x10¹⁶ cm^-3 with a mobility of 1100 cm²/Vs was shown for GaN on sapphire. Besides all these achievements, it is recognized that the semiconductor surface plays a significant role in determining the performance of the devices. Therefore, understanding the state of the surface after processing and fabrication steps is necessary to develop methods to achieve the best performance on such devices. The need for proper passivation leads to the evaluation of a variety of dielectrics based on different deposition methods. Surface sensitivity techniques such as XPS allow for the evaluation of the surface electrical properties, examining proper passivation, processing steps and possible leakage mechanisms. Based on this evaluation, it was found that LPCVD silicon nitride offers a good alternative as a passivation layer. Removal of band bending in AlGaN (x < 0.6) and reduction in band bending for x > 0.6 strongly indicate no or greatly reduced surface/interface states. Results on the performance and further limitations of Schottky diodes based on these materials achievements will be discussed.

AlGaN is an attractive material for optoelectronic emitters and high power electronic (HPE) devices because its energy gap (E_G) is large, it emits in the UV, E_G can be tuned to a specific emission frequency, has a large breakdown field, the donor depth of the dopant, Si, is relatively small out to about 80% Al, and it forms a dense 2-dimensional electron gas (2DEG) when combined with GaN in a hetero-structure. Since obtaining the largest possible electron concentration in the 2DEG is frequently required for HPE devices because it minimizes the on-resistance (R_ON), most of the HPE device structures are grown with an (0001) orientation with the top layer containing more Al. This produces a tensile stress that cannot be relieved by the first order basal plane or second order prismatic dislocations slipping in from the surface because the plane strain caused by the lattice mismatch does not create a shear stress on their slip planes. As a result, the structure becomes bent if there is no plastic deformation, or plastic deformation is created by the formation of pyramidal or partial dislocations or by basal plan dislocations being formed spontaneously. By analyzing nano-indentations into, and micro-compressing pillars made from, high quality GaN material and calculating their associated stress fields, we provide insight into how the mismatch stress will be relieved in the (0001) grown AlGaN. This is done by determining the load necessary for the nano-indenter to create a large strain in a high quality GaN crystal with no increase in the load, which is often described as a ‘pop-in’ event; determining a similar load for (0001) oriented micro-pillars etched into the crystal, and also measuring the angles the slip traces on different exposed planes make with the vertical using an AFM; determining the the burgers vector and slip planes of the dislocations formed by both processes using a TEM; and analyzing the shear stresses in selected basal, prismatic, and pyramidal slip systems and comparing them with the experimental results.

AlN thin films has become a promising candidate for high-temperature power electronics, piezoelectric sensors, ultraviolet light emitting diodes (LEDs) and other optoelectronic devices, due to its unique physical properties, such as high thermal conductivity, high thermal stabilities, high surface velocity of acoustic wave(SAW) and ultra wide band gap.
In this study, the temperature-dependent optical and electrical properties of AlN/sapphire thin films with different thickness of epitaxial layers were investigated. The samples were prepared by metal-organic chemical vapor deposition (MOCVD) technique. Temperature-dependant (from 300K to 825K) ellipsometry parameters(psi and delta) of the three samples in the wavelength ( 195nm-1650 nm) at three incident angles of 50^o, 55^o and 60^o were measured by using a dual rotating-compensator Mueller matrix ellipsometer. Based on the best fit optical models and fitting algorithms by using Eometrics software, surface roughness, every layer thickness, the dependence of optical constants ( n & k ) and absorption coefficient on temperature were derived, and the fitted results are in good agreement with measured ones. It was observed that, when the temperature was raised up to 650K, the band tail of absorption edge for the samples all became more obviously and had a larger red shift than before. Comparing the fitted results of these three samples, the sample with 404nm-thick epitaxial layer had much better absorption properties and higher band gap energy than other two samples especially at high temperature. The sample with 117nm -thick epitaxial layer had the highest surface roughness and the worst absorption properties. So we argue that the thickness of epitaxial layer probably play a crucial role in the physical performance and the crystalline quality of AlN thin films at high temperature. To confirm this inference and elucidate the fundamental mechanism of the physical phenomena, other measurements such as PL, HRXRD, and high temperature Hall-effect equipment have also been employed to investigate the effect of epitaxial layer thickness on the electrical and optical performance.

For ultrahigh-voltage (UHV: > 10 kV) applications, SiC bipolar devices are of academic and technological interest. UHV and low-loss power devices are key components for future smart grids and high-voltage power supplies [1,2]. Since a typical voltage of power distribution is 6.6-7.2 kV, 13–15 kV power devices are required for constructing single-phase converters. However, several issues in the material and device physics must be addressed before UHV SiC devices exhibit a full potential and good reliability. This paper describes control of carrier lifetime and analyses of a breakdown phenomenon in SiC, aiming at development of UHV SiC bipolar devices.
The acceptor level of carbon vacancy (Vc) has been identified to be the primary carrier-lifetime killer in SiC [3]. The authors succeeded in reduction of Vc density from 1E13 to below 3E10 cm^-3 by high-temperature oxidation. The nearly Vc-free region can be extended to a 150–200 μm deep region by increasing the oxidation temperature or oxidation period. On the other hand, the Vc defects can be intentionally generated by either low-energy electron irradiation (kick-out of carbon atoms by particles) or high-temperature thermal treatment (approaching the equilibrium defect density). By these techniques, the Vc density can be changed in the wide range from 1E11 to 1E16 cm^-3. Although the typical carrier lifetime of as-grown SiC epitaxial layers is 1 us, the carrier lifetime can be controlled from about 10 ns to over 50 μs by combination of the elimination and intentional generation of Vc defects.
Toward quantitative analyses of breakdown phenomena in high-voltage devices, the authors have started a basic study on the impact ionization coefficients in SiC [4]. Various types of dislocation-free pn structures having different doping and thicknesses were fabricated, and the photo-multiplication characteristics were measured by using a filtered short-wavelength light (250–270 nm). Separation of electron-initiated and hole-initiated avalanche phenomena was made by employing p⁺/p/n⁺ and n⁺/n/p⁺ diode structures. From the electric-field dependence of multiplication factors experimentally obtained, the impact ionization coefficients were accurately determined in the electric-field range from 1.0 to 3.3 MV/cm. Furthermore, the ionization coefficients were extracted in the wide temperature range from 150 to 673 K. Device simulation by using the new set of impact ionization coefficients has enabled prediction of accurate breakdown voltage (including its temperature dependence) for any kinds of SiC devices.
Impacts of carrier-lifetime control and accurate determination of the impact ionization coefficients on 10–20 kV PiN diodes are described at the symposium.
[1] J. Wang et al., IEEE Indust. Electronics Magazine, June, 2009, p. 16.
[2] T. Kimoto, Jpn. J. Appl. Phys., 54, 040103 (2015).
[3] K. Danno et al., Appl. Phys. Lett., 90, 202109 (2007).
[4] H. Niwa et al., IEEE Trans. Electron Devices, 62, 3326 (2015).

SiC-MOSFETs, which are key device for high efficient electric power conversion, have still had serious problems (e. g. low channel electron mobility and threshold voltage variation) whose origin is thought to be insufficient quality of SiO₂/SiC interface. For further improvement of interface quality, it is important to clarify the origin of poor interface quality. There are several techniques for characterizing MOS interface properties. Deep level transient spectroscopy (DLTS) [1] is one of powerful techniques capable of macroscopic quantitative evaluation of trap density at/near MOS interface. For not only macroscopic but also microscopic evaluation, scanning DLTS, which measure trap distribution by stimulating trap using electron beam, was proposed. On the other hand, DLTS using SPM [2] has also been proposed and its feasibility has been shown. However, in our best knowledge, in spite of SPM’s advantage of high spatial resolution 2-dimensional (2D) imaging ability, SPM based DLTS 2D imaging has not been reported. In this paper, super-higher-order scanning nonlinear dielectric microscopy (SHO-SNDM) [3] based local DLTS and its 2D imaging are proposed. This method is demonstrated with oxidized SiC wafer. We measured three n-type silicon face (4°-off) 4H-SiC wafer samples on which 45-nm-thick thermally grown silicon dioxide film was formed. Two of them were followed by post oxidation annealing (POA) in nitric oxide ambient with different annealing conditions: (a) 10 min in 1250°C and (b) 60 min in 1150°C. We label the samples without POA, with POA in condition (a) and with POA in condition (b) as #1, #2 and #3, respectively. By analyzing the acquired images, time-constant t and magnitude c(t) of local transient capacitance response were obtained at each pixel. At first, all local DLTS spectra were added and averaged in each images. Clear peaks were observed between 0.4ms and 1ms, which was roughly consistent with the time-constant of O2 trap at RT, i.e. one of the previously reported traps detected by macroscopic constant capacitance DLTS [5]. In addition, highest peak value was obtained from #1 (without POA) and lowest peak value was obtained from #3 (POA at 1250°C for 10min), which is consistent with macroscopically obtained result. Furthermore, we obtained local DLTS images and found they had dark and bright areas, which can be translated as trap distribution. Thus, we conclude that this technique can contribute to understanding of physical properties of SiO₂/SiC interface.
[1] D. V. Lang: J. Appl. Phys. 45 (1974) 3023.
[2] A. L. Tóth et al.: Mat. Sci. Semi. Proc. 4 (2001) 89.
[3] N. Chinone et al.: J. Appl. Phys. 116 (2014) 084509.
[4] Gang Liu et al.: Appl. Phys. Rev. 2 (2015) 021307.
[5] A. F. Basil et al.: J. Appl. Phys. 109 (2011) 064514.

Silicon Carbide (SiC) is one of excellent semiconductor materials for power semiconductor application because of its large bandgap. SiC metal-oxide-semiconductor (MOS) field-effect-transistors (FETs) still suffer from severe degradation of channel electron mobility due to imperfect SiO₂/SiC interface [1]. Usually, SiO₂/SiC interface quality has been characterized by fabricating MOS capacitor on the sample, which needs additional processes following the oxidation and annealing process. Because, in research & development (R&D) of devices, many sample fabrications and characterizations are required, simple characterization technique with shorter characterization time is effective to shorten the R&D cycle.
Previously, it has been suggested that scanning nonlinear dielectric microscopy (SNDM) [2] gives images which may correlate with the interface state density of SiO₂/SiC interface [3]. SNDM measurement does not require additional process after oxidation and annealing process. Therefore, SNDM is a candidate of easy and sophisticated method for interface quality characterization.
In this paper, oxidized (45-nm thick SiO₂) four silicon-face (Si-face) and five carbon-face (C-face) wafers heat treated under various post-oxidation-annealing conditions are measured by SNDM and method for evaluating SiO₂/SiC interface quality using SNDM is proposed.
2μm × 2μm areas on these nine samples were measured by SNDM in air at room temperature. For interface quality evaluation, we calculated a standard deviation (STD) of signal level in each SNDM image and then this STD value was divided by the mean value of SNDM signal in each image. We call this value “normalized STD”. We examined the relationship between normalized STD and macroscopically measured interface trap densities (Dit) evaluated by conventional High-Low method using MOS capacitor. It was found that normalized STD had very good correlation with Dit, i.e. it was lineally proportional to Dit. In addition, the data were reproducible even with different tip. This means that normalized STD is a universal parameter showing the SiO₂/SiC interface quality both for Si and C-face. These results demonstrate that Dit in oxidized Si-face and C-face can be estimated from SNDM image without fabricating MOS capacitor. Thus, this technique measuring normalized STD by SNDM enables us to quickly examine the effect of variation of process parameters in MOS fabrication and to effectively reduce the time needed for R&D cycle.
[1] Gang Liu et al.: Appl. Phys. Rev. 2 (2015) 021307.
[2] Y. Cho et al.: Rev. Sci. Instrum. 67 (1996) 2297.
[3] N. Chinone et al.: Proceedings of ICSCRM2015(in print).

The interface between 4H-SiC and SiO₂ in metal oxide semiconductor field effect transistors (MOSFET) contains many electrically active defects, which adversely affect the performance of SiC microelectronic devices by lowering the electron mobility. The devices' electrical properties are improved by a number of treatments, the most prevalent of which is a nitric oxide (NO) post-anneal. Additionally, devices fabricated on different crystallographic faces of SiC show markedly different performance. Furthermore, newer passivation schemes such as boron and phosphorous anneals cause significant performance gains, with relatively poor understanding of the underlying mechanisms. Our previous work on NO annealed devices has shown an inverse relationship between anneal time and the width of the transition layer (w_TL) at this interface, which is correlated with improved channel mobility, increased N interfacial density, and decreased charged interface trap density. More recent work analyzing w_TL at interfaces of varying orientation has revealed much narrower interfaces that do not appear to decrease in thickness when subject to an NO post-oxidation anneal, contradicting the expected trend.

To further explore the characteristics of these interfaces, high resolution transmission electron microscopy (HRTEM), high-angle annular dark-field scanning TEM (HAADF-STEM), and spatially resolved electron energy-loss spectroscopy (EELS) have been used. We have investigated SiC/SiO₂ interfaces fabricated on the Si-face, with and without miscut, as well as on the a-face. Transition layer information was obtained using EELS at the Si-L_2,3 C-K, and O-K edges. Hyperspectral unmixing of the EELS data using machine learning techniques has revealed previously obscured bonding states at the interfaces, helping to explain the origins of mobility enhancement caused by NO anneals. Various interfacial states are presented and compared, and the effect of both substrate orientation and NO post-oxidation annealing is explored.

Boron and phosphorous annealed devices were analyzed with similar techniques, revealing significantly different mechanisms of incorporation for the passivating species compared to NO. P was found to preferentially cluster throughout the oxide, potentially explaining the origins of polarization instability observed in such devices. In contrast, B distributes more uniformly, but with a pile-up at the interface accompanied by an adjacent depletion region, which is expected to have significant effects on device performance.

Our results explore the differences in the chemical and electronic structure of the 4H-SiC/SiO₂ interface for different processing methods, and demonstrate the importance of controlling the quality of the interface in SiC power electronics. Our methods provide a framework for analyzing devices processed under a range of various conditions.

*Supported by ARL under Grants No. W911NF-11-2-0044 and W911NF-07-2-0046, and NSF GRFP Grant No. DGE 1322106

Electronically detected magnetic resonance (EDMR) is a technique, which allows for the observation and characterisation of defects within semiconductors. Offering selectivity and sensitivity advantages over traditional electron paramagnetic resonance (EPR) techniques. Even with these advantages interpretation has long proved challenging, with many potential candidate defects seeming to qualitatively explain an observed signal. In this approach defect spectra are identified by comparing EDMR measurement to extensive ab initio calculations. This allows a defect identification based upon atomic composition, symmetry, and hyperfine (HF) structure. This approach was initially successfully applied to the identification of bulk defects has now been extended to defects at the SiC / SiO₂ interface.

A universally agreed upon description of the SiC / SiO₂ interface is a challenge with models varying from the abrupt to the highly disordered, thankfully as a starting point the EDMR was able to guide the way. From the anisotropy of the g-tensor it is clear that the defect(s) of interest is on the SiC side of the interface in a crystalline environment. This has allowed the simulations using an abrupt interface based upon the model of Devynck and Pasquarello, allowing the defects studied to be considered in a crystalline environment, at and just below the interface. After an exhaustive survey of the potential defects, both suggested by previous literature and imagined, we were able see an excellent agreement between the EDMR and the simulation from the family of defects based upon carbon dangling bond(s), with the carbon dangling bond(s) aligned along the surface. This is in good agreement with the work of Bardeleben et al where a defect of similar type was observed in an oxidised porous sample (PbC - Centre).

Silicon Carbide (SiC) based devices have been an emergent device technology for the last 20 years. Huge leaps forward have been made during this time, taking devices from the lab bench to commercially available diodes, MOSFET, and integrated power modules. For the full potential of SiC to be realized, a number of challenges remain to be overcome. Key amongst these is the high defect concentration inherent in SiC devices, to tackle this, defect identification and passivation is critical.

Combining the single defect selectivity of electrically detected magnetic resonance measurement (EDMR) with theoretical modelling gives the potential to unambiguously identify performance limiting defects within fully processed devices. Comparing the EPR parameters, defect symmetry, charge state, multiplicity, and elemental composition allows defect identification with a high degree of confidence. Through this combination of techniques a systematic approach has been formulated to facilitate defect identification. Once a defect is identified the interaction of the defect with various atomic and molecular species are considered. This allows a systematic approach to passivation, moving away from the current bottom-up approach.

This approach was initially used to study defects within N-implanted pn-junctions, allowing the N_CV_Si to be identified as the main source of N-dopant deactivation and poor mobility. The work of Kimoto et al. and Miyake et al. showed an improvement in device characteristics after a high temperature C-anneal. This was suggested to be due to the ‘healing’ of V_C present within the lattice. With the N_CV_Si identified a competing mechanism has been identified resulting in the conversion of the N_CV_Si defect into the N_CC_Si which shows excellent agreement with the available experiment data.

Silicon carbide power devices switching greater than 100kHz enable new benchmarks in power converter performance. These converters will enable power systems where all the sources and loads are connected by converters. These new systems are multifunctional and highly-integrated. However, their realization requires research in areas such as: advanced power electronic control across many converters, concepts for distributed storage, and active filtering across many converters.

A primary concern of SiC field-effect structures for power electronics is the reliability of the gate oxide under operating conditions, such as the high internal temperatures attained during power switching operations. Applications of a potential bias on the gate electrode of a metal-oxide-SiC device regulates the carrier concentration in the transistor channel. Stable device operation requires that the electric field across the dielectric remain constant in time, i.e. during the entire life-cycle of the device, as well as space, i.e. from source to drain. Imperfections at the SiO₂/SiC interface result in localized points for electrical breakdown and also scattering centers that reduce the carrier mobility within the FET channel. Although circuit designers prefer large area gates for optimum device performance, oxide reliability issues usually force a compromise between gate size and device lifetime. We report on large area (1000µm diameter) n-MOS capacitors with extremely low gate leakage current densities (<10 nA/cm²), measured during accelerated age testing at high temperature (600C). Additionally, the thermal generation of equilibrium minority carriers (holes) during inversion biasing in these structures, provides a measure of the structural and electrical quality of the SiO₂/SiC interface itself.

n-MOS capacitors were fabricated on 6H-SiC and 4H-SiC substrates. The gate oxide (~ 39 nm) was grown via dry oxidation at 1150C, followed by a 900C Ar anneal and a 2 hour 1175C NO anneal. The gate metal is 100 nm of Pt sputtered at 350C. Each sample has fifty two 100 - 1000 µm diameter gates. The noise of our electrical characterization system at 630C is ±2pA for the current-voltage data and ±2pF for capacitance-voltage data.

Gate Leakage Current 330C < T < 630C: Following thermal stress, oxide leakage measurements were made on independently processed chips, with 500 & 1000 µm gates. Chip 1 was held at 530C for 5hours; the current density (J) of all devices is below 2pA/cm². Chips 2 and 3 were measured at 330C < T < 630C. Below 450C, all 10 devices exhibit J< 5nA/cm², irrespective of size or location on the 1cm² substrate. On chip 2, two 1mm capacitors have J<4nA/cm² even at 630C and 50% of the gates are <10nA/cm² at all temperatures. This data along with the fact that the flat band voltage for all the gates is close to theory demonstrates the stability of the oxide with respect to time-dependent dielectric breakdown.

High frequency inversion capacitance at 300C < T < 630C: 1 MHz C-V characteristics of a 1000 µm capacitor were obtained by sweeping from accumulation (Vg=10V) to Vg=-8V at 0.4 V/s without using optical illumination to generate minority carrier, i.e. in the dark. For T>450C as the gate bias voltage drops below 0V, holes thermally generated from the n-type substrate create an inversion layer under the gate. The temperature dependence of the measured inversion capacitance is in agreement with the delta depletion approximation.

Ultrafast laser irradiation offers a unique approach to modifying material properties at the surface. One of the most intriguing phenomenon observed in ultrafast laser-matter interaction studies is the formation of high spatial frequency laser induced periodic surface structures (HSFL). In this work, the characteristics and possible mechanisms of HSFL formation in SiC as well as its effect on electrical conductivity is discussed.
Recent studies have suggested a connection between the surface defect density and HSFL formation in SiC evidenced by the laser spot size dependence on HSFL formation threshold. In our study, the formation of HSFL is observed to also be highly dependent of temperature. Preliminary result indicates that the threshold of HSFL formation increases when irradiated at 800°C compared to room temperature. This suggests stronger interactions between the irradiating laser and the electronic states induced by crystallographic defects and impurities. This is reasonable considering infrared laser irradiations would be absorbed mainly through multi-photon processes due to the relatively large band gap of SiC. Additionally, at the same irradiation fluence, significantly less debris is observed at 800°C. This debris, at room temperature, was studied with XPS and Auger and shown to be silicon oxides. Hence, temperature is observed to have a significant effect on the ablated materials chemistry.
The formation threshold of HSFL decreases as the number of pulses is increased. We speculate defect accumulation within the crystal leads to a higher degree of laser absorption with each laser pulse. The absorbed laser energy is then proportional to the magnitude of local ablation leading to the HSFL morphology. Laser interactions with semiconductors have indicated significant bond softening occurs during ultrafast laser induced band gap collapse and are strongly linked to the formation of point defects in crystals. The mechanism of point defect formation in semiconductors will be thoroughly discussed in the context of SiC.
Finally, large area irradiations of 4H-SiC substrates show significant electrical conductivity increase when HSFLs are present. The experiments are conducted in air (1 atm), vacuum and high purity N₂ (0.8 atm) environments. Notably, laser irradiations in N₂ environment yield consistently, several orders of magnitude, higher electrical conductivity compared to air and vacuum environments. We suggest a higher degree of nitrogen incorporation to the SiC surface chemistry during and after strong transient non-equilibrium conditions induced by laser irradiation. We will discuss the role that vacancy concentration and bonds softening play in Nitrogen incorporation. The use of N₂ ambient environment may also prevents oxide formation during irradiation and subsequent native oxide formation outside the irradiation chamber.

The advent of high quality SiC wafers has stimulated the use of this material in applications ranging from high power, high frequency and/or high temperature MOSFET-like devices to applications in bio-technology. Such SiC biomedical applications make use of its good bio-compatibility and high chemical inertness. In such bio applications, understanding and controlling the surface termination is critical, since can influence the biocompatibility. For example it has been found that when a polymeric surface is treated to become N-enriched, it promotes cell adhesion. Due to the important role of N in the electrical passivation of SiC and foreseeing its applications in bio-compatible devices, the characterization of nitrogen up-take at the SiC surface was investigated in this work.
Different SiC nitridation methods were performed: N₂ plasma exposure, NO or NH₃ thermal nitridations. The atomic N quantification, its chemical environment, wettability, and surface morphology were obtained after HF etching to remove the formed film. Different amounts of N and oxygen (O) that remained after etching were quantified at the SiC wafer surface. N incorporation was mainly in the silicon nitride-like form, with smaller proportion of silicon oxynitride. The more N incorporated, the less O was detected, and the increase in the N/O ratio resulted in a significant increase in the hydrophobicity on the SiC surfaces. Qualitatively this surface wettability effect is consistent with the behavior of N as a passivating agent of the SiC/N/SiO₂ MOSFET devices. Variable control of SiC surface energies, from primarily hydrophilic to hydrophobic, with a simple and controllable atomic additive that is also effective in device performance, can provide new opportunities for SiC biomedical applications.

Cubic silicon carbide (3C-SiC) is a promising new material for switching devices in the medium voltage range because of its superior channel mobility compared to hexagonal silicon carbide (4H and 6H-SiC). Due to the lack of 3C-SiC bulk material as substrates for epitaxy, 3C-SiC is typically grown on either silicon or hexagonal SiC. Growth on silicon substrates reduces cost, but also leads to a large number of defects in the grown layer. These defects are caused by the mismatch in the lattice constant, thermal expansion coefficienct, and the basic lattice structure (polar vs. unipolar). This leads to defects including anti-phase boundaries, dislocations, stacking faults, and twins.

We will present the heteroepitaxial growth of 3C-SiC on hexagonal silicon carbide substrates and homoepitaxially on 3C-SiC templates using our hot filament chemical vapor deposition (HF-CVD) technique. These substrates promise superior layer quality compared to silicon substrates due to their much better match in lattice parameters and thermal expansion. While conventional CVD has been extensively used to grow 3C-SiC, there are only a limited number of reports of HF-CVD growth of 3C-SiC and even fewer reporting the FWHM of the double rocking curve. Still, the HF-CVD method holds the promise of improved growth because of the hot filaments that precondition the gases, cracking silane and propane and creating monoatomic hydrogen. This additional degree of freedom enables further optimization of the growth process and growth at lower temperatures.

3C-SiC epi layers ranging in thickness from 0.6 to 15 µm were grown in a high-vacuum HF-CVD system on both on-axis 6H wafers and 3C-on-4H templates purchased from Ascatron (Sweden). Silane (25-50 sccm) and propane, diluted with 5 slm hydrogen, flow through an array of 1800°C filaments before reaching the substrate. Nominal growth parameters are a substrate temperature and pressure of 1450°C and 3 Torr respectively. Growth is initiated after a hot-hydrogen etch and a carbon-precursor preflow. Typical growth rate is 1-4 µm/hour. Multiple runs were performed with varying carbon to silicon ratio. Crack-free layers were obtained with surface topology varying from rough to smooth. The domains are clearly oriented. Micro-Raman confirmed the presence of crystalline 3C-SiC and XRD omega scans revealed a FWHM as low as 149 arcsec. High quality material, comparable to values in the literature as determined by XRD, was obtained for a C:Si ratio in the range around 0.45 to 0.50.

We will present the latest results using high resolution scanning electron microscopy and atomic force microscopy for surface imaging, X-Ray rocking measurements to assess the crystalline quality, and micro-Raman to evaluate doping and strain. A comparison to growth on low-cost silicon substrates will be included.

This talk presents the current research activities of the BU Computational Electronics Group aimed at developing multi-scale modelling approaches to study semiconductor materials and devices. The first part of this talk will discuss the application of this methodology to understand the breakdown properties of wide band gap semiconductors, in particular GaN, AlGaN and AlInN. Starting from the DFT-based electronic structure calculation and computing the carrier-phonon interaction without including fitting parameters, it will be shown that it is possible to predict macroscopic device performance of GaN p-i-n structures. Subsequently, we will discuss the breakdown characteristics of AlGaN and AlInN alloys with regard to their potential use in power devices. Finally we will show hoe the modelling approach can be applied to the study of complex power devices, such has GaN-MOS power switches.

The work at Boston University has been supported in part by the U.S. Army Research Laboratory through the Collaborative Research Alliance (CRA) for MultiScale multidisciplinary Modeling of Electronic materials (MSME), and NSF.

For decades, density functional theory (DFT) has systematically underestimated one-electron band gaps in insulators and semiconductors. Unfortunately, this problem has been conflated with other difficulties surrounding the calculation of defect levels across these gaps, especially in semiconductors. It is often claimed that a good DFT band gap is required to obtain accurate estimates of defect levels and that hybrid screened exchange (HSE) functionals, which admix a fraction of non-local exchange - a fraction that can be semi-empirically adjusted to fit the experimental band gap, provide a path to the accurate calculation of defect levels. However, Schultz and Edwards have shown that defect levels calculated from total energies have no relation to the one-electron band gap — that for a variety of exchange correlation potentials that yield widely varying one-electron band gaps, the defect levels are to a surprising degree invariant [1]. Moreover, Schultz and coworkers have shown that, within the Local Moment Counter Charge (LMCC) approximation [2], DFT can do extremely well estimating experimental band gaps in a variety of materials including Si, GaAs, and CsI using the full spectrum of calculated defect levels to define the gap when these defect levels span the experimental gap [1,3,4]. We have recently applied the LMCC method to cubic SiC. The experimental band gap (2.39 eV) compares well with the defect band gap (2.4 eV) obtained from the LMCC. We will compare these results to results for hexagonal SiC, and also present results comparing defect levels in cubic and hexagonal GaN.

[1] P. A. Schultz and A. H. Edwards, Nulear Instruments & Methods in Physis Researh, Section
B: Beam Interactions with Materials and Atoms 327 , 2 (2014).
[2] P. A. Schultz, Phys. Rev. Lett. 84, 1492 (2000)
[2] P. A. Schultz, Phys. Rev. Lett. 96, 246401 (2006).
[3 R. Van Ginhoven and P. A. Schultz, J. Phys. Condens. Matter 25, 495504 (2013).

GaN is a highly promising material for solid state lighting and high power electronics. Light emission and charge transport in GaN are regulated by the dynamics of excited carriers at femtosecond to nanosecond timescales. The microscopic carrier scattering processes occurring in this ultrafast regime are challenging to access experimentally and not completely understood, yet they are crucial to understand GaN based light emitting devices. In particular, the rate at which carriers with excess energy with respect to the band edges (so-called hot carriers, HCs) lose energy and relax to the band edges remain the subject of debate. This talk will discuss first principles calculations of HC dynamics in GaN and address the rate and microscopic mechanisms of HC energy loss. Employing density functional theory plus ab initio electron-phonon (e-ph) calculations, we compute the e-ph scattering relaxation times (RTs) for electrons and holes with energies within 5 eV of the band edges, and resolve the contribution of the different phonon modes to the RTs. We find a significant difference in the dynamics of hot electrons and holes in GaN, which we attribute to the different density of states and orbital character of the valence band and conduction band states. We compute a RT of approximately 10 fs for electrons at the conduction band minimum, in excellent agreement with the experimental lifetime of 16 fs. While we find a dominant contribution to the RTs by the long-range polar interaction of the longitudinal optical (LO)-mode at the band edges, we also find dominant contributions by the non-polar phonon modes at higher energies into bands, a result that challenges the accepted notion that the relaxation mechanism for HCs in GaN is LO phonon emission. Our work is the first ab initio calculation of e-ph RTs in a polar material; it introduces novel grid sampling and e-ph matrix element interpolation techniques, which will be discussed briefly.

Due to its unique optical and electrical properties, wurtzite gallium nitride (GaN) is an important compound semiconductor in a variety of electronic and optoelectronic device technologies. In many of these devices, high electric fields and current densities often lead to elevated temperatures and mechanical stresses, both of which may compromise device performance and reliability. Owing to its high spatial resolution, micro-Raman spectroscopy is one of the most useful techniques in measuring local temperature rise, stress, and electric field in GaN-based high electron mobility transistors (HEMTs). In this work, we discuss the complex dependence of the optical phonon frequencies of wurtzite GaN on a finite electric field, which is critical in properly decoupling the contributions of strain, stress, temperature rise, and electric field to changes in the Raman spectrum of devices under bias.
In the presence of a finite electric field, wurtzite crystals deform by changes in the lattice constants a and c (associated with macroscopic strain) and in the internal structural r parameter (describing the Ga-N bond length along the c-axis). These changes in atomic coordinates affect the interatomic force constants (IFCs) and shift the phonon frequencies. The electric field, however, is different from an imposed mechanical stress in that the electric field changes the internal structural parameters of the unit cell and phonon frequencies even at zero macroscopic strain (fixed values of the lattice constants). To quantify these frequency shifts, it is important to include separate contributions of the strain and electric field in the linear potential deformation theory formalism, which shows that there must be a contribution of the field to the frequency shift apart from the IPE-induced strain.
To support this theory, we have calculated the contribution of the electric field apart from the IPE-induced strain with density functional theory (DFT) and measured the zone center optical phonon frequency shifts in wurtzite GaN HEMTs biased in the pinched OFF state using micro-Raman spectroscopy. Our DFT calculations show that the E₂ high and A₁ (LO) modes shift by -1.38 and 2.16 cm^-1/(MV/cm), respectively, with the electric field along the c-axis apart from the IPE-induced strain. These coefficients are an order of magnitude larger than those associated with the IPE-induced strain and properly account for the observed Raman peak shifts in GaN HEMTs with increasing drain bias in the pinched OFF state. This result helps to clearly explain the reason the pinched OFF state removes the effect of the electric field and IPE-induced stress on micro-Raman temperature measurements in the ON state. In a broader context, a quantitative understanding of this mechanism is also required for accurate measurements of temperature, stress, strain, and electric field via micro-Raman spectroscopy in all wurtzite and zincblende crystals.

We are simulating how misfit dislocation arrays evolve during growth and annealing of lattice-mismatched III-nitride heteroepitaxial thin films. III-nitrides typically have very high densities of dislocations due to a lack of inexpensive native substrates. While devices in III-nitride materials typically have a higher tolerance to dislocations than other semiconductors, there is still a strong correlation between the defect density and the device performance and lifetime. In addition to the defects which propagate from the substrate, lattice mismatch can lead to nucleation and growth of misfit dislocations to relieve the layer strain.

Our goal is to quantify the kinetic and energetic parameters that govern the evolution of the dislocation array, and to integrate that knowledge into a predictive simulator. In particular, we are initially exploring misfit dislocations which enable relaxation of layer strain for a-plane AlGaN/GaN films. Here the shear stress is resolved onto both the prismatic and less mobile pyramidal planes, providing the opportunity to simultaneously observe kinetic relaxation processes that are expected to proceed at different rates in the same sample.

The simulator has been adapted from our previous work on Ge_xSi_(1-x)/Si films, recognizing the substantially different dislocation densities, energetics, configurations, and kinetics between these materials. For Ge_xSi_(1-x)/Si, we were able to show that refinement of dislocation nucleation models using only around two dozen experimental data points allowed for quantitative prediction on (110) interface films. We are extending such refinement methods to the III-nitrides through growth and in-situ TEM annealing of films based on critical thickness and excess stress calculations.

In addition to the experimental refinement of the dislocation simulator, we have also performed first principles calculations to explore the effect of dislocation core structures on defect levels in the bandgap of GaN. Using density functional theory, we have identified the presence of a midgap state for the a-type edge dislocation, and predict that it can be passivated by the migration of oxygen interstitials to the dislocation core. Using the results from hybrid theory DFT for the position of the deep state for the a-type edge dislocation, initial Shockley-Read-Hall calculations predict that the deep state is unlikely to lead to significant recombination currents.

In summary, our overall goal is to combine experiment, simulation, and refinement to produce a robust simulator of misfit dislocation arrays and – through first principles calculations – their (opto)electronic properties in III-nitride heteroepitaxial thin films.

We would like to acknowledge the support of the NSF through grant DMR-1309535.