Robert R. Keller National Institute of Standards and Technology
W. Jud Ready Georgia Institute of Technology
Meyya Meyyappan NASA Ames Research Center
Manish Chhowalla Imperial College London
B1: Carbon Nanotube Devices - FETs and Interconnects
Monday AM, November 29, 2010
Room 310 (Hynes)
9:15 AM - **B1.1
Application of Carbon Nanomaterials to Interconnects and Transistors for Low Power-consumption Large-scale Integrated Circuits.
Shintaro Sato 1 2 3 Show Abstract
1 , Fujitsu Laboratories Ltd., Atsugi Japan, 2 , MIRAI-Selete, Atsugi Japan, 3 , AIST, Tsukuba Japan
As the dimensions of large-scale integrated circuits (LSIs) decrease, it is becoming more and more difficult to improve the speed and the power consumption of LSIs just by miniaturization. We are trying to employ carbon nanomaterials including carbon nanotubes (CNTs) and graphene, which have excellent electrical properties, for interconnects and transistors of future low power-consumption LSIs. In this presentation, I will talk about CNT interconnects, which have been addressed at Fujitsu and MIRAI-Selete for years. Special emphases will be placed on the fabrication process of CNT vertical interconnects  and their reliability. I will also explain our recent progress on the application of graphene to transistor channels. Graphene synthesis on a 200-mm Si wafer and the fabrication of graphene transistors using newly-developed transfer-free processes  will be described. Furthermore, a self-organized structure consisting of graphene connected vertically to aligned CNTs  will be introduced. Possible applications of such a structure will also be described.
The work related to CNT interconnects was completed as part of the MIRAI Project supported by NEDO. The graphene-related work was partly supported by the Japan Society for the Promotion of Science (JSPS) through its “Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program).”
 S. Sato, et al., Sensors and Materails, 21, 373 (2009).  D. Kondo, et al., Appl. Phys. Express 3, 025102 (2010).  D. Kondo, et al., Appl. Phys. Express 1, 074003 (2008).
9:45 AM - B1.2
Direct Comparison of Separated Carbon Nanotube Thin-film Transistors Using 95% and 98% Semiconducting Nanotubes and Their Application in Digital Integrated Circuits.
Chuan Wang 1 , Jialu Zhang 1 , Chongwu Zhou 1 Show Abstract
1 Electrical Engineering, University of Southern California, Los Angeles, California, United States
Pre-separated, semiconducting enriched carbon nanotubes hold great potential for thin-film transistors and integrated circuit applications due to their high mobility, high percentage of semiconducting nanotubes, and room-temperature processing compatibility. Here in this paper, we report, for the first time, the progress on the application of separated nanotube thin-film transistors for macroelectronic integrated circuits. We have systematically and directly compared the key performance metrics such as on-current density, on/off ratio, transconductance, and mobility of devices using separated nanotubes with 95% and 98% semiconducting nanotubes and revealed the trade-off between the on-current density and on/off ratio. The devices with optimized performance have been used to demonstrate integrated digital logic blocks with symmetric input/output behaviour, which is crucial to allow the cascading of multiple stages of logic blocks and larger scale integration. Moreover, due to the highly uniform nature of the devices, integrated inverters with different voltage gains have be achieved by simply changing the device dimensions in the layout design, and the results are in accordance with conventional silicon field-effect transistor circuit design theory. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.
10:00 AM - B1.3
Inverters based on Carbon-nanotube Transistors with Switching Frequencies Above 1 MHz on Glass.
Hyeyeon Ryu 1 , Daniel Kaeblein 1 , Ute Zschieschang 1 , Oliver Schmidt 2 , Hagen Klauk 1 Show Abstract
1 Organic Electronics, Max Planck Insitute for Solid State Research, Stuttgart Germany, 2 Electrical Engineering and Information, Technology,Chemnitz University of Technology, Chemnitz Germany
Nanoscale field-effect transistors (FETs) based on individual semiconducting carbon nanotubes are of interest for circuits with high integration densities that can be made on inexpensive, large-area substrates, such as glass or flexible plastics. While the static performance of FETs based on individual carbon nanotubes has been discussed many times [1-3], there are only a few reports on the dynamic performance of carbon-nanotube circuits [4-6]. Bachtold et al. and Javey et al. measured signal delays of 30 msec  and 750 µsec , but the switching speed of their circuits was limited by off-chip interconnects that introduced with large parasitic capacitcances. Chen et al. realized fully integrated circuits with a record delay of 1.9 nsec , but these complementary circuits required p-channel and n-channel carbon-nanotube FETs, the latter of which are difficult to obtain and are usually not stable in air. We have fabricated arrays of p-channel carbon-nanotube FETs on glass substrates, integrated the FETs with on-chip load resistors based on vacuum-deposited amorphous carbon films, and measured signal delays as small as 12 nsec. First, an array of probe pads was defined by electron-beam lithography, Ti/AuPd evaporation, and lift-off. Gate electrodes were then defined by e beam lithography and deposition of 30 nm thick Al. The Al gates were briefly exposed to an oxygen plasma to create a 3.6 nm thick AlOx layer, and a 2.1 nm thick phosphonic acid monolayer was then allowed to self-assemble from solution. The total thickness of the AlOx/SAM gate dielectric is 5.7 nm. Carbon nanotubes produced by arc discharge were then deposited from a suspension. Using scanning electron microscopy an individual nanotube was located on each gate, and a pair of AuPd source/drain contacts was defined by e beam lithography for each device. The channel length is ~400 nm. Some of the devices are metallic, but many show useful FET characteristics with ON/OFF ratios up to 107 and ON-state drain currents >1 µA at 1 V. To realize logic circuits we fabricated load resistors on the same substrate by evaporating a thin layer of amorphous carbon, patterned by e-beam lithography. The resistors have excellent linearity and resistances between 105 and 108 Ω, depending on the geometry and film thickness. Inverters composed of a carbon-nanotube FET and an amorphous-carbon load resistor have full output swing and small-signal gain up to 15. To estimate the dynamic performance of the FETs we extracted the time constants from the measured output-signal transitions. When the FETs switch from the OFF-state to the ON-state, the time constant is about 12 nsec, which suggests a maximum frequency of ~10 MHz.  Javey et al., Nano Lett. 2005, 5, 345.  Appenzeller et al., Phys. Rev. Lett. 2004, 93, 196805.  Chen et al., Appl. Phys. Lett. 2005, 86, 123108.  Bachtold et al., Science 2001, 294, 1317.  Javey et al., Nano Lett. 2002, 2, 929.  Chen et al., Science 2006, 311, 1735.
10:15 AM - B1.4
Stable Conversion of Separated Carbon Nanotube Thin-film Transistors from P-type to N-type by Atomic Layer Deposition of High-k Oxide and Its Application in CMOS Digital Circuits.
Jialu Zhang 1 , Chuan Wang 1 , Yue Fu 1 , Yuchi Che 1 , Chongwu Zhou 1 Show Abstract
1 Electrical Engineering, University of Southern California, Los Angeles, California, United States
Pre-separated, semiconducting enriched carbon nanotubes hold great potential for thin-film transistors (TFTs) and integrated circuit applications due to their extraordinary mobility, high on/off ratio and room-temperature processing compatibility. The main challenge it still facing is how to fabricate air stable N-type thin-film transistors with industry compatible techniques. Here in this paper, we report the method of converting as-made P-type separated nanotube thin film transistors (SN-TFTs) into N-type transistors by adding a high-k oxide layer on top of the device using Atomic Layer deposition (ALD) and its application in CMOS macroelectronic digital circuit. The absorption of oxygen and accumulation of fixed charge in the nanotude dielectric layer interface during the ALD process are proved to be the reasons of the carrier type conversion by designed experiments. The N-type devices exhibit comparable electrical performance as the P-type SN-TFTs in terms of on-current, on/off ratio and device mobility. A CMOS inverter with symmetric input/output behaviour and large noise margin has also been demonstrated. The excellent performance gives the feasibility of cascading multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.
10:30 AM - B1.5
All-semiconducting Nanotube Networks: Towards High Performance Printed Nanoelectronics.
Nima Rouhi 1 , Dheeraj Jain 1 , Katayoun Zand 1 , Peter Burke 1 Show Abstract
1 Electrical Engineering and Computer Science, University of California-Irvine, Irvine, California, United States
In this work, we present progress towards devices fabrication using all semiconducting nanotubes as the starting material. DC analysis of device characterization shows a high mobility, up to 40 cm2/V-s, and good on/off ratio in the range of more than 103 and 104 in some cases. A critical issue is the ink formulation and dependence of electronic properties on the nanotube density after deposition.I.FABRICATIONDevices reported here were fabricated using a solution enriched up to 90% in semiconducting single walled carbon nanotubes (diameter range – 1.2-1.7 nm, length range 300 nm to 5 μm). These solutions were made using density gradient centrifugation process for the separation of nanotubes with different chiralities. Prior to the deposition of nanotubes, the surface of Si/SiO2 wafer was modified with APTES (a conventional method). Nanotube solution was then either spin-coated or poured vertically on these wafers.Following the nanotube deposition, the wafer was patterned for source and drain deposition using standard photolithography. We also studied the effect of gate length on mobility, and on/off ratio, for devices with different gate lengths (5~100 μm).E-beam evaporation was used to deposit source and drain electrodes (Pd/Au). The Si wafer acts as the back gate and 300 nm of SiO2 was used as the gate dielectric.II.ELECTRICAL MEASUREMENTSThe ID-VD extracted from the dc measurement shows that the current-voltage relationship is linear for small VD ranging from -1 V to 1 V (triode region), indicating good ohmic contact between nanotubes and electrodes. By applying more negative VD the devices clearly show saturation behavior. Since we are using purified all-semiconducting (90% semiconducting) tubes in the channel, we are expecting high on/off ratio, which is true in our devices. The on/off ratio is more than 1000 in almost all devices. Mobilities up to ~40 cm2/V-s are observed using conventional MOSFET equations and curve fitting the ID-VD characteristic.III.CONCLUSIONIn summary we reported thin film transistors fabricated using semiconductor-enriched carbon nanotubes. The dc electrical measurements show a great improvement in terms of mobility (up to 40 cm2/V-s), on/off ratio (10,000), and transconductance compared to previous works. Since these are some of the first spin-on, all semiconducting nanotube devices ever made, these initial results are indeed quite promising for printed RF electronics.
10:45 AM - B1.6
New Dynamic Air-brush Technique for SWCNTs Deposition: Application to Fabrication of CNTFETs for Electronics and Gas Sensing.
Paolo Bondavalli 1 , Louis Gorintin 1 , Pierre Legagneux 1 Show Abstract
1 Physics, Thales Research and Technology, Palaiseau France
This contribution deals with Carbon Nanotubes Field Effect transistors (CNTFETs) based gas sensors fabricated using a new dynamic air-brush technique (patented) for SWCNTs (and nanomaterials in general) deposition. The main novelty is that our technique is compatible with large surfaces, flexibles substrates and allows to fabricate high performances transistors exploiting the percolation effect of the SWCNTs networks achieved with extremely reproducible characteristics. Indeed we have developed a machine which allows us the dynamic deposition on heated substrates of SWCNT solutions, improving dramatically the uniformity of the SWCNTs mats. In the frame of our research the CNTFETs have been developed for gas sensing applications using a patented approach shown in previous presentations. Indeed we have fabricated arrays of CNTFETs achieved using four different metal electrodes on the same chip to exploit the change of metal/SWCNTs junction characteristics as a function of the gas detected in order to identify a sort of electronic fingerprinting. This phenomenon is related to the change of the metal work function and so of the Schottky barrier and seems to be extremely selective. Although the deposition technique has been developed to fabricate CNTFETs, this technique is extremely versatile and can be used for other kinds of applications such as fabrication of bolometers, replacements of ITO layers, in OLED, for light and cheap ultracapacitors on flexible substrates. This technique could really allow these nanomaterials to strike the market on these applications. We will presents statistics on the distribution of the CNTFETs fabricated with our technique which demonstrate its suitability for industrial applications. Moreover results of gas sensing using compact chips composed by 4 different metals electrodes will be shown (NO2, NH3, Humidity, DMMP for concentration between 100ppb et 10ppm).This work has been performed in the frame of the Projects NANOSENSOFIN (CO sensing) and CAPTEX (explosives sensing) funded by ANR.
11:15 AM - **B1.7
Energy Dissipation in Carbon Nanotube and Graphene Electronics.
Eric Pop 1 Show Abstract
1 Electrical & Computer Engineering, University of Illinois, Urbana, Illinois, United States
Power consumption is a significant challenge, often limiting the performance of integrated circuits from mobile devices to massive data centers. Carbon nanoelectronics have emerged as potentially energy-efficient future devices and interconnects, with both large mobility and thermal conductivity. This talk will focus on power dissipation in carbon nanotubes and graphene, with applications to low-energy devices, interconnects and memory elements. Experiments have been used to gain new insight into the fundamental behavior of such devices, and to better inform practical device models. The results suggest much room for energy optimization in nanoelectronics through the design of geometry, interfaces, and materials.
11:45 AM - B1.8
Thermionic Field Emission in Carbon Nanotube Transistors and Proposal of Surface Inversion Channel Model.
David Perello 1 , Innam Lee 1 , Seong Chu Lim 2 , Woo Jong Yu 2 , Young Hee Lee 2 , Minhee Yun 1 Show Abstract
1 Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, Pennsylvania, United States, 2 Department of Energy Science, Sungkyunkwan University, Suwon Korea (the Republic of)
Carbon nanotube transport has been studied by many researchers. However, no analytical model describing transport has been reported in the literature, nor has any explicit dependence of transport characteristics been clarified by using a single CNT. In this work, we derived and confirmed with experimental evidence a novel theoretical model that is based on innovative assumptions at specific gate voltages (this is a strict requirement). The model we derived is an analytical correlation of saturation current and differential conductance with the work function of the metal. This model fits very well to the experimental observations and clarifies the long-sought-after dependence of contact resistance (differential conductance) with the work function of the contact metal by using a single CNT contacted by over a hundred metal contacts with 5 different metal types (Hf, Cr, Ti, Au, Pd). This type of fabrication and analysis has never been performed before, giving the results unprecedented consistency within statistical errors and allowing us to confirm the first-to-date CNT transport model proposed and derived in the literature.The systematic nature of this study goes far beyond prior analysis of transport by taking a proven and historical theory and adapting it with specific conditions for CNTFETs, without the use of any unphysical correlation constants in the fitting. The simple and elegant theoretical model derived is further applicable to others materials and systems where many standard spectroscopic and electrical measurement techniques cannot be utilized due to size or material degradation involved in the testing.We secondly examined electrical measurements of CNT FETs with the same metal types as above on a single CNT over the range 30 K < T < 300 K to extract information about the energy barriers and dipoles at the contact for various metal contact types. We propose a “surface inversion channel” or SIC model to explain underlying transport mechanisms at the unpinned metal-carbon nanotube (CNT) interface. The model is extracted from interpretations of the Schottky barrier measurements of devices, and confirmed by our first-observation of field-enhanced, ‘contact’ band to band tunneling. The SIC model explains a breadth of open questions in the debate between contact and doping effects in CNT, including why long-term (unprotected) air-stable n-type CNT transistor operation is difficult, or why specific metal-contacted CNT are (weakly) ambipolar even after air exposure, while other metal-contacts with lower work function are strictly unipolar p-type. In addition to clearing up previous inconsistencies in the literature regarding CNT band alignments, both the model and core methodology are applicable in examining other low dimensional systems.
12:00 PM - B1.9
Enhanced Electron Field Emission from Carbon Nanotube Matrices.
Archana Pandey 1 , Abhishek Prasad 1 , Mark Engelhard 2 , Chongmin Wang 2 , Yoke Yap 1 Show Abstract
1 Physics, Michigan Technological University, Houghton, Michigan, United States, 2 EMSL, Pacific Northwest National Laboratory, Richland, Washington, United States
Field emission from as-grown carbon nanotube (CNT) films often suffered from high threshold electric field, and low emission site density due to screening effects. These problems can be resolved by patterned growth of CNTs on lithographically prepared catalyst films. However, these approaches are expensive and not applicable for future emitting devices with large display areas. Here we show that as-grown CNT films can have low emission threshold field and high emission density without using any lithography processes. We have reduced screening effects and work function of as-grown CNT films and created the novel CNT matrices by addition vapor- and/or liquid- phase deposition. Furthermore, these CNT matrices can continuous emit electrons for 40 hours without significant degradation.The fabrication of our CNT matrices is described as follows. First, CNT films were grown by plasma-enhanced chemical vapor deposition. These vertically-aligned multiwalled carbon nanotubes (VA-MWCNTs) are having typical length and diameter of xx microns and xx nm, respectively. Spacing between these CNTs is ~xx nm in average, leading to poor emission properties due to the screening effect. These as-grown samples were then subjected to the deposition of strontium titanate (SrTiO3) by pulsed-laser deposition to reduce both the work function and screening effect of CNTs. The emission properties of these coated samples can be further improved by fully filled the spaces between VA-MWCNTs by plo-methyl metha acrylate (PMMA). The coating of SrTiO3 on as-grown VA-MWCNTs was confirmed by transmission electron microscopy (TEM) and x-ray photoelectron spectroscopy (XPS). The field emission threshold electric field was decreased from 3.8 V/µm for as-grown VA-MWCNTs to 1.8 V/µm for SrTiO3 coated VA-MWCNTs. The addition filling with PMMA and mechanical polishing can further reduce the threshold to 0.775V/µm for the so called PMMA-STO-CNT matrices. Long term emission stability and emission site density were also enhancedBased on our theoretical simulation, a new emission model was then proposed to explain the enhanced performances of our CNT matrices. All these results will be discussed in the meeting. *E-mail address: email@example.com (Y. K. Yap)This work was supported by the Defense Advanced Research Projects Agency (Contract number DAAD17-03-C-0115 through the U.S. Army Research Laboratory), and the U.S. Department of Army (Grant number W911NF-04-1-0029 through the City College of New York). A portion of the research was performed using EMSL, a national scientific user facility sponsored by the Department of Energy's Office of Biological and Environmental Research located at Pacific Northwest National Laboratory.
12:15 PM - B1.10
Electrical Resistivity and Contact Resistance in Carbon Nanotube Vertical Interconnects.
Nicolo Chiodarelli 1 2 , Yunlong Li 1 , Kai Arstila 1 , Olivier Richard 1 , Daire Cott 1 , Marc Heyns 1 3 , Stefan De Gendt 1 4 , Guido Groeseneken 1 2 , Philippe Vereecken 1 5 Show Abstract
1 , imec, Leuven Belgium, 2 Department of Electrical Engineering, Katholieke Universiteit Leuven, Leuven Belgium, 3 Metallurgy and Materials Engineering , Katholieke Universiteit Leuven, Leuven Belgium, 4 Chemistry Department, Katholieke Universiteit Leuven, Leuven Belgium, 5 Center for Surface Chemistry and Catalysis, Katholieke Universiteit Leuven, Leuven Belgium
Carbon Nanotubes (CNT) are carbon allotropes with outstanding electronic properties. Charge transport can be ballistic, current densities larger than 10^9 A/cm^2 can be sustained without degradation and a high thermal conductivity has been reported. For these reasons, CNT could be the perfect material for manufacturing vertical interconnects of improved performances, reliability and heat-transfer capability as required for the future generations of microchips. The electrical performance of current vertical CNT interconnects, though, are still far from their ballistic limit. The reasons reside in the poor control on the quality of both the CNT and their electrical contacts. Growing CNT of sufficient high quality using catalytic CVD processes, in fact, is not straightforward within the limited temperature budget for the wiring levels of advanced microchips: about 400C. Moreover, electrically testing the quality of both CNT and contacts can only be done after a complex process for integrating the material into dedicated and properly designed 3D structures. Hence, the risk of materials modification or of introducing spurious components which would corrupt the electrical characterization is increased. This work addresses the issues mentioned above by integrating and electrically characterizing vertical CNT bundles grown with a catalytic CVD method. A process flow is practically implemented on 200mm wafers to selectively grow CNT into via conduits at temperatures as low as 400C. The structure and the process were designed to closely mimic those of real contacts such that all the integration issues encountered can be directly translated and applied to real microchips.The electrical characterization is based on measurements of the CNT resistance as a function of the CNT length which is tightly controlled by tuning the polishing time during a chemical mechanical polishing step. With this technique which is quite unique for vertical CNT interconnect, the two most important parameters for quantitatively assess the electrical quality of the CNT and the contacts are extracted: the electrical resistivity and the contact resistance. These parameters are used for electrically benchmarking different CNT growth conditions and to evaluate the impact of process steps on both the contacts and the CNT. Thus, the methods proposed constitute a powerful technique for optimizing the process and develop CNT of superior electrical quality. This can be of relevant technological importance for interconnects as well as for all those applications that rely on the electrical properties of CNT grown with a catalytic CVD method at low temperature.
12:30 PM - B1.11
Towards Extremely Low Resistance in Highly Organized SWNT Interconnect Devices.
Young-Lae Kim 1 , Hyun Young Jung 2 , Swastik Kar 3 , Yung Joon Jung 2 Show Abstract
1 Electrical and Computer Engineering, Northeastern University, Boston, Massachusetts, United States, 2 Mechanical and Industrial Engineering, Northeastern University, Boston, Massachusetts, United States, 3 Department of Physics, Applied Physics and Astronomy, Rensselaer Polytechnic Institute, Troy, New York, United States
Highly organized single-wall carbon nanotubes (SWNTs) networks and bundles are becoming the most promising candidate replacing copper-based interconnects in the future semiconducting industry. Here, we present the strategy of using highly organized SWNT network structures with extremely low contact resistance as well as enhanced electrical conductivity. Nanoscale organized SWNT network architectures were fabricated by using a template guided fluidic assembly process, developed in our laboratory. These SWNT network structures can withstand current densities up to~ 3×10^7 A/cm^2, comparable or better than copper at similar dimensions. Also, to decrease resistivity of SWNT network structures further, Pt nanoclusters sized in 1-2 nm were decorated on the surface of SWNTs. The increase in conductivity of the SWNT is caused by an increase in conduction channels close to their Fermi levels due to decorated Pt nanoclusters, with a possible conversion of the semiconducting SWNTs into metallic ones. Furthermore, we investigated the effect of cleaning processes on the contact resistance of our developed SWNT based interconnect devices. We have found that with improved cleaning processes after SWNT assembly (using warm acetone, IPA, and longer photoresist developing time), the contact resistance between SWNTs and contact electrodes of Ti/Au was decreased as low as 0.74 % of the overall resistance in the SWNT network structures, showing the significance of removing PMMA residues or other organic impurities that might exist on the surface of SWNTs. These results demonstrate a big step toward the integration of carbon nanotubes with comparatively high current density and extremely low contact resistance for future nanoscale electrical interconnect applications.
12:45 PM - B1.12
3-D Assembly of SWNTs for CMOS Interconnects.
Taehoon Kim 1 , Cihan Yimaz 1 , Sivasubramanian Somu 1 , Ahmed Busnaina 1
1 NSF Nanoscale Science and Engineering Center for High-rate Nanomanufacturing (CHN), Northeastern University, Boston, Massachusetts, United States