Symposium Organizers
Robert R. Keller National Institute of Standards and Technology
W. Jud Ready Georgia Institute of Technology
Meyya Meyyappan NASA Ames Research Center
Manish Chhowalla Imperial College London
B1: Carbon Nanotube Devices - FETs and Interconnects
Session Chairs
Monday PM, November 29, 2010
Room 310 (Hynes)
9:15 AM - **B1.1
Application of Carbon Nanomaterials to Interconnects and Transistors for Low Power-consumption Large-scale Integrated Circuits.
Shintaro Sato 1 2 3
1 , Fujitsu Laboratories Ltd., Atsugi Japan, 2 , MIRAI-Selete, Atsugi Japan, 3 , AIST, Tsukuba Japan
Show AbstractAs the dimensions of large-scale integrated circuits (LSIs) decrease, it is becoming more and more difficult to improve the speed and the power consumption of LSIs just by miniaturization. We are trying to employ carbon nanomaterials including carbon nanotubes (CNTs) and graphene, which have excellent electrical properties, for interconnects and transistors of future low power-consumption LSIs. In this presentation, I will talk about CNT interconnects, which have been addressed at Fujitsu and MIRAI-Selete for years. Special emphases will be placed on the fabrication process of CNT vertical interconnects [1] and their reliability. I will also explain our recent progress on the application of graphene to transistor channels. Graphene synthesis on a 200-mm Si wafer and the fabrication of graphene transistors using newly-developed transfer-free processes [2] will be described. Furthermore, a self-organized structure consisting of graphene connected vertically to aligned CNTs [3] will be introduced. Possible applications of such a structure will also be described.
The work related to CNT interconnects was completed as part of the MIRAI Project supported by NEDO. The graphene-related work was partly supported by the Japan Society for the Promotion of Science (JSPS) through its “Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program).”
[1] S. Sato, et al., Sensors and Materails, 21, 373 (2009). [2] D. Kondo, et al., Appl. Phys. Express 3, 025102 (2010). [3] D. Kondo, et al., Appl. Phys. Express 1, 074003 (2008).
9:45 AM - B1.2
Direct Comparison of Separated Carbon Nanotube Thin-film Transistors Using 95% and 98% Semiconducting Nanotubes and Their Application in Digital Integrated Circuits.
Chuan Wang 1 , Jialu Zhang 1 , Chongwu Zhou 1
1 Electrical Engineering, University of Southern California, Los Angeles, California, United States
Show AbstractPre-separated, semiconducting enriched carbon nanotubes hold great potential for thin-film transistors and integrated circuit applications due to their high mobility, high percentage of semiconducting nanotubes, and room-temperature processing compatibility. Here in this paper, we report, for the first time, the progress on the application of separated nanotube thin-film transistors for macroelectronic integrated circuits. We have systematically and directly compared the key performance metrics such as on-current density, on/off ratio, transconductance, and mobility of devices using separated nanotubes with 95% and 98% semiconducting nanotubes and revealed the trade-off between the on-current density and on/off ratio. The devices with optimized performance have been used to demonstrate integrated digital logic blocks with symmetric input/output behaviour, which is crucial to allow the cascading of multiple stages of logic blocks and larger scale integration. Moreover, due to the highly uniform nature of the devices, integrated inverters with different voltage gains have be achieved by simply changing the device dimensions in the layout design, and the results are in accordance with conventional silicon field-effect transistor circuit design theory. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.
10:00 AM - B1.3
Inverters based on Carbon-nanotube Transistors with Switching Frequencies Above 1 MHz on Glass.
Hyeyeon Ryu 1 , Daniel Kaeblein 1 , Ute Zschieschang 1 , Oliver Schmidt 2 , Hagen Klauk 1
1 Organic Electronics, Max Planck Insitute for Solid State Research, Stuttgart Germany, 2 Electrical Engineering and Information, Technology,Chemnitz University of Technology, Chemnitz Germany
Show AbstractNanoscale field-effect transistors (FETs) based on individual semiconducting carbon nanotubes are of interest for circuits with high integration densities that can be made on inexpensive, large-area substrates, such as glass or flexible plastics. While the static performance of FETs based on individual carbon nanotubes has been discussed many times [1-3], there are only a few reports on the dynamic performance of carbon-nanotube circuits [4-6]. Bachtold et al. and Javey et al. measured signal delays of 30 msec [4] and 750 µsec [5], but the switching speed of their circuits was limited by off-chip interconnects that introduced with large parasitic capacitcances. Chen et al. realized fully integrated circuits with a record delay of 1.9 nsec [6], but these complementary circuits required p-channel and n-channel carbon-nanotube FETs, the latter of which are difficult to obtain and are usually not stable in air. We have fabricated arrays of p-channel carbon-nanotube FETs on glass substrates, integrated the FETs with on-chip load resistors based on vacuum-deposited amorphous carbon films, and measured signal delays as small as 12 nsec. First, an array of probe pads was defined by electron-beam lithography, Ti/AuPd evaporation, and lift-off. Gate electrodes were then defined by e beam lithography and deposition of 30 nm thick Al. The Al gates were briefly exposed to an oxygen plasma to create a 3.6 nm thick AlOx layer, and a 2.1 nm thick phosphonic acid monolayer was then allowed to self-assemble from solution. The total thickness of the AlOx/SAM gate dielectric is 5.7 nm. Carbon nanotubes produced by arc discharge were then deposited from a suspension. Using scanning electron microscopy an individual nanotube was located on each gate, and a pair of AuPd source/drain contacts was defined by e beam lithography for each device. The channel length is ~400 nm. Some of the devices are metallic, but many show useful FET characteristics with ON/OFF ratios up to 107 and ON-state drain currents >1 µA at 1 V. To realize logic circuits we fabricated load resistors on the same substrate by evaporating a thin layer of amorphous carbon, patterned by e-beam lithography. The resistors have excellent linearity and resistances between 105 and 108 Ω, depending on the geometry and film thickness. Inverters composed of a carbon-nanotube FET and an amorphous-carbon load resistor have full output swing and small-signal gain up to 15. To estimate the dynamic performance of the FETs we extracted the time constants from the measured output-signal transitions. When the FETs switch from the OFF-state to the ON-state, the time constant is about 12 nsec, which suggests a maximum frequency of ~10 MHz. [1] Javey et al., Nano Lett. 2005, 5, 345. [2] Appenzeller et al., Phys. Rev. Lett. 2004, 93, 196805. [3] Chen et al., Appl. Phys. Lett. 2005, 86, 123108. [4] Bachtold et al., Science 2001, 294, 1317. [5] Javey et al., Nano Lett. 2002, 2, 929. [6] Chen et al., Science 2006, 311, 1735.
10:15 AM - B1.4
Stable Conversion of Separated Carbon Nanotube Thin-film Transistors from P-type to N-type by Atomic Layer Deposition of High-k Oxide and Its Application in CMOS Digital Circuits.
Jialu Zhang 1 , Chuan Wang 1 , Yue Fu 1 , Yuchi Che 1 , Chongwu Zhou 1
1 Electrical Engineering, University of Southern California, Los Angeles, California, United States
Show AbstractPre-separated, semiconducting enriched carbon nanotubes hold great potential for thin-film transistors (TFTs) and integrated circuit applications due to their extraordinary mobility, high on/off ratio and room-temperature processing compatibility. The main challenge it still facing is how to fabricate air stable N-type thin-film transistors with industry compatible techniques. Here in this paper, we report the method of converting as-made P-type separated nanotube thin film transistors (SN-TFTs) into N-type transistors by adding a high-k oxide layer on top of the device using Atomic Layer deposition (ALD) and its application in CMOS macroelectronic digital circuit. The absorption of oxygen and accumulation of fixed charge in the nanotude dielectric layer interface during the ALD process are proved to be the reasons of the carrier type conversion by designed experiments. The N-type devices exhibit comparable electrical performance as the P-type SN-TFTs in terms of on-current, on/off ratio and device mobility. A CMOS inverter with symmetric input/output behaviour and large noise margin has also been demonstrated. The excellent performance gives the feasibility of cascading multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.
10:30 AM - B1.5
All-semiconducting Nanotube Networks: Towards High Performance Printed Nanoelectronics.
Nima Rouhi 1 , Dheeraj Jain 1 , Katayoun Zand 1 , Peter Burke 1
1 Electrical Engineering and Computer Science, University of California-Irvine, Irvine, California, United States
Show AbstractIn this work, we present progress towards devices fabrication using all semiconducting nanotubes as the starting material. DC analysis of device characterization shows a high mobility, up to 40 cm2/V-s, and good on/off ratio in the range of more than 103 and 104 in some cases. A critical issue is the ink formulation and dependence of electronic properties on the nanotube density after deposition.I.FABRICATIONDevices reported here were fabricated using a solution enriched up to 90% in semiconducting single walled carbon nanotubes (diameter range – 1.2-1.7 nm, length range 300 nm to 5 μm). These solutions were made using density gradient centrifugation process for the separation of nanotubes with different chiralities. Prior to the deposition of nanotubes, the surface of Si/SiO2 wafer was modified with APTES (a conventional method). Nanotube solution was then either spin-coated or poured vertically on these wafers.Following the nanotube deposition, the wafer was patterned for source and drain deposition using standard photolithography. We also studied the effect of gate length on mobility, and on/off ratio, for devices with different gate lengths (5~100 μm).E-beam evaporation was used to deposit source and drain electrodes (Pd/Au). The Si wafer acts as the back gate and 300 nm of SiO2 was used as the gate dielectric.II.ELECTRICAL MEASUREMENTSThe ID-VD extracted from the dc measurement shows that the current-voltage relationship is linear for small VD ranging from -1 V to 1 V (triode region), indicating good ohmic contact between nanotubes and electrodes. By applying more negative VD the devices clearly show saturation behavior. Since we are using purified all-semiconducting (90% semiconducting) tubes in the channel, we are expecting high on/off ratio, which is true in our devices. The on/off ratio is more than 1000 in almost all devices. Mobilities up to ~40 cm2/V-s are observed using conventional MOSFET equations and curve fitting the ID-VD characteristic.III.CONCLUSIONIn summary we reported thin film transistors fabricated using semiconductor-enriched carbon nanotubes. The dc electrical measurements show a great improvement in terms of mobility (up to 40 cm2/V-s), on/off ratio (10,000), and transconductance compared to previous works. Since these are some of the first spin-on, all semiconducting nanotube devices ever made, these initial results are indeed quite promising for printed RF electronics.
10:45 AM - B1.6
New Dynamic Air-brush Technique for SWCNTs Deposition: Application to Fabrication of CNTFETs for Electronics and Gas Sensing.
Paolo Bondavalli 1 , Louis Gorintin 1 , Pierre Legagneux 1
1 Physics, Thales Research and Technology, Palaiseau France
Show AbstractThis contribution deals with Carbon Nanotubes Field Effect transistors (CNTFETs) based gas sensors fabricated using a new dynamic air-brush technique (patented) for SWCNTs (and nanomaterials in general) deposition. The main novelty is that our technique is compatible with large surfaces, flexibles substrates and allows to fabricate high performances transistors exploiting the percolation effect of the SWCNTs networks achieved with extremely reproducible characteristics. Indeed we have developed a machine which allows us the dynamic deposition on heated substrates of SWCNT solutions, improving dramatically the uniformity of the SWCNTs mats. In the frame of our research the CNTFETs have been developed for gas sensing applications using a patented approach shown in previous presentations. Indeed we have fabricated arrays of CNTFETs achieved using four different metal electrodes on the same chip to exploit the change of metal/SWCNTs junction characteristics as a function of the gas detected in order to identify a sort of electronic fingerprinting. This phenomenon is related to the change of the metal work function and so of the Schottky barrier and seems to be extremely selective. Although the deposition technique has been developed to fabricate CNTFETs, this technique is extremely versatile and can be used for other kinds of applications such as fabrication of bolometers, replacements of ITO layers, in OLED, for light and cheap ultracapacitors on flexible substrates. This technique could really allow these nanomaterials to strike the market on these applications. We will presents statistics on the distribution of the CNTFETs fabricated with our technique which demonstrate its suitability for industrial applications. Moreover results of gas sensing using compact chips composed by 4 different metals electrodes will be shown (NO2, NH3, Humidity, DMMP for concentration between 100ppb et 10ppm).This work has been performed in the frame of the Projects NANOSENSOFIN (CO sensing) and CAPTEX (explosives sensing) funded by ANR.
11:00 AM - B1:CNT Devices
Break
11:15 AM - **B1.7
Energy Dissipation in Carbon Nanotube and Graphene Electronics.
Eric Pop 1
1 Electrical & Computer Engineering, University of Illinois, Urbana, Illinois, United States
Show AbstractPower consumption is a significant challenge, often limiting the performance of integrated circuits from mobile devices to massive data centers. Carbon nanoelectronics have emerged as potentially energy-efficient future devices and interconnects, with both large mobility and thermal conductivity. This talk will focus on power dissipation in carbon nanotubes and graphene, with applications to low-energy devices, interconnects and memory elements. Experiments have been used to gain new insight into the fundamental behavior of such devices, and to better inform practical device models. The results suggest much room for energy optimization in nanoelectronics through the design of geometry, interfaces, and materials.
11:45 AM - B1.8
Thermionic Field Emission in Carbon Nanotube Transistors and Proposal of Surface Inversion Channel Model.
David Perello 1 , Innam Lee 1 , Seong Chu Lim 2 , Woo Jong Yu 2 , Young Hee Lee 2 , Minhee Yun 1
1 Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, Pennsylvania, United States, 2 Department of Energy Science, Sungkyunkwan University, Suwon Korea (the Republic of)
Show AbstractCarbon nanotube transport has been studied by many researchers. However, no analytical model describing transport has been reported in the literature, nor has any explicit dependence of transport characteristics been clarified by using a single CNT. In this work, we derived and confirmed with experimental evidence a novel theoretical model that is based on innovative assumptions at specific gate voltages (this is a strict requirement). The model we derived is an analytical correlation of saturation current and differential conductance with the work function of the metal. This model fits very well to the experimental observations and clarifies the long-sought-after dependence of contact resistance (differential conductance) with the work function of the contact metal by using a single CNT contacted by over a hundred metal contacts with 5 different metal types (Hf, Cr, Ti, Au, Pd). This type of fabrication and analysis has never been performed before, giving the results unprecedented consistency within statistical errors and allowing us to confirm the first-to-date CNT transport model proposed and derived in the literature.The systematic nature of this study goes far beyond prior analysis of transport by taking a proven and historical theory and adapting it with specific conditions for CNTFETs, without the use of any unphysical correlation constants in the fitting. The simple and elegant theoretical model derived is further applicable to others materials and systems where many standard spectroscopic and electrical measurement techniques cannot be utilized due to size or material degradation involved in the testing.We secondly examined electrical measurements of CNT FETs with the same metal types as above on a single CNT over the range 30 K < T < 300 K to extract information about the energy barriers and dipoles at the contact for various metal contact types. We propose a “surface inversion channel” or SIC model to explain underlying transport mechanisms at the unpinned metal-carbon nanotube (CNT) interface. The model is extracted from interpretations of the Schottky barrier measurements of devices, and confirmed by our first-observation of field-enhanced, ‘contact’ band to band tunneling. The SIC model explains a breadth of open questions in the debate between contact and doping effects in CNT, including why long-term (unprotected) air-stable n-type CNT transistor operation is difficult, or why specific metal-contacted CNT are (weakly) ambipolar even after air exposure, while other metal-contacts with lower work function are strictly unipolar p-type. In addition to clearing up previous inconsistencies in the literature regarding CNT band alignments, both the model and core methodology are applicable in examining other low dimensional systems.
12:00 PM - B1.9
Enhanced Electron Field Emission from Carbon Nanotube Matrices.
Archana Pandey 1 , Abhishek Prasad 1 , Mark Engelhard 2 , Chongmin Wang 2 , Yoke Yap 1
1 Physics, Michigan Technological University, Houghton, Michigan, United States, 2 EMSL, Pacific Northwest National Laboratory, Richland, Washington, United States
Show AbstractField emission from as-grown carbon nanotube (CNT) films often suffered from high threshold electric field, and low emission site density due to screening effects. These problems can be resolved by patterned growth of CNTs on lithographically prepared catalyst films. However, these approaches are expensive and not applicable for future emitting devices with large display areas. Here we show that as-grown CNT films can have low emission threshold field and high emission density without using any lithography processes. We have reduced screening effects and work function of as-grown CNT films and created the novel CNT matrices by addition vapor- and/or liquid- phase deposition. Furthermore, these CNT matrices can continuous emit electrons for 40 hours without significant degradation.The fabrication of our CNT matrices is described as follows. First, CNT films were grown by plasma-enhanced chemical vapor deposition. These vertically-aligned multiwalled carbon nanotubes (VA-MWCNTs) are having typical length and diameter of xx microns and xx nm, respectively. Spacing between these CNTs is ~xx nm in average, leading to poor emission properties due to the screening effect. These as-grown samples were then subjected to the deposition of strontium titanate (SrTiO3) by pulsed-laser deposition to reduce both the work function and screening effect of CNTs. The emission properties of these coated samples can be further improved by fully filled the spaces between VA-MWCNTs by plo-methyl metha acrylate (PMMA). The coating of SrTiO3 on as-grown VA-MWCNTs was confirmed by transmission electron microscopy (TEM) and x-ray photoelectron spectroscopy (XPS). The field emission threshold electric field was decreased from 3.8 V/µm for as-grown VA-MWCNTs to 1.8 V/µm for SrTiO3 coated VA-MWCNTs. The addition filling with PMMA and mechanical polishing can further reduce the threshold to 0.775V/µm for the so called PMMA-STO-CNT matrices. Long term emission stability and emission site density were also enhancedBased on our theoretical simulation, a new emission model was then proposed to explain the enhanced performances of our CNT matrices. All these results will be discussed in the meeting. *E-mail address: ykyap@mtu.edu (Y. K. Yap)This work was supported by the Defense Advanced Research Projects Agency (Contract number DAAD17-03-C-0115 through the U.S. Army Research Laboratory), and the U.S. Department of Army (Grant number W911NF-04-1-0029 through the City College of New York). A portion of the research was performed using EMSL, a national scientific user facility sponsored by the Department of Energy's Office of Biological and Environmental Research located at Pacific Northwest National Laboratory.
12:15 PM - B1.10
Electrical Resistivity and Contact Resistance in Carbon Nanotube Vertical Interconnects.
Nicolo Chiodarelli 1 2 , Yunlong Li 1 , Kai Arstila 1 , Olivier Richard 1 , Daire Cott 1 , Marc Heyns 1 3 , Stefan De Gendt 1 4 , Guido Groeseneken 1 2 , Philippe Vereecken 1 5
1 , imec, Leuven Belgium, 2 Department of Electrical Engineering, Katholieke Universiteit Leuven, Leuven Belgium, 3 Metallurgy and Materials Engineering , Katholieke Universiteit Leuven, Leuven Belgium, 4 Chemistry Department, Katholieke Universiteit Leuven, Leuven Belgium, 5 Center for Surface Chemistry and Catalysis, Katholieke Universiteit Leuven, Leuven Belgium
Show AbstractCarbon Nanotubes (CNT) are carbon allotropes with outstanding electronic properties. Charge transport can be ballistic, current densities larger than 10^9 A/cm^2 can be sustained without degradation and a high thermal conductivity has been reported. For these reasons, CNT could be the perfect material for manufacturing vertical interconnects of improved performances, reliability and heat-transfer capability as required for the future generations of microchips. The electrical performance of current vertical CNT interconnects, though, are still far from their ballistic limit. The reasons reside in the poor control on the quality of both the CNT and their electrical contacts. Growing CNT of sufficient high quality using catalytic CVD processes, in fact, is not straightforward within the limited temperature budget for the wiring levels of advanced microchips: about 400C. Moreover, electrically testing the quality of both CNT and contacts can only be done after a complex process for integrating the material into dedicated and properly designed 3D structures. Hence, the risk of materials modification or of introducing spurious components which would corrupt the electrical characterization is increased. This work addresses the issues mentioned above by integrating and electrically characterizing vertical CNT bundles grown with a catalytic CVD method. A process flow is practically implemented on 200mm wafers to selectively grow CNT into via conduits at temperatures as low as 400C. The structure and the process were designed to closely mimic those of real contacts such that all the integration issues encountered can be directly translated and applied to real microchips.The electrical characterization is based on measurements of the CNT resistance as a function of the CNT length which is tightly controlled by tuning the polishing time during a chemical mechanical polishing step. With this technique which is quite unique for vertical CNT interconnect, the two most important parameters for quantitatively assess the electrical quality of the CNT and the contacts are extracted: the electrical resistivity and the contact resistance. These parameters are used for electrically benchmarking different CNT growth conditions and to evaluate the impact of process steps on both the contacts and the CNT. Thus, the methods proposed constitute a powerful technique for optimizing the process and develop CNT of superior electrical quality. This can be of relevant technological importance for interconnects as well as for all those applications that rely on the electrical properties of CNT grown with a catalytic CVD method at low temperature.
12:30 PM - B1.11
Towards Extremely Low Resistance in Highly Organized SWNT Interconnect Devices.
Young-Lae Kim 1 , Hyun Young Jung 2 , Swastik Kar 3 , Yung Joon Jung 2
1 Electrical and Computer Engineering, Northeastern University, Boston, Massachusetts, United States, 2 Mechanical and Industrial Engineering, Northeastern University, Boston, Massachusetts, United States, 3 Department of Physics, Applied Physics and Astronomy, Rensselaer Polytechnic Institute, Troy, New York, United States
Show AbstractHighly organized single-wall carbon nanotubes (SWNTs) networks and bundles are becoming the most promising candidate replacing copper-based interconnects in the future semiconducting industry. Here, we present the strategy of using highly organized SWNT network structures with extremely low contact resistance as well as enhanced electrical conductivity. Nanoscale organized SWNT network architectures were fabricated by using a template guided fluidic assembly process, developed in our laboratory. These SWNT network structures can withstand current densities up to~ 3×10^7 A/cm^2, comparable or better than copper at similar dimensions. Also, to decrease resistivity of SWNT network structures further, Pt nanoclusters sized in 1-2 nm were decorated on the surface of SWNTs. The increase in conductivity of the SWNT is caused by an increase in conduction channels close to their Fermi levels due to decorated Pt nanoclusters, with a possible conversion of the semiconducting SWNTs into metallic ones. Furthermore, we investigated the effect of cleaning processes on the contact resistance of our developed SWNT based interconnect devices. We have found that with improved cleaning processes after SWNT assembly (using warm acetone, IPA, and longer photoresist developing time), the contact resistance between SWNTs and contact electrodes of Ti/Au was decreased as low as 0.74 % of the overall resistance in the SWNT network structures, showing the significance of removing PMMA residues or other organic impurities that might exist on the surface of SWNTs. These results demonstrate a big step toward the integration of carbon nanotubes with comparatively high current density and extremely low contact resistance for future nanoscale electrical interconnect applications.
12:45 PM - B1.12
3-D Assembly of SWNTs for CMOS Interconnects.
Taehoon Kim 1 , Cihan Yimaz 1 , Sivasubramanian Somu 1 , Ahmed Busnaina 1
1 NSF Nanoscale Science and Engineering Center for High-rate Nanomanufacturing (CHN), Northeastern University, Boston, Massachusetts, United States
Show AbstractCarbon nanotubes (CNTs) have been considered as potentially useful interconnect materials for future VLSIs, due to their superior electrical properties, including their abilities to sustain a high current density and to exhibit ballistic transport along the tubes. Recently many researchers reported that bundle of CNTs could be grown selectively in via holes using chemical vapor deposition (CVD). However, CNT growth (synthesis) requires high temperatures that would damage CMOS circuits (causing metal diffusion and causing shorts). In our present work, room temperature directed assembly is utilized to assemble nanotubes in the vias instead of CNT synthesis. The electric field assisted directed assembly method assembles the SWNTs aligned perpendicular to the substrate in the vias. The process is very fast (less than a minute per wafer) and is scalable. This makes it a very promising approach for large-scale assembly of CNTs. Three dimensional assembly has been accomplished before, however, it mostly involved assembly between two electrodes where the separation between electrodes has to be with few microns and where the SWNT is connected the two electrodes. This requires having two metal layers already on the wafer for the SWNT to connect in 3-D. We developed a new 3-D assembly technique using only one electrode that’s connected to the SWNT, wherein another electrode is used that is placed far away (more than 1 cm away) from the wafer to maintain the applied potential. The assembled nanotubes are then connected to the next layer of the CMOs circuit and since all nanotubes ends are connected to each metal, contact resistance is expected to be small.
B2/Y2: Joint Session: Nanocarbon-based Electronics Integration
Session Chairs
Monday PM, November 29, 2010
Ballroom B, 3rd floor (Hynes)
2:30 PM - **B2.1/Y2.1
Carbon-based Materials as Key-enabler for ``More Than Moore".
Franz Kreupl 1
1 , SanDisk Corp., Milpitas, California, United States
Show AbstractCarbon-based materials like are heavily investigated as future CMOS-like devices and in interconnect applications. While much of the interest has been devoted to the device aspects in competition to conventional CMOS transistors, the talk here will focus on some less known applications of carbon. Proposed are interconnect applications like on-chip and DRAM capacitors, gate material or through-silicon vias (TSV), novel non-volatile memories, sensors or superior diodes. The quality and resistivity of the carbon layer depends on the deposition method, precursor and temperature, but optimum conditions can be found to achieve a benefit over competing materials in terms of temperature budget, resistivity, stress and ease of integration .The mere properties of the carbon layer is as important as their interaction with different interfacing materials like high-k materials, semiconductors and metals. Some important question which needs to be answered are, is there diffusion of carbon or from the interfacing materials? How does this impair breakdown behaviours? What are the effective work-functions for different interface materials? The answers to these questions will lead us to applications of graphene-like layers in MIM capacitor structures, DRAM capacitors and mid-gap gate-material, attractive for low power CMOS. The question on how these graphene-like layers interface with silicon will give us in the end powerful low-barrier Schottky diodes which can deal with the high temperature requirements of a front-end process. Therefore, for the first time, carbon-silicon Schottky-diodes can be incorporated in a CMOS flow. Stress, built during deposition of the many layers during a process has serious impact on the integration. Thin layers of carbon can reduce the overall stress and can ease the integration. For through-silicon vias the most economic approach of “via-first” was limited up to now to c-Si or poly-Si approach due to the high temperature requirement. Carbon layers can fill very high aspect ratio vias (up to 400) and offer a much better alternative to Si in terms of resistivity, stress and cost. If modifications of the carbon layers can be achieved at reasonable temperatures the overall resistivity can be dropped down to 10 uOhmcm which makes it already attractive for competition with W and Cu wiring. The study of maximum possible current densities in the carbon layers results in the finding of a new non-volatile memory based on the conductivity of different carbon configurations. This will not only enable cross-point memory architectures but could also be implemented in configuring FPGAs.Finally, the spin transport properties of carbon may be beneficial to solve the problems of the high current densities in spin-torque magnetic memories and for the ubiquitous GMR sensors where Neel coupling limits the sensitivity.Overall, the properties of carbon promise applications in a wide range of possible “More than Moore” scenarios for microelectronics.
3:00 PM - **B2.2/Y2.2
Optical Properties of Single and Few-layer Graphene: A Flexible New Material Set.
Tony Heinz 1
1 , Columbia University, New York, New York, United States
Show AbstractGraphene provides many distinctive mechanical properties, including very high strength and flexibility. Combined with the unique characteristics of electrons in graphene, the material offers the possibilities for a wide range new applications. In this paper, we present results of recent investigations of the optical properties of graphene. In addition to their intrinsic scientific interest, these studies help to lay the foundations for a range of photonic and optoelectronic applications from transparent electrodes to tunable infrared optical elements. The system of single-layer graphene (SLG) is known to provide unusually high carrier mobility and sheet conductivity. On the other hand, the material is highly transparent. Over a broad range of wavelengths in the near-infrared to visible, experiments by our group and others have shown that the absorption of SLG conforms closely to the theoretically predicted value of πα = 2.3%, where α denotes the fine-structure constant. Departures from this simple result have been observed at both shorter and longer wavelengths. In the infrared, electrical gating and doping can significantly modify the absorption.A richer set of optical response can be seen in few-layer graphene samples. Our measurements reveal peaks in the absorption spectrum that evolve systematically with the layer thickness of the graphene samples. These features can be understood in terms of a picture of zone-folding of the bulk 3-D graphite bands to produce the 2-D bands of FLG. In addition, external perturbations can be used to tune the band structure and optical response. For the case of graphene bilayer, measurements of the material in the presence of a perpendicular applied electric field demonstrate the possibility of induction of a tunable band-gap that can exceed 200 meV in size.A further distinctive features of graphene is the possibility of applying very high levels of strain. We discuss the development of these strains by bending graphene layers placed on a polymer substrate. In this fashion, strains of several percent can be produced. We have been able to examine the phonon structure of graphene under the influence of such strains by means of Raman spectroscopy. This provides insight into the response of the graphene phonons, as well as a methodology for the local characterization of strain.
3:30 PM - B2.3/Y2.3
Seeding Atomic Layer Deposition of High-k Dielectrics on Epitaxial Graphene with Organic Self-assembled Monolayers.
Justice Alaboson 1 2 , Qing Hua Wang 1 , Albert Lipson 1 , Jonathan Emery 1 , Michael Bedzyk 1 2 , Jeffrey Elam 2 , Michael Pellin 1 2 , Mark Hersam 1
1 Materials Science and Engineering, Northwestern University, Evanston, Illinois, United States, 2 , Argonne National Laboratory, Argonne, Illinois, United States
Show AbstractFor graphene-based field-effect transistors and related nanoelectronic devices, chemical functionalization schemes are needed to integrate graphene with high-k dielectrics. Here, we report on the use of the organic molecule perylene-3,4,9,10-tetracarboxylic dianhydride (PTCDA) as a seeding layer for the atomic layer deposition (ALD) of HfO2 and Al2O3 dielectrics on epitaxial graphene (EG) grown on the SiC (0001) surface. PTCDA forms a well-ordered, self-assembled monolayer on EG as observed by ultra-high vacuum scanning tunneling microscopy at room temperature. While ALD-grown dielectric films on bare graphene were discontinuous and riddled with pinholes, uniform and ultrathin ALD films were achieved on PTCDA-functionalized EG as determined by atomic force microscopy. X-ray reflectivity measurements establish that both PTCDA and graphene remain intact after ALD deposition. Capacitors were fabricated on PTCDA-EG utilizing a 10nm HfO2 and 3nm Al2O3 dielectric stack, where capacitance values of ~700 nF/cm2 and leakage currents of ~5 x 10-9A/cm2 were measured at 1 V gate bias. The high capacitance and low leakage current measured across the dielectric stack demonstrate the viability of organic self-assembled monolayers as seeding layers for high-k dielectrics in graphene-based nanoelectronics.
4:15 PM - **B2.4/Y2.4
Graphene: A Tunable Electronic Surface.
Michael Fuhrer 1
1 Center for Nanophysics and Advanced Materials, University of Maryland, College Park, Maryland, United States
Show AbstractGraphene is unique: a massless, gapless two-dimensional electron system contained in a single-atom thick plane of carbon. While the properties of the two-dimensional electron system have been widely studied, the fact that graphene consists of all surface atoms offers new opportunities to exploit graphene as a tunable electronic surface and interface. In this talk, I will first discuss the electronic structure of graphene, and its implications for electronic properties, and then I will discuss its tunable surface properties. A back-gate voltage can be used to tune graphene’s workfunction over a range of some 600 meV, and chemical doping, such as deposition of alkali metal in ultra-high vacuum or in an electrochemical cell, can extend this range much further, opening possibilities for graphene as a workfunction-matched interface for organic semiconductors. Graphene may be used as a sensitive detector to observe chemical reactions occurring on its surface at concentrations below 1/1000th of a monolayer, and the tunable workfunction of graphene offers the possibility of electronically tunable catalytic action. Finally, ion irradiation can be used to create atomic vacancies in graphene which have local magnetic moments. These moments couple strongly to conduction electrons in graphene via the Kondo effect, offering the possibility of tuning conduction-electron-mediated magnetism in graphene via defect engineering.
4:45 PM - **B2.5/Y2.5
Nanoelectronics and Macroelectronics Based on Carbon Nanotubes.
Chongwu Zhou 1
1 Electrical Engineering, University of Southern California, Los Angeles, California, United States
Show AbstractCarbon nanotubes offer great promise but also face significant challenges for future electronic applications. This talk will focus on our recent work on: 1. Assembly and integration of massive aligned nanotubes for nanoelectronics, 2. Metal tube removal based on light irradiation, and 3. Thin film transistors (TFTs) based on separated nanotubes for macroelectronics. We will report our wafer-scale processing of aligned nanotube electronics. Massive aligned nanotubes were synthesized over complete 4 inch quartz and sapphire substrates, and then transferred to Si/SiO2 substrates. CMOS analogous fabrication was performed to yield submicron high performance transistors and defect-tolerant logic circuits.In addition, we will present the metal-to-semiconductor conversion of carbon nanotubes induced by light irradiation. The light irradiation process is scalable to wafer-size scales and capable of yielding improvements in the channel-current on/off ratio up to 5 orders of magnitude in nanotube-based field-effect transistors. Furthermore, we will report wafer-scale processing of TFTs based on separated nanotube, including key technology components such as assembly of high-density, uniform separated nanotube networks, high-yield fabrication of devices with superior performance, and demonstration of organic light-emitting diode (OLED) control circuit. References[1] “CMOS-analogous wafer-scale nanotube-on-insulator approach for submicron devices and integrated circuits using aligned nanotubes”, Chongwu Zhou et al., Nano Letters, Vol. 9, 189, 2009. [2] “Scalable Light-Induced Metal to Semiconductor Conversion of Carbon Nanotubes”, Chongwu Zhou et al., Nano Letters, Vol. 9, 3592, 2009. [3] “Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications”, Chongwu Zhou et al., Nano Letters, Vol. 9, 4285, 2009.Keywords: carbon nanotubes, nanoelectronics, macroelectronics, thin film transistors
5:15 PM - B2.6/Y2.6
Fabrication of Electronic Devices with Highly-enriched Semiconducting Single Walled Carbon Nanotubes.
George Tulevski 1 , Aaron Franklin 1 , Bhupesh Chandra 1
1 , IBM T.J. Watson Research Center, Yorktown Heights, New York, United States
Show AbstractThe exceptional transport properties of Single-Walled Carbon Nanotubes (SWCNTs) make them promising materials for various technological applications where high mobilities and current densities are desired. Despite their promise, the implementation of SWCNTs into technologies is limited by the materials processing tools available to sort and assembly SWCNTs into sophisticated structures. This talk will focus on our recent efforts to overcome these limitations, including recent results on sorting and assembly of SWCNTs for the fabrication of electronic devices. Enrichment of semiconducting SWCNTs is achieved using a modified size-exclusion chromatography technique to yield solutions with > 97% semiconducting SWCNTs. The material and semiconducting yield is characterized both optically and electrically. The method is simple and highly scalable to large quantities. Following separation, the SWCNTs are assembled into aligned arrays to form multi-channel CNT-FETs with short channel lengths (100 – 500nm). The arrays can be selectively placed anywhere on the substrate and can extend for millimeters. The devices display high drive currents while maintaining large on/off ratios (> 106), even at channel lengths were direct transport occurs. The CNTs were also used as the active material in thin-film transistors and display similarly high performances. The results described here show a possible path forward for the integration of SWNCTs into future technologies.
5:30 PM - B2.7/Y2.7
Large-scale, Bottom-up, CMOS-compatible Integration of Chirality-sorted Carbon Nanotubes.
Aravind Vijayaraghavan 1 2 , Marc Ganzhorn 2 , Ninette Stuerzl 2 , Frank Hennrich 2 , Ralph Krupke 2
1 , Massachusetts Institute of Technology, Cambridge, Massachusetts, United States, 2 , Karlsruhe Institute of Technology, Karlsruhe Germany
Show AbstractIn order to realize the tremendous potential of single-walled carbon nanotubes (SWCNTs) in electronic, optoelectronic and electromechanical applications, it is essential to integrate SWNTs into existing microelectronic products and techniques. Specifically, SWNTs of a particular type (chirality) need to be assembled at specific locations and orientations in lithographically patterned circuits at close to 100% efficiency. We demonstrate here, how this can be accomplished. SWNTs are sorted into single-chirality fractions, for example by selective polymer wrapping. They are also enriched to high-purities in only semiconducting species, centered on a favorable diameter of 1.4 nm, using density-gradient ultracentrifugation. We have shown previously that SWNTs and graphene can be assembled at ultra-large-scale integration densities using dielectrophoresis (DEP), which in addition is self-limiting to one SWNT per device location. By adapting DEP for sorted SWNT solutions, we assemble SWNTs of specific chirality or electronic type at nearly 100% integration densities. DEP can simultaneously assemble SWNT devices in multiple orientations, and is the only CMOS compatible route available for doing so. Pre- and post-processing steps to extract high performance from such devices are also described.In addition to its importance in applications, understanding fundamental SWNT properties also critically depends on the ability to study them specifically. We show that by fabricating arrays of identical SWNTs, we can perform multiple measurements on identical SWNTs and correlate interesting features. For instance, we demonstrate a strong correlation between D-peak in Raman spectroscopy, dark-exciton peaks in photoluminescence spectroscopy and low conductance and mobility in electron transport measurements. References: Vijayaraghavan, A., et al, Toward Single-Chirality Carbon Nanotube Device Arrays, ACS Nano, 2010, 4(5), 2748-2754.Ganzhorn, M.; et al; Large-scale, CMOS-compatible integration of high-performance semiconducting single-wall carbon nanotube devices. SubmittedVijayaraghavan, A.; et al, Dielectrophoretic Assembly of High-density Arrays of Graphene Devices for Rapid Screening. ACS Nano 2009, 3(7), 1729–1734.Vijayaraghavan, A.; et al, Ultra-Large Scale Directed Assembly of Single-Walled Carbon Nanotube Devices. Nano Letters 2007, 7, 1556-1560.
5:45 PM - B2.8/Y2.8
Selective Integration of Individual Metallic Single-walled Carbon Nanotubes for Parallel Sensor Assembly.
Brian Burg 1 , Julian Schneider 1 , Vincenzo Bianco 2 , Niklas Schirmer 1 , Dimos Poulikakos 1
1 Department of Mechanical and Process Engineering, ETH Zurich, Zurich Switzerland, 2 Dipartimento di Ingegneria Aerospaziale e Meccanica, Seconda Università degli Studi di Napoli, Napoli Italy
Show AbstractThe dielectrophoretic separation of individual metallic single-walled carbon nanotubes (SWNTs) from heterogeneous solutions and their simultaneous deposition between electrodes is achieved and confirmed by direct electric transport measurements. Out-of-solution guided parallel assembly of individual SWNTs was investigated for electric field frequencies between 1 and 200 MHz. At 200 MHz, 19 of the 22 deposited SWNTs (86%) displayed metallic behavior, whereas at lower frequencies the expected random growth distribution of 1/3 metallic SWNTs prevailed. A threshold separation frequency of 188 MHz is extracted from a surface-conductivity model, and a conductivity weighting factor is introduced to elucidate the separation frequency dependence. Low-frequency experiments and numerical simulations show that long-range nanotube transport is governed by hydrodynamic effects whereas local trapping is dominated by dielectrophoretic forces. The electrokinetic framework of dielectrophoresis in low-concentration solutions is thus provided and allows a deeper understanding of the underlying mechanisms in dielectrophoretic deposition processes for long and large-diameter SWNT-based low-resistance device integration, such as piezoresistive SWNT based pressure sensors.Reference: Burg, B. R.; Schneider, J.; Bianco, V.; Schirmer, N. C.; Poulikakos, D. Langmuir 2010, DOI: 10.1021/la1013158.
Symposium Organizers
Robert R. Keller National Institute of Standards and Technology
W. Jud Ready Georgia Institute of Technology
Meyya Meyyappan NASA Ames Research Center
Manish Chhowalla Imperial College London
B5: Poster Session: Carbon-Based Electronic Devices
Session Chairs
Manish Chhowalla
Robert Keller
Meyya Meyyappan
Jud Ready
Tuesday PM, November 30, 2010
Exhibition Hall D (Hynes)
B3: Graphene Devices - FETs
Session Chairs
Tuesday PM, November 30, 2010
Room 310 (Hynes)
9:30 AM - **B3.1
Graphene Electronics and Optoelectronics.
Phaedon Avouris 1
1 , IBM T.J. Watson Research Center, Yorktown Heights, New York, United States
Show AbstractThe excellent carrier transport properties in graphene and the modest tuning of the current by a gate field make graphene ideal for high-frequency analog device applications. I will discuss the device physics, fabrication and operation of RF graphene transistors on a wafer scale with cut-off frequencies up to 100GHz using epitaxially grown graphene. Despite the gapless nature of graphene, built-in electric fields at graphene-metal contacts can be used to construct ultrafast photoconductors. Such devices will be demonstrated and utilized for the reliable detection of 10GBit/s optical data streams. I also will discuss the electrical bandgap opening in bilayer graphene and demonstrate bilayer transistors operating at room temperature.
10:00 AM - B3.2
Optimizing the Characteristics of Graphene Field-effect Transistors through Dielectric Engineering and Self-aligned Gating.
Damon Farmer 1 , Yu-Ming Lin 1 , Phaedon Avouris 1
1 , IBM TJ Watson Research Center, Yorktown Heights, New York, United States
Show AbstractMuch of the interest surrounding graphene is due to the high field-effect carrier mobility that is exhibited by graphene-based field-effect transistors (FETs). This makes graphene a material of great promise as the active element in electronic devices, particularly those based on high-frequency operation. However, many key issues still need to be addressed in order to fully exploit graphene for technological applications. For instance, the two-dimensional nature of the graphene lattice causes it to be very sensitive to its material environment. As a result, many of the challenges in the field of graphene electronics are fundamental material engineering issues. This includes preservation of the carrier mobility after gate dielectric deposition and the elimination of parasitics in graphene devices. Here, we present a device fabrication process that addresses both of these issues by employing mobility-preserving gate dielectrics in conjunction with a self-aligned gating technique that minimizes the parasitic capacitances and resistances in the device. The self-alignment process utilizes the inherent nucleation inhibition of atomic-layer-deposited films with the graphene surface to achieve electrical isolation of the gate electrode while simultaneously maintaining electrical access to the graphene channel. This process produces electrode separation lengths of only 15 - 20 nm, which allows for improved device stability and performance. Due to the aforementioned sensitivity of graphene to its environment, the material compatibility issues that must be overcome in order to realize such devices will be given particular emphasis.
10:15 AM - B3.3
Comparative Study of the Effective and Hall Mobility of Graphene.
Archana Venugopal 1 , Xuesong Li 3 , Carl Magnuson 3 , Boyang Han 3 , Wiley Kirk 2 , Luigi Colombo 4 , Rodney Ruoff 3 , Eric Vogel 1 2
1 Electrical Engineering, University of Texas at Dallas, Richardson, Texas, United States, 3 Mechanical Engineering and Texas Materials Institute, University of Texas at Austin, Austin, Texas, United States, 2 Materials Science and Engineering, University of Texas at Dallas, Richardson, Texas, United States, 4 , Texas Instruments Incorporated, Dallas, Texas, United States
Show AbstractABSTRACT:Graphene has been the subject of extensive electrical characterization since 2004.[1, 2] As in semiconductor based FETs, the effective mobility (µeff) is typically used as the parameter to gauge and compare the device performance, and µeff is extracted from Id – Vg characteristics. The extraction of µeff values in graphene FETs are either based on a model proposed by Kim et al.[3], which assumes a charge carrier concentration (n) independent mobility or the Drude model[1] that assumes a carrier concentration specific mobility. Hall mobility studies[4] report a carrier concentration dependence different from either of these assumed behaviours. The relationship between Hall and µeff extracted from field effect transistors in graphene is not well understood. A comparative study of the mobility in exfoliated graphene has been performed using split C-V and Hall effect measurements between 5 K and 295 K, the results of which will be presented. The electronic transport characteristics of CVD graphene grown on Cu[5] as measured by the Hall effect and extracted from split C-Vs as a function of domain size[6] and temperature, will also be presented.REFERENCES:1.Novoselov, K.S., et al., Electric Field Effect in Atomically Thin Carbon Films. Science, 2004. 306(5696): p. 666-669.2.Berger, C., et al., Ultrathin Epitaxial Graphite: 2D Electron Gas Properties and a Route toward Graphene-based Nanoelectronics. The Journal of Physical Chemistry B, 2004. 108(52): p. 19912-19916.3.Kim, S., et al., Realization of a high mobility dual-gated graphene field-effect transistor with Al[sub 2]O[sub 3] dielectric. Applied Physics Letters, 2009. 94(6): p. 062107-3.4.Zhu, W., et al., Carrier scattering, mobilities, and electrostatic potential in monolayer, bilayer, and trilayer graphene. Physical Review B, 2009. 80(23): p. 235402.5.Li, X., et al., Large-Area Synthesis of High-Quality and Uniform Graphene Films on Copper Foils. Science, 2009. 324(5932): p. 1312-1314.6.Li, X., et al., Evolution of Graphene Growth on Ni and Cu by Carbon Isotope Labeling. Nano Letters, 2009. 9(12): p. 4268-4272.
10:30 AM - B3.4
Graphene-based Nanogenerators with Fully Rollable and Transparent Characteristics.
Dukhyun Choi 1 , Sang-Woo Kim 2 , Won Mook Choi 3 , Hyeon-Jin Shin 3 , Jae-Young Choi 3 , Young Hee Lee 4
1 Mechanical Engineering, Kyung Hee University, Yongin, Gyeonggi, Korea (the Republic of), 2 School of Advanced Materials Science and Engineering, Sungkyunkwan University, Suwon Korea (the Republic of), 3 , Samsung Advanced Institute of Technology, Yongin Korea (the Republic of), 4 Department of Physics, Sungkyunkwan University, Suwon Korea (the Republic of)
Show AbstractChemical vapor deposition-grown large-scale graphene sheets are employed as transparent electrodes to realize fully rollable transparent (RT) energy harvesting nanodevices using piezoelectric zinc oxide (ZnO) nanorods (called nanogenerators). Based on in-situ two probe resistance experiments and a computed simulation, we demonstrate the electrical and structural stability of graphene-based nanogenerators under external mechanical loads such as those experienced with bending or rolling. For the integrated nanogenerator, a heterogeneous three-dimensional (3D) nanostructure consisting of 1D ZnO nanorods on a 2D graphene electrode is successfully fabricated. It is investigated that our graphene electrode, with its extremely high carrier mobility at room temperature and a Schottky contact to the ZnO nanorods, results in RT-nanogenerators with excellent charge scavenging performance. The graphene-based device is expected to lead to new types of multifunctional, reliable nanosystem applications such as multiplex touch sensors and artificial skins equipped with tactile sensors.
10:45 AM - B3.5
Experimental Evaluation of AlN as a Dielectric for Graphene-based Devices.
Mark Fanton 1 , Joshua Robinson 1 2 , David Rearick 1 , Michael LaBella 1 , Kathleen Trumbull 1 , Randal Cavalero 1 , Matthew Hollander 1 2 , Zachary Hughes 1 2 , David Snyder 1
1 Electro-Optics Center, Penn State University, Freeport, Pennsylvania, United States, 2 Materials Research Institute, Penn State University, University Park, Pennsylvania, United States
Show AbstractTraditional semiconductor field effect structures rely on the use of thin oxide films to isolate the gate electrode from the channel. The use of oxides on carbon-based structures presents some unique challenges considering the high thermodynamic driving force for reaction between carbon and oxygen. In this work AlN was successfully used as a dielectric for fabricating field effect structures on epitaxial graphene on semi-insulating SiC. A process was developed for deposition of 10-20nm thick AlN films on graphene by molecular beam epitaxy. Films were grown by RF-plasma-assisted MBE at deposition temperatures between 100°C and 350°C. Growth was initiated using metal rich process conditions to prevent damage to the graphene film by the nitrogen plasma source and to encourage full coverage by the dielectric. Growth was initiated using metal rich process conditions to prevent damage to the graphene film by the nitrogen plasma source and to encourage full coverage by the dielectric. Characterization of the graphene film by Raman spectroscopy before and after AlN deposition indicated no significant degradation in structural properties. Prior to deposition of AlN the graphene films exhibited a mobility of 800cm2/V-s, and a sheet carrier density of 8x1012cm-2, as measured by Hall effect. After deposition of the dielectric the mobility decreased to as low as 350cm2/V-s and the carrier concentration increased to as much as 1.5x1013cm-2. Changes in mobility and carrier concentration will be discussed in terms of structural changes observed by Raman spectroscopy and transmission electron microscopy and changes in chemistry as monitored by x-ray photoelectron spectroscopy.
12:00 PM - B3.7
Solution-gated Graphene FET Arrays for Chemical and Biological Sensing.
Benjamin Mailly Giacchetti 2 1 3 , Allen Hsu 1 3 , Han Wang 1 3 , Ki Kang Kim 1 3 , Jing Kong 1 3 , Tomas Palacios 1 3
2 Materials Science, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States, 1 Electrical Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States, 3 Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States
Show AbstractGraphene holds great potential for bioelectronic applications and, more specifically, for fast high-sensitivity pH measurements and biosensing. Its monolayer structure (just one carbon atom thick) in combination with its very high carrier mobility enable high transconductance and low noise which are key parameters for chemical sensors with electronic readout. In fact, single molecule detection has already been demonstrated in graphene gas sensors. In this paper we report on the fabrication and preliminary characterization of the first solution-gated graphene field-effect transistor (SGFET) arrays that can operate in various liquid environments. These devices are optimized for the detection of changes of pH or of a biomolecule concentration in liquid electrolytes. These molecules induce changes in the transport properties of graphene that can easily be detected electronically.The active channel of our devices is mostly single-layer graphene films grown by low pressure chemical vapor deposition on copper foils and transferred onto a silicon substrate. After patterning the graphene film by O2 plasma etching, we deposit Ti/Pd/Au (2.5nm/45nm/15nm) drain and source contacts in order to fabricate graphene transistors. A SU8 polymer layer is then added to protect the contacts. Next, we wire-bond the graphene device to a chip carrier. In addition, a PDMS-based encapsulation technology has been developed to insulate the wires, from the electrolyte. The performance of the SGFET sensors can then be characterized by using a silver chloride reference electrode immersed in the solution as the top gate voltage.In summary, our study aims at demonstrating that graphene with its scalable technology, very high sensivity and low noise has the potential to surmount the challenges of existing silicon technologies for accurate pH and biosensing applications. Our on-going work focuses on functionalizing the graphene surface to make it selective to specific analytes. In addition, we have demonstrated that HEK 293 cells can grow and survive on our graphene films with good adhesion, which paves the way for cellular recording with graphene devices.
12:15 PM - B3.8
High Frequency Top-gated Graphene RF Ambipolar FETs Using Large-area CVD Graphene and Advanced Dielectrics.
Osama Nayfeh 1 , Madan Dubey 1
1 Sensors and Electron Devices Directorate, United States Army Research Laboratory, Adelphi, Maryland, United States
Show AbstractAmbipolar top-gated field effect transistors (FETs) based on large area Cu catalyzed CVD-grown monolayer graphene interfaced to advanced dielectrics have been constructed and examined both for their material and electrical qualities. Interfacing of the graphene with novel insulators/substrates could be tailored for the particular application and provide for enhanced device functionality. In contrast to graphene FETs using SiO2-based top-gate dielectric, which show asymmetric electron/hole mobility (with larger hole mobility), and Dirac point shifted to positive levels, FETs constructed using advanced piezoelectric AlN show Dirac point almost near neutral levels and near symmetric electron/hole mobility. The DP is shifted likely due to compensation of the intrinsic p-type doping by n-type doping introduced by the AlN deposition and potentially via a contribution of polarization-induced carrier density. We have developed a simple drift-diffusion model to simulate the devices in the scattering-limited regime wherein key parameters are extracted from inverse modeling. Finally, we demonstrate a top-gated graphene FET with the first observation of RF operation with GHz cut-off frequency based on large area CVD graphene.
12:30 PM - B3.9
Temperature Dependant Spin Precession Measured in Exfoliated Graphene Utilizing Non-local Detection.
Joseph Abel 1 , Akitomo Matsubayashi 1 , John Garramone 1 , Vincent LaBella 1
1 , University at Albany, Albany, New York, United States
Show AbstractThe use of the electron spin has gained considerable attention lately as a possible substitute for charge-based electronics [1,2]. This talk will focus on the measurement of spin precession of a non-local spin device fabricated utilizing graphene as a transport channel. The device is fabricated similar to other non-local spin devices reported in the literature [3]. The device is prepared with exfoliated graphene on SiO2. The injection and readout contacts were fabricated with and without aluminum oxide as a tunnel barrier which was deposited using thermal evaporation of Al in ultra high vacuum (UHV) and then subsequent oxidation in O2. Then Co/Au was deposited under high vacuum and 100-200-nm-wide contacts were patterned using e-beam lithography followed by a standard liftoff technique. Scanning electron microscopy and optical images will be presented of the fabrication process and the device. The results from temperature dependant non-local Hanle measurements will be presented showing the spin precession in the graphene channel.
[1] Behin-Aein, B., Datta, D., Salahuddin, S., Datta, S. Nat Nano 5:266-270 (2010)
[2] Dery, H. Dalal, P., Cywinski, L. & Sham, L.J. Nature 447, 573-576 (2007)
[3] Tombros, N., Jozsa, C., Popinciuc, M., Jonkman, H.T., Van Wees, B.J. Nature, 448 (7153), pp. 571-574 (2007)
B4: Defects and Reliability in Nanocarbon
Session Chairs
Tuesday PM, November 30, 2010
Room 310 (Hynes)
2:30 PM - B4.1
Reliability of Carbon Nanotube-based Interconnects, Vias, and Electrical Networks.
Mark Strus 1 , Ann Chiaramonti 1 , Young Lae Kim 2 , Yung Joon Jung 3 , Robert Keller 1
1 Materials Reliability, National Institute of Standards and Technology, Boulder, Colorado, United States, 2 Electrical and Computer Engineering, Northeastern University, Boston, Massachusetts, United States, 3 Mechanical and Industrial Engineering, Northeastern University, Boston, Massachusetts, United States
Show AbstractBecause of their high current carrying capability and appreciable thermal conductivity, single and bundled carbon nanotubes (CNTs) have emerged as a potential replacement for copper in future integrated circuit interconnects and vias, where minimum feature sizes will be smaller than 45 nanometers. In additional to their notable thermal and electrical properties, CNTs possess extraordinary mechanical strength and flexibility making them ideal candidates for thin-film electrical networks with applications in organic light-emitting displays and photovoltaics. While previous researchers have either investigated the physical properties of individual CNTs or concentrated on the fabrication required to incorporate them into final device form, the long-term performance and reliability of the entire CNT-based electrical devices remains largely unstudied. In the current work, we investigate the failure mechanisms of fluidically self-assembled single-walled CNT networks and dielectrophoretically fabricated individual multiwalled CNTs [1] when subjected to various conditions of electrical and thermal stress. Using the method of isothermal resistance change [2], where CNTs connected to metallic electrodes are subjected to direct currents at controlled temperatures for long periods of times, we calculate the activation energy of electromigration-based failure mechanisms. CNT interconnects are also stressed with either direct or alternating currents to determine the conditions where CNT devices are most vulnerable to either thermal-induced or electromigratory failure. In situ scanning electron microscope voltage-contrast methods and transmission electron microscope images of failed interconnect cross-sections are used to identify the location, origin, and propagation of failure. This new understanding of the potential lifetimes, performance issues, and failure mechanisms of CNT-based devices will be integral to the future improvement of CNT interconnect/network design and manufacture.[1] Kim et al., ACS Nano 3 (2009) 2818-2826[2] Park et al, Appl. Phys. 59 Lett. (1991) 175-177
2:45 PM - B4.2
Characterization of Electrically Stressed Carbon Nanotube Interconnect Assemblies by In-situ Transmission Electron Microscopy.
Ann Chiaramonti 1 , Mark Strus 1 , Young Lae Kim 2 , Yung Joon Jung 3 , Robert Keller 1
1 Materials Reliability Division, The National Institute of Standards and Technology, Boulder, Colorado, United States, 2 Electrical and Computer Engineering, Northeastern University, Boston, Massachusetts, United States, 3 Mechanical and Industrial Engineering, Northeastern University, Boston, Massachusetts, United States
Show AbstractTransmission electron microscopy (TEM) is an indispensible tool for the study of materials at the nanometer scale and beyond. Ever since the first clear high-resolution electron microscopy (HREM) images of the individual walls in a multiwall carbon nanotube (CNT) were published by S. Iijima in 1991 [1], TEM has enabled groundbreaking research in this field and continues to be the tool of choice for imaging carbon-based structures at the highest spatial resolutions. Not only can TEM imaging provide real-space structural information at length scales corresponding to individual atoms, but transmission electron diffraction can be used to determine the chirality of individual single walled CNTs, thus indirectly characterizing their electronic structure. While CNTs have been proposed as a possible replacement for copper in microelectronic circuit interconnects, their behavior in such highly integrated systems is poorly understood and there are considerable manufacturing challenges to overcome before they are fully compatible with CMOS processing. One key to the eventual use of CNTs in interconnect architectures is a knowledge of their reliability in fully integrated, device-level structures, which means not only the CNT assembly itself but also its interface with metal electrodes and the dielectric material which encases it. This paper investigates the structural evolution of the carbon-metal and carbon-dielectric interfaces in CNT-based interconnect structures under conditions of AC and DC electrical stress. We will present in-situ TEM results, where simplified model CNT interconnect structures are tested inside of the microscope column, in order to observe in real-time how they respond to electrical stressing and Joule heating at the nanometer scale. I-V characteristics will be presented and correlated with TEM images of the CNT interconnect before and after failure. The reliability of CNT assemblies will be assessed via lifetime (to open circuit failure) measurements, and real-time post-mortem structural characterization of damage in the CNT bundle itself, CNT/metal, and CNT/dielectric interfaces will be shown. [1] S. Iijima, Nature 354 (1991) 56.
3:00 PM - B4.3
Voltage-contrast Scanning Electron Microscopy as a New Technique for Statistical Analysis of Metallic and Semiconducting SWNT Devices and Location and Characterization of Defects.
Aravind Vijayaraghavan 1 2 , Simone Dehm 2 , Frank Hennrich 2 , Ralph Krupke 2
1 , Massachusetts Institute of Technology, Cambridge, Massachusetts, United States, 2 , Karlsruhe Institute of Technology, Karlsruhe Germany
Show AbstractSingle-wall carbon nanotubes (SWNTs) are edging closer to electronic applications, with successful techniques now available for sorting and large-scale integration. When SWNTs are integrated into arrays or circuits at high densities, it is required to characterize the number and location of metallic and semiconducting devices among them. This is true even when such arrays are assembled using high-purity semiconducting SWNT solutions since it becomes critical to locate stray metallic devices that would significantly affect overall performance.Here, we describe voltage-contrast scanning electron microscopy (VC-SEM), as a fast, user-friendly and non-invasive technique for the simultaneous electronic characterization of arrays of SWNTs devices. We demonstrate how metallic and semiconducting SWNTs can be distinguished in an SEM under the influence of a substrate bias, and describe the underlying mechanism. In addition, devices containing SWNTs with defects can also be identified. On closer inspection, we can reveal the location and nature of such defects with nano-scale resolution. Anomalies such as charge-injection into the substrate which leads to hysteresis, as well as in-situ characterization of the creation and annealing of defects (defect engineering) will also be demonstrated using VC-SEM.References:Vijayaraghavan, A., et al, Imaging defects and junctions in single-walled carbon nanotubes by voltage-contrast scanning electron microscopy, Carbon 2010, 48(2), 494–500. (Featured on cover of Carbon 48(4))Vijayaraghavan, A.; et al, R. Imaging electronic structure of carbon nanotubes by voltage-contrast scanning electron microscopy. Nano Research 2008, 1, 321-332. Vijayaraghavan, A.; et al, Ultra-Large Scale Directed Assembly of Single-Walled Carbon Nanotube Devices. Nano Letters 2007, 7, 1556-1560.
3:15 PM - B4.4
Nanomechanical Imaging and Manipulation of Graphene via Ultrasonic Force Microscopy - ``nano-dome" Corrugations and Graphene ``nano-ironing".
Oleg Kolosov 1 , Franco Dinelli 2 , Andrew Hoyle 1 , Vladimir Falko 1
1 Physics Department, Lancaster University, Lancaster United Kingdom, 2 , CNR - IPCF, Pisa Italy
Show AbstractWhereas graphene unique properties are attracting ever increasing attention since its discovery [1], theoretical and experimental studies focus on graphene electronic properties – carrier mobility, bandgap, conductivity etc. with its mechanical properties being often overlooked. At the same time, it is these nanomechanical properties including elastic moduli, adhesion to substrate, thermal expansion and their nanoscale variability that determine graphene-substrate interface that in turn affects graphene electrical