Symposium Organizers
Soeren Steudel IMEC
Shelby F. Nelson Eastman Kodak Company
Veit Wagner Jacobs University Bremen
Heiko Thiem Evonik Degussa GmbH
F1: Organic Semiconductor Material
Session Chairs
Monday AM, November 29, 2010
Room 309 (Hynes)
10:00 AM - **F1.1
Designing Solution-processable Materials for Organic Thin-film Transistors.
John Anthony 1
1 , University of Kentucky, Lexington, Kentucky, United States
Show AbstractThe drive for low-temperature processing in organic electronics has hastened the development of new materials that are conveniently processed from solution. Because highly crystalline organic materials are required for high field-effect mobilities, semiconductors must be carefully designed to allow for rapid crystallization during solvent-casting. This talk will focus broadly on our functionalization strategy to yield soluble, highly crystalline material, with detailed case-studies on functionalization studies that improve intermolecular close-contacts, accelerate the rate of crystallization and improve stability of these otherwise reactive aromatic molecules. For instance, the symmetry of the solubilizing groups has a significant impact on lateral and longitudinal shift of the chromophores in the solid state, and this phenomenon can be used to fine-tune crystal packing to yield enhanced mobility. Other desymmetrization of the chromophore leads to severe degradation of the observed transistor performance. Using derivatives substituted on only one end with a variety of functional groups changes the packing dramatically, typically yielding the less-desirable 1-D pi-stacking motif. Desymmetrization by increasing chromophore length leads to reasonable short-range order but signifiant long-range disorder, due to a lack of preferred orientation between adjacent pi-stacked systems. Further increases in chromophore length that re-symmetrize the system restore the desired pi-stacking motifs. However, with such large linearly-fused chromophores, strategies must be developed to stabilize the semiconductor against the most common decomposition pathways.
10:30 AM - F1.2
High Mobility TIPS-Pentacene Field Effect Transistors (FETs) Fabricated Using Solution Shearing.
Gaurav Giri 1 , Eric Verploegen 1 2 , Hector Becerril 3 , Alberto Salleo 4 , Michael Toney 2 , John Anthony 5 , Zhenan Bao 1
1 Chemical Engineering, Stanford University, Stanford, California, United States, 2 Stanford Synchrotron Radiation Lightsource, Stanford University, Stanford, California, United States, 3 Chemistry, Brigham Young University, Rexburg, Idaho, United States, 4 Material Science and Engineering, Stanford University, Stanford, California, United States, 5 Chemistry, University of Kentucky, Lexington, Kentucky, United States
Show AbstractSolution deposition of organic semiconductors (OSC) is a leading contender for producing large-area, inexpensive, and flexible organic electronics. A recently developed solution shearing method (SS) has demonstrated better organic field effect transistor (OFET) performance compared to simple drop casting or spin casting methods. In this method, an organic semiconductor (OSC) solution is sandwiched between two substrates, a non wetting ‘shearing substrate’ and a wetting ‘device substrate’; the latter is heated to a controlled temperature. As the OSC solution is sheared by translating the upper shearing substrate, semiconductor crystallization occurs on the bottom device substrate. Using the well-studied small molecule OSC 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS-Pn), SS has achieved a wide range of reproducible morphologies, which results in differing FET performance. SS can be used to vary many deposition conditions, such as OSC concentration, deposition temperature, shearing speed, etc. Certain conditions have yielded remarkable FET performance. The best shearing conditions yield large area films (> 4 cm^2) on which FETs show an average charge carrier mobility of > 2 cm^2/Vs with transistors showing mobilities as high as 4.7 cm^2/Vs, a current On/Off ratio of > 10^6, low hysteresis and a threshold voltage of -10 V. This is the best performance in terms of mobility for TIPS-Pn that has been reported in literature. We quantitatively measure the molecular ordering resulting from SS and how this ordering impacts charge carrier performance, and we investigate the relationship between the morphological anisotropy and anisotropy in the charge carrier transport. Finally, this study also outlines whether SS can impart the same morphological characteristics and increased charge transport performance for other OSCs.
10:45 AM - F1.3
Polymer and Nanoparticle Mediated TIPS-Pentacene Crystallization: Towards Enhanced Performance Consistency in Small-molecule-based Solution Processible Organic Thin-film Transistors.
Zhengran He 1 , William Durant 1 , Kai Xiao 2 , John Anthony 3 , Jihua Chen 2 , Michael Kilbey 2 , Dawen Li 1
1 Electrical and Computer Engineering, The University of Alabama, Tuscaloosa, Alabama, United States, 2 Center for Nanophase Materials Sciences, Oak Ridge National Lab, Oak Ridge, Tennessee, United States, 3 Deparment of Chemistry, University of Kentucky, Lexington, Kentucky, United States
Show AbstractOrganic thin-film transistors (OTFTs) with 6,13-bis(triisopropyl-silylethynyl)-pentacene (TIPS-pentacene) active layers have attracted much attention due to their room-temperature, solution-based deposition process and impressively high mobility ( up to 1.8 cm2/V.s).[1] However, OTFTs based on TIPS-pentacene polycrystalline films severely suffer from crystal growth anisotropy, which results in poor performance consistency.[2] In this work, in order to mediate the crystallization of TIPS-pentacene, SiO2 nanoparticles (~20 nm) or polymers are mixed with TIPS-pentacene in solution, and subsequent drop-casting of the blend solutions yields uniform film morphology with enhanced average mobility and significantly reduced performance variation. With a top-contact configuration and without hexamethyldisilazane (HMDS) treatment on substrate, the field-effect mobility from pure TIPS-pentacene films varies dramatically from 0.5 to 5×10−3 cm2/V.s, while TIPS-pentacene blends with 2-10% silicon dioxide nanoparticles consistently demonstrate mobilities of 0.1-0.4 cm2/V.s. In addition, three polymers with different crystallinity and solubility parameters: poly(vinylidene fluoride-hexafluoropropylene) (PVDF-HFP, solubility parameter δPVH= ~23 [MPa]1/2), poly(α-methyl styrene) (PαMS, δPαMS= 18.8 [MPa]1/2) and polyisobutylene (PiB, δPiB= 15.6 [MPa]1/2) are blended with TIPS-pentacene (δTP= 18-19 [MPa]1/2)[3]. The polarity- and polymer crystallization-driven phase separation in these systems are systematically correlated with device performance, optical microscopy, and X-ray diffraction. Interestingly, PVDF-HFP introduces lateral phase separation in the blend films while the other two polymers resulted in vertical phase separation with TIPS pentacene domains. Unlike the situations in pure TIPS-pentacene transistors, HMDS treatments on gate dielectrics turn out to reduce the device performance in the polymer/TIPS-pentacene system, most likely caused by the modified film/substrate interfacial energies upon polymer addition. Average mobilities of up to 0.2 cm2/V.s are achieved in these polymer/small molecule blend systems with optimized substrate treatment, device configuration and drop-casting conditions.[1] Park, S.K., Jackson, T.N., Anthony, J.E., Mourey, D.A., Appl. Phys. Lett., 91, 063514 (2007)[2] Chen, J., Tee, C.K., Shtein M., Martin D.C., Anthony, J.E., Org. Electron., 10, 696 (2009)[3] Chen, J., Martin D.C., Anthony, J.E., J. Mater. Res., 122, 1701 (2007)
11:30 AM - **F1.4
High-mobility Organic Thin-film Transistors with Improved Shelf-life Stability.
Hagen Klauk 1
1 , Max Planck Institute for Solid State Research, Stuttgart Germany
Show AbstractPentacene is one of the most popular small-molecule semiconductors for organic p-channel thin-film transistors (TFTs), because it provides relatively large field-effect mobilities of about 1 cm2/Vs [1]. However, pentacene is very susceptible to oxidation, so the carrier mobility of pentacene TFTs degrades rapidly when the devices are exposed in air [2]. Recently, a six-ring fused heteroarene, dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (DNTT), has been synthesized that has a crystal structure and a thin-film morphology very similar to those of pentacene, but which is much less susceptible to oxidation [3]. As a result, the field-effect mobility of DNTT TFTs is as large as that of pentacene TFTs, but the DNTT devices have much better shelf-life stability [3,4]. We have fabricated flexible low-voltage DNTT TFTs that have hole mobilities between 1 and 2 cm2/Vs and on/off current ratios between 107 and 108. Due to the better oxidation resistance, the mobility of the DNTT TFTs degrades much less rapidly compared with pentacene TFTs: While the mobility of the pentacene TFTs decreases by about an order of magnitude within just a few months, the mobility of the DNTT TFTs is still about 70% of its initial value after 8 months of continuous exposure to air. Using a low-temperature shadow-mask process we have also fabricated flexible unipolar ring oscillators based on DNTT TFTs and measured signal propagation delays as low as 11 µsec per stage, which is within a factor of 30 of the fastest organic ring oscillators reported to date [5], despite the more relaxed design rule (10 µm instead of 2 µm) and despite the smaller supply voltage (3 V instead of 10 V). [1] C. Rolin et al., Appl. Phys. Lett., vol. 89, p. 203502 (2006). [2] H. Klauk et al., Adv. Mater., vol. 19, p. 3882 (2007). [3] T. Yamamoto et al., J. Am. Chem. Soc., vol. 129, p. 2224 (2007). [4] U. Zschieschang et al., Adv. Mater., vol. 22, p. 982 (2010). [5] K. Myny et al., Org. Electronics, vol. 11, p. 1176 (2010).
12:00 PM - F1.5
A New Solution-process for High Mobility and Small Variation in Organic TFT Performance via Liquid Crystal Film.
Hiroaki Iino 1 2 , Jun-ichi Hanna 1 2
1 Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, Yokohama, Kanagawa, Japan, 2 , JST-CREST, Yokohama, Kanagawa, Japan
Show AbstractThe materials research for organic thin film transistors (OTFTs) has been extended to exploration of materials suitable for fabrication of crystalline thin films by solution processes. It is reported that solution processed OTFTs fabricated with polycrystalline thin films such as TIPS-pentacene and beozothienobenzothiophenes (BTBT) derivatives show high field effect transistor (FET) mobility over 1 cm2/Vs. Uniformity of the solution-processed films, however, is not so good as those of polymer and vacuum evaporated films because of recrystallization of materials during the solution processes: in fact, we often get a wide variation of FET performance in the solution processed OTFTs. In this paper, we propose a new solution-process using liquid crystalline films as a precursor for polycrystalline thin films for OTFTs. We selected two liquid crystalline materials as model compounds, i.e., dialkylated-terthiophene and BTBT derivatives, 8-TTP-8 and C10-BTBT, respectively. These materials are crystals at room temperature and exhibit liquid crystal phase in a certain elevated temperature range. We spin-coated solutions of these materials on thermal oxidized Si wafer at the liquid crystalline temperatures in an oven, and then cooled them to room temperature in order to make them crystallized. The spin-coating solutions of 8-TTP-8 and C10-BTBT in liquid crystal phases at 88 oC and 113 oC, respectively, gave quite uniform crystalline films: we could not see any structures on the surface of the crystalline films in hundreds micron scale by optical microscopy and laser microscopy; the films were molecularly flat and exhibited wide terrace structures over 10 μm from AFM images. FETs fabricated with 8-TTP-8 exhibited a small variation of FET mobility of 0.14 cm2/Vs, and TFTs fabricated with C10-BTBT exhibited FET mobility of 3 cm2/Vs, which is three times higher than those of crystalline film spin-coated at room temperature and successive post thermal annealing previous reported and as good as those of the films fabricated by vacuum evaporation. We discuss the origin of these good performances of TFTs fabricated via liquid crystalline phase, in addition to a new result on new OTFT materials with process-durability and high FET mobility over 1 cm2/Vs.
12:15 PM - F1.6
Solution Processed n-Channel Organic Field-effect Transistors with High Uniformity and Electrical Stability.
Shree Tiwari 1 , Keith Knauer 1 , William Potscavage 1 , Bernard Kippelen 1
1 School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractWe report on high performance n-channel organic field-effect transistors (OFETs) based on solution-processed [6,6]-phenyl C61 butyric acid methyl ester ([60]PCBM) with very good uniformity, electrical stability, and reproducibility. In our previous studies, solution-processed n-channel OFETs with [60]PCBM have been shown to produce electron mobility values higher than 0.1 cm2/Vs on the inorganic gate dielectric layers of thermally grown SiO2 or HfO2 deposited by atomic layer deposition (ALD) passivated with a thin buffer layer of crosslinkable divinyltetramethyl-disiloxanebis(benzocyclobutene) (BCB) on top, resulting in 30 V or 3 V operation respectively [1, 2]. BCB was used to minimize electron trapping at the dielectric/semiconductor interface, which is the primary limiting factor for n-channel conduction [3]. Here, we demonstrate the very high uniformity and reproducibility in [60]PCBM OFETs on Al2O3 by ALD)/BCB dielectric layer by fabricating several devices on the same substrate. On a single substrate, 64 devices with channel width (W) of 1000 μm and 32 devices with W = 2000 μm were fabricated. To calculate the average performance parameters, 16 (W = 1000 μm) or 8 (W = 2000 μm) devices of identical geometry were taken into account for channel lengths (L) of 25, 50, 100 and 200 μm. The 16 devices with W/L of 1000 μm/100 μm operated at 10 V exhibit excellent n-channel performances with an average electron mobility value of 0.11 ± 0.01 cm2/Vs and an average threshold voltage (VTH) of 1.6 V. The same number of devices with W/L of 1000 μm/50 μm exhibited similar average electron mobility value of 0.11 ± 0.01 cm2/Vs with average VTH of 2.0 V. All the devices exhibited high current on/off ratios (105-106) and sub-threshold slopes of about 0.4 V/decade. Transfer characteristics scanned for 3000 times at a time interval of 1 second between scans showed very good reproducibility of electrical characteristics in N2 atmosphere without any significant change in the performance parameters. After a continuous DC bias stress (VGS = VDS = 10 V) for 12 hours, the devices showed a decay of ~ 20% in drain current. Our results show that [60]PCBM can produce highly uniform and electrically stable n-channel OFETs on inorganic dielectrics with a BCB buffer layer on top.
[1] S.P. Tiwari, X.-H. Zhang, W.J. Postcavage, Jr., and B. Kippelen, J. Appl. Phys. 106, 054504 (2009).
[2] S.P. Tiwari, X.-H. Zhang, W.J. Postcavage, Jr., and B. Kippelen, J. Appl. Phys. 95, 223303 (2009).
[3] L.-L. Chua, J. Zaumseil, J.-F. Chang, E.C.W. Ou, P.K.H. Ho, H. Sirringhaus, and R.H. Friend, Nat. 434, 194 (2005).
F2: Dielectrics for TFTs
Session Chairs
Monday PM, November 29, 2010
Room 309 (Hynes)
2:30 PM - **F2.1
Fabrication and Stability of Low-temperature Solution-processed Organic Transistors.
Alberto Salleo 1 , Youngmin Park 1 , Leslie Jimison 1 , Jonathan Rivnay 1 , Tobin Marks 2 , Antonio Facchetti 3 2
1 , Stanford University, Stanford, California, United States, 2 Chemistry , Northwestern University, Evanston, Illinois, United States, 3 , Polyera Corp., Skokie, Illinois, United States
Show AbstractThere is great interest in being able to fabricate transistors from liquid precursors at temperatures lower than ~120°C, which makes them compatible with low-cost flexible substrates. We describe the fabrication of a hybrid organic/inorganic TFT from solution using a high capacitance sol-gel ZrOx dielectric cured at room temperature and an unannealed semiconducting polymer. The TFT swings from completely off to completely on within 3V on the gate, has an on/off ratio of the order of 105 and exhibits a mobility of approximately 0.2 cm2/V.s.While favorable static device characteristics are necessary conditions to make a dielectric/semiconductor pair technologically interesting, they are not sufficient. Gate bias stress for example has been studied in order to determine whether electrical device stability is satisfactory. In this regard, an “accelerated testing” procedure will be proposed to quickly determine the stabilized threshold voltage of organic transistors. From the materials standpoint, recently bias stress has been associated to water at the semiconductor/dielectric interface. By using directionally crystallized films of an n-type semiconductor (PDI8-CN2) processed at low temperature from solution, we will show that bias stress also depends on intrinsic properties of the semiconductor layer, such as its microstructure.
3:00 PM - F2.2
Low Cost Solution-processed High-k Gate Dielectric Materials for Large Area Circuit Applications.
Wan-Yu Lin 1 2 , Robert Mueller 1 , Kris Myny 1 , Soeren Steudel 1 , Jan Genoe 1 , Paul Heremans 1 3
1 , imec, Leuven Belgium, 2 Metallurgy and Materials Engineering(MTM), Katholieke Universiteit Leuven , Leuven Belgium, 3 Department of Electrical Engineering(ESAT), Katholieke Universiteit Leuven , Leuven Belgium
Show AbstractOne of the key challenges to manufacture low cost circuits (e.g. RFID tags, row driver) and backplanes on flexible substrates lie in the realization of reliable gate-dielectric with a high specific capacitance required for low voltage, high current drive. Flexible substrates necessitate deposition techniques with process temperatures lower than 150°C, making the production of high quality gate dielectric materials more difficult. Here we show a promising integration scheme for thin film circuits using anodization. Aluminium oxide can be fabricated easily and inexpensively by anodization of aluminium at room temperature, giving rise to an ultra-thin, smooth, and dense gate dielectric. Up to now, however, only single OTFTs have been shown with an anodized gate-dielectric. The reason is the difficulty of realizing two independent patterned metallization layers for source/drain and gate, which is required for circuits and AM-OLED backplanes. We show that only a uniform film of Al gives rise to a controlled and uniform oxide over large area. A novel method is also demonstrated to pattern the gate (aluminium) and overlying gate oxide (aluminium oxide) into individual islands, and to process source-drain contacts without side leakage between source and gate at the edge of these islands. Furthermore, we have fully characterized the properties of our anodized aluminium oxide, by demonstrating OTFT’s and unipolar circuits (inverter, 19-stage ring oscillator) with channel-length down to 3um at supply voltages as low as 2V.
3:15 PM - F2.3
High-k Gate Insulators for Thin Film Transistors Grown by Remote Plasma Atomic Layer Deposition.
Fu Tang 1 , Chiyu Zhu 1 , Robert Nemanich 1
1 Department of Physics, Arizona State University, Tempe, Arizona, United States
Show AbstractHigh-k oxides have been widely employed in the Si based nanoscale transistors in order to reduce the gate tunneling current and energy consumption. Recently, the application of high k dielectrics is also emerging in other semiconductor areas including as thin film transistors (TFTs) for flexible electronics. A high-k gate dielectric layer can significantly reduce the threshold voltage, increase the on/off current ratio and enhance the mobility of TFTs. One of the limiting factors in implementing high-k materials for flexible electronics is the development of a low temperature deposition process. In this work, we investigated the growth of Hf oxide, La oxide, and a Hf-oxide/La-oxide layered structure using remote plasma atomic layer deposition (ALD) at temperatures ranging from ~80°C to ~250 °C. The atomic bonding structure of the film was determined by in situ XPS. In a remote plasma process, the activated oxygen species enables a reduced temperature for ALD growth and ion induced damage to the film can be minimized. The XPS results indicated that for low temperature growth of pure Hf oxide, a significant amount of weakly bonded molecular oxygen was absorbed in the film deposited. This oxygen could lead to instabilities and adversely affect the function of TFTs. We established that increased the plasma power, resulted in a decrease of the amount of the absorbed oxygen. A post treatment of He or Ar plasma was also effective for removing the weakly bounded oxygen. We argue that the molecular oxygen is adsorbed at defect sites, and that the higher plasma power reduces the absorbed oxygen content either by diminishing the defected density and/or through photo-induced desorption. In addition, the pure Hf oxide films show a grained morphology which apparently reflects the polycrystalline nature of the Hf oxide. In order to suppress the crystallization of the oxide and to obtain a smooth morphology, we deposited 1-3 cycles of La-oxide between two adjacent Hf-oxide cycles. The multilayered films showed a significant improvement of the morphology compared with the roughness of the pure Hf oxide film. Process parameters were also identified that resulted in a relatively low concentration of carbon residue. *Work by US Army Cooperative Agreement W911NF-04-2-0005 (FDC-10-4.6)
3:30 PM - F2.4
UV Assisted Solution-based Zirconium Oxide Gate Dielectric for Low-voltage Operation of Organic Field Effect Transistors.
Young Min Park 1 , Alberto Salleo 1 , Juergen Daniel 2
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 , Palo Alto Research Center, Palo Alto, California, United States
Show AbstractOrganic field effect transistors (OFETs) have been attractive for low-cost and low-temperature processing of electronic devices such as RFID tags, sensors and electronic paper. For practical applications of OFETs, there is a need to develop nanometer-scale gate dielectric with high capacitance and low gate leakage current to achieve low-voltage operation. In this regard, inorganic high-κ metal oxide dielectrics have been investigated due to their high dielectric constant as well as the ability to functionalize their surface with self-assembled monolayers(SAM). Inorganic metal oxide, however, have required either vacuum processing or relatively high-temperature anneals, making them incompatible with low-cost solution processing on flexible substrates. Here, we demonstrate low-voltage polymeric OFETs operated below a gate voltage of -3V, fabricated with solution-processed zirconium oxide (ZrOx) at room temperature. ZrOx was deposited via a sol-gel process and cured by UV irradiation under ambient conditions, eliminating the need for a high-temperature anneal. UV irradiation decomposed the zirconium based sol-gel films into thin films composed of only Zr and O on a heavily doped Si substrate, as confirmed by X-ray photoelectron spectroscopy. The areal capacitance of UV cured dielectrics ranged from 470 to 522nF/cm2, and showed a dependence on UV irradiation time. Introduction of an Octadecyl-phosphonic acid (ODPA) SAM on the surface of ZrOx reduced the leakage current from the order of 10-4 A/cm2 to 10-7 A/cm2 at an applied voltage of -3V while making the dielectric more compatible with organic semiconductors. We demonstrate polymer OFET devices using poly(2,5-bis(3-dodecylthiophen-2yl(thieno[3,2-b]thiophene) (PBTTT C-14) on the solution-processed, UV cured ZrOx dielectric operating at low-voltage (|VGS|<3V) with high field effect mobility (µ~0.2 cm2/V.s) and high on-off current ratio (105~106).
3:45 PM - F2.5
Pressure Dependence on the Physical Properties of SiO2 Gate Oxide Formed by Inductive Coupled Plasma Oxidation.
Beomjong Kim 1 , Dongchan Kim 1 , Yoonjae Kim 1 , Hanjin Lim 1 , Jueun Kim 1 , Wookyeol Yi 1 , Daehyun Kim 1 , Bonghyun Kim 1 , Youngwan Kim 1 , Sungho Kang 1 , Youngseok Kim 1 , Woojun Lee 1 , Seokwoo Nam 1
1 , Samsung Electronics Co. Ltd., Hwasung Korea (the Republic of)
Show AbstractRecent semiconductor devices need low thermal budget process to scale down. The plasma oxidation is one of the most promising candidates. In this work, we investigated the pressure effect on the physical properties of the oxide grown by inductive coupled plasma oxidation. The activation energy (Ea) and electron temperature (Te) were calculated. The Te decreases as the pressure increases but the Ea increases with pressure. It is supposed that the pressure dependence on the Ea is related to the energy of oxygen ions participating in oxidation. In the low pressure region, ions are the major oxidants and they are accelerated by the plasma sheath potential. Because the potential is linearly proportional to the Te, the ions have more kinetic energy at the higher Te. These highly kinetic ions can easily break the Si-Si bonding and lower the energy barrier of oxidation. It reduces the Ea at low pressure below 100mTorr. In this case, the strong collisions can make the interfacial defect sites by damaging the initial silicon surface. The interfacial trap density estimated by charge pumping method shows the inverse proportionality with the pressure. At the higher pressure region, (> 100mTorr) the major oxidants are the oxygen radicals and the mean free path of these radicals decreases with pressure, the chance to reach at the silicon surface decrease. Thus, the Ea increases with pressure, although the Te is constant at over 100mTorr. The normalized field effective mobility is compared between samples of different pressures and the peak increases as the process pressure increases. For getting better interface, it is the key to lower the Te. From this point of view, the pressure is a very effective process parameter and it could come with an improved mobility and interface properties.
4:30 PM - F2.6
Precursor Design and Engineering for Low-temperature Deposition of Gate Dielectrics for Thin Film Transistors.
Anupama Mallikarjunan 1 , Laura Matz 1 , Andrew Johnson 1 , Raymond Vrtis 1 , Manchao Xiao 2 , Mark O'Neill 2 , Bing Han 1
1 , Air Products and Chemicals, Inc., Allentown, Pennsylvania, United States, 2 , Air Products and Chemicals, Inc., Carlsbad, California, United States
Show AbstractThe electrical and physical quality of gate and passivation dielectrics significantly impacts the device performance of thin film transistors (TFTs). As low temperature TFT processing becomes a requirement for novel applications and plastic substrates, there is a need for materials innovation that provides gate dielectrics having good density and dielectric constant (k), low leakage, low charge density (measured by flatband voltage or Vfb), low wet etch rate (WER), and high breakdown voltage (Vbd). The passivation dielectric also needs to act as a barrier to protect the TFT device. In this context, this paper discusses structure-property relationships and strategies for precursor development in silicon nitride, silicon oxycarbide (SiOC) and silicon oxide films; and demonstrates the value of precursor engineering for low temperature plasma enhanced chemical vapor deposition (PECVD) of SiO2 gate dielectrics (that are used with polysilicon TFTs for example). For SiO2 deposition, organosilicon precursors containing different types and amounts of Si, C, O and H bonding were experimentally compared to the industry standard TEOS (tetraethoxysilane) at different process conditions and temperatures. In general, carbon incorporation into these low temperature oxide (LTO) films was not detected by XPS or FTIR; and the O/Si ratio was between 2.1-2.2. However, major differences were identified in film quality especially WER (correlating to film density) and k values (correlating to moisture absorption). The paper will discuss a systematic methodology for optimization of the functionality of the precursors to enable superior performance over TEOS. It is advantageous to have precursors that are more plasma-driven and show less uncontrolled deposition as temperature is lowered. This is illustrated by the electrical performance with an optimized material, AP-LTO® 770. For example, under identical deposition conditions at 200°C, a TEOS SiO2 had a 6:1 BOE (Buffered Oxide Etch) WER of 538 nm/min vs 275 nm/min for AP-LTO® 770 film. This improvement comes due to higher density (measured by X –ray reflectivity) and lower moisture content (seen by FTIR) in the AP-LTO® 770 SiO2 films. Correspondingly, leakage current, k, Vbd, Vfb all show performance improvements over TEOS films. Additionally, the precursor has a lower B.P. than TEOS (B.P=169°C), simplifying current delivery and uniformity issues seen for large substrates. The design and development of such novel precursors is a key factor to successfully enable manufacturing of advanced low temperature processed devices.
4:45 PM - F2.7
Low-damage Preparation of SiO2 Dielectric Thin Film by the Photo-assisted Oxidation Processing.
Takehito Kodzasa 1 , Sei Uemura 1 , Kouji Suemori 1 , Manabu Yoshida 1 , Satoshi Hoshino 1 , Noriyuki Takada 1 , Toshihide Kamata 1
1 , National Institute of Advanced Industrial Science and Technology, Tsukuba Japan
Show AbstractWe have already reported that low-temperature (about 170C) preparation technique of SiO2 dielectric thin film that has high resistivity and extremely smooth surface by the photo oxidation processing. However convenient plastic films such as polyethylene terephthalate (PET), polystyrene (PS) and Poly(methyl methacrylate) (PMMA) are easily damaged by heating over 150C or light irradiation. Now, in this paper, we report that SiO2 thin film with high insulation performance can be obtained with no damage against light irradiation. And we show that the SiO2 dielectric thin film having high insulating property is prepared by the low-temperature processing below 100C by improving the pre- and post- processing of the photo oxidation of thin film.
5:00 PM - F2.8
Effect of Hydrogen on Electrical Performance of Charge-trapping Device Structure of SiAlON/Si3N4/SiO2/ Stacks.
Nam Nguyen 1 , Ziyuan Lu 2 , Markus Wilde 3 , Toyohiro Chikyow 1
1 Advanced Electronic Materials Center, National Institute for Materials Science, Tsukuba Japan, 2 Test and Analysis Division, NEC Electronic Corporation, Kawasaki Japan, 3 Institute of Industrial Science, University of Tokyo, Tokyo Japan
Show AbstractSilicon Aluminum Oxide Nitride (SiAlON) thin films are investigated as a new class of hydrogen diffusion barrier materials to replace the top silicon oxide layer in Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) charge-trapping flash memories devices. SiAlON thin films were deposited at temperature of 300 °C and oxygen partial pressure of 10-5 torr by pulsed laser deposition (PLD). The interfacial structure, chemistry along with the chemical composition, thickness, roughness of individual layer and H profile of MONOS stacks were analyzed using X-ray reflectivity (XRR), x-ray photoelectron spectroscopy (XPS), and nuclear reaction analysis (NRA). The changes observed in the interfacial structure, chemistry and H concentration of the MONOS device structures were correlated with their electrical performance. The results demonstrated that by using SiAlON to replace the top silicon oxide layer yields 1) reduced H concentration at the SiO2/Si interface and 2) enhanced electrical performance of MONOS memories devices. These findings suggest that SiAlON layer can effectively store hydrogen and it is a more effective diffusion barrier than the structurally open SiO2.
5:15 PM - F2.9
Small Molecule-polymer Blend Organic Field Effect Transistors with Long-term Environmental and Operational Stability Using Fluoropolymer/Oxide Bi-layer Top Gate Dielectric.
Do Kyung Hwang 1 , Canek Fuentes-Hernandez 1 , Jungbae Kim 1 , William Potscavage 1 , Sung-Jin Kim 1 , Bernard Kippelen 1
1 School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractOver the last several years, organic field-effect transistors (OFETs) have made great progress. However, long-term environmental and operational stabilities are still two major issues for commercialization of OFETs. Recently, much effort has been devoted to improve environmental and operational stabilities of OFETs. In most studies, OFETs with a bottom-gate geometry have been used. OFETs with a top-gate geometry are relatively rare because the choice of gate dielectric materials is limited since its deposition can potentially damage the organic semiconductor layer. An amorphous fluoropolymer, CYTOP, has been shown to be a promising candidate for the realization of top-gate geometries because it dissolves in fluorinated solvents that are orthogonal to most organic semiconductor materials. The CYTOP has an excellent chemical stability and is highly hydrophobic, which leads to OFETs with good operational stability. Instead of using a single layer of CYTOP, CYTOP/high-
k oxide bi-layer as top-gate dielectric combines the excellent chemical properties of CYTOP with the high film quality and large capacitance density of high-
k oxides. In addition, this bi-layer top gate dielectric can be an encapsulation layer against environmental exposure.
Here, we report on the improved stability and performance of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene)-poly(triarylamine) (PTAA) blend OFETs with a top gate geometry using a CYTOP/Al2O3 bi-layer. OFETs fabricated with a single Al2O3 layer operate below 8 V due to a high capacitance density of 78.6 nF/cm2, but show a large hysteresis and low average mobility value of 5.5(±1.9)×10-3 cm2/Vs. On the other hand, the devices with a single CYTOP layer show an average mobility value of 0.39±0.16 cm2/Vs without hysteresis. However, they operate at high voltages, up to 50 V, due to a low high capacitance density of 2.3 nF/cm2. In contrast, OFETs using the CYTOP/Al2O3 bi-layer show no hysteresis and an average mobility value of 0.46±0.08 cm2/Vs below 8 V, due to a relatively high capacitance density of 34.8 nF/cm2. After 20,000 multiple scans or under 24 h constant dc bias stress in an inert atmosphere, OFETs with the CYTOP/Al2O3 bi-layer show no degradation of mobility or threshold voltage. Upon air exposure, and after an initial variation, negligible changes in mobility and threshold voltage were measured in OFETs with the CYTOP/Al2O3 bi-layer after being stored in air for over five months.
5:30 PM - F2.10
Biocompatible and Biodegradable Materials for Organic Field Effect Transistors.
Mihai Irimia-Vladu 1 4 , Pavel Troshin 2 , Melanie Reisinger 1 , Guenther Schwabegger 3 , Reinhard Schwoediauer 1 , Vladimir Razumov 2 , Helmut Sitter 3 , Siegfried Bauer 1 , Niyazi Sariciftci 4
1 Soft Matter Physics , Johannes Kepler University, Linz Austria, 4 Linz Institute for Organic Solar Cells (LIOS), Johannes Kepler University, Linz Austria, 2 Institute of Problems of Chemical Physics, Russian Academy of Sciences, Chernogolovka Russian Federation, 3 Institute of Semiconductor and Solid State Physics, Johannes Kepler University, Linz Austria
Show AbstractOrganic electronics has the potential to develop electronic products that are biocompatible, bioresorbable, biodegradable or even capable to bio-metabolize. An ideal solution for the production of such devices involves the fabrication of the electronics either from natural materials, or from materials that have been proved to be at least biocompatible. Here we report the combination of biocompatible and biodegradable substrates based on hard gelatine capsule or commercially available plastic foil based on starch, corn and polylactic acid (Ecoflex®, BASF) with fully natural or materials found in common commodity products, as gate dielectrics and organic semiconductors in low operating voltage organic field effect transistors (OFETs). In a first example, low operating voltage OFETs are built on commercially available biodegradable plastic foil (Ecoflex®, BASF), comprising naturally occurring dielectrics: adenine, guanine, cytosine, thymine and widely accepted perylene diimide-a simple red dye used extensively in cosmetic industry. In a second example, complete bio-materials based OFETs are introduced based on glucose, lactose, sucrose, for the gate dielectrics with vacuum processed indigo or solution processed beta-carotene as organic semiconductors respectively. In a third example, fully degradable devices are produced on hard gelatine capsule substrates substrate comprising layers of adenine and guanine for organic dielectrics and indanthrene yellow G and indanthrene brilliant orange RF (two vat dyes used extensively in textile industry) for the organic semiconductor. Tremendous improvement of the OFETs characteristics are feasible simply by employing aurin, a naturally occurring red-orange pigment as a smoothening layer for Ecoflex and hard gelatine capsule substrates or by employing the anodization of the aluminium gate electrodes in combination with organic dielectric layers for the samples built on glass substrates. Such transistors may be seen at the heart of organic electronic circuits, to be used in low-cost, large volume disposable or throwaway applications, such as food packaging, plastic bags, disposable dishware etc. There is also significant potential to use such electronic items in biomedical implants.The work was financially funded by Austrian Science Foundation “FWF” within the National Research Network NFN on Organic Devices (P20772-N20, S09712-N08, S09706-N08 and S9711-N08) as well as by Russian Foundation for Basic Research (07-04-01742) and Russian Ministry of Science and Education (02-513-11-3382).
F3: Poster Session: Organic and CNT TFT
Session Chairs
Monday PM, November 29, 2010
Exhibition Hall D (Hynes)
9:00 PM - F3.2
Adjustable Memory Effect in Organic Thin Film Transistors via Embedded Nanoparticles in Pentacene Layer.
Sumei Wang 1 2 , Paddy, K. L. Chan 1 , Dennis,C. W. Leung 2
1 Department of Mechanical Engineering, the Hongkong Polytechnic University, Hongkong China, 2 Department of Applied Physics, the Hongkong Polytechnic University, Hongkong China
Show AbstractOrganic devices have attracted considerable attentions due to the simplicity of fabrication process, flexible property and low manufacturing cost. Here we demonstrate organic nonvolatile transistor memory devices based on silver nanoparticles embedded in pentacene thin films layer. The transistor transfer characteristics exhibit large hysteresis (memory window) when the gate bias sweeps from positive value to negative and then back to positive. The memory window can be adjusted by varying the Ag nanoparticle location within the pentacene layer. A memory window as large as 90V was achieved in the pentacene (15 nm)/Ag nanoparticle (5nm)/pentacene (25 nm) device, which is three times larger than that of the conventional structure where the Ag NPs are directly deposited on the silicon dioxide dielectric layer. The influence of silver nanoparticle size on the performance of memory device was also studied. When the nanoparticle size was 1nm, the memory device showed a long retention time of more than 5×104 seconds with a distinct on/off current ratio of 10. The memory effect was explained by a model based on Ag nanoparticle-induced traps. This work demonstrates a simple route of tuning the memory behavior in organic thin film transistors, which has potential for memory applications in flexible electronic circuits.
9:00 PM - F3.3
A Detailed Experimental Study of the Short Channel Effect in PPV Based Organic Field Effect Transistors.
Ali Veysel Tunc 1 , Elizabeth von Hauff 1 , Juergen Parisi 1
1 Department of Physics, EHF Laboratory, University of Oldenburg, Oldenburg Germany
Show AbstractThe origin of the short channel effect in polymer-based field effect transistors (FETs) was investigated. Here, we employed poly [2-methoxy,5-(3',7'-dimethyl-octyloxy)]-p-phenylene vinylene (MDMO-PPV) in blends with different ratios of 1-(3-methoxycarbonyl) propyl-1-phenyl[6,6]C61 (PCBM). Bottom contact and bottom gate with interdigitated structure on SiO2 insulating substrates with channel lengths of 20, 10, 5 and 2.5 µm were used for these studies. In this work we demonstrate that the short channel effect is not only influenced by the device geometry but there is also a correlation between the hole current and field effect mobility, contact resistance and short channel behavior in PPV FETs. We observed that increasing the PCBM content in the blend leads to an increase in the hole current and field effect mobility, a decrease in the contact resistance, as well as a deviation from the saturation behavior of the output characteristics of the FET. This effect is attributed to a change in the polymer chain ordering in the source channel which in turn influences the charge transport properties in the polymer film. We show that using a self assembled monolayer on the SiO2 gate dielectric, known to affect polymer chain ordering, also influences the transistor parameters.
9:00 PM - F3.5
High Mobility, Low Voltage Operating C60 Based N-type Organic Field Effect Transistors.
Mujeeb Ullah 1 , Mihai Irimia-Vladu 2 , Melanie Reisinger 2 , Yasin Kanbur 3 , Guenther Schwabegger 1 , Reinhard Schwoediauer 2 , Siegfried Bauer 2 , Niyazi Sariciftci 4 , Helmut Sitter 1
1 Institute of Semiconductor and Solid State Physics, Johannes Kepler University Linz, Linz Austria, 2 Institute of Soft Matter Physics (SOMAP), Johannes Kepler University Linz, Linz Austria, 3 Department of Polymer Science and Technology, Middle East Technical University, Balgat, Ankara Turkey, 4 Linz Institute of Organic Solar Cells (LIOS), Johannes Kepler University Linz, Linz Austria
Show AbstractWe report the state-of-the-art of C60 based bottom gate-top contact transistors fabricated by using different organic materials (BCB, Polyethylene and Adenine) / metal-oxide (AlOx) bilayer as gate dielectric. The engineering of the metal-oxide and the organic material passivation bilayer combines the advantages of having a high dielectric metal oxide and a thin passivation layer of polymer or small molecule capped on AlOx layer. The passivation layer helps both smoothing the dielectric surface and suppressing the leakage current while providing good interface properties with the semiconductor layers. This results in OFETs that operate at voltages less than 500 mV. The AlOx layers are readily processable from solution and cured at low temperature, instead of traditionally sputtering or high temperature processing, thus this process is suitable for low-cost organic field effect transistors (OFETs) manufacture. The output characteristics of the OFETs show well saturation behavior while the transfer characteristic display an on/off ratio in excess of 103. The OFET devices have a high field effect mobility, which ranges from 2 - 5 cm2/V s for different passivation layers, with low threshold voltages in the range of 20 mV to 5o mV.
9:00 PM - F3.6
Capacitance-Voltage Measurement of an Ambipolar Pentacene Field Effect Transistor in Operation by Using Displacement Current Measurement.
Yuya Tanaka 1 , Yutaka Noguchi 1 2 , Hisao Ishii 1 2
1 Graduate School of Advanced Integration Science, Chiba University, Chiba Japan, 2 Center for Frontier Science, Chiba University, Chiba Japan
Show AbstractRecently, organic field effect transistors (OFETs) have been extensively studied because of their low cost, light weight, flexibility and so on. However the operation mechanism is not yet well understood and OFET has not been put to practical use. Since typical organic semiconductors have an extremely small number of thermal carriers due to their large energy gap and are mostly used without any intentional dopants unlike inorganic FETs, OFETs seem to be driven by the injected carriers from the source electrode. Therefore it is quite important to understand the mechanism of channel formation due to carrier injection in OFET. Capacitance-voltage measurement is crucial to understand the carrier injection and accumulation in OFETs, and has been applied to various OFETs. We also have investigated OFETs by using one of C-V methods, displacement current measurement (DCM)[1]. In this technique, a current through a device is measured under a ramp voltage, and the observed current is proportional to the effective capacitance of the device. C-V measurement including DCM is two-terminal measurement, but transistors are three terminal devices. Thus, the observed carrier behaviors by conventional C-V methods are not the same in operating transistors. In order to understand the channel formation process in OFETs, we need to measure C-V in an operation transistor. In literature [2], an attempt to measure C-V of operating transistor have been reported by measuring both source-gate and drain-gate displacement currents simultaneously. But in the method, the measurement accuracy was limited due to the coexistence of displacement and actual currents in the observed current: the measurement condition was restricted to separate both the components. So, the quality of the obtained C-V curve was not enough to discuss the mechanism of the formation and annihilation process of channel. In this study, we have proposed another method to measure C-V of an operating transistor and succeeded to observe a subtle change of the capacitance during the channel formation. By applying a voltage between a source and drain electrodes with an isolated battery, only displacement current between a gate and the battery was measured. Since it is not necessary to separate displacement and actual currents, high accuracy is achieved. From the observed results of an ambipolar pentacene FET with a tetratetracontance (C44H90) buffer layer on SiO2 insulating layer, we could clearly observe the channel formation and annihilation processes in operating transistor and determine the pinch-off voltage. These results demonstrate that DCM is the powerful tool to investigate the channel formation process of OFET in detail. [1] S. Ogawa et al., Jpn. J. Appl. Phys. 42, L1275 (2003). [2] Y. Majima et al., Jpn. J. Appl. Phys. 46, 1 (2007).
9:00 PM - F3.7
Tetracene Thin Films on Organic Dielectrics: Growth, Structure, and Functional Properties.
Clara Santato 1 , Julia Wuensche 1 , Simone Bertolazzi 1
1 , École Polytechnique Montréal, Montréal, Quebec, Canada
Show AbstractTetracene vacuum-sublimed films exhibit interesting charge carrier transport and electroluminescence properties.These films have been used to demonstrate the first Organic Light Emitting Field Effect Transistors (OLEFET), one of the most promising classes of devices in the field of plastic optoelectronics. Investigating the role played by the morphology and surface chemistry of the dielectric substrate as well as establishing sound structure-property relationships in organic semiconductor films are among the keys to understand and improve OLEFET performance.Here we present our results on the growth, morphology, structure, and functional properties of vacuum-sublimed tetracene films deposited on different organic dielectric substrates, namely HMDS- and OTS-treated SiO2, polystyrene, parylene, polymethylmethacrylate. All the results have been compared with those obtained on SiO2 dielectric substrate, employed as reference.In terms of field effect transistor (FET) performance, the most interesting results were observed for tetracene FET based on polystirene and parylene gate dielectrics.A careful atomic force microscopy (AFM) study performed since the early stages of the growth (i.e. on films whose nominal thickness was 3, 5, 10, 17, 25 and 35 nm) revealed the good substrate surface coverage, large particles' size (expressed in terms of correlation length), and low particles' density obtained for tetracene films deposited on parylene and polystirene dielectric substrates. These results are able to explain the tetracene FET performance.The AFM observations were compared with the results collected during a synchrotron grazing incidence x-ray diffraction study carried out on these same tetracene films. Information concerning the film crystalline structure, the particles' size, but also the molecular arrangement in the cell were useful to get a deeper insight on the FET performance.The complexity and richness of the results we collected indicate the number of semiconductor- and dielectric-related features to be considered to rationally design the new generation of plastic optoelectronic devices.
9:00 PM - F3.8
Polymer Source-Gated Transistors.
S. Georgakopoulos 1 , D. Sparrowe 2 , F. Meyer 2 , Maxim Shkunov 1
1 Advanced Technology Institute, University of Surrey, Surrey United Kingdom, 2 Chilworth Technical Centre, Merck Chemicals Ltd., Southampton United Kingdom
Show AbstractThe reliability and stability of organic transistors has been steadily improving. Recently, amorphous conjugated co-polymer Field-Effect Transistors (FETs) have exhibited outstanding stability in air [1] and narrow mobility spread across large numbers of transistors and several different processing methods [2]. However, significant challenges remain until practical large-scale production of sufficiently high-performance devices can be realized. Two of these challenges are the high operating voltage of organic FETs and short-channel effects requiring downscaling of the dielectric layer. We demonstrate organic transistors capable of overcoming these two limitations.In Field-Effect Transistors (FETs) the gate modulates the conductance of a channel with ohmic source/drain contacts, and the current saturates when the drain end is depleted of carriers. In a novel type of thin film transistor, namely Source-Gated Transistor (SGT), a Schottky barrier at the source modulates the current through the device, and the depletion region causes pinch-off of the conductive channel at much lower voltages than for FETs. SGTs retain strong saturation even for short channel lengths and thick dielectric layers.In this work we have fabricated SGTs with an amorphous π-conjugated polymer semiconductor that demonstrate source-gating in organics for the first time. The properties of our polymer SGTs generally follow the predictions developed for inorganic SGTs [3], including low-voltage saturation and good operation in short channels. The low-voltage saturation of organic SGTs provides an opportunity for the realization of solution- processable transistors with low power consumption. Also, the dielectric layer is not required to be downscaled, allowing for simpler fabrication, including low-temperature printing processes. References[1] W. Zhang, et al. J. Am. Chem. Soc. 131, 10814 (2009)[2] J.M. Verilhac, Org. Electron., 11, 456 (2010)[3] J.M. Shannon, E.G. Gerstner. IEEE Electr. Device Lett., 24, 405 (2003); J.M. Shannon, F. Balon. Solid State Electron., 52, 449 (2008); T. Lindner, G. Paasch, S. Scheinert. IEEE T. Electron. Dev., 52, 47 (2005)
Symposium Organizers
Soeren Steudel IMEC
Shelby F. Nelson Eastman Kodak Company
Veit Wagner Jacobs University Bremen
Heiko Thiem Evonik Degussa GmbH
F4/MM4: Joint Session: Vacuum Deposited Metaloxide TFT
Session Chairs
Shelby Nelson
Erin Ratcliff
Tuesday AM, November 30, 2010
Constitution B (Sheraton)
9:30 AM - **F4.1/MM4.1
Fully Transparent n and p-type Oxide TFTs.
Elvira Fortunato 1
1 Materials Science, FCT-UNL, Caparica Portugal
Show AbstractTransparent electronics is growing so fast and is today one of the most advanced topics for a wide range of device applications, where the key component are wide band gap semiconductors, and oxides of different origin play an important role, not only as passive component but also as an active component similar to what we observe in conventional semiconductors. In this paper we will review the main achievements related to fully transparent n-type oxide based TFTs as well as to p-type oxide based TFTs produced at CENIMAT/I3N.
10:00 AM - F4.2/MM4.2
P-Type Tin Monoxide Semiconductor Fabricated by Sputtering.
Po-Ching Hsu 1 , Wei-Chung Chen 1 , Tzu-Ming Wang 1 , Chung-Chih Wu 1 , Hsing-Hung Hsieh 2 , Ching-Sang Chuang 2 , Yusin Lin 2
1 Graduate Institute of Electronics Engineering, National Taiwan University, Taipei Taiwan, 2 , AU Optronics Corporation, Hsinchu Taiwan
Show Abstractp-type tin monoxide (SnO) is one of the most promising p-type oxide TFT material [1]. Here, we report the fabrication of SnO p-type oxide semiconductor on glass substrates by the TFT-industry compatible sputtering technique, which is different from the previous reports (e.g. epitaxy on crystalline substrates by pulsed laser deposition etc. [1, 2]). By using targets of appropriate compositions, SnO films on glass substrates were successfully obtained by deposition at room temperature, followed by post annealing. The as-deposited film showed an amorphous phase, while polycrystalline tin monoxide phase was obtained after thermal annealing. By judiciously controlling the working gas during the sputtering, we can not only modulate the Sn/O ratio in SnO films, but also improve the orientations/crystallinity of the SnO phase. We also observed that appropriate combinations of working gases can significantly decrease the post-annealing temperature required for the formation of the SnO phase, making the whole process temperature compatible with the glass substrates. With a <450°C process, the p-type Hall mobility of 0.1-1 cm2V-1s-1 and p-type carrier concentration down to the order of 1017 cm-3 were successfully achieved in the SnO films, which meet the requirements for active layers of thin-film transistors. The realization of p-type SnO films by room-temperature sputtering and low-temperature post annealing demonstrates the possibility of large-area and low-cost p-type oxide TFT fabrication. [1] Y. Ogo, H. Hiramatsu, K. Nomura, H. Yanagi, T. Kamiya, M. Hirano, and H. Hosono, Appl. Phys. Lett. 93, 032113 (2008). [2] Ho-Nyeon Lee, Hyung-Jung Kim, and Chang-Kyo Kim, Jpn. J. Appl. Phys. 49, 020202 (2010).
10:15 AM - **F4.3/MM4.3
The Improvement of Photo-induced Bias Stability of the Oxide TFT.
Chang Jung Kim 1 , Sun Il Kim 1 , Jae Chul Park 1 , Sang Wook Kim 1 , Ihun Song 1 , U-In Chung 1
1 , Samsung Advanced Institute of Technology (SAIT), Yongin-si Gyeonggi-do Korea (the Republic of)
Show AbstractWe successfully fabricated the high stable amorphous hafnium-indium-zinc-oxide (HIZO) thin film transistors (TFTs) with SiOF gate insulator layer and SiOx/SiON passivation layer by systematically investigating the role of various gate insulator layers and passivation layers under negative-bias-temperature illumination-stress (NBTIS) condition. For example, the instability of the TFTs with SiOx passivation layer (threshold voltage shift (ΔVth)~ -6.5V) is less than that of the TFTs with SiONx passivation layer (ΔVth ~ -8.5V). Also, we could get better photo-induced bias stability after back channel treatments. Finally, using the SiOF gate insulator, the back channel treatments, and the SiOx (inner)/SiONx (outer) passivation layers, the instability of the amorphous HIZO TFTs were drastically improved by the suppression of the positive charge trapping sites under the NBTIS conditions. These are very promising results for applications in large area AMLCD and AMOLED display with high intensity light source.
11:15 AM - **F4.4/MM4.4
Improvement of Performances and Stability of a-In-Ga-Zn-O TFT by Low-temperature Annealing.
Kenji Nomura 2 , Hideo Hosono 1 2 , Toshio Kamiya 1
2 Frontier Research Center, Tokyo Institute of Technology, Yokohama Japan, 1 Materials and Structures Laboratory, Tokyo Institute of Technology, Yokohama Japan
Show AbstractTransparent amorphous oxide semiconductor represented by a-In-Ga-Zn-O (a-IGZO) is widely accepted as a channel material of driving /switching thin-film transistors (TFTs) for next-generation flat-panel displays such as high-resolution active-matrix (AM) organic light-emitting displays and large-size / high fram rate AM –liquid-crystal displays (LCD) because they have better performances such as large mobilities of ~10 cm2(Vs)-1 and substhreshold slope swing (S) values than a-Si:H TFTs even when they are fabricated at room temperature. To date, many efforts have been devoted to improve TFT characteristics including stability against electrical stress for practical-use. It is known well that post thermal annealing over 300 oC is effective to improve TFT characteristics due to the reduction of subgap defect states in a-IGZO channels. However, it is indispensible to reduce annealing temperature for developing stable and high-performance flexible electronic devices. In this paper, we report improvement of performances and stability of a-IGZO TFTs by low-temperature annealing. Bottom-gate and top-contact a-IGZO TFTs were fabricated on thermally-oxidized SiO2/ c-Si. The a-IGZO channel layers were deposited at room temperature (RT) and subjected subsequently to annealing at 100-400oC in dry O2, wet O2, or ozone atmospheres. Electron-beam evaporated Ti / Au electrodes were used as source / drain contacts. Constant current stress and light illuminated negative bias stress tests were examined to evaluate TFT stability. We found that strong power oxidation atmospheres such as wet O2 are effective to reduce subgap defects state for high-temperature annealing over 300oC. The 400oC-wet annealed TFTs exhibited best performances such as saturated mobility (μsat) ~ 12.4 cm2(Vs)-1 and S ~ 112 mV/dec. However, both the dry and wetO2 annealing caused large negative threshold voltage shifts originating from increase of donor density in the channel for low-temperature annealing at < 200oC. It was found that ozone thermal annealing can improve TFT characteristics even at 150oC, and the 150oC-ozone annealed TFTs exhibited reasonably good performances such as μsat ~ 11.9 cm2(Vs)-1 and S ~ 260 mV/dec. The TFT stability under constant current bias and light illuminated negative bias for TFTs with a wider range of channel quality will also be presented.
11:45 AM - F4.5/MM4.5
High Mobility Amorphous Metal Oxynitride Thin Film Semiconductors.
Yan Ye 1 , Rodney Lim 1 , Anshu Gaur 1 , John White 1
1 AKT, Applied Materials, Inc, Santa Clara, California, United States
Show AbstractAmorphous thin film semiconductors are preferred over polycrystalline films for large-area electronics manufacturing because of better local uniformity and consistency of structure through the thickness of the deposited film. Linked to their bond ionicities, single-metal oxides, such as In2O3, Ga2O3, ZnO and SnO2, tend to form films that are highly crystalline in structure. Combining several of these metal oxides by simultaneous deposition to form a single film such as InGaZnO, creates competition amongst the various oxides and frustrates the formation of any long-range crystalline structures; thereby producing a substantially amorphous structure.A different approach to produce amorphous semiconductor materials has been explored, using a single-metal system. The amorphous phase is achieved by promoting competition between reactions responsible for the growth of compounds from the same metal but different crystalline structures. We used zinc as the metal and both oxygen and nitrogen as reactants in a reactive sputtering process. By adjusting the ratio of the reactants, we are able to make the reaction dominated by either oxygen or nitrogen, or balanced with equivalent reaction rates. As the result, we are able to produce films of crystalline zinc oxide ZnO, nitrogen doped crystalline zinc oxide ZnO:N, amorphous or highly disordered nanocrystalline zinc oxynitride ZnON, or crystalline zinc nitride Zn3N2. Each film has its own chemical and physical properties. We observed that the highest mobility is attained from amorphous zinc oxynitrides. Even though the films produced from the multi-reactant process have a highly disordered structure, they exhibit a higher Hall mobility than the crystalline films produced from preferential growth under the dominance of a single reaction. Moreover, the mobility of the ZnON films deposited at low temperature is higher than that of InGaZnO. Furthermore, the mobility increases as electron carrier concentration decreases over a wide range of the carrier concentration. This characteristic is opposite from the behavior of InGaZnO and indicates that carrier transport in the new semiconductor is dominated by a different mechanism, likely due to different constitutions of conduction band bottom, as will be discussed. Stability of the films and devices made with the new semicoductor has been tested under various stress conditions. Shelf life of an as-deposited film deposited at 50C was about 30 days when it was exposed to room air without any passivation or other protection. Failure is due to the adsorption of moisture and pollutants in the air. An annealed film has been exposed to room air without any protection for more than 600 days without degradation. Thin film transistors (TFTs), active matrix-TFT arrays, and e-ink displays have all been made successfully with the new semiconductor material. Tests of the TFTs under high-temperature and bias-temperature stress have been performed and results will be presented.
12:00 PM - F4.6/MM4.6
High Performance Amorphous-oxide-semiconductor with Indium Tin Zinc Oxide (ITZO) for Thin Film Transistor.
Masashi Kasami 1 , Mami Nishimura 1 , Masayuki Itose 1 , Masahide Matsuura 1 , Shigeo Matsuzaki 1 , Hirokazu Kawashima 1 , Futoshi Utsuno 1 , Koki Yano 1
1 Advanced Research Laboratories, Idemitsu Kosan Co., Ltd., Chiba Japan
Show AbstractTransparent amorphous oxide semiconductors (TAOS) are of growing interest in the context of thin film transistor (TFT) channel layers for transparent electronics and various electronics applications because of their high mobility and large area uniformity. In particular, the most popular TAOS is indium gallium zinc oxide (IGZO), and there have been many studies on practical applications as the backplane of AM-OLED and 2k×4k display panels. Although IGZO was mobility of the order of ~10 cm2/Vs, higher mobility has been needed to fabricate next generation applications such as a super high-vision panel and to integrate driver circuit. Moreover, an etching stopper layer was necessary for using in the conventional pattering process because IGZO was acid soluble. Therefore, the TAOS with insolubility in various acids was needed to be adopted the conventional TFT process. We developed new oxide semiconductor of indium tin zinc oxide (ITZO) with high electrical performances and processability. Since our developed ITZO target has low resistivity, it was possible to be deposited by direct current (DC) sputtering. The obtained film was amorphous and PAN (phosphoric, acetic and nitric acid) insoluble. In this work, we studied electrical and practical properties of ITZO films deposited under various deposition conditions at room temperature.In the as-deposited ITZO films, the carrier density and Hall mobility decreased with increasing oxygen partial pressure. In the post annealed films, however, their carrier density and Hall mobility maintained almost constant values independent of oxygen partial pressure. Hall mobility and carrier density of their post annealed films, which were annealed at 300 °C for 1 hour, were 30 cm2/Vs and ~1018 cm-3, respectively. ITZO film was soluble in oxalic acid, as same as transparent electrodes such as amorphous ITO and IZO films. However it was insoluble in PAN which was used in conventional pattering process of source and drain electrode. Also the etching rate of ITZO film for oxalic acid was about 2~5 nm/sec at 40 °C as same as that of IZO. We fabricated the ITZO channel TFT using photolithography technique. The channel length and width were 20 μm and 10 μm, respectively. The field-effect mobility was 20 cm2/Vs, it was higher than that of IGZO TFT. It was noted that its threshold voltage, S-factor, and On/Off ratio were -5 V, 0.4 V/dec., and 108, respectively.
12:15 PM - F4.7/MM4.7
Transparent MgZnO-based Metal-semiconductor Field Effect Transistors and Devices.
Alexander Lajn 1 , Heiko Frenzel 1 , Tobias Diez 1 , Fabian Kluepfel 1 , Friedrich Schein 1 , Holger von Wenckstern 1 , Marius Grundmann 1
1 Semiconductor physics group, University of Leipzig, Leipzig , Saxony, Germany
Show AbstractTransparent electronics combined with transparent light emitters permit the fabrication of fully transparent displays. New designs, which involve higher information content, better ergonomics, augmented reality applications, lower power consumption and new aesthetic aspects, are feasible; e.g. in car wind shields, windows, sun glasses, monitors or cell phones.
The authors report on the fabrication of transparent rectifying contacts (TRC) on MgZnO thin films and their application in field-effect transistors and inverters. The TRC are fabricated by reactive sputtering of an about 5 nm thick silver oxide or platinum oxide layer and a subsequently deposited metallic conducting capping layer of about 5 nm thickness. An average transmission of 70 % (60%) in the visible spectral range was achieved for the AgxO (PtOy)-based TRC. Using standard photo-lithographic techniques, transparent metal-semiconductor field-effect transistors (TMESFET) utilizing TRC as gate electrodes and ZnO:Al for the source and drain contacts were processed.
These devices reach a channel mobility of 12 cm2/Vs and on/off-ratios of 106 1. These performance values are only slightly lower compared with those of opaque MESFETs2. With that, the devices meet the requirements for the use in transparent displays formulated by Wager3. Furthermore the TMESFETs operate at low voltages; a voltage sweep of only about ΔV = 2.5 V is required to switch between on- and off-state. In addition, with 120 mV/dec, the sub-threshold slope of the TMESFETs is only a factor of two higher than the thermodynamic limit of 60 mV/dec.
The advantages of MESFETs (compared to state of the art transparent MISFETs) were successfully transferred to inverter circuits, yielding a maximum gain of 200 at a supply voltage of only 4 V and a low uncertainty range of 0.3 V. The effect of irradiating the inverter circuits with visible light was studied and no significant influence of red and green light was observed. When irradiated with blue light, a 15% decrease of the gain was observed. Furthermore, the stability of the inverter circuits at temperatures between room temperature and 150°C was investigated. Thermal degradation of the AgxO-gate electrodes started at temperatures of about 90°C4, nevertheless the inverters remained fully operational up to 150°C.
In summary, the authors present a promising approach to transparent electronics based on TRC including fully transparent MESFETs and inverter circuits.
1. Frenzel
et al. , J. Appl. Phys.,
107, 114515 (2010)
2. Frenzel
et al. , Appl. Phys. Lett.
92, 192108 (2008)
3) J. F. Wager, Science,
300, 1245 (2003)
4) Frenzel
et al. , Thin Solid Films,
518, 1119 (2009).
12:30 PM - F4.8/MM4.8
Low-temperature Processing of Metal-semiconductor Field-effect Transistors Based on Amorphous Gallium-indium-zinc-oxide and Indium-zinc-oxide Thin Films.
Michael Lorenz 1 , Alexander Lajn 1 , Heiko Frenzel 1 , Holger von Wenckstern 1 , Marius Grundmann 1 , Pedro Barquinha 2 , Elvira Fortunato 2 , Rodrigo Martins 2
1 , Universität Leipzig - Institut für Experimentelle Physik II, Leipzig Germany, 2 CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa and CEMOP-UNINOVA, Caparica Portugal
Show AbstractThe physics and application of amorphous oxide semiconductors (AOS) are an emerging field of interest. Compared to covalent semiconductors like a-Si:H the influence of the disorder on the mobility of the charged carriers is negligible and not limited to values below 1cm
2/Vs[1]. Besides, AOS can be deposited at room temperature and thus electronics on flexible substrates are possible.
The authors demonstrate metal-semiconductor field-effect transistors (MESFET), which exhibit excellent electrical characteristics, e.g. channel mobilities up to 15cm2/Vs and a subthreshold swing of S=69mV/decade. The IZO or GIZO channel material and the AgxO-Schottky gate electrodes were all deposited at room-temperature. The influence of a low temperature annealing step (T=150°C) after device production is furthermore investigated.
IZO and GIZO thin films were grown by radio frequency magnetron sputtering at room temperature on Corning 1737 glass substrates. The composition of In and Ga controls the net doping concentration, which determines the extension of the space charge region below the Schottky contact. Accordingly, the IZO and GIZO thin films were grown with thicknesses of 16nm and 160nm, respectivelly. Subsequent annealing at 150°C has strong effects on the electrical properties of the thin films (e.g. Hall-effect mobility) as well as on the device characteristics, e.g. higher field-effect mobilities and lower values for the minimum subthreshold swing S=∂VG/∂log(ISD). The MESFET were fabricated by standard photolithography using lift-off technique. The ohmic source-drain electrodes were sputtered using an Au target in an argon atmosphere. The Schottky gate contacts were dc-sputtered by means of an Ag target in a mixed argon/oxygen atmosphere, which yields a partial oxidization of Ag and hence to higher effective barrier heights for the Schottky contact.
The effective barrier heights of the Schottky contacts (SC) on IZO and GIZO channel material are 0.85eV and 0.96eV, respectively. The ideality factor n of contacts on GIZO were determined for the annealed thin films to be n=1.5 and for the as-grown thin film n=1.8 while the values for n on IZO thin films are approx. 1.7 .
For MESFET on annealed GIZO channel material the source-drain current can be controlled over 8 orders of magnitude with a gate sweep voltage of ΔVG=2.5V. Transistors on the sample chip have the highest field-effect mobility of 15 cm2/Vs and best reproducibility. For annealed IZO channel material the minimum substhreshold swing is S=69mV/decade, which is near the theoretical minimum of 60mV/decade at room temperature and one of the best values reported so far even if compared with the extensive literature on oxide TFTs[2].
[1] R. Martins, P. Barquinha, I. Fereira, Goncalves, and E. Fortunato, J. Appl. Phys. 101, 044505 (2007)
[2] M. Grundmann, H. Frenzel, A. Lajn, M. Lorenz, F. Schein, and H. v. Wenckstern, Phys. Status Solidi A, 207 (2010)
12:45 PM - F4.9/MM4.9
Thermal Annealing and Time Dependent Electric Field Gating Studies of Conductivity Stability in Amorphous Indium Zinc Oxide Thin-film Transistors.
Charles Sievers 1 2 , Thomas Gennett 2 , Joseph Berry 2 , David Ginley 2 , John Perkins 2 , Charles Rogers 1
1 Department of Physics, University of Colorado, Boulder, Boulder, Colorado, United States, 2 , National Renewable Energy Laboratory, Golden, Colorado, United States
Show AbstractThe high electron mobility (10 – 50 cm2/V-s) of low carrier concentration semiconducting amorphous indium zinc oxide (a-IZO) makes a-IZO an attractive channel layer material for transparent thin film transistors (TTFTs). However, even modest thermal processing, such as is required for lithographic processing, can lead to large increases in carrier density in a-IZO. Here, we are studying the temperature dependence and the electric field gating of a-IZO conductivity in thin-film transistors in an effort to understand and control these carrier density changes. For as-grown films, we find that the electric field gated a-IZO conductivity has a two-stage time dependent response. First, the electric field produces a prompt change in conductivity, consistent with electron depletion physics. This quick response is then followed by a slow relaxation process with a time sale of order 10 minutes, strongly suggesting the presence of positive mobile ions in the as-grown films. Sequences of short thermal anneals at temperatures ranging from 100 to 300 °C yield an initial increase the conductivity from 1e-4 to 1e2 S/cm and then a subsequent decrease to a more stable conductivity of 1-10 S/cm. Furthermore, these anneals reduce the magnitude of the long time scale conductivity changes in the gating. Comparative studies of exposed and SiO encapsulated a-IZO channel layers over a range of environments from vacuum to pure oxygen suggest that the thermal and slow electric field response both trace to mobile positive ions, which can be driven from the films by suitable baking during device fabrication.
F5/MM5: Joint Session: Solution Processed Metaloxide Semiconductor
Session Chairs
Erin Ratcliff
Heiko Thiem
Tuesday PM, November 30, 2010
Constitution B (Sheraton)
2:30 PM - **F5.1/MM5.1
Low Temperature Processed Amorphous Oxide Semiconductor Thin-film Transistors.
John Wager 1 , Ken Hoshino 1 , Layannah Feller 1 , Rick Presley 1
1 School of EECS, Oregon State University, Corvallis, Oregon, United States
Show AbstractAmorphous oxide semiconductor (AOS) thin-film transistors (TFTs) appear to be well positioned for near-term commercial entry into the flat-panel display market as a replacement for hydrogenated amorphous silicon TFTs. This application mandates a maximum process temperature of approximately 300-350 °C. Process constraints for future flexible display and flexible electronics products promise to be even more challenging, requiring a maximum temperature of ~150 °C, or even lower. The purpose of this presentation is to review our work on reduced temperature processing of AOS TFTs.
3:00 PM - F5.2/MM5.2
Solution-processed Aluminum Indium Oxide Thin-film Transistor with Low Temperature Annealing.
Young Hwan Hwang 1 , Seok-Jun Seo 1 , Jun-Hyuck Jeon 1 , Byeong-Soo Bae 1
1 Lab. Optical Materials & Coating (LOMC), Dept. of Materials Science & Engineering, KAIST, Daejeon Korea (the Republic of)
Show AbstractOxide semiconductor has plenty of advantages such as transparency due to their large bandgap, high electron conduction property, high uniformity in large-scale fabrication applications, and environmental stability. Thus, it is expected that oxide semiconductor do a significant role in many applications such as, flat-panel displays, flexible displays, radiofrequency identification tags, and smart windows. Typically, oxide TFTs have been fabricated using vacuum-process which enables low temperature process. Recently, solution-processed oxide TFTs get intensive attraction since they can be prepared by simple and low cost methods. However, its high annealing temperature restricts the use of the solution-processed oxide TFTs as an active layer in TFT applications. Previously we have reported the aluminum indium oxide (AIO) TFTs which can be prepared with relatively low temperature process. (i.e. 350 °C) [1] In this study, we have applied additional annealing for the purpose of decreasing the annealing temperature. The vacuum annealing, which is understood as an effective tool to remove the remaining organics inside the film and increase the carrier concentration, was adopted to increase the conductivity of the film. After the vacuum annealing, the film was annealed under oxygen surrounding to optimize the carrier concentration in the film and decrease the surface oxygen deficiency which is related to off current of the TFT for better TFT performance. All the annealing process was performed at the 200 °C and 250 °C, individually. The resultant AIO TFT annealed at 250 °C exhibits a channel mobility of 3.5 cm^2/Vs, a subthreshold slope of 0.6 V/dec, and an on-to-off current ratio of ~10^6. In addition, based on the results of low temperature annealing, solution-processed AIO TFT fabricated on the flexible substrate will be demonstrated.[1] Y.H. Hwang, J.H. Jeon, S. Seo, and B. Bae, “Solution-processed, high performance aluminum indium oxide thin-film transistors fabricated at low temperature”, Electrochem. Solid-State Lett. 12, H336 (2009).
3:15 PM - F5.3/MM5.3
ZnBeMgO Nanostructured Based UV Detectors by Spin Coating.
Neeraj Panwar 1 , Jose Liriano 1 , Ram Katiyar 1
1 Department of Physics, University of Puerto Rico, San Juan United States
Show AbstractThe detection of ultraviolet radiation is of prime importance in the field of space, environment and biological applications etc. ZnO is a direct band semiconductor having wurtzite hexagonal structure with a band gap Eg ~ 3.37 eV which can be easily tuned by alloying it with MgO (Eg= 7.5 eV) and BeO (Eg= 10.8 eV). By this approach, one can cover the deep UV range avoiding interference from the visible spectrum and these detectors can work in the harsh enviornment. Zn1-x-yBexMgyO films were prepared on sapphire (Al2O3) and Si substrates by novel spin coating method. Starting materials were dissolved in 2-methoxyethanol and monoethanolamine (MEA) used as solvent and stabilizer respectively. The molar concentration of the solutions was 0.5M. The solutions were coated on the substrates rotated with 3000rpm for 30s. The films were then dried at 300°C for 10 min for evaporating the solvents and removal of organic residuals. The effect of deposition steps, annealing temperature variation and variation in Be and Mg concentration at Zn-site have been carried out. It was identified that with 15 deposition steps and 15 and 20 at% of Be and Mg concentration and 450°C annealing temperature produce film with best properties. XRD patterns of the films revealed that the pristine film has a wurtzite type structure. However, the doped films exhibited the preferential c-axis orientation along (002) indicating that the c-axis of the grains becomes uniformly perpendicular to the substrate surface. No extra peaks corresponding to BeO or MgO could be noticed in the XRD patterns of the films. From the optical measurements it was observed that for the pristine ZnO film, the cutoff wavelength was 364nm which decreased to 320nm for Zn0.65Be0.15Mg0.20O film which lies in UV-B region. The dark current, photoresponsivity and other optical measurements have been carried out on the films with inter-digitated electrodes and the results will be presented in the meeting.
3:30 PM - F5.4/MM5.4
Synthesis of Morphologically Controlled ZnO Nanostructures and Spray Deposition of Hybrid ZnO/Ag Nanostructured Films for Transparent Conductor Applications.
Saahil Mehra 1 , Rodrigo Noriega 5 , Mark Christoforo 3 , Sujay Phadke 4 , Dietm