MRS Meetings and Events

 

EQ11.03.07 2022 MRS Spring Meeting

Vertically Stacked Memristor Configuration with Individual Half-Cell Tunability

When and Where

May 10, 2022
11:00am - 11:15am

Hawai'i Convention Center, Level 3, 318A

Presenter

Co-Author(s)

Vasileios Manouras1,Spyros Stathopoulos1,Themis Prodromakis1

University of Southampton1

Abstract

Vasileios Manouras1,Spyros Stathopoulos1,Themis Prodromakis1

University of Southampton1
Recent developments in resistive switching technologies have been focused on the fabrication and characterization of new memristor configurations in an attempt to combat sneak path problems and enhance the already attractive low consumption properties of memristors, while ensuring high number of states and configurability. We have developed a three terminal, double-stack memristor comprising of two fully working memristive half-cells. This device was fabricated using conventional photolithography techniques for patterning, followed by evaporation of electrodes or sputtering of metal oxide active material. The final device has a Metal-Insulator-Metal-Insulator-Metal material stack.<br/><br/>This configuration provides access to both half-cells, through the shared electrode in the middle of the stack, enabling fine tuning capabilities of the total device ,which can also be read as a single unit cell, by using the top and bottom electrodes to assess its state. Preliminary characterization results indicate an increase in tunability and memory capacity. The ability to control either one of the half-cells independently, as well as switch them simultaneously, improves controllability of the states screened when reading the entire cell. Moreover, simultaneous reset of both half-cells, due to application of voltage pulsing between the top and bottom electrodes , can lead to greatly reduced memory-erase power consumption. The additional memristor also functions as a tunable serial resistance for overvoltage protection, when the device is probed or switched as a single cell. Finally, this configuration enables in-depth testing of complementary and memristor-fuse theories by allowing separate forming of each half cell and the possibility to test multiple configurations of device materials, device types and device polarities.

Symposium Organizers

Yoeri van de Burgt, Technische Universiteit Eindhoven
Yiyang Li, University of Michigan
Francesca Santoro, Forschungszentrum Jülich/RWTH Aachen University
Ilia Valov, Research Center Juelich

Symposium Support

Bronze
Nextron Corporation

Publishing Alliance

MRS publishes with Springer Nature