SRC 2023 Microelectronic & Advanced Packaging Roadmap Panel—Student Poster Session

Matthew Bergschneider, University of Texas-Dallas—DFT Modeling of Atomic Layer Deposition of Ru Interconnect Metal for EUV Scaling

This work applies density functional theory (DFT) simulations to understand the underlying surface reaction mechanisms involved in the selective deposition of Ru metal for use in vias or interconnects. Ruthenium-ALD with bis-(ethylcyclopentadienyl)-ruthenium [Ru(EtCp)2] and O2 as reactants shows promising surface selectivity, but necessitates activation steps for desorption of ligands to complete each ALD cycle. DFT modeling of Ru(EtCp)2 on Ru surfaces reveals that ALD processes are limited by the strong aromatic-ring interaction with the metallic surface. Introduction of H2 as a nonoxidizing co-reactant gas in place of O2 can overcome these barriers by saturation of the Cp π-bonds, lessening the bonds to the metallic Ru surface. This study aims to provide a comprehensive understanding of leveraging ligand-surface, surface-hydrogen, and ligand-hydrogen interactions to achieve oxygen-free ALD with the Ru(EtCp)2 precursor at moderate-to-low temperatures.

Zhuoqi Cai, Georgia Tech—Investigating BEOL Interconnect Options in SRAM Cells at the 7nm Technology Node

Yuri Choe, University of Washington—High-throughput Reactor Design for Rapid Screening of Atomic Layer Deposition Processes

Jander Cruz, California State Northridge—Improving EUV Resist Uniformity using NP-SIMS

Using NP-SIMS, we explore influence of organic additives on the resulting uniformity of EUV resists. Systematic changes to the formulation of as cast films including the use of photodecomposable quenchers (benzoate and para-cyanobenzoate) and additive loading skews unveil ionic conditions that promote optimal molecular homogeniety-which can improve lithographic performance.

Vincent Flores, University of Illinois Urbana-Champaign—Low Temperature Chemical Vapor Deposition of SiNx Thin Films in Deep Features

Silicon nitride (SiNx) thin films have multiple applications in the manufacturing of microelectronic devices, ranging from gate dielectrics to encapsulation layers and diffusion barriers. The back-end applications of SiNx films include etch stop layers, conformal spacers, and seamless gapfill of trenches or vias. These applications impose strict requirements on the growth process and film quality: SiNx films must be deposited at temperatures below 400 °C to avoid device degradation caused by interfacial reactions, and in many applications the films must be grown conformally. Essentially all existing processes to grow SiNx films use ammonia or dinitrogen as the nitrogen source, and thus growth requires the cleavage of either N-H or N≡N bonds; these bonds have high thermochemical bond dissociation energies, which likely are responsible for the relatively high onset temperatures for film growth. To develop improved methods to achieve the conformal and superconformal growth of SiNx at low temperatures, we are developing a new class of precursors for SiNx films that do not require the cleavage of N-H or N≡N bonds. One of these precursors, 1,3-di-tert-butyl-2,2-diazido-1,3-diaza-2-silacyclopent-4-ene, is a colorless, distillable liquid that can be synthesized reproducibly and in good yield. Thermogravimetric analyses and shock tests show that this diazidosilane precursor is safe to handle. We will present details of the synthesis and characterization of this new precursor, and preliminary CVD screening experiments conducted toward the growth of SiNx films.

The low melting temperature of eutectic Sn-Bi alloys (139°C) makes eutectic Sn-Bi a suitable low-temperature alternative to high-Sn, lead-free solders in electronics packaging. The low eutectic temperature allows for a peak reflow temperature of 180°C rather than the 240°C reflow temperature required for Sn-Ag-Cu (SAC) alloys. Lower reflow temperatures reduce warpage-induced solder joint defects. However, the strain-rate sensitivity of Sn-Bi alloys results in poor drop-shock performance despite having high reliability in thermal cycling. The literature shows evidence in bulk solders that microalloying with Sb and Ag can improve ductility and mitigate the strain-rate sensitivity of Sn-Bi alloys. Improved ductility and a low strain-rate sensitivity are known to enhance drop-shock performance and create a more reliable joint. In this presentation, we will compare the bulk microstructures of eutectic Sn-Bi with Sb and Ag additions to the microstructure in solder joints on Cu and ENIG (electroless nickel immersion-gold) substrates. Our results demonstrate how small changes in composition due to dissolution from the substrates make the microstructure more heterogeneous and how those changes impact the mechanical properties of Sn-Bi solder joints.

Melisa Gulseren, University of California-Davis—Merging Metasurfaces and Nanomechanical Resonators for IR Sensing

This paper describes our recent efforts to integrate efficient metamaterial absorbers with radiofrequency (RF) nano/micro-electromechanical systems (NMEMS) to achieve spectrally selective sensing in the infrared (IR) frequency band. The devices will be applied to detect structurally unique components with distinctive infrared spectral fingerprints, such as gases or metabolites. The design is composed of an ultrathin metasurface made of subwavelength nanoresonators able to absorb IR light with desired wavelength. The ultrathin nature of such design allows an easy integration with NMEMS resonators to simultaneously achieve tailored optical and electromechanical properties. The proposed approach permits to quickly translate targeted IR light into a DC voltage. We have analyzed, designed, fabricated, and measured metal-insulator-metal (MIM) based metasurfaces and demonstrated optical lithography for metasurface patterning to improve scalability and repeatability of the proposed sensors to enable fabrication in a large scale. 

Zhouhang Jiang, RIT—A Sloshing Bathtub Model for Endurance Degradation in Ferroelectric FET 

In this work, we performed a comprehensive experimental and modeling study of the endurance cycling degradation in ferroelectric FET (FeFET) and proposed a sloshing bathtub model for endurance degradation. We show that: i) polarization (PFE) switching is the main source of cycling degradation as demonstrated by severe degradation during the bipolar cycling with PFE switching pulses while much less degradation without PFE switching; ii) under grounded S/D write scheme (float S/D write scheme), endurance degradation is initiated by electron injection from channel (gate) side during positive (negative) half-cycle and electron movement through the ferroelectric (FE) bulk during negative (positive) half-cycle, respectively; iii) once FE bulk defects are fully charged up, electrons pile up at the FE/interlayer (FE/IL) interface, resulting in a steep VTH increase; iv) a sloshing bathtub model is proposed to explain the endurance degradation and can reproduce observed data.

Chetan Jois, Purdue University—Phase Field Simulations and Experimental Observation of Void Evolution in Solder in Microbumps under Thermal Aging

One of the significant reliability challenges to microbumps in heterogeneously integrated packages is void evolution in the solder volume accompanied by the formation of Cu-Sn intermetallic along the Cu pillar sidewalls on thermal aging at high temperatures. In this study, a reaction-diffusion mechanism accounting for surface diffusion in addition to bulk diffusion, is proposed to explain the solder voiding and intermetallic growth. The void evolution, and intermetallic formation which drives the voiding, are then simulated using the phase-field method. Simulations of void evolution are performed for bumps of different sizes, and the increase in resistance is estimated for different solder bump sizes. The voiding is also experimentally characterized using a novel test device which consists of multiple sub-30 µm pitch Cu-Sn-Cu junctions directly observable under a Scanning Electron Microscope. The simulations in this study are validated by comparing the voiding rate and void pattern observed experimentally.

Chih-Yu Lee, University of Maryland, College Park—Combinatorial Investigation of Phase Change Materials Guided by Machine Learning

Ge-Sb-Te (GST) has been widely studied as phase change materials (PCM) due to its ability for fast and reversible switching between amorphous and crystalline states. With its non-volatile and multi-level characteristics, it has great potentials for novel memory and computing applications. Through combinatorial thin film deposition, we investigate a wide composition range within the GST ternary system. We quantitatively evaluate the relationship among structure, composition and functional properties in electrical (resistance and resistance drift) and optical (refractive index and permittivity) domains using various machine learning and data-visualization tools. Previously, we have identified Ge4Sb6Te7 as a new high-performance composition with properties better than those of Ge2Sb2Te5 [1,2]. In this study, we demonstrate optimizing multiple properties (crystallization temperature and bandgap) at the same time through multi-objective optimization. This work was supported by SRC nCore IMPACT and ONR MURI.

Mohamadali Malakoutian, Stanford—400°C-Grown Diamond Heat Spreader for Post-Device Integration

The ever-increasing power requirements for various electronic applications, including 5G/6G, make thermal management in devices critical. Joule heating in the device channel due to increased power causes performance degradation and premature failure. These effects can be mitigated by increasing the heat transfer coefficient to the heat-sink through a thermally conductive material such as diamond. Integration of diamond to the top of a device, which is in close proximity to the channel, can be achieved through direct chemical vapor deposition. This can be done before or after device fabrication; however, we have chosen a device-first approach to remove device fabrication challenges. Since post-fabrication diamond growth at normal temperatures (>650°C) increases the chance of gate dielectric failure and higher leakage current, a lower-temperature growth technique <400°C was developed for our device-first approach. At temperatures <500°C, the original gas mixture (H2 and CH4) resulted in a more soot-like carbon with significantly lower sp3 incorporation. Through this study, we were able to achieve high-quality and high-grade crystalline diamond growth at 400°C by adding oxygen species. During low temperature growth, oxygen incorporation was necessary for sp2 carbon etching, which was originally achieved through high-temperature H2-plasma during >650°C growth. Supporting Raman measurements of the <400℃ grown diamond showed a strong sp3 peak with a small FWHM (~6 cm-1) and a weak sp2 peak similar to that of >650°C growth.

Madison Manley, Georgia Tech—Cobalt Atomic Layer Deposition for Chip to Wafer Heterogeneous Integration and Bonding

To improve the performance and energy of electronics, there is a need for tighter integration to minimize electrical interconnect delays and energy. Unfortunately, there is a slowdown in traditional device scaling for nanoscale CMOS technology as on-chip interconnects parasistics are becoming dominant with device scaling. Therefore, there is a growing interest in 3D heterogeneous integration technologies due to their dense interconnections between chips and low latency and power consumption. In this work, we will demonstrate a 3D integration technology that enables ultra-dense input/output (I/O) bonding to approach on-chip via densities using cobalt selective atomic layer deposition (Co ALD). The goal is to demonstrate an array of chiplets simultaneously 'bonded' to a wafer using gas phase selective deposition of the I/O interconnect bonds onto the aligned copper pads. The paper will reports the experimental results of test beds containing Cu/Gap/Cu lateral and vertical test structures; the gap sizes range from 50 nm – 200 nm and pitches range is 1µm – 10µm. The results show the feasibility of using selective Co ALD as high-density Cu-Cu interconnect bonding. SEM and XPS are used to characterize the testbed before and after Co deposition and to measure the selectivity of Co ALD on the Cu and Si3N4 substrate. The Co ALD chip-to-wafer bonding process does not require an external mechanical force or extreme chemical mechanical polishing (CMP) and surface cleanliness. In addition, the Co ALD process has exceptional film thickness controllability at the angstrom range which provides the potential to aggressively shrink the Cu I/O pitch to sub-micron. 

Hannah Margavio, North Carolina State State—Low Temperature Area Selective Deposition via Simultaneous Deposition and Etching

One source of inefficient power use in semiconductor devices is nano-scale pattern misalignment, which can lead to excess resistance, open circuits, and electrical shorts. Mitigating inefficient energy use in devices requires development and integration of self-aligned bottom-up patterning techniques such as area selective deposition (ASD). In this study, we use thick TiO2/Si line space patterns to demonstrate thick W ASD via simultaneous deposition and etching. We find that the selectivity of W deposition on Si-H versus TiO2 can be controlled by manipulating the TiO2 etch rate. Slower TiO2 etching can be induced by lowering the processing temperature to 220oC and leads to highly selective W growth. Fast TiO2 etching at 280oC causes enhanced surface roughening of the etch feature and leads to selectivity loss by unpurged deposition precursors. The present ASD mechanism extends to other interconnect materials including Mo. In situ quartz crystal microbalance studies show that 10 cycles of MoF6 and SiH4 at 180oC lead to linear mass gain on an Al2O3 surface and linear mass loss, corresponding to Mo ALD and TiO2 CVE, respectively. Exposing TiO2/Si line space patterns 5 cycles of MoF6/SiH4 at 180oC deposits 9 nm of Mo in the Si regions removes 5 nm of TiO2 as confirmed by STEM EDS elemental mapping.

Geng Ni, University of Texas, Arlington—Mechanism of Alloying Elements Affecting the Rate of Electromigration of Sn Based Solder Interconnects

Alloy element effect on electromigration reliabiliry of Sn is studied by Cross-strip samples. In conclusion, effect of alloy element on electromigration (EM) reliability of Sn based solder is investigated. Alloying can be most beneficial when the element exists as IMC phase (two-phase equilibrium effect). Ands some elements (e.g Ag and Cu) may increase EM rate when in dilute concentration.

Persi Panariti, Illinois Institute of Technology—New Oxidants for ALE of Cu Probed by X-Ray Absorption Spectroscopy

Atomic Layer Etching (ALE) is a relatively new technique for subtractive semiconductor fabrication. Proof-of-concept demonstrations are impressive, yet ALE has not been widely adopted. Current ALE uses harsh chemistry (e.g. halogens or plasma, etc.) that damages structures or induces high temperature mobility of the ALE metal. Both issues plague the ALE of copper. However, successful and scalable Cu ALE provides new avenues to high aspect ratio structures, selective Cu ALD (via intermittent back-etch of to improve selectivity) and other uses. Understanding of the oxidation (activation) of metallic Cu surfaces and the removal of those activated Cu species is a high-value target for ALE.

Chinmoy Nath Saha, University at Buffalo—Temperature-Dependent Pulsed IV and RF Performance of  β-(Alx Ga1-x)2O3/Ga2O3 hetero-structure FET (HFET) with ex-situ passivation

This presentation reports b-(AlxGa1-x)2O3/Ga2O3 (AlGaO/GaO) heterostructure FETs (HFETs) with improvement of peak transconductance (gm), current gain (fT) and power gain (fMAX) cutoff frequencies. Highly scaled transistors (gate lengths of 160-200 nm) were fabricated with self-aligned source/drain regrowth, scaled source access lengths. The fabricated HFETs show an enhancement-mode operation with record high trans-conductance of 80 mS/mm among b-Ga2O3 devices and a peak current density of 74 mA/mm. Small signal measurements show fT and fmax of 30 and 37 GHz respectively at 10 V drain voltage with record  fT.LG product 4.8 GHz-mm . While the cutoff frequencies are highest to date among b-Ga2O3 FETs, they are limited by high source resistance at the regrowth interface. We also report a study of the temperature-dependent pulsed current voltage (IV) and RF characterization before and after silicon nitride (Si3N4) passivation. A moderate DC-RF dispersion (current collapse) is observed before passivation in gate lag measurements at sub-microsecond pulsing. The dispersion in the gate lag is possibly attributed to the interface traps in the gate-drain access region. Temperature dependent RF measurements up to 250 0C do not show degradation in the cutoff frequencies. The current collapse is eliminated after Si3N4 passivation. At 200 ns pulse widths, a 50% higher current is observed compared to DC at high drain voltages. RF performance of the passivated devices do not show degradation at room temperature and high temperature. These results show that ex-situ deposited Si3N4 is a potential candidate for passivation of b-(AlxGa1-x)2O3/Ga2O3 HFETs for future RF applications.

Balreen Saini, Stanford—Phase Evolution in Hf0.5Zr0.5O2 Films during Rapid Thermal Annealing: An In-Situ X-ray Diffraction Study

Ferroelectric (FE) HfO2-based thin films have attracted considerable attention for their applications in memory devices such as 1T1C FE random-access-memory (FeRAM) and FE field-effect-transistor (FeFET) owing to their dimensional scalability and compatibility with CMOS process flows. It is known that a suitable capping layer is essential for the FE phase formation of the as-deposited amorphous HfO2 films through post-metal deposition rapid thermal anneal (RTA). In this work, we attempt to visualize the FE phase formation in PE-ALD deposited initially amorphous Hf0.5Zr0.5O2 (HZO) thin films during RTA in-situ using synchrotron X-rays at low angles of incidence. We study multiple samples with/without top or bottom TiN electrode. All films first crystallize into orthorhombic (O-) or tetragonal (T-) phase as noted by the appearance of a diffraction peak matching both O(111) and T(101) reflections. For films without a top electrode, irrespective of having a bottom electrode TiN, the initial O- or T-phase peak decreases in intensity and the monoclinic M(11-1) reflection peak evolves and becomes the dominant peak. We hypothesize a O-/T- phase distortion into M-phase, possibly due to an in-plain strain, can lead to this observation. Electrical measurements are performed to confirm the FE O-phase presence in samples with top electrode. 

Kidae Shin, Yale—Tuning Capacitance – Voltage Hysteresis in a Monolayer Ferroelectric ZrO2 on Si (001)

A single atomic layer of ZrO2 on Si (001) has been reported to exhibit ferroelectric switching behavior. Being at the ultimate thickness limit of a monolayer (ML), this system has the potential advantage of aggressively scaling down device size. Based on density functional theory (DFT) calculations that attribute the polarization switching to displacements of Zr-O dipoles, we aim to control the magnitude of capacitance – voltage hysteresis by tuning the density of Zr-O dipoles in the ML ZrO2 film. In this talk, we report how this goal could be achieved through a combination of molecular beam epitaxy (MBE), x-ray photoelectron spectroscopy (XPS) and capacitance – voltage (C-V) measurements. Specifically, the film annealing conditions were tuned to control the density of Zr-O dipoles, and the variation in the density of Zr-O dipoles was confirmed by the XPS measurements of Zr 3d states. The C-V measurements of the ML ZrO2 films with varying density of Zr-O dipoles show that the magnitude of the hysteresis is proportional to the density of Zr-O dipoles.

Tian Sun, University of Notre Dame—Improved Growth of Low-Temperature GaN for BEOL Technologies By Growth-Anneal Strategies

GaN is an ideal candidate for BEOL access transistors due to its intrinsic properties of high electron mobility and large bandgap. However, high quality crystalline GaN is always grown at temperatures higher than the BEOL-compatible range. GaN grown at 450 °C by reducing the growth temperature of the conventional 2-step strategies can be made, but the crystalline films typically have very poor mobilities, due to the presence of many defects and relatively poor crystallinity. In this work, we demonstrate the growth of GaN at BEOL-compatible temperatures by MOCVD with electrical properties nearing those necessary for access transistors. By manipulating the V/III ratio of the precursors, we were able to obtain amorphous GaN with increased mobility and a significantly reduced carrier concentration comparable to crystalline GaN grown at 725 °C.  The electrical properties can be further improved by growth-anneal cycling strategies and laser annealing, resulting in mobilities ~15 cm2/V-s under BEOL constraints.

Ashita Victor, Georgia Tech—Reconstituted SiO2 Tier with Integrated Copper Heat Spreader

Jiadi Zhu, Massachusetts Institute of Technology—Highly-scaled, High-performance Transistors based on Wafer-scale Monolayer MoS2

In the past decades, the microelectronics has been rapidly developed and has confronted with may problems. We will not only need devices with higher performance and higher integration density at the front-end-of-line to continue the scaling and enables more powerful integrated circuits, but also need devices that can introduce more functionalities at the back-end-of-line. In both cases, devices based on low-dimensional materials, especially 2D materials, can be a very promising candidate, due to their low-leakage current, high-mobility and atom-level thickness.