1:30 PM - EP11.5.01
Tomographic Filament Observation and Scaling Projection of RRAM in 3 x 3 nm Dimension
Umberto Celano 2,Yi Hou 3,Ludovic Goux 1,Andrea Fantini 1,Robin Degraeve 1,Olivier Richard 1,Hugo Bender 1,Malgorzata Jurczak 1,Wilfried Vandervorst 2
1 IMEC Leuven Belgium,2 Department of Physics and Astronomy KU Leuven Leuven Belgium,3 Peking University Beijing China1 IMEC Leuven BelgiumShow Abstract
Oxide-based resistive switching memory (RRAM) is considered as a valuable non-volatile storage technology, because it offers fast switching, high endurance and good scalability [1,2]. RRAM operation relies on the resistance modulation of a conductive filament (CF). The CF is considered as a reversible local valence-change in the oxide (insulator) of a metal-insulator-metal structure [1-3]. While the usage of CMOS-friendly materials have paved the way to the sub-1X node integration for RRAM , the filament observation is still a challenge, and assessing the ultimate scaling-capability of resistive switching (RS) is hampered by lithography. In this work we experimentally observe in three-dimension (3D) the CF in bipolar oxide-based RRAM. This is enabled by scalpel C-AFM, which collects C-AFM images of the conductive filament at different depths leading to a full 3D-characterization of the conductive volumes. Due to the role of the oxygen vacancies (Vo) in defining the composition of the CF and its conductive properties, scalpel C-AFM is carried out in high vacuum (10-5 mbar) in order to minimize the interaction of the CF with the oxygen in the ambient. Next, by exploiting the modulation of the contact area of an AFM-tip we demonstrate resistive switching in a device as small as 3 x 3 nm. Finally, by statistical analysis of RS in 3 x 3 nm devices together with the shape of CFs, we demonstrate that the modes of operation observed, can be related to the number of defects contained in the CF and modelled through a low-defects assisted quantum-point-contact (QPC). Our observations physically explain the sub-10nm operation of RRAMs and provide strong evidences that the CF behaves as a defect modulated quantum point contact. Our results indicate possible scalability for the RS mechanism in the ~ 10 nm2 regime.
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 U. Celano et al., Nano Lett. 2014, 14, 2401–2406.
2:30 PM - *EP11.5.04
2D Electrolytes for the Development of 2D Crystal Memory
Susan Fullerton 2,Ke Xu 1,Hao Lu 2,Weihua Wang 3,Hanchul Kim 3,Iljo Kwak 4,Kyeongjae Cho 3,Andrew Kummel 4,Alan Seabaugh 2
1 Department of Chemical and Petroleum Engineering University of Pittsburgh Pittsburgh United States,2 Department of Electrical Engineering University of Notre Dame Notre Dame United States,1 Department of Chemical and Petroleum Engineering University of Pittsburgh Pittsburgh United States2 Department of Electrical Engineering University of Notre Dame Notre Dame United States3 Department of Materials Science and Engineering University of Texas at Dallas Richardson United States4 Department of Chemistry University of California, San Diego La Jolla United StatesShow Abstract
A new approach to memory will be presented that relies on the electrostatic gating of 2D crystals using lithium ions. Specifically, the development of a 2D electrolyte based on cobalt crown ether phthalocyanine (CoCrPc) will be emphasized, and the first device results will be presented. The proposed design for the memory device consists of two, 2D crystal layers, such as graphene or MoS2, separated by a 2D electrolyte. Source and drain contacts, deposited on the top 2D crystal layer, are used to detect the resistance of the channel, which is modulated by the presence or absence of Li+ at the surface. When Li+ is near the channel, image charge is induced in the channel resulting in a low resistance (1) state, and when the Li+ is moved away from the channel via a gate, the channel is switched to the high resistance (0) state. Li+ will be toggled back and forth between energetically favorable sites within the crown ethers of the CoCrPc molecule to create the two states. Density functional theory calculations indicate that induced charge on one or the other of the electrodes will modulate the energy barrier encountered by the ions, making fast switching (~ 1 ns) and long retention (> 1 year) possible. Unlike resistive random access memory (RRAM), where conductive filaments are formed and broken to create the 0 and 1 states, this memory concept relies on the physisorption of ions to the 2D crystal and there is no charge exchange. We have demonstrated the solution-phase deposition of an ordered monolayer of CoCrPc on graphene. Li+ is introduced to the crowns of the CoCrPc by exposure to a solution of LiClO4 and solvent, followed by annealing. To explore the electronic properties of this 2D electrolyte, a simplified device has been fabricated: a backgated graphene field-effect transistor covered with a monolayer of CoCrPc:LiClO4. Initial current-voltage measurements indicate that the backgate can be used to pull Li+ to the channel surface, inducing n-type doping with sheet carrier densities of ~ 4 x1012 cm-2. While this state can be retained for the duration of the measurement (~ minutes), the ion response to the backgate is slower than predicted, and may include both a fast and a slow contribution. Efforts are currently underway to understand the materials properties that are limiting the switching speed, and longer retention measurements are planned.
This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of six SRC STARnet Centers, sponsored by MARCO and DARPA, and NSF grant #ECCS-GOALI-1408425.
8:00 PM - EP11.6.01
Tuning Stoichiometry in Atomic Layer Deposited NiOx by Changing Deposition Temperature
Raisul Islam 1,Nobi Fuchigami 2,Pranav Ramesh 1,Donovan Lee 2,Karl Littau 2,Kurt Weiner 2,Krishna Saraswat 1
1 Electrical Engineering Stanford University Stanford United States,2 Intermolecular Inc. San Jose United StatesShow Abstract
Nickel Oxide (NiOx), with its p-type behavior and nickel-vacancy controlled conductivity, is a promising electronic material for non-volatile memory, logic and photovoltaic device applications. In ReRAM devices, it has shown low voltage operation and fast programming. In solar cells, its low valence band offset and high conduction band offset with Si make it a good candidate for hole-selective, electron-blocking contacts.
Recently Ni amidinate (Bis(N,N’-di-t-butylacetamidinato) nickel(II)) has been shown to be a stable metal-organic compound suitable for ALD deposition of different Ni compounds such as metallic Ni, NiNx, NiOx etc. In this work, we present a detailed recipe optimization of ALD NiOx. We present stoichiometry control by changing the deposition temperature. We observe that very close-to-stoichiometric films can be deposited using the optimized recipe. However, the films show some over-stoichiometry (x>1), which is the main source of p type conduction in NiO.
NiOx was deposited using alternating pulses of Ni amidinate precursor and ozone in an Intermolecular Tempus A-30 ALD system. The precursor temperature was varied from 80 °C to 120 °C and the substrate temperature was varied from 150 °C to 280 °C. The deposition rates, film crystallinity, and film stoichiometry were determined using X-ray reflectivity (XRR), X-ray diffraction (XRD) and X-ray photoemission spectroscopy (XPS) respectively. Strong ALD behavior is observed from 150 °C – 200 °C. In this ALD temperature window the growth rate as a function of precursor pulse time saturated quickly, and the film non-uniformity across a 300 mm wafer was
8:00 PM - EP11.6.02
Evaluation of Dynamic Negative Capacitance Ferroelectric MOSFET Characteristics for Low Power Circuit Application
Yang Li 2,Yong Lian 1,Kui Yao 2,Ganesh Samudra 1
1 National Univ of Singapore Singapore Singapore,2 Institute of Materials Research and Engineering. A*STAR (Agency for Science, Technology and Research) Singapore Singapore,1 National Univ of Singapore Singapore Singapore2 Institute of Materials Research and Engineering. A*STAR (Agency for Science, Technology and Research) Singapore SingaporeShow Abstract
Due to negative capacitance (NC) effect, ferroelectric MOSFET (FeFET) has been investigated as a next generation low power logic device. Reported simulations based on Landau theory on static response show FeFET plausibly outperforms intrinsic MOSFET with subthreshold swing (SS) K of ferroelectric, determined by the energy barrier in the middle of the double well potential which governs neighboring dipole switching. It prolongs the switching time beyond 1ns, making it larger than the rise/fall time of integrated circuits (< 1 ns). The static model does not capture this effect, leading to disagreement with the measured FeFET characteristics.
Based on Landau-Khalatnikov theory with damping effect, dynamic characteristics of FeFET are evaluated. Key model parameters are extracted from experimental results. The negative capacitance induced SS enhancement only manifests when operation frequency is below a few of MHz. At high frequency, due to the large K, polarization lags the time evolution of electric field and its magnitude gets smaller. For transient response as a switch, if the rise/fall time of gate voltage is 1 us, sub-60 mV/dec SS does not occur during forward switching but only during backward one. There is always a hysteresis loop generated in IDS-VG relationship, consistent with the measurements. Furthermore, transient response of the inverter consisting of n- and p-channel FeFETs is simulated for the first time. It shows that the dynamic voltage transfer curve has a larger noise margin, but its short circuit switching power is much higher than the static prediction. This issue severely hinders the use of FeFET to solve heat dissipation problem on chip beyond Si-CMOS technology. Finally, for different K, the maximum operation frequency at which electric characteristics of dynamic and static FeFETs are the same is worked out. It clearly shows that novel ferroelectric materials with low K must be realized to practically utilize FeFET advantages for high speed circuit application.
8:00 PM - EP11.6.03
Activation Ratio of Heavily Phosphorus Doped Silicon with a New Factor
Minhyeong Lee 1,Sun-Wook Kim 1,Eunjung Ko 1,Hyunchul Jang 1,Daehong Ko 1
1 Yonsei Univ Seoul Korea (the Republic of),Show Abstract
As a promising candidate for the next generation transistors, heavily phosphorus doped silicon has been studied to enhance the electron mobility and reduce the source/drain contact resistance. It is very important to analysis the density of electrically activated phosphorus for low resistance. However, there have been few fundamental studies on the activation ratio of phosphorus doped silicon.
In this study, we investigated electrical properties of phosphorus doped silicon epitaxial film. In order to obtain information of phosphorus atoms which were electrically active, sheet resistance measurement and Hall Effect measurement were conducted. Additionally, phosphorus dopant concentration was characterized by secondary ion mass spectroscopy (SIMS) depth profile experiments.
Based on the probability function of electrons occupying the donor state, we studied the activation ratio of phosphorus atom. By introducing a new factor which is called a degeneracy factor, we calculated the activation ratio as a function of phosphorus concentration within Si:P thin films. By using the equation with this factor, the density of electrically activated phosphorus could be easily estimated.
8:00 PM - EP11.6.04
Fabrication of Porous Layer-by-Layer Materials as Low-k Dielectrics for Electronic Interconnects
Daekyun Jeong 1,Jiwon Lee 1,Jaegab Lee 1
1 Kookmin University Seoul Korea (the Republic of),Show Abstract
As the device is scaled down, low-k dielectric material is needed to improve the semiconductor device performances. In the existing process, the dielectric constant of the low-k dielectric layer with high density is the same value of the entire layer. So the dielectric constant is adjusted through the variation of the deposited material. But it is very difficult to make low-k dielectrics by itself. On the other hands, air gap process is used for low-k property. But it is vulnerable to physical damage because the support layer does not exist. So when the Cu inside TSV is inflated in post annealing process, damages such as projection and crack on side wall barrier layer may be increased due to the expansion and protrusion.
In this work, to obtain lower dielectric constant, porous polymer layers with various pore size and/or pore density were used by self-assembled Layer-by-Layer condition. To solve these problems, the LbL flexible layer deposition was used to make low-k dielectrics. LbL layer is formed by stacking with PAH (polyallylamine hydrochloride), and PSS (polystyrene sulfonate) which have nano scale pores. As the control of pH condition, pore size and density in multiple layers of PAH / PSS are changed. In addition, contraction by utilizing elasticity by use of the porous layer and expansion can be adjusted and recovered.
8:00 PM - EP11.6.05
The Study of Random Dopant Fluctuation (RDF) Effects for Varying Fin Height on 10-nm n-Type Si FinFET
Changho Shin 1,Hyun-Yong Yu 1
1 Korea Univ Seoul Korea (the Republic of),Show Abstract
Silicon complementary metal oxide semiconductor (CMOS) devices have been continuously scaled down according to Moore’s law. As the device is downsized, short channel effects (SCEs) have been emerged as a major issue. In order to improve SCEs, FinFETs substituted conventional planar MOSFETs these days. Also, to obtain a high drain saturation current (Id,sat), have been increased the height of fin by the industry. In sub-10-nm CMOS technologies, process-induced threshold voltage (Vth) variation is a serious issue because it degrades device reliability. As the total channel volume in the device is reduced, Vth variation in the source/drain (S/D) region due to random dopant fluctuation (RDF) becomes larger than Vth variation caused by other factors such as line-edge roughness and work-function variation.
Several research groups have suggested metal-interlayer-semiconductor (M-I-S) structure instead of traditional metal-semiconductor (M-S) structure to obtain better performances of devices by lowing the contact resistivity in n-type Si MOSFET. We have demonstrated that M-I-S S/D structure can induce the reduction of RDF effect in 10 nm technology of n-type Si FinFETs by using TCAD simulation. The M-I-S structure will efficiently suppress RDF effect because S/D doping concentration can be lowered by using the structure with maintaining other electrical performances of FinFETs.
In summary, we have demonstrated the impact of varying fin height on 10-nm n-type Si FinFET using TCAD simulation. When the fin height is higher, Vth variation becomes small, Id,sat is increased in M-S structure having a 5 × 1020 cm-3 S/D doping concentration [i.e., Id,sat = 1063 μA/μm, σ(Vth) = 11.19 mV for fin height of 9.2 nm and Id,sat = 1121 μA/μm, σ(Vth) = 9.277 mV for fin height of 25.725 nm]. However, in the case of 5 × 1019 cm-3 S/D doping concentration, When the fin height is higher, Vth variation becomes small, Id,sat does not increase [i.e., Id,sat = 57 μA/μm, σ(Vth) = 6.777 mV for fin height of 9.2 nm and Id,sat = 58 μA/μm, σ(Vth) = 4.321 mV for fin height of 25.725 nm]. In order to solve the trade-off between σ(Vth) and Id,sat, We using M-I-S S/D structure having a lower contact resistivity. Compared to the shorter fin of 9.2 nm with M-S S/D structure having a 5 × 1020 cm-3 S/D doping concentration, the taller fin of 25.725 nm with M-I-S structure having a 5 × 1019 cm-3 S/D doping concentration provide ~ 1.69 × increase in Id,sat with ~ 0.42 × reduce Vth variation of RDF effects [i.e., Id,sat = 493 μA/μm, σ(Vth) = 11.19 mV for fin height of 9.2 nm and Id,sat = 835 μA/μm, σ(Vth) = 4.729 mV for fin height of 25.725 nm]. Further study on the fin height will be required to improve the device performance with reducing RDF-induced Vth variation.
8:00 PM - EP11.6.06
Electrical and Optical Characterization of Si1-xGex Layers Grown by RF-PECVD
Ghada Dushaq 1,Mahmoud Rasras 1,Ammar Nayfeh 1
1 Masdar Institute Abu Dhabi United Arab Emirates,Show Abstract
Growth of high quality Si1-xGex layers on Si has a lot of interest due to the excellent optical and electrical properties of Si1-xGex . From an optical perspective SiGe has high index of refraction, low optical dispersion, and the possibility to tune the silicon physical properties and reduce the band gap by controlling Ge content which makes it very useful for photo-detectors application. Furthermore, the bulk hole and electron mobility of Ge are approximately four and two times higher than conventional Si channel, respectively, which makes it an excellent candidate for the next generation of high mobility channel devices. The challenge is the lattice mismatch between Ge and Si which results in threading dislocations. Several techniques have been adopted to deposit Ge and SiGe thin-films on crystalline Si. For instance encompassed radio-frequency (rf) or magnetron co-sputtering, ion implementation, oxidizing of SiGe, MHAH by CVD, and plasma enhanced chemical vapor deposition (PECVD) Have been used. In our work rf-PECVD is used to grow SiGe thin films on silicon. PECVD method offers an excellent step coverage characteristic, low deposition temperature and it is suitable for growing of multilayers with differing SiGe composition.
In the present work we investigate the structural, electrical and optical properties of the rf-PECVD grown Si1-xGex on Si. In the experiment, three samples with different SiH4/GeH4 gas ratios (0.2/1.0,0.5/1.0 and 1.0/1.0 SiH4/GeH4) are grown on p-type Si < 100> substrate with a resistivity of 0.02Ω at 650°C and 800mtorr. High-Resolution Scanning Electron Microscopy cross section images of the samples show a ~ 400nm thin film of SiGe in 0.2/1.0 and 0.5/1.0 samples. However when an equal amount of gases are used island formation appears and the growth is in Volmer-Weber (VW) mode. The absorption spectrum and the index of refraction data of the three samples are extracted from UV/VIS/NIR spectrophotometer and ellipsometery, respectively.
Using the PECVD 400nm Si1-xGex layers, MOS capacitors were fabricated. The SiGe thin film is cleaned with HF and passivated with ~1.6nm of SiN to enhance the surface termination and restrict the diffusion of Ge to the gate oxide. After this, Atomic Layer Deposition (ALD) is used to deposit 8nm of Hafnium oxide (HfO2) as the gate oxide. Finally, 360nm of Al is deposited using e-beam evaporator through a shadow mask to define the gates. The Capacitance-Voltage (C-V) measurements of the structure carried out at 1MHz shows a typical high frequency response. This indicates the quality of interfaces and the Si1-xGex layer. Moreover, the results show that SiGe layers grown by rf-PECVD are attractive for future electronic and photonic applications.
8:00 PM - EP11.6.07
The Metal-Interlayer-Semiconductor Source/Drain with Contact Metal of Tantalum Nitride (TaN) for 7 nm n-type Ge FinFET
Ahn Juhan 1,Hyun-Yong Yu 1
1 Korea Univ. Seoul, Korea Korea (the Republic of),Show Abstract
Germanium (Ge) is regarded as the most promising material to resolve the difficulty of scaling down of silicon (Si) based devices because it has high carrier mobility for both electron and hole, and it is highly compatible with Si CMOS technology process. However, regardless of the characteristic benefits of Ge, it has severe drawback in terms of contact resistivity at the source/drain(S/D) region because of its large density of gap-state which induces Fermi-level pinning closer to the valence band edge. In order to lower contact resistivity, prospective technique of inserting interfacial layer between metal and semiconductor region known for metal-interfacial layer-semiconductor (M-I-S) structure has been suggested to improve contact resistivity in recent studies. In this structure, some metals with low workfunction are mainly suggested for contact metal in many researches: representatively, Ti or Al. In fabrication process, however, most metals might not be compatible owing to high processing temperature. For that reason, it is demanded that some materials should substitute pure metals that can endure at very high temperature. Metal nitride such as tantalum nitride (TaN) can be the great alternative since they already have used for high-k metal gate, moreover it has great temperature stability and lower workfunction value than Ti. By using TaN as a contact material, despite of getting affordable specific contact resistivity (SCR) values by the TaN/undoped-ZnO/n+-Ge (mostly lower than Ti/undoped-ZnO/n+-Ge), this offers variations in SCR and drive current of devices. It is because TaN has some grain orientations with three workfunction values, which means an average workfunction value over an area varies due to a distribution ratio of orientations. To overcome this, TaN/doped-ZnO/n+-Ge was suggested because interlayer doping enables alleviation of SCR variation by increasing electron-tunneling probability at a TaN/ZnO interface so that can ignore Schottky barrier height at the interface, consequently, make devices reliable and SCR could also be improved.
We extracted the metal workfunction induced SCR variation by physics-based calculation model for 500 times of simulation and successfully analyzed the method for reducing variations by adopting heavily doped interlayer. Average SCR values are sufficiently compatible compared to Ti used M-I-S (~3*10^-8 Ω*cm2 and ~1*10^-9 Ω*cm2 for undoped and doped case.) The SCR value ratios between maximum and minimum are drastically reduced from ~x50 to ~x3 by interlayer doping. Furthermore, we identified device performance on the basis of extracted SCR data in n-type Ge based 7 nm FinFET by TCAD.
In conclusion, we investigated advantages of using TaN as a contact material in M-I-S S/D structure. TaN can be the great alternative of pure metal in M-I-S S/D, and the structure of metal nitride introduced M-I-S S/D with heavily doped interlayer might have a chance of replacing pure metal used M-I-S S/D.
8:00 PM - EP11.6.08
The Screen Effect in Resistive Switching Memory Prepared by Thermal Process Based-Atomic Layer Deposition
Yihui Sun 1,Xiaoqin Yan 1,Xin Zheng 1,Yue Zhang 1
1 University of Science and Technology Beijing School of Materials Science and Engineering Beijing China,Show Abstract
The demand for high-performance memory devices is stronger than ever before due to that the lithography technology gradually approaches its physical limit. Resistive random access memory (RRAM) presents a promising candidate for its nice properties of fast switching speed, low operating voltage. Ion drifting is the key to realize the resistive switching in resistive random access memory (RRAM). So it becomes a major issue to investigate the mechanism of ion migration in RRAM.
In this paper, the screen effect in resistive switching memory was put forward firstly to account for the absence of RS behavior in Au/T-ALD ZnO film/AZO device. Subsequently, annealing processing was utilized to weaken the screen effect, and an enormous enhancement in on-off ratio was acquired. The screen effect was further modulated by varying annealing temperatures and the maximal on-off ratio of ~105 can be obtained after 600 °C annealing owing to its least free carriers in ZnO film. Meanwhile, the different characteristics under positive and negative biases are figured out: the switch ratio increases with positive biases and remains unchanged in negative biases. According to thermionic emission and P-F emission respectively, there will be more carriers motivated when elevating positive potential, while the free carriers keep stable under negative bias. The results above manifested that the freer carrier, the more significant screen effect. This study has a bright future for applications in building memory with high performance and gives unique version of ion drifting in RRAM.
8:00 PM - EP11.6.09
Electrical and Structural Properties of Ni-InGaAs with and without InAs Capping Layer
Sim-Hoon Yuk 1,Chel-Jong Choi 1
1 School of Semiconductor and Chemical Engineering Chonbuk National University Jeonju Korea (the Republic of),Show Abstract
Ni-InGaAs alloy formed using interfacial reaction between Ni and InGaAs driven by rapid thermal annealing (RTA) process was studied as an ohmic contact n+InGaAs having a doping concentration of 5×1019 cm3. An investigation of the electrical and structural properties of Ni contact to InGaAs, with and without 3 nm thick InAs capping layer was made as a function of RTA temperature. InAs has a very small bandgap which leads to the reduction of the heterojunction barrier. A specific contact resistance (ρc) of 1.92×10-6 and 1.05×10-7 Ωcm2 were obtained for the as-deposited Ni contacts to InGaAs substrates with and without InAs capping layer, respectively. On annealing at 400°c the specific contact resistance(ρc) decreased to 1.23×10-7 and 1.20×10-8 Ωcm2 for the InGaAs samples with and without InAs caaping layer, respectively. The thermal stability was improved by InAs capping layer that blocks the out-diffusion as confirmed from the phase-evolution studies
8:00 PM - EP11.6.10
Depth Characterization of Chemical States in GeSn Thin Film by HAXPES
Koji Usuda 1,Riichiro Takaishi 1,Masahiko Yoshiki 1,Kohei Suda 2,Atsushi Ogura 2,Mitsuhiro Tomita 1
1 Corporate Ramp;D Center Toshiba Corporation Kawasaki Japan,2 Nanotech Lab. Meiji University Kasawaki JapanShow Abstract
GeSn alloy is a novel material as a high hole mobility MOSFET channel substituting Si and as a stressor for strained channels. Furthermore, modulation of the band structure by the increasing Sn composition is expected to improve the performance of optical devices such as photodetectors. However, the solubility limit of Sn within a GeSn alloy is considered to be approximately 1 atomic% and the suppression of Sn segregation during GeSn growth, while increasing the Sn composition, is essential to obtain high-quality GeSn films. Hence, depth profile characterization of the Sn composition and the chemical state within the GeSn film is important to investigate the growth mechanism, in detail. Therefore, in this presentation, hard X-ray photo emission spectroscopy (HAXPES) analysis was used to achieve depth characterization of the chemical state of Sn within a GeSn alloy.
HAXPES measurements were carried out with excitation energy of 7943.95 eV, take-off angle (TOA) of 89.5 degrees, and a SCIENTA R4000 electron analyzer at BL16XU, SPring-8. Since the inelastic mean free path (IMFP) for HAXPES is several times deeper than that for conventional X-ray photoelectron spectroscopy (XPS) (KRATOS, AXIS Ultra, Al-Kα), HAXPES analysis is expected to be useful to identify simultaneously the variation of chemical state at a surface part and the underlying bulk part of a GeSn film. Thin GeSn alloy films with the thickness of typically 30-50 nm were grown on (001) Ge substrates at low temperature (~360 degrees) by the metal-organic chemical-vapor-deposition (MOCVD) method using specially prepared Ge (t-C4H9GeH3) and Sn ((C2H5)4Sn) source gases. The target compositions of Sn were 2% and 3%, respectively.
Initially, we observed the splitting of the Sn3d5/2 spectrum into two peaks (M1 and M2) for high Sn composition (3%) GeSn film by conventional HAXPES measurement, whereas the spectrum of a low Sn composition (2%) GeSn film remained single. The binding energy of the newly split peak (M2) was lower than that of the Sn3d5/2 peak (M1) and the peak position of M1 approximately coincided with that of the abovementioned 2% GeSn film. To clarify the newly split Sn3d5/2 spectrum, total reflection mode HAXPES (TR-HAXPES) measurement was carried out for the 3% GeSn film. As a result, only a single Sn3d5/2 spectrum was observed by the measurement. Since the position of the observed peak of the Sn3d5/2 spectrum by the TR-HAXPES, closely coincided with the newly observed split Sn3d5/2 peak (M2) taken by conventional HAXPES measurement for the 3% GeSn film, the newly observed split Sn3d5/2 spectrum for the 3% GeSn was identified as a peak derived from the Sn segregation formed at the film surface. On the other hand, only a single Sn3d5/2 spectrum was observed by XPS measurements for both 2% and 3% GeSn film.
Hence, it is concluded that depth profile characterization of the Sn chemical state within a GeSn film possible by combining normal HAXPES and TR-HAXPES measurements.
8:00 PM - EP11.6.11
Polarization Switching of the Incommensurate Phases Induced by Flexoelectric Coupling in Ferroelectric Thin Films
Limei Jiang 1
1 School of Materials Science and Engineering Xiangtan University Xiangtan China,Show Abstract
The polarization switching of the incommensurate (INC) phases induced by flexocoupling in perovskite ferroelectric thin films is investigated
with a multi-field coupling theoretical framework combining the flexoelectric effect. The dominant factors of the formation of INC phases
that show antiferroelectric-like double hysteresis loops are examined. The simulations show that mechanical boundary conditions have little influence on the polarization responses of INC phases. The polarization switching behaviors of INC phases are governed by the flexocoupling types described by different flexocoupling coefficients. Only the transverse flexocoupling coefficient related INC phases show antiferroelectric-like double hysteresis loop. The longitudinal flexocoupling coefficient related and shear flexocoupling coefficient related INC phases show imprint-like hysteresis loops and hysteresis loops similar to those of the ferroelectric phase, respectively. The observed different polarization switching behaviors are rationalized by free energy density curves of the INC phases.
8:00 PM - EP11.6.12
Dead Layer Effect and Its Elimination in Ferroelectric Thin Film with Oxide Electrodes
Yichun Zhou 1,Limei Jiang 1
1 School of Materials Science and Engineering Xiangtan University Xiangtan China,Show Abstract
Interfacial dead layer effect has been widely noticed in the past and was thought to be responsible for the critical thickness of ferroelectric thin film. Despite extensive studies, the origin is still under fierce debate. The dead layer even exists at the perfect interface without defects and impurities. In this paper, we studied the effects of the electrode/ferroelectric interface on the polarization properties of nano-scale BaTiO3 ferroelectric capacitors by first-principle calculation. A thin layer with reversed polarization is found in the TiO2-teminated LaNiO3/BaTiO3/LaNiO3 capacitor. This pinned domain with reversed polarization at the top interface of ferroelectric film acts as a dead layer and reduces the total polarization. Based on our analyses, this reversed polarization is argued to originate from the intrinsic polarization instability near the top interface of TiO2-teminated ferroelectric thin film and an interfacial electrical field. An interface modification method has been adopted to remove such dead layer effects. Our results show that a LaXO3 (X=Fe, Co) or YNiO3 (Y= Sr, Ba) buffer layer can effectively remove the dead layer effect in BaTiO3 film.
8:00 PM - EP11.6.13
Pseudo-Single Crystal Ferroelectric Grown by Selectively Nucleated Lateral Crystallization for High-Performance Ferroelectric Field-Effect Transistors
Jaehyo Park 1,Seung Ki Joo 1
1 Department of Material Science and Engineering, Seoul National University Seoul Korea (the Republic of),Show Abstract
The nonvolatile memory technology with conventional floating-gate transistor is facing its poor electrical performance. Therefore, there are strong demands for new memory concepts to replace its contemporary technology. Recently, the ferroelectric field-effect transistors (FeFET) have been highly considered for the next generation of memory application because of their scalability, nonvolatility, low power consumption, and non-destructive readout operation. Utilizing the two stable polarization states incorporating with the gate insulator can obtain not only data storage, but also a sub-kT/q subthreshold slope which is large breakthrough for low power FETs. The most commonly used ferroelectric materials are Pb(ZrxTi1-x)O3 (PZT), SrBiTaO9 (SBT), BiFeO3, and poly(vinylidenefluride) (PVDF) and the most commonly used FeFET structure is metal-ferroelectric-insulator-semiconductor (MFIS). In theory, the FeFET can obtain a nanosecond program/erase (P/E) speed with below 6 V of low-bias, while the conventional floating gate showed a millisecond P/E speed with over 20 V of high-bias. In addition, almost unlimited endurance P/E cycles in FeFET, while the convention floating-gate transistors showed maximum 106 endurance cycles. However, depolarization issue in the ferroelectric layer is retarding its potential to the industrial implementation. The depolarization problem is mainly originated from the grain-boundaries and loss of charge compensation in MFIS structure. The grain-boundaries in ferroelectric result in gate leakage path and oxygen vacancy accumulation. In addition, the charge compensation loss in MFIS structure always exists due to is finite dielectric constant of semiconductor. Unfortunately, there were no significant solutions for controlling the grain boundaries or suppressing the charge compensation loss.
In this work, we developed and fabricated MFIS-FET with a novel crystallization method termed "selectively nucleated lateral crystallization (SNLC)" to control the grain-boundaries. The separating the nucleation seeds and grain-growth at a desirable location could achieve large grains over 50 μm in a very uniform rectangular structure. The electrical properties, including P/E swithcing speed, retention time, fatigue, and gate leakage current, of SNLC MFIS-FET was significantly improved in comparison with the poly-grained MFIS-FET. it is significantly important to grow a single crystal, single domain ferroelectric on Si. Having a free-grain boundary ferroelectric film might be possible solution for realizing a high performance MFIS-FET for replacing the current floating gate transistors.
8:00 PM - EP11.6.14
Al-Graded AlxGa1-xN Layers on Vicinal GaN(0001) Substrate: Growth, Structure and Electrical Properties
Andrian Kuchuk 2,Petro Lytvyn 2,Chen Li 1,Hryhorii Stanchu 2,Yuriy Mazur 1,Morgan Ware 1,Mourad Benamara 1,Vasyl Kladko 2,Aleksander Belyaev 2,Gregory Salamo 1
1 Institute for Nanoscience and Engineering, University of Arkansas Fayetteville United States,2 V.Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine Kyiv Ukraine,2 V.Lashkaryov Institute of Semiconductor Physics, National Academy of Sciences of Ukraine Kyiv Ukraine1 Institute for Nanoscience and Engineering, University of Arkansas Fayetteville United StatesShow Abstract
Compositionally graded AlxGa1-xN layers have recently become very interesting as a result of their potential to enhance p-type doping due to the so-called polarization doping effect . The buildup and relief of strain is a critical process in any epitaxial system. For the graded AlxGa1-xN structures, there appears to be many interesting strain-related effects due to the large strain accumulation during the growth.
In this study, we report on epitaxial Al-graded AlxGa1-xN structures grown by PA-MBE and their properties probed at the nanoscale. It was found that growth on vicinal GaN (0001) substrates and the accumulation of strain during the growth can modify the step-flow growth and result in a giant step-bunching effect . The resulting extraordinary macrosteps which are found to run perpendicular to the miscut direction, [1-100], on the as-grown surface, act as localization centers for free surface charge as seen in Kelvin force probe microscopy as a lateral modulation of charge carriers directly correlated with the steps. Finally, using nanoscale probes of the charge density in cross sections of the samples, we have directly measured, semi-quantitatively, both n- and p-type polarization doping resulting from the gradient concentration of the AlxGa1-xN layers.
 J. Simon, V. Protasenko, C. Lian, H. Xing, D. Jena, Science 327, 60-64 (2010).
 A.V. Kuchuk, P.M. Lytvyn, Chen Li, et al. ACS Appl. Mater. Interfaces DOI:10.1021/acsami.5b07924 (2015).
8:00 PM - EP11.6.15
Characterizing Device Properties of Potential Ferroelectric Co-Crystals
Timothy Reece 1,Axel Enders 2
1 Univ of Nebraska-Kearney Kearney United States,2 Department of Physics and Astronomy University of Nebraska at Lincoln Lincoln United StatesShow Abstract
Organic electronics is a rapidly growing field based on carbon-based polymers and small molecules. A special class of organics and a potential key enabler for new and unique organic based technologies are molecular ferroelectrics (MFE). The electrically switchable remanent polarization associated with these materials can be useful for any many applications including information storage.
Recently, it was determined that a particular combination of ferroelectrics, croconic acid (CA) and 3-hydroxyphenalenone (3-HPLN), can be easily combined to form 2D and 3D ferroelectric co-crystals. The discovery was made using a solvent-free surface science approach. According to theoretical estimates, the electric polarization in these co-crystals is about twice as large as the polarization found in the crystalline form of the constituent molecules. Building on this result, other candidates for molecular ferroelectric co-crystals are under investigation. In this study, Sawyer Tower measurements on thin film capacitors are used to explore the polarization hysteresis, switching fields, fatigue, retention and other properties of these unique ferroelectrics.
8:00 PM - EP11.6.16
FTIR Ellipsometry Study on RF Sputtered Permalloy-Oxide Thin Films
Md Abdul Ahad Talukder 1,Yubo Cui 1,Maclyn Compton 1,Wilhelmus Geerts 1,Luisa Scolfaro 1,Stefan Zollner 2
1 Texas State Univ San Marcos United States,2 Physics NMSU Santa Cruz United StatesShow Abstract
Fe doped NiO thin films, interesting for possible application in resistive RAM devices, were studied by ellipsometry. The inclusion of Fe will allow in a mean to adjust atom mobility, morphology and texture, all relevant for the switching behavior of the oxide. Fe doped NiO maintains the rocksalt crystal structure up to a shy 2 at%. At higher concentration γ-Fe2O3 is detected in samples prepared by the chemical co- precipitation method . The x-ray diffraction spectra of sputtered Ni0.81Fe0.19O (PyO) thin films however confirm a rocksalt crystal structure suggesting that sputtered PyO films are in meta-stable form. In this paper we investigate the optical properties of PyO in the far infrared.
Fused quartz and SiO2 covered Si wafers that were roughened at the back with a sandblaster were used as substrates. Prior to loading them into an AJA sputter system they were cleaned ultrasonically in water, acetone, and IPA. Deposition was done by reactive rf magnetron sputtering (240 Watt) from a Py target using a sputter gas of 80% Ar and 20% O2 (p=10-3 Torr). The films were deposited at different substrate temperatures (RT-500 oC). X-ray powder diffraction measurements done with a Panalytical Empyrean X-ray diffractometer confirm the rocksalt crystal structure. The texture appears to vary strongly as a function of temperature. The chemical composition of the samples was measured using EDAX. The Ni to Fe atomic ratio was similar to the concentration of the target and the O concentration was estimated to be 60 % +/-1%.
The samples were characterized by ellipsometry from 200nm to 40 um using various Woollam ellipsometers. The △ and Ψ spectra measured at five different angles of incidence from 250-1000 nm were used to determine the film thickness and optical properties of the PyO. The thickness of the films was approximately 80 nm consistent with the deposition rate measured from the thickness monitor (1.2A/sec). The optical properties of PyO in the infrared can be described by a Lorentzian phonon peak at 382 cm-1, slightly red shifted from the phonon peak of single crystalline NiO (390 cm-1). Reflection measurements done with a Thermo-Nicolet FT-IR system using a solid substrate beam splitter and a deuterated triglycene sulphate detector on dual ion beam sputtered PyO thin films showed a phonon peak in the same part of the IR spectrum. The phonon peaks of nickel ferrite, magnetite, hematite, and maghemite are inconsistent with the measured peak at 382 cm-1, confirming the rocksalt crystal structure of RF and DIBS sputtered PyO thin films.
Work at TxSTate was funded by DOD (HBCU/MI grant W911NF-15-1-0394) and work at NMSU by the National Science Foundation (DMR-1104934). This work was performed, in part, at the Center for Integrated Nanotechnologies, an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science.
 P. Mallick, Chandan Rath, R. Biswal, N.C. Mishra, Indian J. Phys. 83 (4) 517-523 (2009).
8:00 PM - EP11.6.17
Ab Initio Modeling of Vacancies, Antisites, and Si Dopants in Ordered, CuAu-I Type, InGaAs
Jingyang Wang 1,Binit Lukose 2,Michael Thompson 3,Paulette Clancy 2
1 School of Applied and Engineering Physics Cornell University Ithaca United States,2 School of Chemical and Biomolecular Engineering Cornell University Ithaca United States3 Department of Materials Science and Engineering Cornell University Ithaca United StatesShow Abstract
As rapid advances in semiconductor technology shrink transistor gate lengths below 10 nm, silicon-based devices are slated to reach a limit in performance. One promising solution to this bottleneck is to replace Si with In0.53Ga0.47As, a III-V material with a narrow, direct band gap (0.75 eV at 300 K) and high electron mobility (8450 cm2V-1sec-1) , in next-generation n-type MOSFET devices. One of the major challenges in using InGaAs for practical applications is to increase free electron concentration sufficiently. For Si-doped InGaAs, the best current experimental result with 10 min of furnace annealing at temperature above 700°C yields a free electron concentration of 1.4x1019 cm-3 , still insufficient for realistic applications. We have investigated the origin of low dopant activation in InGaAs, using ab initio Density Functional Theory and GW calculations. We have calculated formation energies for all relevant charged and neutral point defects in Si-doped In0.5Ga0.5As in an ordered CuAu-I type crystal structure. These defects include Si substitutional defects, Si interstitials, vacancies and antisites. Using these data, we have identified the optimal annealing conditions and temperature for maximal dopant activation. Specifically, we report that SiAs, a deep acceptor, is responsible for the self-compensation of Si-induced donors under As-poor annealing conditions, while other acceptor-like defects such as cation vacancies and antisites do not play as significant a role in limiting the extent of n-type doping, due to higher formation energies. We find that, under cation-poor conditions, the formation energies of charged SiIn and SiGa are negative, suggesting the possibility of high n-type dopability. We have identified the electrical properties of each defect; in particular, Si-interstitials, VAs, AsIn and AsGa are assisting defects, while SiAs, cation vacancies, InAs and GaAs are killer defects. The formation energies of native defects calculated in this work using LDA DFT with a GW band gap correction agree well with previous results reported by Komsa and Pasquarello using hybrid DFT calculations . [Publication in preparation]
 Y. Takeda, A. Sasaki, Y. Imamura, and T. Takagi, J. Appl. Phys. 47(12), 5405 (1976).
 A. G. Lind et. al., J. Vac. Sci. Technol. B 33(2), 021206 (2015).
 H.-P. Komsa and A. Pasquarello, J. Phys: Condens. Matter 24, 045801 (2012).
8:00 PM - EP11.6.18
Effect of Al2O3 Monolayer Inclusion in Symmetric Nanoscale Metal-Insulator-Metal Capacitors
Sita Dugu 1,Shojan Pavunny 1,Ram Katiyar 1
1 University of Puerto Rico San Juan United States,Show Abstract
Metal-insulator-metal (MIM) capacitors with greater capacitance in a small footprint are needed for various applications such as charge based memory, power decoupling, signal filtering, and analog signal processing. For these applications, the device capacitance must be stable enough with respect to applied voltage and temperature. Along with the high capacitance density (ε0k/td) and the limited thermal budget necessary for back-end integration, a low leakage current and a small voltage dependence of the capacitance (VCC) are necessary for the projected device functionality, which set the great challenges for the densely scaled MIM capacitors. The microelectronic chips are trending from low-k dielectric SiO2 (k∼3.9) to high-k dielectrics SiON (k ∼4−7), Al2O3 (k ~ 10), HfO2 (k ∼22), Ta2O5 (k ∼25), etc. to meet the above requirements. Strontium Titanate having very high dielectric constant (k∼300) has been widely studied due to its low dielectric loss (tan δ), incipient ferroelectricity, good chemical stability, and high breakdown strength, which permit technological applications in microelectronics and photonics. Al2O3 on the other side has a large band gap, kinetic stability, and thermodynamic stability on Si up to high temperatures. In this study, 0.4 nm (one monolayer) thick atomic layer deposited (ALD) amorphous Al2O3 layer is symmetrically sandwiched within amorphous silicon-modified SrTiO3 (SSTO) thin films (200-20 nm) grown by pulsed laser deposition(PLD). A systematic study was carried out on fundamental material characteristics of Pt/SSTO/Al2O3/SSTO/Pt stacks such as structural, optical, dielectric, and electrical properties. Resultant dielectric constants (dissipation factor) of the stacked samples were estimated to be ~45 (∼0.04), ~35 (∼0.071) and ~17 (∼0.047) for the dielectric thicknesses of 200 nm, 100 nm and 20 nm, respectively, at 100 kHz and at ambient conditions. The quadratic voltage coefficient of capacitance (VCC) obtained for the aforementioned stacks were 5.53 ppm/V2, 20 ppm/V2 and 328 ppm/V2 and the numerical values for room temperature leakage current at an applied bias of 2 V were 4.5x10-6 A/cm2, 3.67x10-6 A/cm2 and 4.96x10-2 A/cm2, in the order of decreasing thickness. The aforementioned results along with detailed analysis will be presented in regards to the intended silicon technology device applications.
8:00 PM - EP11.6.19
Silicon Substituted Strontium Titanate: A Promising High-k Dilectric Material
Sita Dugu 1,Shojan Pavunny 1,Yogesh Sharma 1,Ram Katiyar 1
1 University of Puerto-Rico San Juan United States,Show Abstract
Silicon technology, driven by Moore’s law, demands new material systems to realize fast switching and low power consumption for higher density logic and memory devices. In this regard strontium titanate is one of the most researched perovskite (ABO3) oxides, due to its superior characteristics, such as high dielectric constant ε and low dielectric loss (tan δ), good chemical stability, high breakdown strength and large optical bandgap, which permit technological applications like dynamic random access memories (DRAM), insulating sheets in resistive random access memories (ReRAM), gate oxide films in metal-oxide-semiconductor field-effect transistors (MOSFET), voltage controlled tunable permittivity sheets in microwave devices, buffer layers in optical waveguides, etc. A systematic study was carried out on fundamental material characteristics such as structural, microstructural, optical, dielectric, and electrical properties of phase-pure silicon-modified SrTiO3 polycrystalline electroceramics, synthesized using high energy solid state reaction technique. The asymmetry and splitting in the X-ray diffraction spectra and the observation of first order transverse optical TO1 and longitudinal optical LO4 modes in Raman spectra (normally forbidden) revealed the distortion in the cubic lattice as a result of breaking of inversion symmetry due to silicon doping. An optical energy gap Eg of 3.27 eV was determined for the sample by diffuse reflectance spectroscopy. A high dielectric constant of ~400 and very low loss tangent of ~0.03 were obtained at 100 kHz near ambient conditions. The ac conductivity as a function of frequency showed features typical of universal dynamic response (UDR) and obeyed a power law, σac=σdc + Aωn. The temperature dependent dc conductivity followed an Arrhenius relation with activation energy of 123 MeV in the 200 – 500 K temperature range. The linear dielectric response of Pt/SrSi0.03TiO0.97O3/Pt dielectric capacitors was well characterized. The measured leakage current was exceptionally low, 13 nA/cm2 at 8.7 kV/cm, revealing an interface blocked bulk conduction mechanism. Our studies reveal the fundamental physics and materials science of the SSTO electroceramics and its potential applications as a high-k dielectric for the materials-enabled scaling of the next generation of silicon technology devices.
8:00 PM - EP11.6.20
Studies on Holmium Hafnium Oxide for Potential High-k Dielectric Device Applications
Shojan Pavunny 1,Yogesh Sharma 1,Sudheendran Kooriyattil 1,Sita Dugu 1,Rajesh Katiyar 1,James Scott 2,Ram Katiyar 1
1 Department of Physics and Institute for Functional Nanomaterials Univ of Puerto Rico San Juan United States,1 Department of Physics and Institute for Functional Nanomaterials Univ of Puerto Rico San Juan United States,2 Department of Physics, Cavendish Laboratory, University of Cambridge Cambridge United KingdomShow Abstract
Moore’s law which states that the number of transistors per chip doubles approximately every 18 months is the driving force in delivering microprocessors with increased transistor density, faster switching speed, and lower power characteristics from one technology generation to another. In this regard downscaling of the metal-insulator-semiconductor (MIS) stacks and metal-insulator-metal (MIM) capacitors are being implemented in complementary metal-oxide-semiconductor (CMOS) devices. The most difficult challenge to meet this law is to deliver materials with high density at the nanometer scale. One critical component in high performance logic (eg. metal-oxide-semiconductor field-effect transistor (MOSFET)) and memory [e. g., resistive random access memory (RRAM) and dynamic random access memory (DRAM)] devices is a thin layer of insulator/dielectric oxide material with significantly enhanced physical properties (such as large bandgap, high linear dielectric constant, reduced loss tangent, lower leakage currents, and CMOS process compatibility) in order to continue aggressive scaling. Under this context, we have developed the ternary oxide material, Ho2Hf2O7 (HHO) in order to investigate how the addition of Ho2O3 affects the dielectric/physical properties of HfO2 from a high-k engineering point of view. Structural, optical, charge transport, and temperature and frequency dependent dielectric properties of HHO that make this material desirable as an alternative high-k dielectric for future silicon technology devices will be presented. A high reliable dielectric constant of ~20 and a low dielectric loss of ~0.001 were measured at 100 kHz and at ambient conditions without any significant temperature and voltage dependence. The Pt/HHO/Pt capacitor exhibits exceptionally low figures for Schottky emission based leakage currents. In combination with the large observed bandgap Eg of 5.6 eV, determined by diffuse reflectance spectroscopy, these results provide insights into fundamental physics and material science of the HHO metal oxide and its potential application as high-k dielectrics for the next generation of CMOS devices.
8:00 PM - EP11.6.21
Intrinsic Vacancy in Monolayer GaSe: A First-Principles Study by Screened Exchange Hybrid Functional
Dameng Liu 1,Yuzheng Guo 2,John Robertson 3
1 Mechanical Engineering Tsinghua University Beijing China,2 Harvard University Cambridge United States3 University of Cambridge Cambridge United KingdomShow Abstract
GaSe is a layered semiconductor formed by vertically stacked Ga-Se-Se-Ga layer with van der Walls interaction between layers. Few-layer GaSe has been synthesized and fabricated into various devices due to its good electronic and optical properties. One of the most important application is the field effect transistors, which requires the knowledge about the intrinsic defect properties. The defect could alter the transportation properties of GaSe in FET. Therefore, we examined the intrinsic vacancy electronic structure in monolayer GaSe using density functional theory.
The screened exchange hybrid functional is used in this work to give accurate electronic structures. Spin-orbital coupling is less than 10meV in these materials and thus not included in the calculation. The sX hybrid functional gives a band gap of 2.53eV for monolayer and 2.01eV for bulk.
Unlike most other 2D materials with a direct band gap in monolayer, bulk GaSe has direct to indirect band crossing when the number of layers decreases. The conduction band mimmum is at the Gamma point while the valance band maximum moves away from Gamma when the number of layer decreases. We noticed that the direct-indirect band crossing happens at 8 layers GaSe. The charge neutrality levels are calculated for few-layer cases and used to align the band edges.
The formation energy of GaSe is calculated to be 1.65eV, which is consistent with previous works. The formation energy of Ga vacancy in Se rich condition is 2.01eV while the formation energy of Se vacancy in Ga rich condition is 1.58eV.
For Ga vacancy, the 3 Se atoms next to Ga vacancy move outward but still maintain the 3-fold symmetry. The Ga under the vacancy moves further away. The defect state is localized at the 3 Se atoms next to the vacancy. The defect state shares the same 3-fold symmetry as the atomic structure. There is only one +/0 transition state at 0.1eV above the valence band. Thus the formation energy does not change much around when the Fermi level sweeps through the whole band gap. The Ga vacancy introduces p-type doping just 0.1eV above valence band. We have also noticed that the Ga vacancy introduced magnetic moment localized at the nearest neighboring Se atoms.
For Se vacancy, the 3-fold vacancy structure is also maintained. The defect state is also localized around the vacancy. However there is no defect transition level presented in the band gap. Also the magnetic moment is not changed by the vacancy. Considering the larger defect formation energy, Se vacancy is not considered to be responsible for the doping in GaSe monolayer.
In conclusion, the intrinsic defect in monolayer GaSe is studied by screened exchange hybrid functional. Ga vacancy can introduce p-type doping but Se vacancy does not introduce any defect state in the band gap.
8:00 PM - EP11.6.22
Vanadium Doped Hafnium Oxide: A Potential High-k Dielectric Gate-Stack Material
Yogesh Sharma 1,Radhe Agarwal 1,Shojan Pavunny 1,Ram Katiyar 1
1 University of Puerto Rico San Juan United States,Show Abstract
The continued scaling of logic and memory devices adhering to Moore’s law demands for new high-k dielectric materials that can deliver higher capacitance densities at the nanometer scale. Under this context, the effect of doping on the crystal structure, dielectric properties, charge transport, and optical properties of the V2O5—HfO2 (VHO) solid solution is reported. Nanometric-sized VHO ceramic powders were prepared by conventional solid state reaction method by varying V2O5 composition in the range of 0—9 mol% balanced HfO2. X-ray diffraction, transmission electron microscopic (TEM), Raman spectroscopic, and Fourier transform infrared spectroscopic (FTIR) studies were carried out to observe the structural instabilities due to doping. Mixed monoclinic and cubic structures were stabilized in VHO nanoceramics while increasing the vanadium concentration in HfO2 matrix. A high dielectric constant of ∼42, low dielectric loss of the order of ∼10-2, and very less leakage current ~4×10-8A/cm2 at 25 kV/cm were observed in 3mol% VHO sample at ambient conditions. Whereas, temperature (77—550 K), frequency (100 Hz—1 MHz) and electric field independent dielectric properties of all the samples were confirmed showing linear dielectric behavior of VHO nanoceramics. Further, the optical bandgap (Eg) of VHO samples measured by diffuse reflectance spectroscopy showed substantial increase in Eg from 5.7 eV for pure HfO2 to 6.2 eV for 9 mol% VHO sample. High dielectric constant, low leakage current, and high optical bandgap as compared to pure HfO2, make VHO nanoceramic a potential high-k dielectric material for the next generation of complementary metal-oxide-semiconductor (CMOS) devices.
8:00 PM - EP11.6.23
Atomic Layer Deposition of RuO2 and Ru Thin-Films Using Ru(DMBD)(CO)3 Precursor
Dustin Austin 1,Melanie Jenkins 1,John McGlone 1,Charles Dezelah 2,Derryl Allman 3,Sallie Hose 3,John Conley 1
1 Oregon State Univ Corvallis United States,2 SAFC Hitech, Inc. / Sigma-Aldrich Haverhill United States3 ON Semiconductor Gresham United StatesShow Abstract
We report on the development of ALD processes for a novel Ru precursor, η4-2,3-dimethylbutadiene ruthenium tricarbonyl [Ru(DMBD)(CO)3], intended for use in both Ru metal and RuO2 thin films. Ruthenium (Ru) and ruthenium oxide (RuO2) have attracted interest in the semiconductor industry for applications such as CMOS transistor contacts, high-κ metal-insulator-metal capacitor (MIMCAP) electrodes , and seed layers for copper (Cu) electroplating . Ru is a noble transition metal with low bulk resistivity (7.1 μΩ·cm), high work function (4.7 eV), good thermal stability, and low solid solubility with strong adhesion to Cu.1 RuO2 has low resistivity (46 μΩ·cm), an even higher work function (5.1 eV), and good chemical stability. Current technologies for MIMCAPs utilize TaN and TiN electrodes, which can oxidize during atomic layer deposition (ALD) of the insulator to create unwanted interfacial layers. For MIMCAPs with thin high-κ dielectrics, the interfacial layer can comprise a substantial percentage of the dielectric thickness, reducing achievable capacitance and control of voltage linearity. Using RuO2 as an electrode can eliminate interfacial oxide formation and has the additional benefits of templating the high-κ rutile phase of TiO2 at lower deposition temperatures and reduced leakage current due to the larger work function . Owing to the inherent conformality and thickness control, ALD processes for Ru and RuO2 are desirable. However, Ru(CpEt)2, currently the most commonly used ALD precursor for RuO2, exhibits a very narrow ALD temperature windows on SiO2 of only 5˚C .
ALD films were deposited using alternating N2-purge-separated pulses of Ru(DMBD)(CO)3 and either molecular O2 (for Ru metal) or O2 plasma (for RuO2). Depositions were conducted in the range of 200 °C to 325 °C on 6" wafers with pulse times between 0 to 2s for Ru(DMBD)(CO)3 to determine ALD windows and saturation curves. The growth rate for RuO2 was found to be approximately 0.09 nm/cycle, determined using spectroscopic ellipsometry (SE) and x-ray reflectivity (XRR). Grazing incidence x-ray diffraction (GIXRD) measurements show good agreement with database reference cards for RuO2. The resistivity of RuO2 films was measured via four point probe in the range of 125-145 μΩ∙cm, comparable to other ALD films. Atomic force microscopy (AFM) shows an RMS roughness of approximately 0.5 nm for a 47 nm RuO2 thick film. Details of the Ru process will be reported on at the meeting.
 Han et al., Appl. Phys. Lett. 99, 022901 (2011).
 Lane et al., Appl. Phys. Lett. 83, 2330 (2003).
 V. Miikkulainen et al., J. Appl. Phys. 113, 021301 (2013).
8:00 PM - EP11.6.24
Prospects and Issues of Nanomaterials Use in Microelectronics
Michael Jank 1,Anton Bauer 1,Lothar Frey 1
1 Fraunhofer IISB Erlangen Germany,Show Abstract
With respect to future semiconductor technologies, particulate nanomaterials have proven interesting capabilities for end-of-roadmap or post-roadmap devices. Semiconductor nanowires, carbon nanotubes, fullerenes, and various quantum dots can solve bottleneck issues like high aspect ratio via filling or help to increase the efficiency and operability of memories or photonic devices. 2D nanomaterials like graphene and molybdenum disulfide are under discussion for integration as high-mobility channel materials.
More present, nanomaterials are key players in the improvement of manufacturability and already find application in chemical-mechanical polishing and high refractive index liquids for immersion photolithography. In assembly and packaging, silver nanosintering or conductive adhesives based on dispersed particles in organic matrix help to lower the thermal budget during assembly. Furthermore, also interlevel dielectrics, encapsulants, and thermal interface materials benefit from nanosized fillers.
The presentation gives a comprehensive overview on the utilization and technological issues of particulate nanomaterials in current and future semiconductor manufacturing. The review is part of the coordinated support action (CSA): NANOmaterials: STRategies for Safety Assessments in advanced Integrated Circuits Manufacturing (NanoStreeM) which is financed by the European Commission under its program Horizon 2020-ICT-2015 (Grant No. 688194)
8:00 PM - EP11.6.25
Flexoelectric Switching in Mono-Domain BiFeO3 Film to Investigate In-Plane Flexoelectric Effect
Sungmin Park 2,Saikat Das 2,Tae Won Noh 2
1 Physics and Astronomy Seoul National University Seoul Korea (the Republic of),2 Center for Correlated Electron Systems Institute for Basic Science Seoul Korea (the Republic of),Show Abstract
In 2012, mechanical switching of polarization in barrium titanum oxide thin film was demonstrated. The most plausible explanation of the mechanically induced polarization switching is the flexoelectric coupling, which is a coupling between a strain gradient and polarization. Also, recent study computationally simulated the spatial distribution of the tip-induced flexoelectricity and compared with experiments. However, since they used the ultra thin film of barrium titanum oxide , only polarization of out-of-plane component was considered. In this work, We examine the phenomenon of flexoelectric switching of polarization induced by a tip of an atomic force microscope with thin film of bismuth iron oxide, which posses polarization components along both out-of-plane and in-plane directction. Depending on the scan angle during domain writing with assistance of force induced by atomic force microscopy tip, it was possible to make stable ferroelastic switching occured. Experiment results indicate that in-plane flexoelectric effect has significant role in pressure induced switching process.
8:00 PM - EP11.6.26
Ab Initio Simulations of Higher Index Si:SiO2 Interfaces for FinFET Transistors
Hongfei Li 1,Yuzheng Guo 1,John Robertson 1
1 University of Cambridge Cambridge United Kingdom,Show Abstract
Si-based electronic devices have been successful thanks to the good interface between Si and its native oxide SiO2, especially for the traditional Si(001) and Si(110) facets, which have been investigated thoroughly. Some novel three dimensional structures such as FinFET have been introduced, so as to retain good electrostatic control of the channel for smaller devices[1,2]. These non-planar devices can however involve some higher Miller index facets of Si[3,4], such as the Si(n10) and Si(nn1) facets, to form the channel fin sidewalls. The quality of these higher index interfaces determines the final device performance. Therefore, a deep understanding of the higher index Si/SiO2 interfaces is desirable.
The interface based on two kinds of higher index Si facets, Si(n10) and Si(nn1), are good models for the appropriate Si:SiO2 interfaces in the FinFET. It is often noted that these interfaces keep the properties of simpler Si facets such as Si(001), Si(110) and Si(111). However the higher index interface morphology is still unclear. Ogata noted that higher index facets should consist of a larger portion of Si(001) partial facets as the oxidation rate of Si(111) is faster than that of Si(001). Nevertheless, Stesmans found a much stronger ESR signal for Si(111)-like atoms than Si(001)-like atoms. We have investigated thoroughly three higher index interfaces, Si(310):SiO2, Si(410):SiO2 and Si(331):SiO2, by ab-initio methods. It is proved that all these three interfaces could be of good quality without any defects and thus suitable for FinFETs. These interface models are built in steps including MD anneal and cool down. We ensure each Si is 4-fold and each O is 2-fold so that no interface defect appears.
The Si(310): SiO2 interface surface is sawtooth-like and has got one atomic step. Half of the surface Si atoms are Si(110)-like with one dangling bond, while the other half are Si(100)-like with two dangling bonds. MD results show that after oxidation, these dangling bonds are well passivated at the Si(310):SiO2 interface, forming the Si+ and Si2+ sub-oxide states. The PDOS analysis shows a clean band gap and large band offset. Thus the interface could be of good quality.
Oxygen bridges appear in Si(410):SiO2 interface to passivate extra dangling bonds. The partial DOS of the Si(410):SiO2 interface and the Si(331):SiO2 interface are quite similar to those of Si(310):SiO2. Both interfaces have no defects, show a clean band gap, large band offset between Si layers and SiO2 layers, and delocalized band edge orbital in Si layers. Therefore, all of the three higher index interfaces are suitable for FinFET.
 D. Hisamoto et al., Electron Devices, IEEE Transactions on, 47 2320 (2000)
 B. S. Doyle et al., Electron Device Letters, IEEE, 24 263 (2003)
 S. Ogata et al., Appl. Phys. Lett., 98 092906 (2011)
 S. Iacovo and A. Stesmans, Appl. Phys. Lett. 105 262101 (2014)
 Y. Tu and J. Tersoff, Phys. Rev. Lett. 84 4393 (2000)
8:00 PM - EP11.6.27
Optical Readout Write Once Read Many Memory in Ag/ MEH PPV/ ITO Device
Viet Cuong Nguyen 1,Kenji Chee 1,Pooi See Lee 1
1 Nanyang Technology University Singapore Singapore,Show Abstract
An optically readable write once read many memory in Ag/ MEH PPV/ ITO is demonstrated in this work. Utilising light emitting characteristic of OLED structure of Ag/ MEH PPV/ ITO and electrochemical metallisation of Ag, a write once read many memory (WORM) with light emitting capability can be realised. The simple fabrication process and multifunction capability of the device can be useful for future wearable optoelectronics applications where fast and parallel readout can be achieved by photons.
John Robertson, Cambridge University
Martin M Frank, IBM
Andrew C Kummel, University of California, San Diego
Masaaki Niwa, Tohoku University
Applied Materials, Inc.
EP11.7: High K/Metal Gate
Thursday AM, March 31, 2016
PCC North, 200 Level, Room 223
8:00 AM - EP11.7.01
Rare Earth Element Doping of GeO2 for the Improved Interface Quality in Ge MOSFETs
Hongfei Li 1,Yuzheng Guo 1,John Robertson 1
1 University of Cambridge Cambridge United Kingdom,Show Abstract
The passivation scheme for the Ge-based MOSFETs has been a lasting problem, due to the poor Ge:GeOx interface. Although HfO2 can passivate a Si channel well, it fails on the Ge surface due to the high defect density, Dit. Oxygen deficiency defects at this Ge:HfO2 interface introduce gap states which pin the Fermi level in Ge-MOSFETs, especially considering the low migration barrier of oxygen vacancy in the HfO2 layers. Toriumi noted that Y2O3 doped GeO2 can improve the thermal mobility of the GeO2 layers, suppress the metal-Ge interaction and thus benefit the Ge interface. Studies find that the introduction of some rare earth elements including La, Y, and Sc into the Ge:GeO2 interface can effectively lower the Dit[3,4], which provides a plausible method to circumvent the poor properties of the Ge:HfO2 interface. However, what makes rare earth elements doping scheme superior to HfO2 in passivating Ge surface is not fully understood.
DFT calculations showed that the careful built Ge:La2Ge2O7 interface and Ge:HfGeO4 interface both gave a clean band gap and large band offset, which in principle should work for MOSFETs. The different experimental behaviors between HfO2 and the rare earth elements doping scheme regarding passivation should reside in the interfacial oxygen vacancy properties. We have built the Ge:α-Ge(M)Ox interfaces (M for La, Y, Sc, Al and Hf) to investigate the variation of properties of interfacial oxygen vacancy in the rare earth metal doped system. Calculations show that the interfacial oxygen vacancy near the doped metal leads to a weak direct bonding between the rare earth metal and the Ge in the channel layers. The formation energy of such interfacial oxygen vacancy in Ge: Ge(Hf)Ox interface is 0.33eV, quite close to the value for the interfacial oxygen vacancy in the Ge:GeO2 interface. On the contrary, the formation energies for interfacial oxygen vacancy in the La, Y, Sc doped interface are all below zero at the oxygen poor condition, which suggests it is more easily to form oxygen vacancy at the La, Y, Sc doped Ge interface than Hf doped one. However, the Hf-Ge direct bonding at the vacancy region introduces a mid-gap state which should be responsible for the poor interface quality, while the La(Y, Sc)-Ge direct bonding only introduces a defect state below the VBM of Ge layers which leaves a clean band gap.
 A. Dimoulas, et al., Appl. Phys. Lett. 86, 032908 (2005).
 A. Toriumi, et al., J. Appl. Phys. 116 174103 (2014)
 C. Andersson, et al., Solid State Device Research Conference 2009
 A Dimoulas, et al. J. Appl. Phys. 115 114102 (2014)
 H. Li, et al. Appl. Phys. Lett. 101, 052903 (2012)
8:15 AM - *EP11.7.02
High-k/Metal Gate Innovations in FinFET Era
Takashi Ando 1,Balaji Kannan 2,Unoh Kwon 2,Pouya Hashemi 1,Tenko Yamashita 3,Vijay Narayanan 1
1 IBM T.J. Watson Research Center Ossining United States,2 IBM SRDC Hopewell Junction United States3 IBM Research Albany United StatesShow Abstract
As conventional scaling on bulk Si or partially depleted SOI is becoming increasingly challenging, thin body devices are being considered as long-term alternatives. Since Intel first introduced FinFET on its 22nm logic technology , FinFET has become a mainstream device architecture in the semiconductor industry at the 16/14nm nodes [2-4]. In this talk, new challenges and opportunities for high-k/metal gate technology in FinFET era are discussed from the perspectives of effective work function control [5-8] and implementation on high mobility channel materials .
 C. Auth et al., VLSI, pp. 131-132, 2012
 S-Y. Wu et al., IEDM, pp. 48-51, 2014
 S. Natarajan et al., IEDM, pp. 71-73, 2014
 C-H. Lin et al., IEDM, pp. 74-76, 2014
 T. Ando et al., EDL, 34 , pp. 729-731, 2013
 A.R. Trivedi et al., TED, 61 , pp. 1262-1269, 2014
 T. Ando et al., VLSI, pp. 54-55, 2014
 T. Ando et al., IEDM, to be published, 2015
 P. Hashemi et al., VLSI, pp. 16-17, 2015
8:45 AM - EP11.7.03
Wet Sulfur Passivation of the Interfaces between High-k Dielectrics and SiGe(001)
Kasra Sardashti 1,Max Clemons 1,Kai-Ting Hu 1,Serge Oktyabrsky 2,Bhagawan Sahu 3,Lin Dong 4,Naomi Yashida 4,Jessica Kachian 4,Andrew Kummel 1
1 Univ of California-San Diego La Jolla United States,2 University at Albany—State University of New York Albany United States3 TD Research, GLOBALFOUNDRIES USA Albany United States4 Applied Materials Sunnyvale United StatesShow Abstract
Silicon-Germanium is expected to be used in the future CMOS technology due to tunability of its carrier mobility and band gap by variation in Ge content and tensile/compressive stresses. In contrast to Si, SiGe native oxide is a combination of SiOx and GeOx, which has low interface quality and stability in comparison with SiO2. Scaling SiGe devices is crucial in its future application and ALD growth of high-k oxides with small equivalent oxide thickness (EOT) such as Al2O3, HfO2 and TiO2 on SiGe is favorable. The present study determines the effect of the ex-situ sulfur passivation (via (NH4)2S dip) and in-situ NH3 plasma nitridation, prior to ALD, on high-k oxide/SiGe interfaces in terms of oxide leakage and interface and near-interface trap density. MOS capacitors fabricated by Al2O3 and HfO2 ALD at 120°C and 300°C, have been compared by capacitance-voltage (C-V) and current-voltage (I-V) measurements. Compared to HF clean, both ex-situ S-passivation and in-situ plasma nitridation led to smaller gate leakage current for Al2O3. In addition, both methods resulted in surface stability in air up to an hour, which extends the wafer queue time prior to low interfacial defect density ALD oxide deposition. Lower Al2O3/SiGe interface trap density (Dit) relative to HF-treated samples was achieved by ex-situ S-passivation at low ALD temperatures (120 °C) and by in-situ NH3 plasma at high ALD temperatures (300 °C). Angle-resolved X-ray photoelectron spectroscopy (AR-XPS) measurements on SiGe(001) with 0.8nm thick Al2O3 showed that (NH4)2S clean significantly reduces the amount of GeOx at the in Al2O3/SiGe(001) interface, compared to HF clean. Similarly NH3 plasma at 300 °C largely reduced the GeOx and GeON components at the interface and selectively terminated the Al2O3/SiGe interface with Si3N4 and SiON. The universality of the two SiGe passivation techniques was demonstrated by fabrication of HfO2/SiGe MOSCAPs.
9:00 AM - EP11.7.04
Interface Defect Reduction on High-k/Ge and SiGe MOS Device
LiangLiang Zhang 1,Xiaochi Chen 1,James Harris 1,Paul McIntyre 1,Vinaayk Hassan 2,Majeed Foad 2
1 Stanford Univ Stanford United States,2 Applied Materials Inc. Santa Clara United StatesShow Abstract
Interface defect passivation of the Ge or SiGe substrate is very important to achieve high quality interfaces in MOS high performance devices. Al2O3 is one of the most commonly used dielectric materials for Ge and SiGe devices, and extensive studies have been performed on the Al2O3/Ge system. One unsolved question, however, is why the interface quality in these MOS structures has a strong dependence on Al2O3 thickness, where thicker films exhibit increasing interface trap densities - an unexpected result. The other issue is the sensitivity of the interface trap density in metal/Al2O3/Ge MOSCAPs to the nature of the H2/N2 anneal. Further, the presence of a gate metal such as Pt that is effective in dissociating H2 to atomic hydrogen. Such gate metals may not be practical for mainstream MOS technology, and interestingly, we find that they produce inferior interfaces between ALD-Al2O3 and SiGe channels for otherwise identical processing conditions.
Atomic layer deposited Al2O3 layers on Ge and SiGe substrates were synthesizing using a TMA-H2O process at 250oC. Pt or Al gates were e-beam evaporated and H2/N2 (5%H2) furnace anneals (FGA) were performed after gate metal deposition.
Photoluminescence (PL) spectroscopy on as-grown Al2O3/p-Ge samples show decreasing band-edge PL with increasing Al2O3 thickness, suggesting its Al2O3/p-Ge interface has more defects. This could be due to the modification of surface from pulse-by-pulse oxidation and reduction of the interface during ALD. C-V characterization of Pt/Al2O3/p-Ge MOSCAPs shows a similar trend with decreasing Dit response for the thinnest Al2O3 layers. We also find that the formation of GeO2 between Al2O3 and p-Ge is less efficient with thicker Al2O3 films. Angle-resolved x-ray photoelectron spectroscopy (ARXPS) was used to correlate the effects of Al2O3 thickness on Al:O stoichiometry to the electrical data. Hard x-ray synchrotron photoelectron spectroscopy shows a clear inverse correlation of the Al2O3 thickness with the intensity of the Ge +4 feature from GeO2 relative to that of elemental Ge at the interface.
The C-V curves measured for Pt/Al2O3/SiGe MOSCAPs after H2/N2 anneal have large frequency dispersion and Dit response. Experiments show that, even the native oxides of the SiGe channel are removed by 2% HF(aq)/DI-H2O cyclic cleans, a SiOx/GeOx interfacial layer is formed during Al2O3 ALD. In this unintentionally-grown oxide, ARXPS data show that an SiOx-rich layer is present at the interface with Al2O3, and the oxide is GeOx-rich at the interface with Ge. Using Al as gate metal instead of Pt, Al2O3/SiGe MOSCAPs show C-V curves with minimal frequency dispersion and much smaller Dit response. Soft x-ray synchrotron PES characterization of ultra-thin samples reveals that the Al-gated structures form at thicker Al2O3 layer and have only a SiO2–like interfacial layer. This suggests that Al scavenges oxygen from the underlying GeOX layer, producting a SiOX/SiGe interface with much reduced Dit.
9:15 AM - EP11.7.05
Passivation, Functionalization, and Nucleation of TiO2 on SiGe(110) for MIS Structure
Sang Wook Park 1,Jong Youn Choi 1,Naomi Yashida 2,Adam Brandt 2,Jessica Kachian 2,Evgueni Chagarov 1,Andrew Kummel 1
1 Univ of California-San Diego La Jolla United States,2 Applied Materials Sunnyvale United StatesShow Abstract
In order to overcome challenges when scaling down silicon-based complementary metal-oxide semiconductor (CMOS) devices, SiGe has received much attention due to its high carrier mobility and application in strain engineering. Extremely thin oxides with appropriate band offsets can be used to form unpinned contacts on SiGe for a metal-insulator-semiconductor (MIS) contact. TiO2 interfacial layers on Ge are known to form an MIS structure which reduces the tunneling resistance due to the nearly zero conduction band offset (CBO) between TiO2 and Ge. In this study, passivation, functionalization, and nucleation of TiO2 monolayer on SiGe(110) surfaces are discussed, using scanning tunneling microscopy (STM), scanning tunneling spectroscopy (STS), and x-ray photoelectron spectroscopy (XPS).
STM and XPS measurements verify a clean SiGe(110) surface is terminated with adatoms of both Si and Ge atoms. STS measurements indicate the clean (110) surface is pinned mid gap between the valence and conduction band edge due to the dangling bonds of adatoms. In order to passivate the dangling bonds, atomic H was dosed onto the clean SiGe(110) surface at 300°C and the surface was unpinned as demonstrated by STS measurements. The unpinned SiGe (110) surfaces were dosed with a saturation dose of H2O2(g) at room temperature leaving the H/SiGe(110) surface terminated with an ordered monolayer of both Ge-OH and Si-OH sites. STS shows that the Fermi level on the HOOH dosed SiGe(110) is shifted to near the valence band edge due to the formation of surface dipole from the hydroxyl bonds. TDMAT or TiCl4 was subsequently dosed on the HOOH/atomic H/SiGe(110) surfaces at 300K forming Ti bonds to surface. Both TDMAT or TiCl4 dosed SiGe(110) surfaces were annealed to 300°C and XPS measurements verify that Ti-O bonds are totally transferred from Ge atoms to Si atoms forming exclusive Ti-O-Si bonds on SiGe(110) surface consistent with the strong bonding between Si and oxygen pulling Si atoms toward the surface to bond with oxygen while pushing Ge atoms into the subsurface during the annealing. STM demonstrates an ordered monolayer of Ti-O-Si bonds is formed with a row spacing which is double the spacing between adatoms on the clean surface. In addition, STS indicates the Ti-O-Si/SiGe(110) unpinned and therefore can serve as an ideal template for further high-k oxide and MIS oxide deposition.
EP11.8: High K/Metal Gate and Ferroelectrics
Thursday AM, March 31, 2016
PCC North, 200 Level, Room 223
10:00 AM - *EP11.8.01
BTI Reliability of High-Mobility Channel Devices with High-k Dielectric Stacks: SiGe, Ge, and InGaAs
Jacopo Franco 1,Ben Kaczer 1,Abhitosh Vais 1,AliReza Alian 1,Hiroaki Arimura 1,Vamsi Putcha 2,Sonja Sioncke 1,Niamh Waldron 1,Daisy Zhou 1,Laura Nyns 1,Jerome Mitard 1,Hans Mertens 1,Marc Heyns 2,Guido Groeseneken 2,Naoto Horiguchi 1,Nadine Collaert 1,Dimitri Linten 1,Aaron Thean 1
1 imec Leuven Belgium,1 imec Leuven Belgium,2 KU Leuven Leuven BelgiumShow Abstract
Reliability and variability are becoming showstoppers for further scaled CMOS technology nodes. The traditional 10 year reliable operation cannot be guaranteed anymore at the single device level, mainly due to severe Bias Temperature Instability (BTI) in high-k gate stacks inducing both degradation of the average device electrical properties, and additional device-to-device variability. Meanwhile, the combination of finFET architectures with high-mobility channel materials is emerging as the frontrunner option to maintain the usual pace of performance enhancement in future technology nodes, opening new questions about device and material reliability.
We will present a review of our recent studies of BTI in different material systems, highlighting the reliability opportunities and challenges of each novel device family. We will discuss the intrinsic reliability improvement offered by SiGe and Ge pMOS technologies, if a Si cap is used to passivate the channel and to fabricate a standard SiO2/HfO2 gate stack. We will focus on (Si)Ge gate stack optimizations for maximum BTI reliability in planar and finFET device architectures, and on a simple physics-based model able to reproduce the experimental trends. This model framework will be then used to understand the poor BTI reliability and excessive time-dependent variability induced by oxide charge trapping in different high-mobility channel gate stacks as Ge/GeOx/high-k and InGaAs/high-k, independently of the considered device architecture (i.e., planar or finFET). Finally we will discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability and minimize time-dependent variability.
10:30 AM - *EP11.8.02
GeOx Free Interfacial Layer Formation and Its Impact on Physical & Electrical of Metal/High-k/ SixGe1-x Gate Stack
Shariq Siddiqui 1
1 Global Foundries USA Inc. Albany United States,Show Abstract
Silicon-Germanium (SiGe) and Ge semiconductors have been investigated in recent years as p-MOSFET channel materials to replace conventional Si due to their higher hole. Removal of poor quality native oxide and forming a stable interfacial layer (IL) prior to high-k deposition is critical in forming a high quality gate stack for SiGe/Ge channels. There are several techniques to remove the native oxide from SiGe and Ge substrates that include ex-situ wet chemical etching, in-situ chemical etching and thermal decomposition. In this work, a sequential cleaning method using dilute HF and HCl in a low O2 ambient (~30 ppb) was used to remove the native oxide. Controlling oxygen levels is essential to prevent the native oxide re-growth. A high quality interfacial layer was formed using an ozonated water (DIO3) process due to its high oxidation potential (E0 = 2.08 eV).
X-ray photoelectron spectroscopy (XPS) was used to study epitaxially grown un-doped SiGe films. Based on the Si 2p and Ge 2p3/2 surface sensitive XPS peak, it was determined that the IL consisted of mainly SiO2, GeO and GeO2 for all SiGe films studied in this work. The ratio of GeO to GeO2 was controlled by carefully choosing the DIO3 concentration and time for all SiGe films. Subsequent thermal annealing process was used to selectively remove GeOx component of IL, forming SiOx rich IL resulting in a higher quality interfacial layer between the SiGe channel and High-k dielectric. Interfacial layer thickness and band gap (Eg) was also measured using high resolution variable angle deep UV Spectroscopic Ellipsometer (SE). The IL thickness was measured to be ~ 13 Å for all SiGe films studied, whereas IL band gap decreased from 7.8 eV to 6.5 eV when Ge concentration increased from 25 to 75%.
The electrical characterization of HfO2/IL/SixGe1-x interface was conducted using pMOSFET gate last process flow. Characteristics such as hysteresis, leakage current density, and interface state density (Dit) were measured using C-V and I-V techniques. An excellent C-V curve with and without thermal annealing for with inversion layer (Tinv) values strongly dependent on DIO3 time were measured. Further scaling was achieved using carefully introducing nitrogen on top-most layer. Additionally, interface defect density (Dit) ranged between 3 to 6 x 1011 depending on SiGe concentration.
11:00 AM - EP11.8.03
Grain-Boundary Effect in Ferroelectric Field-Effect Transistor
Jaehyo Park 1,Seung Ki Joo 1
1 Department of Material Science and Engineering, Seoul National University Seoul Korea (the Republic of),Show Abstract
The nonvolatile memory technology with conventional floating-gate transistor is facing its poor electrical performance. Therefore, there are strong demands for new memory concepts to replace its contemporary technology. Ferroelectric field-effect transistor (FeFET) with metal-insulator-ferroelectric-semiconductor (MFIS) structure has been considered as a promising candidate for nonvolatile memory because of its scalability, low voltage operation; high program/erasing (P/E) speed, and non-destructive readout. In theory, the FeFET can obtain a nanosecond P/E speed with below 6 V of low-bias, while the conventional floating gate showed a millisecond P/E speed with over 20 V of high-bias. In addition, almost unlimited endurance P/E cycles in FeFET, while the convention floating-gate transistors showed maximum 106 endurance cycles. However, depolarization issue in the ferroelectric layer is retarding its potential to the industrial implementation. The depolarization problem is mainly originated from the grain-boundaries and loss of charge compensation in MFIS structure. Unfortunately, there were no significant solutions for controlling the grain boundaries or suppressing the charge compensation loss.
In this work, we have investigated the grain boundary effects in MFIS-FET fabricated by selectively nucleated lateral crystallization (SNLC) technique. The total structure of MFIS-FET was Pt/Pb(Zr,Ti)O3 (PZT)/ZrTiO4 (ZTO)/p-Si and the MFIS capacitor was formed on various grain boundary densities. The SNLC separates the nucleation and growth mechanism, which makes possible to control the grain size and grain boundaries. It was found that the role of grain boundaries seriously degrades the fatigue and retention characteristics originated from the gate leakage current. The leakage current of high grain boundary showed a high space charge limited current (SCLC) and Schottky emission current while the leakage current of free-grain boundary showed only Schottky emission current. It was observed that the Pb which is the main elements in PZT are absent at the grain boundaries. Thus, the absent Pb is possibly the leakage path for charges to be injected into PZT and eventually diminishes the polarization. Moreover, the Zr/Ti ratio in PZT film is very critical factor because it is directly related to hysteretic properties such as polarization, coercive voltage, and memory windows. Moreover, the absent of Pb in grain boundaries accelerates the electrical performance under hydrogen ambient annealing. Based on the grain boundary degradation effects in MFIS-FET, it is significantly important to grow a single crystal, single domain ferroelectric on Si. Having a free-grain boundary ferroelectric film might be a possible solution for realizing high performance FeFET for replacing the current floating gate transistors.
11:15 AM - EP11.8.04
TiN-Gated Ferroelectric BaTiO3 Devices on Si and Si1-xGex
Martin Frank 1,Lucie Mazet 2,Eduard Cartier 1,Hiroyuki Miyazoe 1,John Bruley 1,Catherine Dubourdieu 2,Vijay Narayanan 1
1 IBM T. J. Watson Research Center Yorktown Heights United States,2 Institut des Nanotechnologies de Lyon, CNRS, Ecole Centrale de Lyon Ecully FranceShow Abstract
Ferroelectric field-effect transistors (FeFETs) are attractive not only for long-term storage, but also as synaptic memory elements for neuromorphic computing or as logic devices with reduced sub-threshold slope over conventional metal-oxide-semiconductor FETs (MOSFETs). However, FeFET integration with silicon CMOS logic technology faces major hurdles, such as the low thermal stability of perovskite ferroelectrics against oxygen loss to the Si substrate and/or the gate electrode. The latter issue is conventionally addressed with noble electrode metals such as Pt or Au, but compounds such as titanium nitride employed in commercial high-k/metal gate logic technology would be preferred from an integration perspective. On the other hand, established CMOS technology elements have yet to be fully evaluated for potential benefits in a FeFET context. For example, ferroelectric properties depend on substrate strain, which could be imparted by Si1-xGex channels (biaxial strain) or embedded Si1-xGex source/drains (uniaxial strain).
To explore these issues, we have fabricated TiN-gated Si and SiGe channel MOS devices with BaTiO3 on SrTiO3 buffer layers grown via molecular beam epitaxy (MBE). We followed low-temperature capacitor and replacement gate transistor integration routes, as the ~1000°C thermal budget required for Si dopant activation would degrade the ferroelectric. A particular challenge when employing pre-patterned Si substrates with oxide isolation is the difficulty to use in situ reflection high-energy electron diffraction (RHEED) to monitor strontium surface coverage during the initial stages of growth, as required to ensure epitaxial registry.
We find that ferroelectric memory capacitor behavior on p-Si is achieved with, e.g., TiN-gated 10 nm BaTiO3 on 1.6 nm SrTiO3, despite a low degree of crystallinity as observed by XRD and TEM. Ferroelectricity is evidenced by a clockwise capacitance-voltage (C-V) hysteresis loop, ruling out trapping of Si majority carriers in the dielectric as a dominant factor. To further exclude ionic conduction, we confirmed that hysteresis is reversibly suppressed when approaching the bulk BaTiO3 Curie temperature of ~120°C, in line with the expected ferroelectric-paraelectric transition. Frequency- and temperature-dependent C-V characteristics indicate a density of Si interface traps similar to that of conventional SiO2/Si gate stacks. These results suggest that ferroelectric BaTiO3 memory devices can be fabricated successfully with the CMOS-friendly gate material titanium nitride.
We have further studied the impact of biaxially strained Si1-xGex substrates, oxidizing crystallization anneals, and gate metals (TiN vs. Pt) on ferroelectric properties. Finally, we describe a fabrication process for TiN-gated BaTiO3 T-gate transistors involving a sputter etch of the perovskites. Technical challenges and achievements will be discussed.
11:30 AM - EP11.8.05
Sub-60 mV/decade Subthreshold Swing in Negative Capacitance FinFET Devices
Asif Khan 1,Korok Chatterjee 1,Juan Duarte 1,Zhongyuan Lu 1,Angada Sachid 1,Sourabh Khandelwal, 1,Ramamoorthy Ramesh 1,Chenming Hu 1,Sayeef Salahuddin 1
1 UC Berkeley Berkeley United States,Show Abstract
Ferroelectric negative capacitor used as the gate oxide in a field-effect transistor (FET) could reduce the sub-threshold swing below 60 mV/decade at room temperature . Recently, negative capacitance phenomena have been experimentally verified in variety of systems: isolated ferroelectric films , ferroelectric-dielectric bilayers ,  and superlattices . Sub-60 mV/dec switching characteristics in various configuration of negative capacitance FETs have been demonstrated in a number of experiment with long channel MOSFETs , , , , . In this talk, we report extremely steep swings as low as 8.5 mV/decade over as high as 8 orders of magnitude of drain current in negative capacitance FinFETs (NC-FinFETs). Our results are different from early works in two ways: (i) our work demonstrates steep swings in both p-type and n-type negative capacitance short channel (Lg=100 nm) FinFETs (NCFinFETs) and, (ii) for the ferroelectric layer, we use an epitaxial, single crystalline ferroelectric capacitor. NC-FinFETs are constructed by connecting a high quality epitaxial Bismuth Ferrite (BiFeO3) ferroelectric capacitor to the gate terminal of both FinFETs. The external connection scheme allows us to compare the behavior of the ferroelectric when it is in an isolated state and when it is used as the gate oxide in a NC-FinFET. We also propose a general procedure to extract the effective “S”-shaped ferroelectric charge-voltage characteristics. The extracted ferroelectric behavior gives important insights into the behavior of the circuit–the most important one being that only a small fraction of the ferroelectric remnant polarization gets switched in a NC-FinFET due to the charge balance conditions in a series capacitor circuit. We also show that a self-consistent simulation scheme based on BSIM-CMG model and Landau-Devonshire formalism using the extracted ferroelectric parameters could quantitatively match the experimental NC-FinFET transfer characteristics.
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 M. Lee et al. IEEE Electron Dev. Lett., vol. 36, no. 4, pp. 294–296, 2015.
11:45 AM - EP11.8.06
Lock Coupled Polarization/Charge Coupling in Pt/BiFeO3/DyScO3/Si Non-Volatile Metal-Ferroelectric-Isulator-Semiconductor Device
Rohit Medwal 1,Surbhi Gupta 1,Shojan Pavunny 1,Rajesh Katiyar 1,Ram Katiyar 1
1 Department of Physics and Institute for Functional Nanomaterials University of Puerto Rico San Juan United States,Show Abstract
Ferroelectric materials based metal-ferroelectric-insulator-semiconductor (MFIS) devices offer the possibility to develop dense, energy efficient, fast and non-volatile ferroelectric random access memory (FeRAM) as a promising replacement to both dynamic random access memory (DRAM) and Flash technologies for the continued scaling. We investigated the polarization locking in the Pt/BiFeO3(BFO)/DyScO3(DSO)/p-Si<100> MFIS structure for non-volatile ferroelectric memory device applications. Here we attempt to shed light on spontaneous polarization coupling between the common interfaces of metal (Pt), ferroelectric (BFO), insulator (DSO) and, semiconductor (Si) in the MFIS device viz. Pt/BFO, BFO/DSO, and DSO/Si. Formation of depletion layers due to electric field induced polarization at the interface leading to asymmetry in the polarization loop is investigated in detail. Temperature dependent (ranging from 200 K to 400 K) direct current charge transport and the associated asymmetric counter-clock wise resistance modulation were analyzed to understand the effect of interface limited charge injection and accumulation on the polarization of MFIS structure.
Thursday PM, March 31, 2016
PCC North, 200 Level, Room 223
1:45 PM - *EP11.9.01
Theoretical Studies of the Switching Mechanism of the Topological Switching Memory (TRAM) Using Superlattice GeTe/Sb2Te3 Phase Change Memories
Kenji Shiraishi 1
1 Institute of Materials and Systems for Sustainability Nagoya University Nagoya Japan,Show Abstract
Superlattice phase change memory (superlattice PCM) consisting of (GeTe)2/Sb2Te3 stacked structure is one of the most promising candidates for next-genperation non-volatile memories and it has received considerable attention in recent years1-3. The memory operations are attributed to small structural change between two atomic configurations before and after switching. Therefore, the energy required for switching between lower and higher resistive states (LRS and HRS) is much lower than that of conventional PCMs utilizing phase transition between crystal and amorphous phases. We have found that atomic configurations of LRS and HRS are not stable but metastable.4 Accordingly, the superlattice (GeTe)2/Sb2Te3 PCM can do cyclic operations. However, the reaction pathway between LRS and HRS has not yet been clarified and the detailed analyses of the structural transition between LRS and HRS are prerequisites for fully understanding the switching mechanism.
We investigate the switching process of the superlattice (GeTe)2/Sb2Te3 PCM using the first-principles electronic-states calculations. The atomic structures and the electronic states were calculated by VASP (Vienna Ab-initio Simulation Package) code,5 which is based on the density functional theory with plane-wave basis sets, a PBE-type exchange-correlation functional6 and the projector augmented-wave method.7 For the calculations, k points of 8 x 8 x 4 Monkhorst-Pack grid8 were used and the cutoff energy was 500eV. VESTA (Visualization for Electronic and STructural Analysis) was used to draw atomic configurations and electronic states.9
In this study, we propose the fully structural transition process from the clue of the structural transition between LRS and HRS we have obtained.10 The atomic configurations are the intermediate states (ISs) during LRS-HRS transition. First, the centered Ge and Te atoms in the LRS move vertically, approaching to the IS with a honeycomb double layer. Next, each honeycomb layer in the double layer slides in different directions and rotates by 60 degrees. Finally, the Ge and Te atoms move vertically again, resulting in HRS. This is our scenario of the switching from LRS and HRS. The opposite process is the same.
This work was performed under the collaboration with LEAP and Hitachi. This work was funded by the “Ultra-Low Voltage Device Project" and supported by METI and NEDO.
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2 N. Takaura, IEDM Tech. Dig., 29.2.1-29.2.4 (2014).
3 R. E. Simpson, Nat. Nanotech. 6, 501 (2011).
4 T. Ohyanagi, Appl. Phy. Lett. 104, 252106, (2014).
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9 K. Momma and F. Izumi, J. Appl. Cryst. 44, 1272, (2011).
10 N. Takaura, VLSI Technology (VLSIT), T130-T131 (2013).
2:15 PM - EP11.9.03
Simulation Study on Reproducing Resistive Switching Effect by Soret and Fick Diffusion in Resistive Random Access Memory
Kentaro Kinoshita 3,Ryosuke Koishi 1,Takumi Moriyama 2,Kouki Kawano 1,Hidetoshi Miyashita 1,Sang-Seok Lee 1,Satoru Kishida 3
1 Tottori Univ Tottori Japan,2 Tottori Integrated Frontier Research Center, Tottori University Tottori Japan,3 Tottori University Electric Display Research Center Tottori Japan,1 Tottori Univ Tottori Japan1 Tottori Univ Tottori Japan,2 Tottori Integrated Frontier Research Center, Tottori University Tottori JapanShow Abstract
A filament (FL) model, in which a conductive FL consisting of oxygen vacancies (VO’s) is formed in the metal oxide (MO) film of an EL/MO/EL structure by a forming process and the resistive switching (RS) effect is caused by generation and repair of VO's, is widely accepted, where EL represent electrode. However, driving forces of VO migration that cause RS are unclear. Koh et al. reported that the oxygen reservoir of a Pt/NiO/Pt structure is the NiO film itself surrounding FL.1) Therefore, a driving force that is different from an electric field drift that is perpendicular to the EL interface is required to cause set switching. One of candidates for this driving force is the Soret force, which works in the direction of a temperature, T, gradient.2)
In this paper, we examined Soret diffusion as a driving force instead of electric field drift of VO's. We succeeded in reproducing pulse response data for wide rise time, trise, range by simulating VO migration assuming Fick and Soret diffusion as driving forces. The change of resistance is suggested to be decided by the relative magnitude of Fick and Soret diffusion.
RS was attempted by simulating VO migration using commercial software (COMSOL Multiphysics). We assumed Soret and Fick diff