Symposium EP12 : Materials Frontiers in Semiconductor Advanced Packaging

The semiconductor industry is entering a new era in which device scaling and cost reduction cannot continue Moore’s Law, a path that was followed for the past few decades. Development of advanced technology nodes requires high investments in new lithography equipment and technologies which ultimately is negatively impacting the cost. Cost continues to be one of the main market drivers, along increased performance, functionality and further reducing the form factor. While advancing the technology nodes continues, its long term future remains uncertain; alternative technologies continue to be investigated that can address the same market drivers however in a more economical way. Today, emerging packaging technologies such as fan-out and more advanced flip-chip packages as well as 3D stacking, have successfully shown to have the ability to bridge this gap and revive the cost/performance curve enabling, at the same time, higher integration and more functionality.
Advanced packaging segment currently has a wide range of platforms, from more mature ones but advancing, such as fan-in and flip-chip, to emerging platforms such as embedded technologies or vertically stacking devices using through-silicon-via interconnects. Innovations in both mature as well as emerging platforms are being brought to the market. They are driven either by the desire of expanding their existing and successfully implemented technologies, with already established processes, know-how and infrastructure, as would be the case for mature platforms, or driven by the need of addressing existing challenges through new emerging technologies.
The presentation will provide an overview of the different advanced packaging platforms having the highest growth (fan-in, flip-chip, embedded technologies, system-in-package and 3D Integration) highlighting current industry activities, innovations and technology trends. Applications driving the future growth of advanced packaging will be included, highlighting market trends and growth, positioning of each packaging platform within this segment and competing forces driving evolution of these platforms.

What drove electronics to what it is today is Transistor Scaling. But the emerging trend for smartphones, IOTs and wearables and all other small systems as well as new era in automotive electronics requires a new electronics system frontier and a set of new frontier materials to go with this new technology frontier. Georgia Tech proposes the new system technology frontier to be System Scaling enabled by scaling of system components and system interconnections. Such a frontier requires an entirely different set of materials to enable system functions that include digital, optical, thermal, RF, mm-wave, power and many others. This paper describes the need, the status of materials and new set of frontier materials.

Georgia Tech has been pioneering glass-based device and systems packaging for such systems scaling because of its many advantages such as dimensional stability, low loss, large-area panel-scale processability, surface smoothness, matched CTE with silicon, chemical inertness, etc. For power supply, quantum leap in storage densities is required enabled by nanosurfaces and a new era of inductors enabled by nano-magnetics. The fundamental limitations in the electromagnetic properties of traditional materials can be overcome with a new class of nanostructured dielectrics and magneto-dielectrics with enhanced permeability and permittivity, loss, frequency stability, thermal stability, linear behavior and tunability, all of which are critical for RF applications. These nanomaterials are now being applied to diplexers, antennas and EMI shields for simultaneous miniaturization and performance enhancement. Nanocopper-based interconnections, without solders, and yet assembled at low temperature, below 200°C, is the next wave of interconnections, assembly and reliability innovation.

In automotive applications, new era of electronics in autonomous driving and all-electric cars are driving the need for unprecedented material advances in high-temperature, high-power handling and ultra-high reliability.

Advanced packaging technology is one of the most critical technologies in semiconductor industry in recent years based on two reasons. Firstly, to continue drive device (or chip) scaling following Moore’s law is now more challenging than ever. Manufacturing cost increases rapidly so that the chip scaling becomes less viable economically. Chip partition plus system integration of multiple chips with a SiP, System-in-Package, advanced packaging technology, has been proposed to either replace or to be complementary to conventional chip scaling, to achieve system scaling. On the other hand, new semiconductor market demands driven by smart mobile computing, cloud computing and Next Big Things (wearable, IoT, etc) are pushing existing packaging technologies, such as wire-bonding, flip-chip, multi-chip-module (MCM) and package-on-package (PoP), beyond their limitation. Innovative advanced packaging technologies are desirable to meet future semiconductor market needs.

Very stringent requirements on maximized system performance (computation speed and memory bandwidth) with minimum consumed power, occupying smallest component area (or form factor), and using most competitive cost have to be fulfilled in order to meet the system demands described above. Leading wafer foundry has developed innovative wafer-level-system-integration (WLSI) technology platforms, which include wafer-level chip scale packaging (aka UFI), integrated fan-out (aka InFO) and 3D-IC with TSV (aka CoWoS) packaging technologies to meet the device requirements from low to high I/O pin-count applications. These advanced packaging technologies are using wafer form processes to achieve the critical performance, power, area and cost goal of system. In this paper, we will discuss the materials employed in those technologies and present their challenges and opportunities in the future.

The traditional, linear, open-loop model of consumption - “design it, build it, use it, throw it away, never think about it again” – has ceased being viable from scientific, economic, societal, and environmental points of view. Nowhere is the failure of this model more apparent than in global electronics. The rapid and global proliferation of cell phones, laptops, servers, and other electronic devices has connected the world in positive ways and on a scale that has narrowed the digital divide between developed and developing countries. However, the devices’ inherently short life and increasing consumer demand worldwide for devices with greater functionality have created a pattern for materials, manufacturing, and electronic product use that threatens their future sustainability.

Sustainability is not limited to issues of environmental impact and the availability of critical materials. Industrial/economic sustainability, societal sustainability, and environmental sustainability, known as the “triple bottom line,” are all required for a fully sustainable system whose stable state “meets the needs of the present without compromising the ability of future generations to meet their own needs." The electronics industry has begun to recognize its role in affecting global sustainability, actively working with NGO’s, governments, and academia to articulate what sustainability would look like for electronics. In this talk I will present the iNEMI Roadmap for Sustainable Electronics developed by the electronics industry, NGO’s, US government (Environmental Protection Agency & the Department of Energy), and universities. The Roadmap has ramifications not only for future electronic systems but also for the goals we have for our nanotechnology research and for our students. Examples from current electronic materials research for consumer electronics, high reliability electronics, and for cloud computing/server systems will illustrate some of the ways we can affect positive change.

Advanced semiconductor packaging technologies such as wire bonding die-stacked Chip Size Package (CSP), Package on Package (POP) and Through Silicon Via (TSV) have been of much interest because they provide the highest packaging density and electrical performance among all semiconductor packaging technologies. To make all these packaging technologies work, novel materials play an enabling role. In this talk, materials trends and challenges for advanced semiconductor packaging technologies are discussed in hope that more collaborations between industry and academia will occur to accelerate the innovations on materials.

In most of these packages the power semiconductors are connected by bond wires, resulting in large resistances and parasitic inductances. Power chip packages have to carry semiconductors with increasing current densities. Conventional wire bonds are limiting their performance. Today's power modules are based on DCB (Direct Copper bonded) ceramic substrates. IGBT switches are mounted onto the ceramic and their top side contacts are connected by thick Al wires. This allows one wiring layer only and makes an integration of driver chips very difficult. Additionally bond wires result in a high stray inductance which limits the switching frequency. Especially the use of ultra-fast switching wide-bandgap semiconductors, like SiC and GaN, is very difficult.

The embedding of chips offers a solution for many of the problems in power chip packages and power modules. While chip embedding was an academic exercise a decade ago, it is now an industrial solution. This paper will show today's available power packages and power modules realized in industrial production as well as in European research projects.
The presentation try to show what concrete form such systems may take in the industrial reality, what requirements these package types will be subjected to and where the development trends may lead in the future. This presentation addresses the impact of the ICs, materials, processes and end product requirements on packaging, interconnect technology, and assembly.

Die-attach method is one of the essential technologies to establish WBG power devises. There are several candidate materials developed in the past decade for WBG die-attach. Ag sinter joining has attracted much attention due to its excellent high temperature stability [1]. This paper reviews the current status of the Ag sinter joining and a new method utilizing film stress migration effect for bonding, so called as stress migration bonding developed by the present authors [2].
Sinter joining with micron-size Ag hybrid particle pastes provide a stable bonding structure at 200 °C without any applied high pressure. The presence of oxygen plays a key role in cleaning the surface of Ag at around 200 °C in air resulting in a successful low-temperature low-pressure Ag sintering joining. Ag can clean its surface around 200 °C in air atmosphere. The Ag hybrid paste lowers its resistivity even below 200 °C. This is a good news because the cost of the hybrid paste without any nanomaterial is much lower than the conventional nanoparticle pastes. At 200 °C, Ag coating provides the highest strength due to Ag sintering ability in air. Thus, Ag sinter joining can be benefitted from the presence of oxygen, which is a great advantage as compared with other sintering materials such as Cu.
Ag sinter joining provide a microporous interlayer, which has strong enough just after the fabrication and can provide stress relaxation between dies and substrates. The microporous structure may bring some concern about the long term microstructural stability at elevated temperature. Recently, it was shown that the Ag microporous structure can be effectively stabilized by adding a small amount of fine SiC particles. Excellent heat-resistance up to 250 °C was proved.
Recently, the Ag thin film stress migration bonding (SMB) method has been developed, providing a perfect bonding without any large voids performed in ambient pressure at 250 °C in air. This joining has two key aspects. One is the reduction reaction of Ag oxides or of other Ag compounds on the surface of Ag at around 200 °C as mentioned above. The other is thermo-mechanical stress caused by thermal expansion mismatch between Ag plating layer and substrates, resulting in massive stress migration of Ag atoms from the bottom of the plating to the surface.
The authors are grateful for the support from the Japan Society for the Promotion of Science (Grant-in-Aid for Scientific Research, Grant No. 24226017).

References
1.K. Suganuma, S. Sakamoto, N. Kagami, D. Wakuda, K. -S. Kim, M. Nogi, Microelectron. Reliab., 52, 375-380 (2012).
2.C. Oh, S. Nagao, T. Kunimune, K. Suganuma, Appl. Phys. Letters, 104, 161603 (2014).
3.D. Wakuda, M. Hatamura, K. Suganuma, Chem. Phys. Lett., 441, 305-308 (2007).

Engineered dielectric fluids are commonly used in liquid cooling systems to maintain a controlled operating environment in applications where forced air cooling is not efficient or feasible. In some liquid cooling systems, high-speed digital, mixed-signal, RF, or microwave components with high dissipated power densities are directly immersed into a pool or circulated dielectric fluids to maintain device temperatures within specification, and in many cases it is unavoidable that the packaging and integration components such as connectors, printed circuit board (PCB) launches and transitions are exposed to the dielectric fluid. To facilitate accurate component design and to understand the impact of the dielectric response of the fluids on system performance, the complex permittivity of these dielectric fluids has been characterized over relevant frequency and temperature ranges.

There are numerous applicable simulation and measurement techniques based on microwave structures to characterize dielectric fluids. In this work, a microstrip ring resonator fabricated on a low-loss printed circuit board is designed, simulated and measured for use in the characterization of three dielectric cooling fluids: 3M^TM Novec^TM 649, 3M^TM Novec^TM HFE-7100 and 3M^TM Fluorinert^TM FC-72. The ring resonator is composed of microstrip transmission line in a closed loop that is capacitively coupled to microstrip transmission line feed lines. Measurements are performed using an Agilent N5227A PNA network analyzer over a broad frequency range from 10 MHz to 50 GHz. The microstrip ring resonator is measured in air and fluids, respectively. Furthermore, the temperature of the dielectric fluid is controlled, to allow characterization at different temperatures. We use ANSYS HFSS, a 3D electromagnetic simulation tool, to provide simulated insertion loss data that is fit to the measured insertion loss. This fitting process provides a method to extract the frequency-dependent relative permittivity and loss tangent of dielectric fluids at different frequencies and temperatures.

We will present the methods and results of this work. We will describe the characterization mechanism of complex permittivity of the fluids using the microstrip ring resonator, measurement process and numerical fitting method using HFSS. We will also present and discuss the frequency and temperature dependence of the complex permittivity of the three dielectric fluids studied in this work.

One-dimensional (1D) materials like single-walled carbon nanotubes (SWNTs) and two-dimensional (2D) materials like graphene, h-BN, and transition-metal dichalcogenides (TMDs like MoS₂) have shown promising applications in electronics. In this context, their thermal properties remain an area of active investigation, particularly with respect to their anisotropic and potentially tunable thermal conductivity, the thermal conductance of their interfaces, and the heat flow in nanoscale devices comparable in size to the phonon or electron mean free paths.
We found that despite its great intrinsic thermal conductivity [1], heat dissipation can be a challenge in graphene transistors, where heat flow is limited by interfaces with adjacent materials and thermal transients are dominated by the surrounding layers [2]. In addition, when devices are scaled below ~1 μm, experiments and theory show that graphene thermal properties become dependent on the system size [3,4]. Conversely, device self-heating measurements can also be used to gain valuable information about the thermal properties of other 2D nanomaterials, such as WTe₂.
We also investigated the in-plane and cross-plane ballistic thermal conductance (G_b) of layered 2D materials based on full phonon dispersions. G_b is approximately one order of magnitude lower in the cross-plane vs. the in-plane direction due to weak van der Waals interactions between layers. We estimated the phonon mean free path of 2D materials, given G_b and the diffusive thermal conductivity [3,5]. We examined the size-dependent thermal conductivity and the ballistic to diffusive transition for a variety of anisotropic layered 2D materials. It is clear that most sub-micron devices and all sub-100 nm devices exhibit some degree of quasi-ballistic heat flow.
The cross-plane thermal transport in multilayer stacks of 2D materials can also be tuned by the reversible intercalation of a guest atomic species in the inter-layer space. By intercalating Li, we have found that the cross-plane thermal conductance of thin MoS₂ stacks can be tuned in real time (of the order of minutes) by over a factor of seven [6]. The Li atoms decrease the thermal conductance from the pristine MoS₂ value due to phonon scattering at Li sites and weakening of out-of-plane vibrational modes.
1D materials like SWNTs can also exhibit strongly tunable thermal conductivity in composites, by controlling the density of SWNTs and the density of their junctions [7]. In particular, we have studied the thermal properties of SWNT networks as a function of chirality (metallic vs. semiconducting) and we have found that chirality plays a lesser role for thermal properties than the individual SWNT lengths and overall junction density. Such SWNT composites exhibit thermal conductivity comparable to Al while having one-tenth the mass density [7].
These results broaden our understanding of thermal transport in 1D and 2D materials, and help us explore their applications for devices, thermal management, and packaging.


[1] E. Pop et al, MRS Bull. 37, 1273 (2012).
[2] S. Islam et al, IEEE Electron Dev. Lett. 34, 166 (2013).
[3] M.-H. Bae et al, Nat. Comm. 4, 1734 (2013).
[4] Z. Li et al, App. Phys. Lett. 105, 023107 (2014).
[5] Z. Li et al, APS March Meeting (2014).
[6] A. Sood et al, MRS Spring Meeting (2015).
[7] F. Lian et al, MRS Spring (2014).

With the current push for device miniaturization, device performance has become increasingly limited by extreme heat dissipation which can lead to materials degradation and device failure. As such, the exploration of new materials and architectures has become critical for better thermal management. In flexible electronics, the use of graphene has been actively explored as an active channel owing to its excellent mechanical pliability, electrical conductivity, and thermal conductivity (as high as 1500-5000 Wm^-1K^-1). Nonetheless, unmitigated heat localization at the graphene-substrate interface remains a technical challenge. Recently, the use of dielectric 2D materials, such as hexagonal boron nitride (h-BN), has been proposed as a means to limit heat transfer through the c-axis of graphene-based heterostructures while promoting heat spreading through the lateral direction. To understand the potential benefits and limitations of these architectures, we use a combined first-principles and classical molecular dynamics approach to identify the most important descriptors that influence the anisotropic thermal transport in 2D heterostructures on amorphous SiO₂, Al₂O₃ and polyimide substrates. Our specific interest is in exploring the relationship between the interfacial interactions and the evolution of the interfacial morphology. In turn, the cross-plane thermal transport, which depends upon the phonon coupling across the interface, is strongly dependent on the interfacial morphology. Our analysis identifies the inhomogeneity of the applied force distribution, primarily determined by the surface roughness, as an important driver for the reduction of the anisotropic thermal conductivity of supported graphene.

Polyethylene terephthalate (PET) is an interesting substrate material for many applications in electronics. It has excellent mechanical and electrical properties which fulfil the needs of the most applications requiring flexible substrates. Furthermore, its price is low compared to commonly used polyimide (PI). The major disadvantage of PET is its low glass transition temperature, Tg, which markedly restricts its use in applications requiring soldering. However, low temperature lead free solders such as tin-bismuth can be used with PET. Due to its good properties there is an increasing interest to use PET material also in applications which are used under harsh environments. For example PET has been widely used to attach LCD displays in industrial electronics. These environments may consist of both high temperature and high level of relative humidity (RH). Under such conditions the tendency of polymers to absorb moisture commonly impairs both their electrical and mechanical properties which may be a critical reliability factor for flexible printed circuit board (PCB) materials. The effects of moisture are accelerated at increased temperatures which may cause marked reliability problems especially under harsh conditions. PET has lower absorption of moisture than PI. However, above its T_g, PET is vulnerable to hydrolysis which may restrict is use considerably. Hydrolysis breaks the molecular structure of PET and makes the material mechanically unreliable.

In this study the behaviour and reliability of PET under high temperature and high humidity was studied for various flex PCB applications. In order to study the degradation process of PET films a study was made with neat PET films. The films were tested at 85°C and 85 % relative humidity (RH) for 6,000 hours. After 2,000 hours of testing the films became fragile and could not be handled anymore. An important factor for this behaviour was found to be the hydrolysis of the ester groups in PET. It was also seen that the modulus of elasticity decreased during aging and the crystallinity of PET samples increased during aging. After 6,000h of testing marked changes were seen in the FTIR spectra of the PET films especially in the bands related to the ester structure of PET.

In addition to the neat films, two different products with PET films were also studied. The first was LCD display and the second was radio frequency identification (RFID) tags. Four environmental tests were used to study the structures: constant humidity tests of 65°C/90%RH and 85°C/85%RH and humidity cycling tests of 10°C-65°C/90%RH (condensation test) and 10°C-85°C/10%-85%RH (humidity cycling test). Both 85/85 test methods made PET very brittle and led to cracking of the PET flex thereby causing failures. No PET related failures were seen in the tests conducted at 65°C although long test duration of 5,000h was used.

Abstract: In the present era of big data and internal of things (IoT), the use of electronic devices in all aspects of our daily life is manifested by the ubiquitous presence of mobile devices such as i-phones and wearable consumer electronic products. To overcome the challenges coming from the need for greater functionality, higher power, and smaller form factor, 3D IC packaging technology for mobile devices has been developed for more than ten years. Mass production of 3D IC devices is behind schedule due to cost because of low yield and uncertain reliability. Electronic industry is introducing 2.5D IC and 3D IC devices in mainframe computers, where cost is not an issue, for the purpose of collecting field data of failure, especially on electromigration. In this talk, the effect of Joule heating on enhancing system level electromigration failure in mobile devices will be presented.

The presence of defective native Cu-oxide has long been a challenge for the microelectronic packaging industry owing to its detrimental effects on adhesion, moisture sensitivity and stress migration. Here we show a low-cost, single-step, sol-gel process that is capable of simultaneously reducing the weak native Cu-oxide while depositing a densely connected hybrid-layer. With this hybrid layer, a marked 9-fold improvement in adhesion at the Cu/hybrid-layer/epoxy interface was observed, along with a substantial decrease in stress-migration rate of Cu during isothermal stress-relaxation experiment. Enhancement in interfacial adhesion at the Cu/hybrid-layer interface and the improvement in stress-migration performance were attributed to the partial reduction of the 2 nm native Cu₂O layer as demonstrated by high-resolution bright-field TEM imaging. The hybrid-layer strategy we developed is expected to be effective in reducing stress- and the related electro-migration behavior of Cu as well as in being a candidate for adhesion improvement to Cu.

Electromigration is an important phenomena that often leads to catastrophic failure in electronic devices. With this in mind, new electronic materials and processing techniques are often tested at high current density and at elevated temperatures in order to determine if electromigration is a problem and how the material or process should be adjusted to mitigate this harmful phenomenon. Recent advances in processing and inks have shown that additive manufacturing can be used in microelectronics with immediate applications in photovoltaics, wearables, sensors, stretchable electronics, and next generation package-as-the-system technologies. However, little is known regarding the long-term reliability of these materials, when they fail, and why they fail. These questions must be addressed before additive manufacturing can be used for advanced packaging applications.

This paper details an investigation on electromigration of Ag and Cu conducting lines printed using self-reducing or "reactive" inks to show how processing parameters can be adjusted to improve device performance and lifetime/reliability. The impact of substrate temperature, ink composition, solvent type, ink dilution, and number of layers on grain size, physical structure/morphology, porosity, resistivity, lifetime, and activation energy are detailed. Structures were printed using drop-on-demand printing and characterized using scanning electron microscopy, x-ray diffraction, energy dispersive x-ray spectroscopy, 4-point probe, and high current density tests at elevated temperature.

This work shows that Ag and Cu reactive inks and printing procedures can be designed to produce conductive lines with excellent conductivity and excellent reliability.

With the trend of big data and internet of things (IoT), mobile device is becoming indispensable in our daily life. Advanced 3D IC packaging technologies which enable broad applications with wider data bandwidth, faster response, lower power consumption, and smaller form factors are in demand. The new packaging elements in 3D IC are through-Si-Vias and microbumps. The latter is being reduced to 20 μm and may approach 1 μm in the future. The effect of shrinking solder joints size on interfacial reaction between Cu and Sn has little been studied. In this report, we prepared different size of Sn on Cu substrate, with diameter changing from 1 μm, 5μm, 10 μm, 20 μm, to 30 μm. We annealed the sample at 180 ^oC, 200 ^oC and 220 ^oC to study intermetallic compound (IMC) Cu₆Sn₅ growth kinetics. We found that the smaller size of Sn/Cu joints has a faster IMC growth rate. A kinetic model will be presented to analysis the faster IMC growth rate in smaller size solder joints.

The physical properties of intermetallic compound (IMC) have received much attention lately because the trend of miniaturization in microelectronic silicon technology has been extended to packaging technology. For example, solder joints (μ-bump) are being reduced to 10 µm in diameter. The reduction has greatly increased the fraction of IMC in the solder joint.

The three most important IMCs in electronic packaging technology are Ni₃Sn₄, Cu₆Sn₅, and Cu₃Sn; there are many publications on their basic properties such as conductivity, thermal expansion coefficient, hardness, Young’s Modulus, and interdiffusion coefficient, except the intrinsic diffusivities. We recall that in an alloy, instead of an IMC, the traditional way to determine the intrinsic diffusivities is through Darken’s marker motion analysis and Boltzmann and Matano’s analysis of interdiffusion. This classical approach needs to measure the concentration profile or gradient across the alloy; however, in a layer-type intermetallic compound the concentration gradient is near zero because we assume a stoichiometric IMC. To overcome the problem, we adopt the Wagner diffusivity, which takes into account the chemical effect of energy of formation of IMC and it replaces the immeasurable parameter by a measurable one.

To further illustrate the chemical effect, we did the XPS and the First principle simulation on the IMC. The results imply the hybrid bonding nature for Ni-Sn in Ni₃Sn₄, which explains the large Gibbs free energy decrease when forming the IMC because covalent bond is stronger than metallic bond.

Through silicon vias (TSV) are vertical interconnects inside silicon (Si) substrates that enable the electrical communication between stacked components in modern 2.5 D/3D microelectronic systems. TSV are typically fabricated by deep etching of Si for vertical holes formation, followed by dielectric layer deposition on the sidewall of the vertical holes and then conductive material filling. In the first time, the vertical holes on Si are typically formed by deep reactive ion etching (DRIE). However, DRIE suffers from the high cost, limited throughput and scalloping of sidewalls.
Metal-assisted chemical etching (MaCE) is a novel wet etching technology for high-aspect-ratio micro- and nanostructures. MaCE is inherently low-cost and able to produce ultra-smooth sidewall. The smoothness of sidewall is critical for the high performance of TSV. In this talk, recent results of MaCE in fabricating deep vertical holes for TSV application will be presented. The physicochemical process during etching, including the mass transport and charge transport, will be addressed and the mechanism of MaCE with high geometric uniformity will be illustrated. Preliminary data of MaCE for high-volume-production of TSV will be shown. The compatibility of MaCE with other processes in TSV fabrication flow as well as 3D spiral etching of silicon for potential photonic crystal applications will also be discussed

FOWLP(Fan-out Wafer Level Package) is one of the potential packages which bring lots of advantages . The technologies had been mainly established by using liquid materials for packaging so far. Recently the activities of developing various kinds of assembly method, package structure is actively ongoing. Production using EMC(Epoxy Molding Compound) has already started in some semiconductor makers, but the evaluations of EMC which is lower-cost than liquid encapsulation for anticipated FOWLP will increase rapidly. In addition, examination that to become 12inch of the wafer size, and a huge panel increases the number of the package by becoming it and lowers the cost is performed at the same time, and the control of the warpage becomes severer. Because we examine it zealously to perform the warpage control of the molding wafer or panel to become large size, and we achieved warpage less than 1mm by combining various kinds of technologies, we report it here.
It is important that we make chip shift small during the package assembly. Because we found that we can make chip shift small by bringing CTE of EMC and CTE of carrier close, we report it.
In addition, it is considered for Next-generation FOWLP to build the both side RDL, and there is a process to grind EMC. When we grind EMC, it is important how we control filler drop and surface roughness. Because we investigated the influence that filler content and filler size, resin type, Abrasive grain gives to abrasion characteristics, we report it.
We go for not only the development of the EMC but also the development of RDL. Therefore combination of both materials examination is possible and reports some combinations examination example here.

Several electronic applications must withstand elevated temperatures during their life-time. Materials and packages for high temperature use have been designed, but they are often very expensive, have limited compatibility with materials, structures and processing techniques and are less readily available than more commonly used organic materials. Electronics industry would benefit from commercially available polymer materials designed for lower temperatures which could, however, reliably withstand elevated temperatures above the typical microelectronics temperature limit of 125°C. Thus there is an increasing interest to use low-cost polymer materials in high temperature applications.

Polymer-based substrates are very commonly used in electronics. Polyimide (PI) substrate is a popular choice when high temperatures are present. PI substrates typically consist of copper foil which is laminated onto the flexible PI base film with a thin adhesive layer. The properties of the adhesive layer are commonly inferior to those of the PI base film and may considerably impair the performance of the substrate. Nevertheless, adhesiveless PI substrates can also be manufactured to overcome the problems related to the adhesives layer. In addition to the organic substrate materials, electrically conductive polymer adhesives (ECA) have been widely used as attachment materials between components and substrates. ECAs are composite materials consisting of polymer matrix which is inherently insulator and conductive particles which have been added to the matrix to ensure electrical conductivity for the material. In anisotropic conductive adhesives (ACA) the concentration of the conductive particles is low and after bonding the adhesive conducts only in z-direction. Advantages of ACAs include absence of lead and flux residues, small number of processing steps, fine-pitch capability and compatibility with many substrate, chip and metallization materials. ACAs are typically thermosets with relatively low glass transition (T_g), and high coefficient of thermal expansion (CTE) values above T_g which may cause problems when used at high temperatures. The reliability of ACAs at high temperatures has not been widely studied. It has been mainly assumed that they are not suitable.

In this study bare silicon test chips were attached on adhesiveless polyimide substrate with ACA. The performance was studied in three high temperature storage tests (180°C, 200°C, 240°C) by measuring their resistances in real-time during testing. Additionally, some samples were removed from the chamber after certain periods of time (60h, 120h, 480h) for cross-sectioning. These samples were used to study the progress of possible corrosion of the materials due to high temperature. The results were studied using statistical methods and in-depth failure analysis was conducted. Additionally, the results were compared with our earlier results of chip structures on PI substrate with adhesive layer.

Microbumps are widely used to interconnect through-Si-vias (TSVs) to enable 3D-IC packaging. The diameter of microbumps is about 10 μm, whereas it is 100 μm in C4 (controlled-collapse-chip-connection) solder joints. As the volume of microbump is 1000 times smaller than that of C-4 joint, under a similar processing condition of time and temperature, microbumps can be completely transformed into IMCs of Cu₆Sn₅ and Cu₃Sn. However, mechanical property of IMCs-joint is barely known but it is expected to be brittle.

In this study, Cu-solder-Cu micro-joint was reflowed at 240 degree C from V-groove in aluminum fixture for mechanical testing, with micro-joint thickness smaller than 10 μm to mimic the diameter of microbumps in 3D IC. Thermal ageing at 120 degree C, 150 degree C and 180 degree C was conducted up to 1000 hours to completely transform Cu₆Sn₅-dominated micro-joint into Cu₃Sn-only micro-joint. Kirkendall void formation and coalescence in Cu₃Sn-joint are microstructurally monitored in real time during annealing. Micro-tensile tests for Cu-Cu₃Sn-Cu joints with embedded Kirkendall void were conducted to measure the degraded adhesion strength due to Kirkendall void growth. Kinetic analysis for IMC-joint phase transformation will be provided.

For as-reflowed micro-joint with joint thickness less than 10 μm and no remaining solder left, aggressive thermal storage was performed at 210 degree C, which is less than the melting point of SAC 305 solder. Accelerated void growth with porous morphology was found along Cu₃Sn/Cu₆Sn₅ interface accompanying void coalescence to relieve surface energy. The as-reflowed Cu₆Sn₅-dominated micro-joints can be completed transformed into Cu-Cu₃Sn (non-porous)-Cu₃Sn (porous)-Cu₃Sn (non-porous)-Cu sandwich structure. The severe degradation of adhesion strength of porous Cu₃Sn-containing-joints was evaluated by micro-tensile test as a function of time. In addition, the precise engineering strain of micro-joint will be measured by video extensometer. The fracture surface and cross-section of porous joints will be respectively studied by high resolution SEM (scanning electron microscope) and TEM (transmission electron microscope). The underlying mechanism of porous Cu₃Sn formation in micro-joint will be given.

Sensor components are used increasingly in various applications. The structure of a sensor component often differs from that of a typical silicon chip used in electronics, which may make their attachment and packaging challenging. Electrically conductive adhesives (ECA) may be used in many applications which have such restrictions. They consist of polymer binder, into which conductive particles are added. In anisotropic conductive adhesives (ACA) the concentration of conducting particles is low and they conduct electrically only in a vertical direction after the attachment process. ACA films (ACFs) are often used in flip chip technology, in which a bare chip is attached directly onto a substrate.

One of the main advantages of ACFs is their low process temperature. This enables their use in many applications. Furthermore, they can be used with many different structures and contact materials. ACF materials have commonly been used in electronics applications, for example in display and radiofrequency identification (RFID) attachments. However, as ACFs are very versatile materials, the interest to use ACFs in sensor applications has increased.

In this study capacitance-based humidity sensor chips were attached onto two different substrates using ACF flip chip technique. Due to its structure the sensor chip had several restrictions in its attachment methods. For the measurements two contacts were manufactured on the sensor chip. However, one of the contacts had to be processed on top of a thin polymer film while the other could be processed directly on the chip substrate. Consequently there was a variation of some 2µm between the heights of the contact areas. Both contact areas had gold coating. No bumping or soldering could be used with the chip. Because of this flip chip technique with ACF was used as the attachment method. To study the effect of attachment pressure three different pressure values were used. Two substrates, a thin FR-4 and a flexible polyimide (PI) substrate, were used A test structure was designed for the sensors, so that the electrical resistance of their interconnections could be measured to monitor their behaviour.

Effect of harsh humidity conditions on the sensor interconnections was studied using a constant humidity test. The test temperature was 85°C and relative humidity 85%. The overall test duration varied from 10,000h to 13,000h. During testing the electrical resistances of the samples were measured in-situ. The resistance values with FR-4 were found to be very stable during testing. Three samples out of 32 failed during the test. The reliability with PI substrate was also found to be excellent, when suitable attachment pressure was used. Consequently, the studied structures were found to be extremely stable under prolonged humid conditions. The results showed that ACF flip chip technique is suitable attachment method for the studied sensor structure.

This paper discusses the impact of substrate temperature, dilution, and ink composition on the electrical and physical properties of low-temperature, self-reducing copper inks. Printable metal inks made from organometallics and metal-salts have made significant advancements over the last few decades with steady decreases in reduction temperature and increases in material quality (lower resistivities, lower porosity, etc.). Recent advances in self-reducing or “reactive” inks, that combine a metal salt with a reducing agent have brought reactive ink reduction temperatures to less than 200 °C or even room temperature.

In this paper, we examine Copper (II) Formate based inks, adjusting ligand type, concentration, solvent properties, and overall dilution to explore the kinetics of the reduction process. These kinetics are tied to the composition and physical morphology of the printed copper and ultimately the electrical properties of simple lines and pads. The physical structure is characterized using X-Ray Diffraction (XRD), Atomic Force Microscopy (AFM), and Scanning Electron Microscopy (SEM) with elemental composition established using Energy Dispersive x-ray Spectroscopy (EDS). Resistivity and electrical performance is characterized using 2-point and 4-point probe techniques. This work shows that high purity, high quality copper can be directly printed from copper reactive inks using drop-on-demand techniques.

An integrated circuit board (IC board) is one of the greatest progress in the electrical industry, and is crucial component in electrical devices in current era.^[1,2] Copper clad laminates (CCLs) are key base material for IC board, consisted of polymeric matrix, glass fabric and copper layer. The material conventionally used for polymer matrix of CCLs are epoxy resins due to their acceptable dielectric and thermal properties. However, modern electrical devices need high speed information transfer at high frequency, there have been increasing demand on high performance CCLs (HPCCLs) having lower dielectric constant (Dk) and dissipation factor (Df) with higher thermal stability.^[3] Herein, we fabricated siloxane-based polymer materials using peroxide-derived radical polymerization of vinyl methyl phenyl oligosiloxane (VMPS) resin. The VMPS resin was synthesized by sol-gel condensation between vinylmethyldimethoxysilane and diphenylsilanediol. Composition of siloxane and peroxide catalyst with curing processes were optimized to obtain low dielectric constant and loss. The optimized phenyl siloxane-based polymer material shows low dielectric constant (Dk≈2.75 @ 1GHz) and, especially, low dissipation factor (Df≈0.0013 @ 1GHz), maintaining in high frequency (up to 10GHz) and high temperature range (up to 300^oC). In the VMPS, high content of rigid phenyl groups are introduced, along with bulky siloxane structure that increases free volume, in order to decrease dielectric constant and dissipation factor of the final product. The fabricated CCLs shows superior dielectric and thermal properties compared to the FR-4 laminate, the conventional epoxy laminate for CCLs, along with flame resistance without any addition of halogenated or phosphorus flame retardant.

[1] J. LaDou, Int. J. Hyg. Environ. Health 2006, 209, 211.
[2] R. Gao, A. Gu, G. Liang, S. Dai, L. Yuan, J. Appl. Polym. Sci. 2011, 121, 1675.
[3] A. Takahashi, Y. Satsu, A. Nagai, M. Umino, Y. Nakamura, IEEE Trans. Electron. Packag. Manuf. 2005, 28, 163.

Alkyl chains in the conjugated polymers are relevant factors with polymer solution processability and intermolecular interaction. Linear alkyl chains lead to polymer stacking closer and attribute to improve charge carrier mobility, but these have a limit the gain high molecular weight because of poor solubility. The branched alkyl chains show enough solubility in common organic solvent than linear alkyl chains, but these also have a disadvantage to intermolecular interaction by steric hindrance from freely rotate alkyl chains. To compensate both alkyl chains defects, we synthesize that replacing commonly employed 2-ethylhexyl (2EH) solubilizing groups with branched 5-ethylnonyl (5EN) chains not only improves solution processability to PCDT-BT polymer, but also induces an advantageous change in polymer self-assembly and backbone orientation in thin films that correlates with an increase in transistor performance.

We report a new CVD-based graphene growth process which is potentially applicable for the cost-effective production. The growth time is significantly reduced for synthesizing large-area monolayer graphene film on copper substrate. The precursor used in the experiment is isoprene, which is inexpensive and easy to handle. The physical morphology and layer configuration of the synthesized graphene domain can be controlled from monolayer four-lobe growth to hexagonal growth and to bilayer growth--through adjustment of key processing conditions. Excellent growth repeatability is demonstrated in the new process. Electronic measurements were conducted to further explore the material quality of the grown graphene samples.

Significant advances have been made in organic semiconductor materials and process developments for printed transistors. The field-effect mobility of organic thin-film transistors (OTFTs) have progressed from gross performance deficiency over a decade ago to meeting application requirements today. This quantum leap in OTFT performance has been propelled by both creative semiconductor design and process innovation. Notwithstanding these achievements, there remain significant technical challenges for translating printed transistors from laboratory to marketplace.
This presentation discusses the issues and challenges of printed transistors, and potential approaches to circumventing these difficulties. Particular emphasis will focus on our process strategy directed to facilitating molecular self-assembly of polymer semiconductors in ambient conditions to enhance their charge carrier transport efficacy. Through simple solution processes, we have been able to drive molecular ordering of polymer semiconductors from low to high crystalline orders, leading to greatly enhanced field-effect mobility.

Various kinds of thin film organic semiconductor devices, including organic transistors, organic photovoltaic cells, and organic light-emitting diodes, have been fabricated on ultrathin plastic films with the thickness of one micrometers. These devices exhibit amazing conformability and bending durability, which are utilized to create novel health-monitoring sensors that can be directly laminated on the surfaces of human skins. The major remaining issues of these ultrathin-film devices are interfaces to establish reliable electric connections and encapsulations. In this work, we report recent progress of interfaces and encapsulations related to ultrathin organic devices. Especially, Au electrodes prepared on one micrometer thick parylene films are pressed by Au electrodes on parylene to obtain reliable interconnections. Mechanical durability of these interconnections was systematically examined by bending and stretching cyclic tests. This work is financially supported by JST/ERATO Bio-harmonized electronics project.

Stretchable and flexible electronic devices have gained significant attention in recent years, as they can be integrated into many systems such as medical sensors, displays, and robots. One of the primary areas of research is designing stretchable interconnects which provide adequate conductivity and mechanical robustness. Metal-based interconnects have been reported to have the highest conductivity, but are not stretchable enough, while elastomer interconnects are not conductive enough. In this paper we report a silver polymer blend that provides excellent conductivity and good stretchability and flexibility.
The blend was prepared by dispersing silver flakes in a Polyvinyl alcohol (PVA) and poly(3,4-ethyl-ene-dioxythiophene) (PEDOT): Poly(styrene sulfonic acid) (PSS) polymer mixture. Silver was chosen as it has the highest conductivity of all metals. PVA is a water soluble polymer and imparts high stretchability to the blend. The novel approach that was taken was the addition of PEDOT: PSS in the blend. PEDOT: PSS is a conductive polymer, which is used in many electronic applications. The PEDOT:PSS provides conductive pathways between the silver flakes, leading to the blend’s superior electrical properties. The addition of PEDOT:PSS also improves the stretchability of the PVA. The conductivity of the blend is further improved by the addition of ethylene glycol to the solution mixture.
The optimization of the above mentioned process will be presented in detail. The electrical properties of the prepared blend sample were measured using the four terminal method, while the mechanical properties where tested using a Materials Testing System. The observed results from these tests will also be presented.

In August 2015, the Department of Defense announced a $171M Cooperative Agreement with FlexTech Alliance to establish a Flexible Hybrid Electronics (FHE) Manufacturing Innovation Institute, subsequently named NextFlex. Based in San Jose, CA, the mission of NextFlex is to catalyze a domestic manufacturing ecosystem in FHE, with an initial focus in human performance monitoring/wearable medical devices, structural health monitoring, wideband array antennas, and soft robotics. The presentation will emphasize NextFlex’s five manufacturing focus areas, which include device integration & packaging, materials, printed flexible components & microfluidics, modeling & test, and standards, testing, and reliability.
Established as a public-private partnership, NextFlex brings together resources from the federal government, state and local governments, companies, universities, and non-profit entities to enable state of the art manufacturing technology for areas critical to both the military and commercial sectors in the United States. The Institute will execute project calls in which its company and university members partner to advance the technology and manufacturing readiness levels (TRLs and MRLs) related to its mission. With a TRL/MRL entry point of 4, NextFlex aims to leverage the R&D investment at federal labs, universities, and companies by maturing select technologies to TRL/MRL 7, at which point they are commercially viable. NextFlex also includes an education and workforce development initiative, with goals of training and retraining a domestic workforce in FHE manufacturing, which includes K-12 STEM outreach efforts, the development of curricula in 2-yr, 4-yr, and graduate programs, and tools for companies to retrain their existing workforce. NextFlex is also standing-up a hub facility in San Jose, CA, which will provide members and non-members access to state-of-the-art FHE manufacturing and characterization facilities as well as the opportunity for prototyping or low-volume manufacturing services.
The first NextFlex projects are expected to be awarded in early 2016 and will be discussed during the presentation. Approx. $5M will address manufacturing challenges related to the packaging and integration of sensors for personal health and asset monitoring devices. Each project is expected to bring together an industrial-academic team, which will provide at least 1:1 cost share for the DoD funds. An update will also be provided on the Institute’s Education & Workforce Development Initiative and on the status of prototyping and low-volume manufacturing hub. Finally, the NextFlex roadmap process will be discussed, with a description of how NextFlex’s investment strategy is determined, including upcoming project call opportunities.

Pure silica dioxide (SiO2) has intrinsic properties that make it ideally suited for many applications. The combination of low dielectric constant, high processing temperature capability, high transmission over a wide wavelength range, and chemical inertness make it suitable for a range of applications in the semi-conductor industry as a substrate of choice in product and process research. The availability of this material in extrinsic formats suitable for manufacturing has been elusive, however. A new process by Corning, Inc. has provided a means to fabricate this material in thinner sheet and larger format than in conventional processes. The nominal thickness in current work is 100 microns in a sheet format of 150 mm x 150 mm. Larger width, continuous ribbons of glass are the process direction as well as multiple layers of silica or multiple component doped silica. It is expected that these materials in a manufacturing friendly format will enable advancement of the state of the art in product production.

This paper discusses the kinetics, mechanical, and electrical properties of drop-on-demand printed SiO₂ dielectrics from sol-gel precursors. With the semiconductor industry beginning to adapt additive manufacturing techniques for wearables, sensors, and flexible electronics, there is a need to develop inks that print high quality materials at low temperatures. Drop-on-demand printing of sol-gels has been used to study the rheology and kinetics of sol-gel hydrolysis and solidification. However, there is little work on the mechanical nor electrical properties of these structures when printed from extremely dilute solutions and at low temperatures (< 200 °C). This paper details the kinetics of drop-on-demand printed sol-gel to show that high-quality SiO₂ films can be printed at reasonable temperatures as long as the drying process is well controlled and the ink is thin-enough to let excess solvent and products rapidly diffuse through any SiO₂ formed at the air/liquid interface of the droplet.

A custom printhead was used to print siloxanes-based sol-gels. The impact of substrate temperature, solvent viscosity, solvent vapor pressure, droplet size, and siloxanes on the, composition, morphology, mechanical properties, and dielectric properties of the printed SiO₂ layers are detailed. The relationship between evaporation, droplet fluid flow, particle aggregation, and the hydrolysis kinetics were simulated using Comsol Multiphysics to establish how the SiO₂ hardens when ultra-thin layers are printed.

Advancement in conventional microelectronics technology has been extensive over the past few decades with component size decreasing exponentially. As component sizes have decreased, new models for packaging have immerged with the microelectronics industry rapidly adopting System-on-a-Chip (SOC) approaches, where multiple functionalities are combined into a single chip. The processing chips in today’s “smart phones” provide a good example where CPU, GPU, and even motion processing, are integrated onto a single die. There are some applications that do not lend themselves to integration at the chip-level, for example, recent lab-on-chip biomedical sensors use discrete components to sense environment and transmit data. Many of these devices require electronics spread over a large area with sensors in one location transmitting data to a processing unit in another location and then transmitted through an antennae circuit elsewhere. For “hard” devices, like our smart phones, this is not a problem; however, for new flexible and stretchable electronic devices, spanning large distances while maintaining electrical contact can be difficult. These devices, ranging from flexible display panels to health sensors, require that any hard components be connect by flexible and deformable electrical interconnects so that the device can conform to its intended surface, such as the human body.

This work details a simple set of processes and chemistries to connect separate chips, or “islands,” by printing free-standing stretchable interconnects based upon recent serpentine designs. For this work, a low-temperature, self-reducing Ag ink was used as the basis to print high-quality silver interconnects. Unlike traditional particle-based inks that effectively print clusters of loosely connected particles, reactive inks print chemical reactions that, if properly designed, produce a high-quality material with excellent material properties. These inks (also known as self-reducing or organometallic inks) can be easier to synthesize than nanoparticle ink and can be designed to react at lower temperatures.

Serpentine stretchable interconnects were printed between two copper islands 10 mm apart using reactive silver inks. Samples were repeatedly cycled up to 180% with no degradation in mechanical nor electrical performance. Numerical simulations agree with experimental results in both deformation shape and an ultimate elongation of 200% was observed. This work demonstrates that island interconnects can be readily fabricated at low cost and efforts using a combination of drop-on-demand printing and reactive inks.