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spring 1997 logo1997 MRS Spring Meeting & Exhibit

March 31 - April 4, 1997 | San Francisco
Meeting Chairs: Linda G. Griffith-Cima, David J. Eaglesham, Alexander H. King

Symposium J—Materials Reliability in Microelectronics VII


J Clement, Digital Equipment Corp
Robert Keller, NIST
Kathleen Krisch, Bell Labs, Lucent Technologies 
John Sanchez, Univ of Michigan
Zhigang Suo, Univ of California-S Barbara

Symposium Support

  • Aetrium, Inc./Sienna Technologies
  • Bell Laboratories, Lucent Technologies, Murray Hill
  • Bell Laboratories, Lucent Technologies, Orlando
  • Digital Equipment Corporation
  • IBM T.J. Watson Research Center
  • Materials Research Corp., Advanced Materials Division
  • Mattson Technology, Inc.
  • Motorola/APRDL
  • Sandia National Laboratories/Electronics Components Center
  • Sandia National Laboratories/Microelectronics & Photonics
  • Tencor Instruments
  • Varian Thin Films

1997 Spring Exhibitor

Proceedings published as Volume 473
of the Materials Research Society
Symposium Proceedings Series.

In sessions below "*" indicates an invited paper.

Chair: Robert R. Keller
Monday Afternoon, March 31, 1997
Salon 5/6

1:30 PM *J1.1 
ADHESION OF INTERFACES IN MULTILAYER INTERCONNECT STRUCTURES, Qing Ma, John Bumgarner, Harry Fujimoto, Intel Corp, Dept of SC1-02, Santa Clara, CA; Michael Lane, Reinhold H. Dauskardt, Stanford Univ, Dept of MS&E, Stanford, CA; Nety Krishna, Applied Materials Inc, Santa Clara, CA.

Interface decohesion is increasingly becoming a reliability concern in multilayer interconnect structures. It is therefore necessary to provide adhesion tests as a part of materials characterization procedures and to study the fundamental material properties that affect interface toughness. A sandwich structure 4-point bend test was developed for measuring the adhesion between interlayer dielectric and metal interfaces. This technique offers well defined and easily controllable fracture processes and simple analyses based rigorously on fracture mechanics. Using this technique, a number of interfaces were studied. For conventional interconnect systems consisting of Al lines and SiO as the interlayer dielectric, the focus is to improve the interface fracture toughness through process engineering. Interface strengthening effects of both mechanical and chemical origin, including interface roughness and thin film plasticity, as well as alteration of chemical bonding, are explored. Potential low dielectric constant materials, such as polymers, porous SiO, and fluorinated oxides, are also studied as candidates for interlayer dielectric materials in the future. A set of experiments on poly(arylene ever) (PAE) is given as an example to illustrate issues involved us these materials.

2:00 PM J1.2 
THE ENERGY RELEASE RATE FOR DEBONDS IN THIN MULTILAYERED FILMS ON SUBSTRATES, Ming Y. He, Guanghai Xu, David R. Clarke, Univ of California-S Barbara, Dept of Materials, Santa Barbara, CA; Qing Ma, Harry Fujimoto, Intel Corp, Dept of SC1-02, Santa Clara, CA.

In this paper, the strain energy release rates for the converging debond crack in a multilayered film on substrates have been calculated using the finite element method. The results for the energy release rate as a function of the intrinsic stress, the thickness of the superlayer, and the modulus ratio will be presented. A simple functional form for the results will be shown. The effects of plasticity of the thin metal layer on the energy release rate have been examined in detail. The results show that the effect of plastic deformation is not significant for the converging debond crack. The effects of the line width have also been addressed. The results show that for two-layer films, the energy release rate for steady state debond cracks decreases dramatically as B/t decreases, in the range B/t < 40, where B is the line width and t is the thickness of the superlayer. For narrow lines the plane strain solutions overestimate the energy release rate. The numerical results are consistent with the experimental observations on lines with different width.

2:15 PM J1.3 
PROGRESSIVE DEBONDING OF INTERFACES IN MULTILAYER INTERCONNECT STRUCTURES, Reinhold H. Dauskardt, Michael Lane, Stanford Univ, Dept of MS&E, Stanford, CA; Qing Ma, Harry Fujimoto, Intel Corp, Dept of SC1-02, Santa Clara, CA; Nety Krishna, Applied Materials Inc, Santa Clara, CA.

Delayed failure and lifetimes of devices may be dictated by progressive debonding along one (or more) bimaterial interfaces. These fractures are driven by residual stresses, thermal cycling and mechanical loading or vibrations. Time dependencies can reflect subcritical cracking enhanced by temperature (creep), moisture or corrosive species (stress corrosion), or even cyclic loading induced crack extension similar to classic metal fatigue. Long-term reliability and life prediction must be addressed in terms of the above time-dependent failure mechanisms. While quantitative adhesion data and their material determinants for device level interconnect structures Is limited, subcritical debonding behavior at or near to bimaterlal interfaces Is almost nonexistent. In this study, we present unique time-dependent delamination data for debonding of SiO interlayer dielectric films from Al lines in interconnect structures. Data is presented in terms of the debond growth rate as a function of the debond driving force, G. Behavior Is rationalized in terms of the salient chemical reaction rate Involving environmental interactions with strained debond tip bonds. Implications for life prediction of devices are discussed.

2:30 PM *J1.4 

As in other engineered structures, fracture occasionally occurs in integrated microelectronic circuits. Fracture can take a number of forms including voiding of metallic interconnect lines, decohesion of interfaces, and stress-induced microcracking of thin films. The characteristic feature that distinguishes such fracture phenomena from similar behaviors in other engineered structures is the length scales involved, typically micron and sub-micron. This length scale necessitates new techniques for measuring mechanical and fracture properties. In this work, we describe non-contact optical techniques for probing strains and a microscopic ''decohesion'' test for measuring interface fracture resistance in integrated circuits.

3:30 PM J1.5 
SCANNING STIFFNESS MICROSCOPY - A NOVEL TECHNIQUE FOR DETECTING SUBSURFACE CRACKS, Ranjana Saha, Stanford Univ, Dept of MS&E, Stanford, CA; Ting Y. Tsui, Advanced Micro Devices, Dept of Matls Technology Development, Sunnyvale, CA; Caroline A. Ross, Komag Inc, Milpitas, CA; William D. Nix, Stanford Univ, Dept of MS&E, Stanford, CA.

Thin film delamination and subsurface cracking represent important reliability issues for the semiconductor and thin film magnetic hard disk industries. Detecting such defects is often difficult and requires complicated specimen cross-sectioning and imaging. Because the sample preparation process itself may cause crack growth, such a method may be used only as a quantitative tool for defect characterization. In the present work, we introduce an in-situ nondestructive technique for detecting subsurface cracks by continuously monitoring the contact stiffness, while dragging a probe across a smooth surface at an ultralight load. As the probe encounters a subsurface crack, the local contact stiffness decreases dramatically. The amount of reduction in contact stiffness depends on the crack geometry and the depth of the crack. Results of the scanning stiffness microscopy experiments conducted on common semiconductor and hard carbon thin films will be described and discussed.

3:45 PM *J1.6 
ADHESION ASSESSMENT OF THIN COPPER FILMS, Michael D. Kriese, William W. Gerberich, Univ of Minnesota, Dept of Chemical Engr & Matls Sci, Minneapolis, MN; Neville R. Moody, Sandia National Laboratories, Livermore, CA.

The adhesion of thin copper films of 100 nm to 1000 nm thickness is tested in order to assess the effect of various processing parameters. Primary investigation is on the effect of very thin ''adhesion promotion'' layers of refractory elements such as chromium and tungsten on two different substrates, namely highly-polished amorphous SiO2 and tape-cast polycrystalline Al2O3 wafers. Other variables assessed include film thickness, residual stress, post-deposition annealing and the use of thick refractory overlayers. 
The films are tested in two geometries via nanoindentation techniques, namely that of planar films and lithographically-processed lines. These techniques are capable of providing a wide range of stress-states and driving forces for crack propagation; stress states include both plane-stress and plane-strain, uniaxial compression and indentation and varying degrees of crack-tip mode mixity. Due to the ductile nature of copper, particularly in an annealed state, its films often have high interfacial toughness, limiting the degree to which adhesive rather than cohesive failure occurs, requiring for practical reasons such a wide range of stress states. The results of the testing are interpreted via traditional theoretical analyses developed for brittle thin films, but is also used as an assessment of more current theoretical work on brittle/ductile interfaces, for which there is a scarcity of experimental confirmation.

4:15 PM J1.7 
EFFECTS OF ADHESION ON THE MEASUREMENT OF THIN FILM MECHANICAL PROPERTIES BY NANOINDENTATION, Ting Y. Tsui, Advanced Micro Devices, Dept of Matls Technology Development, Sunnyvale, CA; George M. Pharr, Rice Univ, Dept of Materials Science, Houston, TX; Caroline A. Ross, Komag Inc, Milpitas, CA.

Experiments have been performed on soft aluminum films deposited on hard ceramic substrates to explore the influences of interfacial adhesion on mechanical property measurement by nanoindentation. The substrate materials included soda-lime silicate glass, aluminum oxynitride (ALON), and a-axis sapphire on which thin films of aluminum were sputter deposited to a thickness of 500 nm. The only major structural difference between the specimens was the nature of the substrate which exerts a strong influence on film adhesion through interfacial chemistry. Aluminum adheres strongly to glass and sapphire, but poorly to ALON. In addition, two different types of films were prepared on sapphire substrates, one with and the other without a 10 nm interlayer of amorphous carbon to reduce film adhesion. Nanoindentation testing of the various materials revealed significant differences in their mechanical behavior. Characterization of the residual hardness impressions by high resolution scanning electron microscopy and atomic force microscopy showed that the differences arise from the influence of interfacial debonding and film delamination on plasticity in the film. Results of the experiments are documented and discussed.

4:30 PM J1.8 

The increasing number of different material layers in microelectronic devices has made the mechanical properties of interfaces between these layers an important issue for device reliability. In this paper, we describe a new technique for measuring the fracture energy of thin film-substrate interfaces. The test procedure is similar to the macroscopic 4-point bending test on samples with a sandwich structure, wherein the tested interface runs along the sample. In contrast to the macroscopic technique where a large interfacial area is tested, our test procedure is designed to investigate interfacial fracture on a microscopic scale. Metal films were sputtered onto SiO2 microbeams which had been made by standard lithography and etching techniques. Subsequently the metal films were notched using a focused ion beam workstation in order to provide a site for crack initiation. The beams were then deflected with a nanoindenter, while the applied load and the displacement of the beam were recorded. With increasing load, a clear deviation from linear-elastic behavior is observed; this can be attributed to crack growth along the interface. Because the measured beam stiffness is a function of the crack length, the crack extension can be monitored quantitatively. Finally, the fracture energy is determined as the work done per unit crack area.

4:45 PM J1.9 
ADHESION CHALLENGES AND SOLUTIONS IN COPPER CVD FOR ULSI APPLICATIONS, Greg Braeckelmann, Dirk Manger, Jean Kelsey, Soon-Cheon Seo, S. Beasor, S. Nijsten, Alain E. Kaloyeros, SUNY-Albany, Dept of Physics, Albany, NY.

Adhesion of Cu interconnects to prior and subsequent metallization layers is of critical importance in the reliability of IC devices. The authors present a systematic study of the adhesion of Cu CVD on various liners of interest for ULSI applications. The study included quantitative measurements (including stud pull and peel tests) of the adhesion strength of Cu on air-exposed and in-situ deposited CVD and PVD TiN, TaN, and WN, as well as x-ray, electron, and ion-beam leased compositional and structural investigations of the liner-Cu interface. These investigations also explored the effects of various ex-situ wet chemical and in-situ plasma clean techniques on enhancing copper's adhesion strengths. The results of these studies will be presented and discussed in terms of in-situ cluster-tool-based processing of the copper and liner layers, versus ex-situ deposition resulting in a vacuum break between the two metallization layers.

5:00 PM J1.10 
ELECTROSTATIC ADHESION TESTING FOR THE EVALUATION OF METALLIZATION ADHESION, Haining S. Yang, Franz R. Brotzen, Daniel L. Callahan, Rice Univ, Dept of MEMS, Houston, TX; Clyde F. Dunn, Texas Instruments Inc, Houston, TX.

Electrostatic adhesion testing (ElATe) employs electrostatic forces to generate delaminating stresses in thin films. Unlike other available adhesion tests, this technique does not require any mechanical contact and can induce purely tensile stresses. The interfacial adhesion strength is readily calculated from the applied electrostatic field at failure and the electrode geometry. The adhesion strength data of several electronic metallizations (e.g., Al, Cu) are analyzed using Weibull statistics and exhibit characteristic strengths consistent with expectations developed from more qualitative tests. Scanning electron microscope observations reveal a blister-type of failure. The size of the blister is typically 15 m in diameter. It is shown that electrostatic adhesion testing is effective in providing quantitative values for the adhesion strength and failure probabilities of electronic metallizations.

Chair: John E. Sanchez
Tuesday Morning, April 1, 1997
Salon 5/6

8:30 AM *J2.1 
INTERCONNECT LIMITS ON GIGASCALE INTEGRATION (GSI), James D. Meindl, Jeffrey A. Davis, Georgia Inst of Technology, J.M. Pettit Microelectronics Research Ctr, Atlanta, GA.

Opportunities for Gigascale Integration (GSI) are governed by a hierarchy of physical limits. The levels of this hierarchy have been codified as: 1) fundamental, 2) material, 3) device, 4) circuit and 5) system. Many key limits at all levels of the hierarchy can be displayed in the power, P, versus delay, td, plane and the reciprocal length squared, L-2, versus response time, t, plane. Power, P, is the average power transfer during a binary switching transition and delay, td, is the time required for the transition. Length, L, is the distance traversed by an interconnect that joins two nodes on a chip and response time, t, characterizes the corresponding interconnect circuit. At the system level of the hierarchy, quantitative definition of both the P versus td and the L-2 versus t displays requires an estimate of the complete stochastic wiring distribution of a chip. Based on Rent's rule, a well known empirical relationship between the number of signal input/output terminals on a block of logic and the number of gate circuits within the block, a rigorous derivation of a new complete stochastic wire length distribution for an on-chip random logic network is described. This distribution is compared to actual data for modern microprocessors and to previously described distributions. A methodology for estimating the complete wire length distributions for future GSI products is proposed. The new distribution is then used to enhance the critical path model that determines the maximum clock frequency of a chip; to derive a preliminary power dissipation model for a random logic network; and, to define an optimal architecture of a multilevel interconnect network that minimizes overall chip size. In essence, a new complete stochastic wiring distribution provides a generic basis for maximizing the value obtained from a multilevel interconnect technology.

9:00 AM J2.2 

Formation and morphological change of voids during electromigration test in polycrystalline Cu interconnects have been investigated at various current density conditions by in-situ FE-SEM observation. Sputtered pure Cu interconnects of 0.5 m mean grain size on W/TiN with interconnect widths between 3 and 0.5 m were used. When current density is higher than 5x10A/cm, elongation of voids toward current direction was observed. At first, voids are formed at grain boundaries, then they grow further and move to cathode direction gradually. However, growth rate of longitudinal direction (i.e., current direction) is much faster than that of lateral direction, and a ratio of length to width of a void increase with time. We defined a void elongation factor as a mean value of the ratio of length to width of voids. The void elongation factor was 2.53 when the current density was 9x10A/cm, and it was 1.31 when the current density was 3x10A/cm at 400C and 50 hours. Occurrence of the void elongation is dependent on grain boundary morphology. It was observed only when the mean grain size was much smaller than the interconnect width. 
It is speculated that shape of a void is determined by a balance of surface atomic flux by the electron wind force and by a force which act to minimize surface free energy. The former surpasses the latter at high current density conditions, at which the void elongation becomes dominant.

9:15 AM J2.3 
EFFECT OF MICROSTRUCTURE ON KINETICS OF ELECTROMIGRATION DAMAGE IN Cu LINES, Alexander Gladkikh, Tel Aviv Univ, Dept of Physical Electronics, Tel Aviv, ISRAEL; Michael Karpovsky, Alexander Palevski, Tel Aviv Univ, School of Physics & Astronomy, Tel Aviv, ISRAEL.

We present results of experimental observations of electromigration in copper. Unpassivated thin film lines of 2 m width and of 150 nm thick were stressed by an electrical current with density of 2106 /cm at temperatures from the range 350-400C. Kinetics of electromigration damage was found to be very sensitive to the film microstructure leading to a variety of damage morphology. Three extremely different variants of damaging were distinguished: a) voids across the conductor lines, as usually observed; b) voids which grew along the lines and did not lead to opens over long time periods; c) global continuous thinning of the lines. An interaction of surface diffusion and grain boundary mass transport is considered to be important for the damage mechanism of electromigration in studied Cu films.

9:30 AM J2.4 
OBSERVATION OF ELECTROMIGRATION VOIDING IN Cu LINES, Seok-Hee Lee, John C. Bravman, Paul A. Flinn, Stanford Univ, Dept of MS&E, Stanford, CA; Lucile Arnaud, LETI, Dept of Microelectronique, Grenoble, FRANCE.

Electromigration failure occurs by nucleation, growth and movement of a void. While much research has been done to understand electromigration voiding in Al-based lines, study of this phenomenon in Cu interconnects is almost totally lacking. For understanding the dynamic voiding processes in the Cu lines, an in-situ technique is necessary. For this purpose, a high voltage scanning electron microscope operated in backscattered image mode has been employed to observe electromigration voiding in passivated Cu lines. Pure CVD Cu films 5000 thick were deposited on TiN/Ti/SiO2 (400/200/6000 ) multilayered film on Si wafers. The films were capped with TiN films 600 thick and patterned by ion milling. A 5000 thick PECVD oxide was used for the passivation of the line. The length of the line was 800 m and the line widths varied from 0.7 to 4.0 m. The relationship between the void dynamics and the microstructure of the line has been examined.

9:45 AM J2.5 
ELECTROMIGRATION BEHAVIOR OF PURE COPPER FILMS DEPOSITED BY THE SELF-ION ASSISTED TECHNIQUE, Oleg V. Kononenko, Victor N. Matveev, Inst of Microelectronics Technology, Chernogolovka, RUSSIA; Vladimir T. Volkov, Inst of Microelectronics Technology, Dept of Novel Film Deposition Techniques, Chernogolovka, RUSSIA.

Copper films were deposited from high purity copper source by the self-ion assisted technique onto oxidized silicon wafers with Ta sublayers. The ions were accelerated toward the substrate by a potential of 0, 3 and 6 kV. The films were patterned into strips 670 m long and 2, 5, 10 m wide using photolithographic procedures and etching in argon plasma. Average drift velocities were measuremented in the films tested under electromigration conditions. Electromigration tests were carried out in vacuum at the temperature range from 200 to 400 C. Electromigration activation energy was obtained for films deposited at the different accelerating voltages.

Chair: Gerald Lucovsky
Tuesday Morning, April 1, 1997
Salon 5/6

10:30 AM *J3.1 
PERFORMANCE AND RELIABILITY OF SCALED GATE DIELECTRICS, Wayne M. Paulson, Philip J. Tobin, B. Maiti, H-H. Tseng, C. Gelatos, Motorola Inc, Austin, TX; Rama I. Hedge, Motorola Inc, APRDL , Austin, TX.

Gate dielectrics for advanced ULSI circuits are rapidly scaling below 10 nm to yield high performance transistors. These thin oxides and oxynitrides present new challenges for both the formation processes and characterization techniques. These thinner dielectrics are also susceptible to process induced damage that affects subsequent reliability. In this overview we will discuss the factors that affect the performance and reliability of scaled gate dielectrics. The oxidation kinetics for both furnace and rapid-thermal processes will be described for thin gate oxides along with pre-oxidation cleaning techniques. Boron transport through thin gate oxides affects the threshold voltage of the transistor. The use of oxynitride dielectrics can retard this transport, so we will discuss the formation of oxynitrides by annealing in either NO or NO as well as the tradeoff with transistor performance. The metrology of thin dielectrics is another issue and we will discuss optical ellipsometry techniques. In addition, the physical analysis of these dielectrics using TEM, AFM, SIMS and XPS will be presented. Traditional CV measurements become more difficult and are supplemented by IV and quantum oscillation techniques. Furthermore, charge-to-breakdown (QBD) and time-dependent dielectric breakdown (TDDB) depend upon the dielectric thickness as well as the injecting interface. The interaction between gate dielectrics and the isolation process is another critical factor for reliable devices. Furthermore, the process integration steps to form the transistor and the multilevel metal processes can directly affect both the quality and reliability of the gate dielectric. The effect of process induced damage will be described by the use of antenna structures. The characteristics of both N-channel and P channel transistors with scaled dielectrics will be presented along with the dielectric and device reliability.

11:00 AM J3.2 
SYNTHESIS OF ULTRA-THIN STACKED OXIDES USING LOW PRESSURE FURNACE CLUSTER PROCESS, P. K. Roy, David C. Brady, Bell Labs, Lucent Technologies, Orlando, FL; S. Chetlur, Orlando, FL; Ya Ma, Bell Labs, Lucent Technologies, Orlando, FL; K. Morse, Cornell Univ, Ithaca, NY.

A mayor hurdle in sub-0.5 m technologies is grooving high quality (low defect, D < 05/cm and interface trap density, D < 2E10/cm) ultrathin gate oxides (GOX) that are robust and manufacturable to ULSI processing. The stacked oxide arguably is the most promising candidate. However, conventional stacked oxidation (grow deposit-grow) involves three separate furnace operations and, therefore, an increased cycle time and a reduced throughput. This work describes a LPCVD stacked oxidation process achieved though growing (100-25 SiO at a temperature of 650C-850C and at a pressure of 0.4-1.0 Torr), depositing (TEOS SiO 15-50 ) and growing (5-15 SiO) in O or NO ambient (800C-900C) to generate high quality 40, 50 and 65 GOXs for sub-0.5 m CMOS technologies. In-process, twin-tub GOX tester were used for characterizing leakage (D,), breakdown (V), tunneling (V) and charge-fluence (N) behaviors of these oxides from both voltage- and current-ramp measurements. Charge trapping characteristics (D, flatband voltage (V) and tunneling voltage (V)) were analyzed with a noncontact surface photovoltage technique (Quantox by Keithley). These stacked oxides are expected to have superior GOX quality and robust to in-process damage during subsequent processing.

11:15 AM J3.3 
IN-SITU STRESS MEASUREMENTS DURING DRY OXIDATION OF SILICON, Chia-Liang Yu, Paul A. Flinn, John C. Bravman, Stanford Univ, Dept of MS&E, Stanford, CA.

Mechanical stress generated during the thermal oxidation of silicon has been an important issue in understanding oxidation kinetics and in controlling gate oxide reliability. In this study, we present results of in situ stress measurements made during dry oxidation with a specially designed wafer curvature system capable of reaching 1200C. Lightly doped P-type 4-inch double-side-polished silicon wafers with orientations of <100>,<110>, and <111> were used. The wafers had clean silicon surfaces on one side and 200 nm thick thermal oxide masks on the other. The wafers were first heated in flowing nitrogen to stabilize them at a desired oxidation temperature, after which oxygen was introduced into the furnace. After periods of up to two hours, the gas flow was returned to nitrogen. Wafer curvature measurements were made during the entire thermal cycle. We observed a transient of increasing curvature after the start of the oxygen flow, during which the curvature increased linearly with the thickness of the oxide grown in this period. The transient of the increasing curvature results from two competing processes: stress generation in the oxide newly formed at the oxide/silicon interface, and stress relaxation of the existing oxide. After the end of oxygen flow, a transient of decreasing curvature was measured, which results solely from stress relaxation. Using a model of the stress relaxation process in thermal oxides derived from our earlier work, these in-situ oxidation measurements are used to interpret the overall oxidation kinetics and to determine the stress distribution through the film thickness.

11:30 AM J3.4 

Ultrathin oxides will be used for the future generation CMOS devices. It is known that for p poly-Si gates, boron diffusion through ultrathin oxides becomes a major problem. In this paper we look at this problem using two approaches: 1) changing the gate material and 2) using oxynitrides. 
Oxidation was carried out in ASM A400 vertical batch furnace. Ultrathin (3-4.5 nm) lightly nitrided oxides were grown using a two-step NO oxidation. Gate materials compared were as-deposited amorphous-Si and as-deposited polycrystalline-Si. BF implantation with different anneals was used for p gate fabrication to study the boron diffusion problem. 
We studied the effect of the boron diffusion through the ultrathin oxide using tunnel current and capacitance-voltage (CV) characteristics. Shifts in flatband voltage (V) were used as a monitor for the amount of boron diffused. Best results were obtained for oxynitrides with amorphous-Si gate. Large shifts were observed for as-deposited polycrystalline-Si gates. These shifts could also be seen in tunnelling characteristics. Reliability of these capacitors is being studied using constant current stressing. A significant reduction in Q is observed for p gates in comparison to n gates. Correlation between post-implantation thermal treatments and reliability will be presented.

11:45 AM J3.5 
STUDY ON THE RELIABILITY OF ULTRATHIN OXIDE GROWN IN 4-INCH SILICON WAFERS BY MICROWAVE PLASMA AFTERGLOW OXIDATION, C. R. Chen, National Tsing Hua Univ, Dept of Elect Engr, Hsinchu, TAIWAN; Tri-Rung Yew, National Tsing Hua Univ, Ctr of Matls Research, Hsinchu, TAIWAN; L. C. Hsia, Mosel-Vetalic Inc, Hsinchu, TAIWAN; Huey-Liang Hwang, National Tsing Hua Univ, Dept of Electrical Engr, Hsinchu, TAIWAN.

Microwave plasma afterglow oxidation method is a new method to grow the ultrathin oxide. Using this method, we can grow the ultrathin oxide used as the gate oxide of devices at low temperature (600C). According to our previous studies, the ultrathin oxide grown by this method, accompanied with NO plasma annealing and pretreatment shows good properties. Breakdown field of the ultrathin oxide was 12 MV/cm, and density of state in the middle of bandgap was reduced to 5 x 10. Microwave plasma afterglow oxidation is a potential technique for fabricating 0.1 m devices because it can grow good quality oxide and has the advantage of low temperature process. We set up a new microwave plasma afterglow oxidation system for investigating the properties of ultrathin oxide grown in 4-inch silicon wafers. We investigate the electrical properties and reliability by analysis of I-V, C-V characteristics and FTIR spectrum. Our study shows that under the proper growth condition, the system can grow uniformly 60-80 A oxide in 40-inch wafers. By FTIR analysis, it proves that general bonding structure of the ultrathin oxide grown by the system at 700C is found to be identical to that of ultrathin oxide grown by dry oxidation. And we find that the FTIR spectrum is independent on the microwave power. The oxide has the optimal fixed oxide charge density that is 8.6 x 10 and the optimal interface state density at the midgap is 7.53 x 10. The optimal breakdown field is 9.5 MV/cm. The breakdown time is 2053 second during 8 MV/cm electric field applied. The charge to breakdown is 9.1 C/cm by a 10 A/cm Fowler-Nordheim tunneling current.

Chairs: Gregg S. Higashi and Kathleen S. Krisch 
Tuesday Afternoon, April 1, 1997
Salon 5/6

1:30 PM *J4.1/P3.1 
CRITICAL ISSUES IN WET CHEMICAL PROCESSING OF ULTRA-THIN GATE OXIDES, C. Robert Helms, Stanford Univ, Dept of Electrical Engr, Stanford, CA.

This paper will first review the requirements for gate insulators for use over the next 15 years. These include gate lengths of 70 nm and oxide equivalent thicknesses down below 20 . Thickness control of better than 3, electrical defect densities down to 0,001 per cm will be required, with wafer sizes 400 mm. The gate insulator must also function as a diffusion barrier to impurities in the gate contact (or contact material itself, if a metal) and exhibit stability to any subsequent higher temperature steps. The critical surface prep requirements will next be discussed. For a modern process up to 7 cleans are performed prior to gate insulator formation, in addition to 3 resist strip operations, wet or dry film etch/strip, and planarization. Numerous cleaning operations are also performed by the wafer suppliers. Critical issues for surface prep include particle deposition and removal, effects of surface prep chemistries on wafer defects (especially for polished CZ wafers), metal deposition and removal, organic and other inorganic contamination, surface roughness, and surface termination. 
It is clear that a lowest Cost of Ownership solution for surface prep in the future must be considered in an integrated framework including the wafer itself, the cleans, and the gate insulator formation and other processes to be performed. In addition, environmental, safety, and health factors must be considered. This is leading to nonaqueous resist strip processes and more application specific tools and chemistries. Thickness control and uniformity is viewed as a key issue. Opportunities for simplified aqueous progate surface prep will next be discussed. Integrated single water ''dry'' cleans will not likely be adopted until gate insulator formation is also performed on a single wafer basis. This may occur in the 10-15 year out time frame when 400 or 450 mm wafers will be ramping into production.

2:00 PM *J4.2/P3.2 

Aggressive transistor performance requirements for advanced IC technologies necessitate the use of ultrathin gate oxides () operating at relatively high fields. Operation of devices with these high fields present a significant reliability concern since time-dependent oxide degradation is accelerated with increasing electric fields. In this talk, we present an overview of reliability assessment of thin gate oxides using lifetime measurements. Accurate prediction of oxide reliability requires an understanding of the effect of electric field on degradation, and here we discuss the field dependence and the impact of bias conditions (accumulation and inversion) on failure times. We address the issue of calculation of the oxide field during accelerated stress tests and show that the ' 'true'' oxide field can differ substantially from that expected from the optical thickness of the oxide because band bending, poly depletion and carrier confinement effects become significant below about 100 . We show that a neglect of these effects can introduce significant errors in lifetime projections from accelerated tests.

2:30 PM *J4.3/P3.3 
SURFACE TREATMENTS WITH UV-EXCITED RADICALS FOR HIGHLY-RELIABLE GATE DIELECTRICS, Takashi Ito, Fujitsu Laboratories Ltd, Electron Devices & Materials Lab, Kanagawa, JAPAN.

The UV-excited chlorine radical treatment is well known to effectively remove trace metal contaminants from silicon surfaces. The process makes high selectivity of silicon etching and was subjected to clearly identify breakdown spots on thin gate dielectrics. After dielectric breakdown, a silicon crystallized filament as small as a few nanometers in diameter was formed which was selectively etched with chlorine radicals. Nonuniformities of silicon native oxide films were identified through the same process by selective etching of silicon surfaces through the native oxide films. Etching of a polysilicon buffer layer of the modified LOCOS structure without any damage and contamination was another application of the process. Densification of native oxide films formed after the conventional wet cleaning was possible by UV ozone treatment. Densities were quantitatively evaluated by glancing angle x ray diffraction technique. Surface treatments with UV chlorine and UV ozone produce clean and uniform silicon surfaces resulting in highly reliable gate dielectrics for ULSIs.

3:30 PM *J4.4/P3.4 
IMPACT OF METAL CONTAMINATION OF 7.0nm GATE OXIDES ON VARIOUS SUBSTRATE MATERIALS, Shuichi Saito, K. Hamada, NEC Corporation, ULSI Device Dev Labs, Kanagawa, JAPAN; David J. Eaglesham, Bell Labs, Lucent Technologies, Dept of Silicon Processing Research, Murray Hill, NJ; Y. Shiramizu, NEC Corporation, ULSI Device Dev Labs, Kanagawa, JAPAN; Janet L. Benton, Bell Labs, Lucent Technologies, Murray Hill, NJ; H. Kitajima, NEC Corporation, ULSI Device Dev Labs, Kanagawa, JAPAN; Dale C. Jacobson, Bell Labs, Lucent Technologies, Murray Hill, NJ; John M. Poate, Bell Labs, Lucent Technologies, Dept of Silicon Processing Research, Murray Hill, NJ.

As gate oxide thicknesses decrease with device size reduction, the metal contamination level must also decrease to maintain device reliability. During gate oxide formation, metal atoms may be included in the oxide from either surface or bulk contamination during the process. The contamination level which affects device performance may be different for these processes. Moreover, the influence of metal contamination on the devices strongly depends on the gettering capability of the substrate. Evaluation of MOS devices has been carried out for different contamination methods (dip method and Fe I/I) and different substrate gettering (p/p+, DZIG, NIG, Fz, and high energy implantation). Device performance was evaluated using gate oxide breakdown voltage and Qbd characteristics for gate oxide reliability and junction leakage current to clarify the influence of damage in high energy implantation. The results suggest that reduced contamination levels are required for thinner gate oxides, and that high energy implantation provides useful gettering.

4:00 PM *J4.5/P3.5 
EFFECT OF Cl IN GATE OXIDATION, Paul W. Mertens, IMEC, Leuven, BELGIUM; Michael J. McGeary, Olin Corp, Microelectronic Materials Div, Cheshire, CT; Marc Meuris, IMEC, Clean Technology Group, Leuven, BELGIUM; Marc M. Heyns, IMEC, Leuven, BELGIUM.

Metallic contamination has a detrimental effect to the electrical integrity of ultrathin gate oxides. Today ultrathin gate oxides show defect levels that are still in excess of the level required for successful ULSI application (>1 GBIT). 
In situ use of Cl in an oxidation furnace results in an effective metal removal. Different chemistries and process schemes for in situ Cl cleaning are compared. The experiments demonstrate that Cl appears to be the most active component. Using a process in which all Cl in the furnace ambient is present as Cl results in a significant source reduction and in a more environmentally benign process. The current study will cover the following aspects of the use of Cl: the basic chemistry of the process, metal removal, effect on gate oxides, and safety and health issues.

4:30 PM J4.6/P3.6 
ORGANIC CONTAMINATION OF SILICON WAFER IN CLEAN ROOM AIR AND ITS IMPACT TO GATE OXIDE INTEGRITY, Masataka Hirose, D. Imafuku, Seiichi Miyazaki, Hirsohima Univ, Dept of Electrical Engr, Hiroshima, JAPAN.

Silicon wafer surfaces after wet cleaning are progressively contaminated with organic molecules in clean room air. The total carbon concentration on a hydrogen-terminated Si(100) surface tends to saturate at a level of about 10 cm when the exposure time exceeds 90 min. In order to understand the influence of the surface organic contamination on the gate oxide integrity, the total carbon concentration before the oxidation was changed from nearly zero to , and 4 5 nm thick gate oxides were grown in wet atmosphere at 850C. It is found that cumulative TDDB failure rate for the MOS capacitors under constant current stress is enhanced when the initial carbon contamination is increased beyond 2x10. The slope of Weibull plot for oxides without carbon contamination is rather steep and the breakdown occurs at electron injection levels of 2-10 C/cm, while the carbon contamination of more than 4x10 causes the breakdown even at 0.1-1 C/cm. Also, the initial tunnel current is well explained by theory for oxides with and without carbon contamination, and the dielectric degradation under the constant current stress occurs through dramatic increase of the direct tunnel current component as a consequence of a localized conducting filament formation in the oxide layer near the interface. It is shown that this degradation is accelerated with the carbon contamination exceeding 2x10.

Chair: Patrick M. Lenahan
Wednesday Morning, April 2, 1997
Salon 5/6

8:30 AM *J5.1 

The impact of thin gate oxide process conditions on dielectric reliability has received extensive research attention. However, the top and bottom electrodes often limit actual gate oxide reliability. For example, the choice of silicon substrate and electrode definition by advanced isolation process modules is a significant factor affecting the integrity of gate oxides. Just as significantly, deposition and doping conditions for the polysilicon gate electrode are also shown to impact gate oxide reliability. The data presented will be analyzed for thin oxide () reliability based on the anode-hole injection model, which enables intrinsic and extrinsic reliability prediction for the low operating voltages in state-of-the-art ICs. With respect to the bottom electrode, the impact of substrate engineering on gate oxide quality will be discussed. The discussion will include the impact of substrate engineering parameters, such as wafer shape, oxygen concentration, doping level and epitaxial versus Czochralski substrate materials. The role of the critical electrode definition processes using advanced LOCOS technologies that reduce field oxide encroachment and the impact of these technologies on gate oxide reliability will be examined. Next, important parameters affecting gate oxide reliability due to engineering of the top electrode will be considered. A materials-intensive study of polysilicon films used as top electrodes for gate oxides is performed using advanced x-ray diffraction and reflectometry analysis. The impact of polysilicon and polysilicon/oxide interface structure to the defect density of gate oxides is related. Finally, the implications of dual p+/n+ polysilicon gate CMOS technology are reviewed by comparing the p+ and n+ gate breakdown mechanisms.

9:00 AM J5.2 

This paper addresses two aspects of Si-SiO interface chemical bonding that impact on electrical performance and reliability. These are i) minimization of suboxide bonding arrangements in an interfacial transition region, and ii) monolayer nitrogen atom interfacial incorporation. The scaling of lateral device dimensions into the deep submicron to 0.1 micrometers mandates gate oxide equivalent thicknesses be reduced to approximately 0.3 nm. In this thickness regime defect generation at Si-SiO interfaces is a major factor in device reliability. Ultra thin nitrided gate dielectrics have been fabricated by conventional furnace oxidation, rapid thermal oxidation, rapid thermal chemical vapor deposition and plasma-assisted oxidation and deposition demonstrating that nitridation improves reliability. Studies using low temperature plasma assisted processing to form the Si-SiO interface and gate dielectric are presented. Four separately controlled steps crucial to fabrication of high performance and high reliability gate oxide structures: i) pre-deposition chemical processing of the Si(100) surface, ii) in situ cleaning of the Si surface, followed by oxidation at 300degC to form the nitrided interface, iii) deposition of a stoichiometric oxide at 300degC, and iv) a rapid thermal anneal (RTA) at 900degC for chemical and structural interface relaxations. The focus here is on chemical reaction pathways for interface formation, and bonding rearrangements that take place during the RTA. The processing sequence described above i) produces a fully nitrided interface and ii) minimizes interfacial suboxide regions, both leading to improved reliability compared to thermally grown oxygen terminated interfaces. Process latitude is increased by performing oxide growth and deposition steps by a 300degC plasma process in which reaction pathways do not require thermal activation making the process insensitive to small substrate temperature variations ( 5-10degC). Because the suboxide minimization process is self-terminating, the RTA at 900degC also provides wide process latitude. Supported by ONR, NSF and SRC

9:15 AM J5.3 
THE EFFECT OF ROUGHNESS FEATURES ON MOS SURFACE NORMAL ELECTRIC FIELD AND FOWLER-NORDHEIM TUNNELING BEHAVIOR, Heng-Chih Lin, Stanford Univ, Dept of Electrical Engr, Stanford, CA; Toshiyaki Yamanaka, Hitachi Ltd, Central Research Lab, Tokyo, JAPAN; Simon J. Fang, Texas Instruments Inc, Dallas, TX; Kwame N. Eason, C. Robert Helms, Stanford Univ, Dept of Electrical Engr, Stanford, CA.

Future CMOS ULSI technology will require a gate oxide as thin as 3nm. At this thickness range, Si/SiO interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, changes the gate oxide Fowler-Nordheim tunneling behavior. The former is the main cause of MOSFET channel mobility degradation in the strong inversion region and may cause oxide reliability problems, while the latter is an important issue in flash memory, where the threshold voltage is controlled by the number of electrons accumulated in the floating gate as a result of this tunneling. 
Different pre-gate cleaning procedures may result in different surface roughness features. High spatial frequency features, even with smaller RMS roughness, may cause higher fluctuations of the surface normal electric field and a higher tunneling current, which may cause more serious electrical and reliability problems in devices than are caused by low spatial frequency features with larger RMS roughness. 
In this research, we used a structure composed of two parallel sinusoidal conducting surfaces to model three-dimensional Poly-silicon/Oxide and Oxide/Si interface roughness. Then we developed a three-dimensional simulator to numerically calculate the electric field inside, and the tunneling current through, the oxide as a function of roughness spatial wavelength, associated amplitude, oxide thickness, and applied voltage. Finally, as an example, we used the tunneling IV curves of LOCOS structure MOS capacitors to demonstrate the validation of this model, where each sample has different intentionally roughened interface characterized by AFM. Our future goal is to create a database relating cleaning procedures, roughness features, and associated device electrical performance, which can be used as a reference for deciding which pre-gate cleaning process is preferable.

9:30 AM J5.4 
REPLACEMENT OF C-V MONITORING WITH NONCONTACT COS CHARGE ANALYSIS, Kelvin Catmull, Rick Cosway, Motorola Inc, Chandler, AZ; Brian Letherer, Greg Horner, Keithley Instruments, Albuquerque, NM.

Modern semiconductor processing facilities often rely heavily on capacitance voltage (C-V) analysis for verification of oxidation furnace cleanliness, both in production and in research and development laboratories. C-V provides an accepted set of electrical test parameters (Vib, Qm, Tox, Dit, etc.) that can be used to monitor tube contamination levels during hot processing as well as pre- and post-processing effects such as preclean condition and post-anneal effectiveness. However, two significant drawbacks of the C-V technology are a) the need for costly and time consuming deposition of MOSCAP electrodes, and b) the reduction in electrically active contaminants due to the MOSCAP processing sequence. A commercially available noncontacting technology called corona-oxide semiconductor (COS) analysis is described here that does not require post-oxidation processing but does measure the fundamental electrical test parameters required for process control and development. Examples of COS in-line process monitoring are presented here, and they we compared directly with traditional polysilicon gate MOSCAP results. Mobile charge, fixed oxide charge, and Si/SiO interface trapped charge were each intentionally introduced to study the detection limits of the techniques. A systematic analysis of the data demonstrates that the strong gettering, cleaning and annealing action of the polysilicon gate deposition process reduces the contamination levels measured by C-V. While the reduced contamination is desirable in terms of ultimate device performance, it is counterproductive when the goal is the monitoring of daily tube contamination levels. The noncontact COS technology is shown to be significantly more responsive to electrically active contaminants, and the data indicate that this difference in sensitivity is due to the immediate, processing-free nature of the COS technology.

9:45 AM J5.5 

We demonstrate that the reliability of the ultrathin (< 10 nm) gate oxide in MOS devices depends on the Fermi level position at the cathode and not at the anode for constant current gate injections (V). The oxide breakdown strength (Q) is less for p+ poly-Si gate than n+ poly-Si gate for a given substrate type, however, it is independent of the substrate doping type. The degradation of oxides is closely related to the electrical field across the gate oxide which is influenced by the cathode Fermi level. P+ poly-Si gate has higher barrier height for tunneled electrons therefore the cathode electric field must be higher to give the same injection current density. Higher electric field gives more high energy electrons at anode and therefore the damage is more at the substrate interface. Different substrate types cause no effect on the oxide electric field therefore not influencing the degradation.

Chair: Kathleen S. Krisch
Wednesday Morning, April 2, 1997
Salon 5/6

10:30 AM *J6.1 
DEUTERIUM POST METAL ANNEALING OF MOSFETS FOR IMPROVED HOT CARRIER RELIABILITY, Isik C. Kizilyalli, Bell Labs, Lucent Technologies, Orlando, FL; Karl Hess, Joseph W. Lyding, Univ of Illinois-Urbana, Urbana, IL.

In CMOS fabrication technologies, low temperature post-metallization anneals in hydrogen ambients are used to reduce Si/SiO interface trap charge densities by hydrogen passivation. This anneal process improves device function by passivating the interface states that are otherwise electrically active. However, subsequent device degradation can be caused by channel hot electrons. According to established theory, this degradation (aging) process occurs in part as a result of hot electrons stimulating the desorption of hydrogen from the Si/SiO (channel/gate-oxide) interface. Recently, it has been demonstrated by the authors that the hot carrier reliability (lifetime) of NMOS transistors annealed in deuterium increases by an order of magnitude compared with those devices annealed in hydrogen. The idea of using deuterium was inspired by experiments in which a scanning tunneling microscope (STM) was used to stimulate the desorption of hydrogen or deuterium from Si(100)2x1:H(D) surfaces under ultrahigh vacuum conditions. It was discovered that deuterium is much more difficult to remove under conditions used to desorb hydrogen. The improved hot electron reliability phenomena can be understood as a kinetic isotope effect where desorption rates involving heavier isotopes are reduced. However, the static chemical bonding is evidently the same for both hydrogen and deuterium since identical transistor characteristics are measured after hydrogen or deuterium treatment prior to hot electron stress. SIMS analysis results verify that deuterium is present at the Si/SiO interface at levels of 10 cm.

11:00 AM J6.2 
SUB 3 NM GATE OXIDE GROWTH AND RELIABILITY, Michel Depas, IMEC, UCP/ASP, Leuven, BELGIUM; Marc M. Heyns, IMEC, UCP-ASP, Leuven, BELGIUM; Hessel Sprey, R. Wilhelm, ASM International, Bilthoven, NETHERLANDS.

Ln this work, the ultrathin (< 3 nm) gate oxide thickness uniformity, yield, and reliability will be discussed. It is demonstrated that the growth of 1.5 nm to 3 nm oxides with an extremely good uniformity (range <.05 nm) can be controlled by low temperature (750-850C) thermal oxidation in a batch furnace with a low-pressure load-lock system. The removal of the chemical oxide with HF prior to oxidation has a minor influence on the tunneling and reliability properties of sub 3 nm oxide MOS stuctures. AIso, the effect of the Si substrate material and the Si surface micro-roughness on oxide yield and reliability becomes less important in this thickness regime compared to thicker oxide layers. It is shown that electon trap creation can still occur in sub 3 nm gate oxides during direct tunneling and Fowler-Nordheim tunneling current stressing and correlates with oxide dielectric breakdown as defined by the charge to breakdown (QBD) value. The lower QBD observed for gate injection compared to substrate injection corresponds with a higher electron trap creation as a function of the injected electron fluence. For the worst case condition of gate injection, no reduction in QBD was observed for 3 nm oxide grown by furnace oxidation at relatively low temperatures (800-850C) compared to RTO at high temperature (1000C).

11:15 AM J6.3 
IDENTIFICATION OF THE MICROSCOPIC STRUCTURE OF NEW HOT CARRIER DAMAGE CENTERS IN SHORT CHANNEL MOSFETS, Curt J. Billman, Patrick M. Lenahan, Pennsylvania State Univ, Dept of ES&M, University Park, PA; W. Weber, Siemens AG, Munich, GERMANY.

Hot carrier effects in short channel MOSFETs involve the creation of interface states as well as the capture of charge carriers within the oxide [1]. To date, only one atomic scale detect has been identified in hot carrier damage: the P center [2]. We have identified two new defects in short channel MOSFETs subjected to the injection of hot holes into the oxide. We have identified these centers in short n-channel ( 1 m) devices stressed with V7 volts and V1 volt. The defects were detected using an ultrasensitive electron spin resonance (ESR) technique called spin dependent recombination (SDR). We observed a total of three defects after hot hole injection. One defect is the previously observed P interface trap center. Both new defects are E centers: MOS E centers have previously been studied with conventional ESR techniques [3]. They are nearly always associated with hole trapping and always involve oxygen deficient silicons with the oxide. The E SDR signal is consistent with what one would expect for a trapped hole near the Si/SiO boundary. It is thus likely that we are observing the structural nature of both oxide charge trapping and the hot carrier induced interface trap formation process.

11:30 AM J6.4 

We further argue in favor of new model for the degradation chain of thin SiO films, which includes four stages: 1) generation of deep traps/negative space charge; 2) self- localization of injection current; 3) formation of local defect spot; 4) appearance of leakage channel -> breakdown region [1,2]. Electrons are trapped in the oxide during stages 1 and 2, leading to a shift in the Fowler-Nordheim tunneling characteristics of MOS structures. The behavior of small MOS structures (area less then 10 cm), subjected to stresses caused by electron injection, demonstrates an obvious Non-Parallel Shift in the tunneling characteristics (NPS effect), measured in the wide current range (10-10 A) from either tunneling interface. This paper describes and compares two different approaches for NPS effect interpretation — Local and Uniform Degradation Models (LDM and UDM). The first approach uses the assumption of small (area 10^-11 cm) Structure-Stable Regions (SSR) formed in noncrystalline SiO films during thermal growth [2]. Due to the high resistance of SSRs to the degradation — negative space charge generation — electron injection is gradually localized in the SSRs, avoiding a screening effect of electron trapping. It is shown that the influence of non-uniformity in the electron injection appears to be more significant, when degraded MOS structure is tested at low voltages (NPS effect). Moreover, the LDM allows to extract the kinetics of injection localization during stressing, which agrees with independent results of our previous study devoted to the anomalous behavior of hole substrate current in pre-breakdown stage of MOS structures [2]. The second approach is based on the assumption of area-uniform space charge formation during stressing. The UDM implies a modification of the oxide tunneling barrier in case of electron trapping inside the tunneling distance which could also lead to the NPS effect [3]. It is shown that any spatial distribution of negative oxide charge is inapplicable to interpret the NPS effect within the framework of the UDM.

11:45 AM J6.5 
A PHYSICALLY-BASED PREDICTIVE MODEL OF SiO CHARGING, Patrick M. Lenahan, Pennsylvania State Univ, Dept of ES&M, University Park, PA; B. D. Wallace, Pennsylvania State Univ, University Park, PA; J. F. Conley, Dynamics Research Corp, Beaverton, OR.

The microelectronics industry is moving towards building in reliability. This approach will require physically based models of the effects of process variation on reliability mechanisms. We have developed, tested. and verified the precision of a physically based model of metal oxide silicon (MOS) gate oxide charging. To the best of our knowledge this represents the first successful quantitative physically based model of SiO charging. Our approach combines results of electron spin resonance (ESR) with standard statistical mechanics of solids intrinsic defect calculations. ESR studies of the past fifteen years establish an oxygen vacancy defect called the E center as the dominant deep hole trap in a wide variety of gate oxides. From the statistical thermodynamics of solids we know that (for the simplest cases) an equilibrium vacancy concentration may be expressed as N = Aexp(-H/kT), where A is a constant. H is the enthalpy of vacancy formation, k is the Boltzmann constant, and T is absolute temperature. We have evaluated E density in a series of oxides grown at 825C. After the deposition of a polysilicon gate they were subjected to anneals in dry oxygen at four higher temperatures. We evaluated the density of E centers in the oxides and obtained an enthalpy of creation as well as a pre-exponential constant. Using the previously measured hole capture cross section of E center (precursors) we quantitatively predict oxide charging as a function of oxide hole fluence. We have tested our quantitative expression on the four aforementioned oxides as well as on other oxides subjected to more extensive processing. We observe close quantitative agreement between our predictive model and experimental results.

Chairs: John E. Sanchez and Steven M. Yalisove 
Wednesday Afternoon, April 2, 1997
Golden Gate B2

1:30 PM *J7.1/I8.1 

Polycrystalline aluminum thin films, typically approximately 0.5 m thick, alloyed with 0.5 wt Cu and deposited by magnetron sputtering at rates of about 1 m per minute, provide the material from which submicron interconnect wiring for VLSI chips is formed. These Al films tend to have (111) crystallographic fiber texture, whether they are deposited on SiO, on Ti on SiO, on TiN on SiO, on TiN on Ti on SiO or on other less common (for current VLSI) substrates. The quality of the texture varies strongly with the substrate, from a very tight orientational distribution of grains with a full width at half maximum of the (111) planes with respect to the surface normal of 2 degrees to a ring texture in Which the (111) planes of typical grains are tilted away from the surface normal by 5 degrees or more. The substrate is critical in determining the texture quality. The submicron wide wires that are formed from these films by lithographically defined reactive ion etching often carry current densities in excess of le5 A/cm. As a result, they are subject to ''damage'' due to electromigration of Al atoms in the direction of the electron flow. Published reports indicate a strong correlation between electromigration damage and the texture of the original aluminum films: the tighter the texture, the more reliable the wires. These dependencies as well as their possible explanation will be discussed.

2:00 PM *J7.2/I8.2 
THE EFFECTS OF GRAIN STRUCTURE AND GRAIN STRUCTURE EVOLUTION ON INTERCONNECT RELIABILITY, Carl V. Thompson, B. D. Knowlton, MIT, Dept of MS&E, cambridge, MA; Harold J. Frost, Dartmouth College, Hanover, NH.

The median value and the variation of the electromigration-limited lifetimes of polycrystalline interconnects is known to be strongly dependent on their grain structures when their gain sizes and their line width are comparable. We have developed simulations of nucleation and growth of islands to form polycrystalline films, and of post-formation normal and abnormal grain growth which define the final grain size distribution and texture. We have simulated the development of columnar grain structures with lognormally distributed grain sizes, as is seen experimentally in many thin film systems including the aluminum films from which interconnects are patterned. We have also simulated post patterning grain structure evolution. Using a simulation of the effects of grain structures on electromigration we have made quantitative predictions of failure times, correlating the statistical characteristics of grain structures with predicted failure statistics. Predictions of failure time have been made as a function of line width. line length, current density, temperature, as-deposited grain structure, and post-patterning grain structure evolution. Owing to a mixture of electromigration mechanisms, the variations in failure statistics with these parameters is complex and is not captured in the simple models used in conventional reliability assessments. Improved process sensitive techniques for reliability assessment will be discussed.

2:30 PM J7.3/I8.3 
ELECTROMIGRATION IN RECRYSTALLIZED Al LINES, Marc J.C. van den Homberg, P. F.A. Alkemade, A. H. Verbruggen, Delft Univ of Technology, Faculty of Applied Physics, Delft, NETHERLANDS; A. G. Dirks, Philips Research Laboratories, Eindhoven, NETHERLANDS; J. L. Hurd, IBM Analytical Services, Hopewell Junction, NY; E. Ochs, Max-Planck-Inst, Inst fur Metallforschung, Stuttgart, GERMANY; S. Radelaar, Delft Univ of Technology, DIMES, Delft, NETHERLANDS.

The microstructure of Al metallization is a very important factor in electro- and stress migration. To investigate its role, we fabricated 200 m long, pure Al test-lines by means of recrystallization in a SiO groove pattern with submicrometer dimensions. The microstructure was characterized carefully by XRD, TEM and Backscatter Kikuchi Diffraction (Orientation Image Mapping). The lines fabricated with a temperature gradient during recrystallization were distorted single-crystals, with a constant lattice curvature of 0.04 /m. It is suggested that this curvature is due to the dislocations in the line, that form as a result of the thermal stress during cooling.The lines fabricated without a temperature gradient, were truly bamboo, i.e. without polygranular segments.Lifetime-measurements are performed at 200 C at a current density of 2 and 8 MA/cm. After 2700 hrs of testing, only 1 out of 15 single-crystalline lines failed and 4 out of 9 bamboo lines. Lifetime-tests on conventionally fabricated lines with similar dimensions have been started. BKD and SEM are used to analyze the failed lines. Sharply facetted and slit-like voids were observed in the bamboo lines. In addition, results of 1/f noise measurements from room temperature up to 200 C will be presented. The spectra show low noise intensities.

2:45 PM J7.4/I8.4 
THE LINEWIDTH DEPENDENCE OF MICROSTRUCTURE AND ELECTROMIGRATION IN DAMASCENE-FABRICATED ALUMINUM INTERCONNECTS, Paul B. Besser, Advanced Micro Devices, Sunnyvale, CA; Shekhar Pramanick, Advanced Micro Devices, Technology Development Group, Sunnyvale, CA; John E. Sanchez, Univ of Michigan, Dept of MS&E, Ann Arbor, MI; David P. Field, TexSEM Laboratories, Provo, UT; Kashmir Sahota, Advanced Micro Devices, Sunnyvale, CA.

As the integrated circuit industry progresses toward 0.18 m technologies, the extendibility of the conventional method of interconnect fabrication (metallization deposition, lithographic patterning, interconnect definition by reactive ion etching) is being questioned, and novel damascene methods of fabricating interconnects are being actively evaluated for both Al and Cu. For conventionally fabricated Al interconnects, it has been well documented that the reliability depends on the microstructure of the aluminum in the interconnect line. In the present work, parallel arrays of 1.0 m deep interconnects have been fabricated using damascene processing methods. A novel Al deposition stack/process was used to fill the trenches, which have essentially vertical sidewalls and vary in width from 0.5 m to 16 m. After chemical mechanical polishing, the grain size and crystallographic texture of the Al in these trenches has been characterized using transmission electron microscopy (TEM) and local electron backscattered diffraction (EBSD), respectively. Narrow lines (0.5 and 1.0 m wide) have a bamboo microstructure, intermediate widths (2.0 m wide) are nearly bamboo, and wide lines (4.0 m and wider) are polycrystalline. The <111> texture of the lines degrades with decreasing linewidth. A secondary <100> component will be demonstrated, and its origin proposed. The electromigration reliability of these damascene Al lines has been measured and will be correlated directly with the microstructure.

3:30 PM *J7.5/I8.5 

This talk will focus ont he use of new UHV low-energy high-flux beam sources, magnetically-unbalanced magnetron sputtering, and ionized magnetron sputter deposition to control nucleation kinetics, microstructure evolution, and preferred orientation during the growth of epitaxial and polycrystalline metal (Al, AlCu, Cu, Mo, and W) and transition metal nitride (TiN, TiAlN, and TiWN) films. Recent results using time and temperature dependent x-ray diffraction and resistivity measurements combined with TEM, XTEM, RBS, and STEM to follow both area-averaged and local interfacial reaction paths and kinetics during the annealing of metal/barrier bilayers will also be discussed.

4:00 PM J7.6/I8.6 
EXAMINATION AND MODELING OF VOID MORPHOLOGIES IN CONVENTIONAL AND HIGHLY TEXTURED Al-Cu INTERCONNECT LINES, Robert J. Gleixner, Stanford Univ, Dept of MS&E, Stanford, CA; Hisahi Kaneko, Toshiba Corp, Microelectronics Engr Lab, Saiwai-ku Kawasaki, JAPAN; William D. Nix, Stanford Univ, Dept of MS&E, Stanford, CA; Mie Matsuo, Hiroshi Toyoda, Toshiba Corp, Microelectronics Engr Lab, Saiwai-ku Kawasaki, JAPAN.

The electromigration lifetime of aluminum interconnect lines shows a strong dependence on the degree of texture in the metal. This observation is explained in terms of a decreased diffusivity along the grain boundaries, generally the dominant path for diffusion and void growth. As the texture in the metal is strengthened, the grain boundary disorder decreases and atomic diffusion is suppressed. 
In this paper, we examine passivated Al-0.5Cu interconnect lines having either TaAl underlayers or conventional Ti/TiN underlayers. Rocking curve measurements confirm that Al deposited on TaAl has a very strong (111) texture (FWHM 0.6 ) compared to Al on Ti/TiN (FWHM 6 ). Interconnect lines of both types were electrically stressed at 200 C and 225 C for 20 hours at a current density of 3 MA/cm. The lines were then stripped of passivation, and the void numbers, sizes, and morphologies were determined. 
Analysis of the void data gave a surprising result: the void volume in the highly-textured Al was than in the conventional Al. However, while voids in conventional Al were observed to follow grain boundaries across the width and sever the line, such destructive void growth was not observed in the highly textured Al. Instead, voids were either highly faceted or shallow and along the line edge, never extending across the line width. The increase in the electromigration lifetime results from this less destructive morphology. By modeling void growth in the observed microstructures, we can explain these differences as a result of the reduced grain boundary diffusivity. This resistance to fatal damage makes highly textured aluminum a promising interconnect material.

4:15 PM J7.7/I8.7 
IMPROVEMENT OF Al(111) TEXTURE IN LAYERED AL-ALLOY INTERCONNECT BY CONTROLLING WATER ABSORPTION OF DIELECTRIC UNDERLAYERS, Tomoyuki Yoshida, Shoji Hashimoto, Hideki Hosokawa, Takeshi Ohwaki, Yasuichi Mitsushima, Yasunori Taga, Toyota Central R&D Labs Inc, Electronics Device Div, Aichi, JAPAN.

Improvement of electromigration (EM) resistance in layered Al-alloy interconnects is important for developing highly reliable submicron VLSI devices. One promising approach is to enhance the (111) crystallographic texture of Al-alloy films, and many efforts have been made. For further improvement in Al(111) texture, it is important to investigate the influence of the surface condition of underlying dielectric films on the texture of Al-alloy films. In this study, the influence of the exposure of underlying dielectric (PSG and BPSG) films to a humid air ambient on Al(111) texture in Al-Si-Cu/Ti/TiN/Ti layered structures has been investigated as a function of the boron content and exposure time of the dielectric films. It was found that the Al(111) texture improves drastically with increasing boron content and exposure time of the dielectric films. The full width at half maximum (FWHM) value of the x-ray diffraction rocking curve for an Al(111) peak reached less than 1 degree. As the FWHM value improved, the Al-alloy surface became smoother and the Al-alloy grain sizes increased. The mechanism of the improved Al(111) texture was investigated. It was confirmed that the improved Al(111) texture is attributed to the improved (002) texture of the bottom Ti films, and that the Ti(002) texture is determined by the surface concentration of the absorbed water in the dielectric films. Furthermore, it was demonstrated that interconnects fabricated from the improved layered structure have excellent EM performance.

4:30 PM J7.8/I8.8 
COMPOSITIONAL EFFECTS ON DIFFUSION BARRIER DEGRADATION IN PVD-TISIN, Warren Franklin McArthur, Kenneth M. Ring, Fei Deng, Paul Morgan Pattison, Karen L. Kavanagh, Univ of California-San Diego, Dept of E&CE, La Jolla, CA.

TiSiN is being investigated as an amorphous diffusion barrier in advanced microelectronic copper metallization schemes. Ternary amorphous diffusion barriers typically fail due to crystallization followed by grain boundary diffusion of Cu. We are studying barrier compositions which lie near the TiN-TiSi phase line; a region of the Ti-Si-N phase diagram which has not previously been investigated. We are interested in the crystallization products and the amorphous to crystalline transformation temperature as a function of composition. In this work PVD-TiSiN films are formed by RF-magnetron co-sputtering Ti and Si in Ar/N. Film composition is controlled by the titanium to silicon target ratio and N partial pressure. Transmission electron microscopy (TEM) and electron diffraction shows that these films are amorphous as-deposited and undergo phase separation to yield titanium nitride and silicon nitride after a 1000C anneal. Bulk resistivity as-deposited (microOhm-cm) is acceptable for use as a contact liner/barrier material and improves with annealing (microOhm-cm after 800C anneal). We will report electrical results versus thermal history for films formed under varying sputtering conditions. We will also report on the composition and microstructure of TiSiN as determined by Rutherford back scattering, TEM and electron diffraction.

4:45 PM J7.9/I8.9 
EFFECTS OF NITROGEN ON PREVENTING THE CRYSTALLIZATION OF AMORPHOUS Ta-Si-N DIFFUSION BARRIER, Dong Joon Kim, Hanyang Univ, Dept of Metallurgical Engrg, Seoul, SOUTH KOREA; Soon Pil Jeong, Korea Inst of Science and Technology, Semicond Mater Research Ctr, Seoul, SOUTH KOREA; Yong Tae Kim, Korea Inst of Science and Technology, Semicond. Mater. Research Center, Seoul, SOUTH KOREA; Jong-Wan Park, Hanyang Univ, Dept of Metall Engr, Seoul, SOUTH KOREA.

Amorphous Ta-Si-N diffusion barrier was deposited by dc sputtering of Ta5Si3 target in (Ar + N) atmosphere. The crystal structure and thermal stability of Ta-Si-N to suppress the Cu diffusion were investigated by X-TEM, XRD, RBS, and AES. When the concentration of N in Ta-Si-N film was higher than 40 at., the Ta-Si-N film remained the amorphous state after annealing at 1100C for 60 min. In this case, the Cu diffusion was prevented by the amorphous Ta-Si-N barrier at the annealing temperatures up to 900C for 30 min. Whereas the Ta-Si-N barrier with N content less than 40 at. began to crystallize and failed to prevent the Cu diffusion after annealing at 700C for 30 min. In the metallurgical viewpoint, it will be discussed that the role of nitrogen prevents the crystallization of the Ta-Si-N film and the diffusion of Cu atoms in the Ta-Si-N diffusion barrier.

Chairs: J Joseph Clement, Robert R. Keller, 
Kathleen S. Krisch, John E. Sanchez and Zhigang Suo 
Wednesday Evening, April 2, 1997
8:00 P.M. 
Salon 7

EFFECT OF CHANNEL PROFILE ENGINEERING ON HOT CARRIER RELIABILITY IN n/MOSFETs WITH 100 nm CHANNEL LENGTHS, Biswajit Das, L. A. Hornak, West Virginia Univ, Dept of E&CE, Morgantown, WV; Samar K. Saha, Silicon Systems Inc, Dept of Adv Process Development, Santa Cruz, CA.

Hot-carrier-induced device reliability issues were studied for different shapes of channel doping profiles in nMOSFETs with effective channel length near 100 nm using device simulation tools. Bulk nMOSFET structures for device simulation were generated by using gate oxide thickness, T = 3 nm and three types of channel doping profiles such as abrupt and steep retrograde with low surface and high substrate concentrations, and step profile with high surface and low substrate concentrations. The device model parameters for numerical device simulation were obtained from the measured data for sub-0.1 m nMOSFET devices. The simulation results indicate that both the peak substrate current and peak impact ionization rate are lower for step channel doping profile in comparison to retrograde profiles. The substrate current and impact ionization rate are also found to decrease with the transition depth of step profile while increase with the transition depth of retrograde profiles. In addition, it is found that the drive current for devices with step channel doping profiles is lower than that of the devices with retrograde channel profiles due to mobility degradation in step channel profiles. Therefore, the shape of channel doping profile must be optimized for performance and reliability of ultrashort channel devices.

EFFECTS OF MoSi POLYCIDE GATE STRUCTURE ON THE GATE OXIDE INTEGRITY, Wen-Koi Lai, National Chiao Tung Univ, Dept of Electronics Engr, Hsinchu, TAIWAN; Han-Wen Liu, National Chiao Tung Univ, Inst of Electronics, HsinChu, TAIWAN; Miin-Horng Juang, Natl Taiwan Inst of Tech, Dept of Electronics, Taipei, TAIWAN; Chun-Su Lee, National Chiao Tung Univ, Inst of Electronics, Hsinchu, TAIWAN; Huang-Chung Cheng, National Chiao Tung Univ, Dept of Electrical Engr, Hsinchu, TAIWAN.

Dielectric reliabilities of two gate structures, i.e., poly-Si/SiO/Si substrate and Mo-silicide/Poly-Si/SiO/Si-substrate, with gate oxide thicknesses of 100, 200, and 300 have been comparatively studied. For the Mo-polycide gate structures, Mo silicide films of different thicknesses-1000, 2000, and 4000 -were respectively co-sputtered by using the c-gun system. 
For the poly-Si gate structures, the sheet resistance decreased as the annealing temperature was increased, due to the poly-Si grain growth. According the Ebd (breakdown field strength) results, thinner oxides have larger Ebd values than thicker oxides due to the less amount of weak spots. However, the Ebd for thinner oxide was more significantly degraded at high annealing temperature above 900C. In addition, thinner oxides caused smaller change-to-breakdown (Q) values than thicker oxides, especially at high annealing temperatures. On the other hand, for the Mo-polycide gate structures, the Ebd of gate oxides was degraded as the thickness of Mo silicides was increased, attributable to the larger thermal-induced stress. And the Ebd degradation is more severe for thinner oxides. Moreover, the Q characteristics also exhibited the similar deterioration with increasing silicide thickness and annealing temperature. 
The polycide gate structure is critical for improving the device performance, especially for ULSI applications. However, with the reduced gate oxide thickness according to scale-down rule, the gate oxide integrity becomes increasingly degraded with the increasing annealing temperature and silicide thickness. Hence, the proper choice of silicide thickness and process conditions is necessary for achieving high performance device and thin dielectric reliability.

(Abstract transferred to J3.4)

STRESS-RECOVERY TRANSIENTS IN ULTRA THIN OXIDES ON SILICON, Per Lundgren, Anders Jauhianien, Lars Ragnarsson, Chalmers Univ of Technology, Dept of Solid State Electronics, Gothenburg, SWEDEN.

The net positive charge appearing in ultra thin oxides on silicon during electrical stress at high electric fields in the direct tunneling regime is unstable and decreases after stress in a field and temperature dependent manner. This behavior is similar not only for plasma deposited and thermally grown oxides but also very similar to effects commonly observed in conventional thicker oxides after various stressing conditions. 
A common model to explain the highly dispersive relaxation transient, where the net positive charge decreases approximately logarithmically with time, invokes the concept of tunneling discharge of defects located throughout the oxide thickness. For ultra thin oxides, the time span would thus be expected to be limited according to such a model. 
We observe no clear sign of saturation for the logarithmic transients after stress in oxides down to a thickness of 2 nm for times from 10 ms up to 1 Ms. These results do not encourage the application of the tunneling distance as the source of the dispersive relaxation in our case, and this might very well extend to all cases where such relaxation is observed.

CHARACTERIZATION OF HOLE TRAPS GENERATED IN THIN SILICON OXIDE FILMS BY ELECTRON INJECTION, Tomasz Brozek, Motorola Inc, Semiconductor Technology Labs, Austin, TX; Eric B. Lum, Chand R. Viswanathan, Univ of California-Los Angeles, Dept of Electrical Engr, Los Angeles, CA.

Hole trapping in the gate oxide of MOS devices under a radiation or electrical stress environments causes instabilities of device parameters and serious reliability problems in MOS transistors and memories. In addition to native traps, hole traps can be generated under high doses of radiation or by high-field electron injection. Hole trap generation under Fowler-Nordheim (F-N) stress in gate oxides of different thickness less than 10 nm is investigated in this work in F-N stressed and virgin devices. PMOS transistors, degraded under various doses of positive and negative F-N injection, were post-stress annealed (to passivate damage and remove trapped electrons and holes) and subjected to substrate hot hole injection to study hole trapping kinetics. Hole injection performed on undamaged, control devices showed that the effective density of trapped holes decreases with oxide thickness with very low or no hole trapping in oxides with thickness smaller than 4.5 nm. Similarly, generation of hole traps was also found to be oxide thickness dependent. In 4.5 nm oxides no hole trap generation was observed even for F-N stress up to 2 C/cm under either polarity. For thicker oxides, the amount of generated traps increases as the F-N stress dose increases. The dependence of trapped hole charge on the hole fluence was used to determine capture cross sections of native as well as generated hole traps. Extracted values for trap density and capture cross section show that high-field stress in 6.5 nm and 9 nm oxides generates mainly hole traps with capture-cross section of about 1.25 x 10^-14 cm. In thicker oxides we have found also a component with a very large cross section (about 2.5 x 10 cm), which, however, seems to be weakly affected by F-N stress.

TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB) MEASUREMENTS ON RPECVD AND THERMAL OXIDES, Conrad Lorenzo Silvestre, Naval Research Laboratory, Washington, DC; John Hauser, North Carolina State Univ, AEMP, Raleigh, NC.

Time Dependent Dielectric Breakdown (TDDB) measurements have been made on 96, 121, and 147 Å oxides deposited by Remote Plasma Enhanced Chemical Vapor Deposition (RPECVD) upon 300°C Si(100) device grade substrates. The oxides were used to form an array of 10 um x 10 um square capacitors. The oxides were then subjected to electron injection from the substrate at 0.1 A/cm constant stress current. Analysis of the forcing voltage during stress showed the RPECVD oxide to have an initial electron trap density of 1.7+/-0.2 x 10 /cm. The stress voltage rose linearly with time, giving net electron trap filling rates of 3.1+/-0.2 x 10 /cm-sec. The TDDB data were analyzed to find breakdown occurring on average in localized areas of (69+/-9 Å ) containing 19+/-4 filled electron traps. A similarly fabricated 92 Å thermal oxide showed an initial electron trap density of 5.6+/-2 x 10 /cm and a net electron trap filling rate of 2.0+/-0.2 x 10 /cm-sec. For the 92 Å thermal and 96 Å RPECVD oxides, both ‰ 100 Å thick, an average localized breakdown area of (68+/-11 Å), containing 18+/-3 filled electron traps was calculated. The breakdown area and electron trap numbers did not vary in a statistically significantly manner with deposition technique or oxide thickness. Analysis of the electric field showed that at breakdown for the thermal oxide 1/E=0.0702+/-0.0008 cm/MV, while the RPECVD oxide had 1/E=0.11+/-0.01 cm/MV.

SUBSTRATE EFFECTS ON THE MEASUREMENT OF METALLIC THIN FILM HARDNESS BY NANOINDENTATION, Ting Y. Tsui, Advanced Micro Devices, Dept of Matls Technology Development, Sunnyvale, CA; George M. Pharr, Rice Univ, Dept of Materials Science, Houston, TX; Caroline A. Ross, Komag Inc, Milpitas, CA.

The ability to accurately measure the mechanical properties of metallic thin films is important in the semiconductor industry in the way these properties are related to device reliability. One popular technique for achieving this is nanoindentation, which has the advantage that properties such as hardness and elastic modulus can be measured without having to remove the film from its substrate. However, according to a widely-held rule of thumb, intrinsic film properties can be measured in a manner which is not influenced by the substrate only if the indentation depth is kept to less than 10 of the film thickness, which is often not practical. In this work, we propose a method for making substrate independent hardness measurements of soft metallic films on hard substrates. The primary problem to be addressed is the substrate-induced enhancement of indentation pile-up and the ways that the pile-up affects the contact area determined from the indentation load-displacement data. Based on experimental observations of soft aluminum films on silicon and hard ceramic substrates, a simple semi-empirical model is developed which accounts for the pile-up and allows the intrinsic hardiness of the film to be measured even when the indenter penetrates through the film into the substrate.

USING THE BLISTER TEST TO MEASURE ADHESION OF METAL AND OXIDE FILMS, Robert J. Hohlfelder, William D. Nix, Stanford Univ, Dept of MS&E, Stanford, CA; Anne S. Mack, Intel Corp, Dept of Components Research, Santa Clara, CA.

The reliability of IC devices is affected be the mechanical integrity of film/substrate interfaces. The provides a way of measuring the fracture toughnesses of these interfaces which is more quantitative than the traditional methods of testing film adhesion. In the blister test, free-standing thin film ''windows'' are fabricated using micromachining techniques. A window is then pressurized until the film debonds from the substrate, forming a circular ''blister'' which may be modelled as a crack advancing along the film/substrate interface. The critical crack extension force, Gc, can be determined from measurements of blister volume and the applied pressure. We describe our continuing work using the blister test to study the interfacial adhesion of systems having integrated circuit applications. We present results for metal (W, Ti) and oxide films on TiN underlayers. The influences of film thickness and interfacial debonding rate are described. Finally, we discuss some of the strengths and limitations of the blister technique.

DEPENDENCE OF STRAIN AND PLASTICITY DURING THERMAL CYCLING OF DIFFERENT ALUMINUM -ALLOY METALLIZATION ON ALLOY COMPOSITION AND PASSIVATION MATERIAL AND GEOMETRY, Heiko Nielen, Herbert Goegel, Siemens AG, Munich, GERMANY; Ingo Eppler, Herbert Schroeder, Werner Schilling, Forschungszentrum Julich GmbH, Inst fur Festkorperforschung, Julich, GERMANY.

Stress-induced voiding and shear plasticity of metallization during thermal cycling should be dependent on various properties of both, metallization and passivation, such as flow stress of the metal and geometry and elastic constants of the passivation Therefore we performed strain measurements on passivated lines of various aluminum-alloys with different passivation materials by x-ray diffraction during thermal cycling between RT and 450C. As samples we used an array of 1 m wide and 0.8 m thick parallel lines, 1 m apart. As metallization sputter deposited Al, AlCu, AlSiCu, AIV, AIMg, AlPd and various compositions of them on Ti/TiN diffusion barrier were used and passivated with different combinations of Si-oxides/-nitrides and different geometries. To account for the interaction, metal-passivation FEM-calculations have been performed and the theory of ''Eigenstrains'' has been used to evaluate the voiding and shear plasticity. First results shows a significant dependence of the strain on the passivating temperature (higher passivating temperature induces higher strain) whereas the passivation material and geometry lead to also visible but smaller effects. The dependence of the flow stress on alloy composition has been verified by stress measurements on continuous films before patterning, so that effects are expected on plasticity of the passivated lines as well. These data are still in the state of evaluation

ISOTHERMAL STRESS RELAXATION IN PASSIVATED AlSiCu LINES WITH DIFFERENT ASPECT RATIOS, Christoph Roths, J. Honings, Ingo Eppler, Herbert Schroeder, Forschungszentrum Julich GmbH, Inst fur Festkorperforschung, Julich, GERMANY.

Stress relaxation (plasticity) in passivated metallization generally has two components, shear relaxation at constant volume changing the stress distribution, e.g., by dislocation motion which can be described by a flow stress, and volumetric relaxation changing the hydrostatic stress, e.g., by voiding. In order to understand the underlying mechanisms we have performed detailed isothermal relaxation experiments for passivated AlSiCU lines with different aspect ratios a (0,2a1) and thicknesses at different temperatures between RT and 350C. 
The stress data show large dependencies of the relaxation on temperature with maxima between 150 and 250C. The maximum shifts to lower temperatures with decreasing aspect ratio. Estimates of the apparent activation energy give 0.6 0.3 eV, which is somewhat smaller than that for grain boundary diffusion. Due to the interaction with the passivation the metal stress or strain changes do not represent the true metal plasticity. Finite element calculations to account for this interaction are on the way. Using the formalism of ''eigenstrains,'' the separated volumetric (voiding) and shear plasticity will be discussed.

MICROMECHANICAL MODELING OF STRESSES AND DEFORMATION IN PATTERNED LINES ON Si WAFERS, Yu-Lin Shen, Univ of New Mexico, Dept of Mech Engr, Albuquerque, NM; Andrew Gouldstone, MIT, Dept of MS&E, Cambridge, MA; Subra Suresh, MIT, Cambridge, MA.

The evolution of stresses and deformation of patterned lines on Si substrates were studied numerically using the finite element method. The model, which has been verified using the system of thermally grown SiO films/lines on Si, is capable of predicting realistic stress fields and the wafer curvatures in directions parallel and perpendicular to the lines during both the patterning and thermal loading operations. In this work we extend the model to Al lines, where plastic yielding can play a significant role in influencing the stresses, damage evolution, and the overall wafer shape changes. Parametric analyses were carried out for examining the effects of anisotropic yield properties. Implications of the numerical findings to the characterization of the mechanical properties of fine metallic lines are discussed.


Local debonding along the interface between the Al lines and the surrounding dielectric can occur as a consequence of contamination during the patterning processes. These pre-existing free surfaces can serve as void-formation sites and cause reliability problems. The evolution of stresses in the interconnect is also affected. This work is aimed at numerically studying the effects of pre-existing debonded areas on the thermo-mechanical characteristics of Al lines, by recourse to the finite element method. Local debonded segments with vanous geometric features are assumed in the model, and the resulting stress and deformation fields are examined in detail from both the two- and three-dimensional analyses. Implications of the findings to the interconnect reliability are discussed.

FINITE ELEMENT CALCULATIONS OF STRESSES AND STRAINS IN PASSIVATED METAL LINES, Ingo Eppler, Herbert Schroeder, Werner Schilling, Forschungszentrum Julich GmbH, Inst fur Festkorperforschung, Julich, GERMANY.

Passivated metal lines, commonly used in integrated circuits, show thermally induced stresses due to the mismatch of the thermal expansion coefficients of the lines and their surroundings. These strains and stresses depend on the geometry and the elastic constants of both line and passivation and, for the case of an array of parallel lines, on the distance between them. For a given set of these parameters, the strains and stresses can be obtained from finite element calculations using a model with plane strain conditions. In order to get the dependences of the strains and stresses from these parameters, systematic finite element calculations have been made for parallel lines with two different passivation geometries (planar and conformal) and with variations in the aspect ratio of the line, the thickness, and the Young's modulus of the passivation and the distance between the lines. Since only the volume mean values of the strains and stresses can be measured easily (wafer curvature method, x-ray), the dependences of these mean values on the different parameters will be presented. Some results are: a) The strains and stresses are nearly independent on the distance between the lines for the conformal passivation type; b) For a planar passivation, an aspect ratio > 1 and a distance between the lines which is equal to the width of the lines, the strains and stresses depend only weakly on the passivation thickness and the aspect ratio of the line; c) In nearly all cases, the metal strains perpendicular to the substrate are compressive on cooling below the passivation temperature, while the other principal strains are tensile, in contrast to the case of a rigid passivation.

SIMULATION OF THE EFFECT OF DIELECTRIC AIR GAPS ON INTERCONNECT RELIABILITY, Lori C. Bassman, Stanford Univ, Dept of Mechanical Engr, Stanford, CA; Benjamin P. Shieh, Stanford Univ, Dept of Electrical Engr, Stanford, CA; Deok-Kee Kim, Richard P. Vinci, Stanford Univ, Dept of Matls Sci & Engr, Stanford, CA; James P. McVittie, Krishna C. Saraswat, Mihael D. Deal, Stanford Univ, Dept of Electrical Engr, Stanford, CA.

The deliberate introduction of air gaps in the passivation between aluminum interconnect lines has been suggested as a means for increasing transmission speed by decreasing dielectric capacitance. FASTCAP simulations, as well as experimental measurements on fabricated structures, have shown that significant reductions in capacitance can be achieved with air gaps. However, reliability issues are of concern for these structures. In this study we have performed simulations on various SPEEDIE-generated geometries to examine the tradeoffs between improved circuit performance and decreased mean-time-to-failure (MTTF). In our investigation of the reliability of air gap structures, we have assumed the dominant failure mechanism to be cracking of the thin layer of dielectric adjacent to the metal (and subsequent aluminum extrusion and shorting). This failure mode would be the result of compressive hydrostatic stress in the metal at one end of a polygranular segment due to electromigration. Stresses in the dielectric resulting from such loading were modeled using the MARC finite element code. For each structure, the hydrostatic stress in the metal corresponding to fracture in the dielectric was used to compute an estimate of the change in MTTF from the case with no air gap. This modeling strategy is valuable for assessing the reliability cost for improved performance from modified interconnect structures.

3-D FINITE ELEMENT SIMULATION OF ELECTRO AND STRESS MIGRATION EFFECTS IN INTERCONNECT LINES, Sven Rzepka, Matt A. Korhonen, Cornell Univ, Dept of MS&E, Ithaca, NY; Eicke R. Weber, Univ of California-Berkeley, Dept of MS&ME, Berkeley, CA; Che-Yu Li, Cornell Univ, Dept of MS&E, Ithaca, NY.

Electromigration (EM) and stress migration (SM) in the chip level interconnects are important reliability concerns in the semiconductor industry. In the deep submicron interconnect lines of next generation (line width m) the problem is being exacerbated because of the smaller line cross sections, larger current densities, and higher thermal stress levels. In realistic modeling of SM and EM there is the fundamental problem that, while diffusion field is local, the resulting local eigenstrains give rise to a nonlocal stress field. Because stress gradients act as driving forces for diffusion, we need to solve this global stress field, which is a continuum mechanics problem necessitating the use of finite element methods in a general case. We have developed a 3-D SM & EM simulator based on a commercial finite element code (ANSYS). The SM & EM problem is solved in two stages: for each time step, (i) first, the diffusion field and the resulting eigenstrains are determined, and (ii) then the stress field is calculated as based on the eigenstrains and boundary conditions. After detailing our approach, we focus on the (i) verification of our 3-D SM & EM modeling tool by comparing the results to analytic models and 1-D simulations, and (ii) application to interconnect line segments with specified grain structure.

RELATIONSHIP BETWEEN STRUCTURE AND ELECTROMIGRATION CHARACTERISTICS OF PURE ALUMINUM FILMS, David P. Field, TexSEM Laboratories, Provo, UT; Oleg V. Kononenko, Victor N. Matveev, Inst of Microelectronics Technology, Chernogolovka, RUSSIA.

Aluminum films were deposited from a high purity aluminum source by the self-ion assisted technique onto oxidized silicon wafers with TiN sublayers. The ions were accelerated toward the substrate by a potential of 0, 3 and 6 kV. The films were patterned into strips 670 (mu)m long and 8 (mu)m wide using photolithographic procedures and wet etching. Average drift velocities were measured in the films tested under electromigration conditions. Electromigration activation energy was obtained for films deposited at accelerating voltages of 3 and 6 kV. It was found that the average drift velocities decreased with increasing acceleration potential, and electromigration activation energy increased with the acceleration potential. The films were characterized using orientation imaging microscopy to obtain the spatial distribution of crystallite orientations. Crystallographic texture and grain boundary structure were seen to vary between the various deposition conditions. It is concluded that these microstructural measures are controlled by the processing conditions. Both texture and boundary structure are shown to affect the electromigration activation energy.


Decreasing feature sizes to nanometer dimensions in integrated circuits requires the application of new materials. Copper, because of its lower resistivity and greater electromigration resistance, is expected to replace aluminum as the material of choice for critical interconnects. A major concern from a reliability perspective is the oxidation of copper. In bilayer aluminum/copper film annealing studies, surface passivation is achieved by the oxidation of surface aluminum to form aluminum oxide, which then acts as a barrier to further oxidation of copper during annealing. However, the pertinent reliability issues associated with this type of passivation in actual interconnects being stressed by electromigration are not completely understood. Patterned aluminum/copper bilayer interconnects were tested at accelerated temperatures from 100 to 250 C with current densities of 1E5 to 7E6 A/cm2. After electromigration the morphology of the bilayered stripe surfaces were characterized by atomic force microscopy. Also, changes in the chemistry of the aluminum oxide passivation layers were determined by Auger electron spectroscopy.

Chair: Robert Rosenberg
Thursday Morning, April 3, 1997
Salon 5/6

8:30 AM *J9.1 

Measurement of the electrical resistance during electromigration stressing is the most widely used technique to obtain information on the time dependence of the degradation process. For simple line structures (typical length 1 mm) often the only information derived is the median time to failure of a set samples. A more detailed examination of the data seems not fruitful because the measurements usually show a complicated and poorly reproducible behavior. We found for short Al lines (length < 20 m) (between bonding pads) a much better defined behavior. Resistance changes (either positive or negative) induced by electromigration saturate and recover completely when the stressing current is switched-off provided that the current density j did not exceed a certain length dependent critical value . For the resistance changes do not recover. The relaxation rate of the recoverable resistance changes scales with the square of the sample length. The temperature dependence of the relaxation rate indicates that grain boundary diffusion is the prevailing transport mechanism. The critical current density depends on the length of the sample in a very similar way as found by Blech for the threshold current density in drift velocity experiments. The magnitude and the time dependence of the recoverable resistance changes strongly suggest that the evolution of mechanical stress during electromigration is responsible for the recoverable resistance changes. Convincing evidence for the origin of the non-recoverable resistance changes was obtained by inspecting the lines by AFM after stressing at current densities above . Always a only single void, hillock or hillock/void pair created during the passage of the DC current was observed. Negative resistance changes correspond to hillock growth and positive resistance changes to void growth. A good description of the magnitude of the voids/hillocks is obtained using literature data for electromigration in Al.

9:00 AM J9.2 
RESISTANCE NOISE AS A PROBE OF STRESS INDUCED VOIDS, Glenn Alers, Bell Labs, Lucent Technologies, Murray Hill, NJ.

Resistance noise is often considered as a fast probe of damage in metal interconnects. However, to obtain quantitative information from noise signals, the different mechanisms of resistance changes need to be understood and isolated. One critical parameter in separating different mechanisms is a careful consideration of the energy and rate of the resistance changes relative to the measurement temperature. A detailed analysis will be given for the magnitude, kinetics, and temperature dependence of different mechanisms of resistance changes including geometry, stress, alloy precipitation and diffusion. As an example of separating different effects, results will be presented from a study of small resistance steps induced at room temperature using specific temperature cycles to induce stress voids. The resistance steps were too rapid to be attributed to precipitation of alloy elements and can only be understood in terms of nucleation of small 10-100 nm stress induced voids in the aluminum line. Detailed statistics were performed on the size and density of the steps and compared with other measurements. The density of voids was similar to that found in SEM analyses after long term aging. The stress level in the line could be calculated from the mean volume of the voids using straightforward assumptions about the energetics of void formation. A stress level of 200 MPa at room temperature was estimated in this way.

9:15 AM J9.3 
KINETICS OF Cu SEGREGATION IN AlCu(1at%) SUBMICRON INTERCONNECTS STUDIED BY RESISTANCE MEASUREMENTS, A. J. Kalkman, G. C. A. M. Janssen, Ad H. Verbruggen, S. Radelaar, Delft Univ of Technology, DIMES, Lorentzweg, NETHERLANDS.

The time dependence of the growth of AlCu precipitates in AlCu(1 at.) thin films is studied by means of resistance measurements at different temperatures. Test samples are 0.5 and 3 m wide lines, patterned out of blanket films with a thickness of 0.5, and covered with 0.5 m of SiN at 400C. The samples are annealed at 400C for 1 hour, and then quickly cooled down to room temperature. Afterwards, the samples are heated within one minute to a measurement temperature between 140C and 240C. At these temperatures, the mobility of the Cu atoms is sufficiently high to enable growth of precipitates, which causes a well-defined decrease in resistance. We found that for the investigated temperature range, the resistance decrease can be accurately modelled by (R(t)-R) = (R)exp(-(t /), with exp(). Excellent fits were obtained resulting in n = 0.670.05, independent of temperature, and E0.03 eV. This value for the activation energy agrees very well with the activation energy that has been reported in literature for both electromigration failure in AlCu and grain boundary diffusion of Cu in Al. The value we found for n is intriguingly close to 2/3 and deviates strongly from the values of n reported for bulk AlCu (n = 1.5-1.8). So far, to our knowledge, values close to 0.67 have only been reported for highly deformed bulk Fe-C and Ge-Cu alloys, suggesting that the observed value for n is related to the high dislocation density in the AlCu films.

9:30 AM J9.4 
THERMAL AND ELECTROMIGRATION STRAIN DISTRIBUTIONS IN 10 m-WIDE Al CONDUCTOR LINES MEASURED BY X-RAY MICRODIFFRACTION, P.-C. Wang, G. Slade Cargill, Columbia Univ, Dept of Chemical Engr, New York, NY; I. C. Noyan, E. G. Liniger, IBM T.J. Watson Research Ctr, Yorktown Hgts, NY; C.-K. Hu, IBM T.J. Watson Research Ctr, Research and Microelectronics Div, Yorktown Heights, NY; K. Y. Lee, IBM T.J. Watson Research Ctr, Yorktown Hgts, NY.

X-ray microdiffraction was applied to study the thermal and electromigration strains in 10 m-wide Al conductor lines with 10 um spatial resolution. X-rays were collimated either by pinholes or by tapered glass capillaries to form x-ray microbeams. Measurements were made in a symmetric-reflection geometry so that the strains normal to the sample surface could be examined at different positions along the conductor lines. Results of thermal strain measurements show that the SiO passivation plays an important role in limiting relaxation of in plane compressive thermal stresses in the Al lines, but that the passivation is not effective in confining the overall thermal expansion of the Al line along the film normaL Cracks in passivation were seen in SEM studies. Electromigration strain measurements show that a linear strain gradient developed within the first few hours of electromigration. The magnitude of the strain gradient changed little until fast stain relaxations occurred near the anode end of the line. Possible mechanisms are discussed in light of these observations.

9:45 AM J9.5 
THERMAL CONDUCTIVITY MEASUREMENTS OF INTERLEVEL DIELECTRICS, Elizabeth B. Varner, Thomas Marieb, Anne S. Mack, Intel Corp, Dept of Components Research, Santa Clara, CA; K. Meyer, Intel Corp, Comp Tech Develop Qual & Reliability, Hillsboro, OR; Kenneth E. Goodson, Stanford Univ, Dept of Mechanical Engr, Stanford, CA.

The thermal conductivity of interlevel dielectrics (ILD) in interconnect structures is an important parameter in determining the temperature rise in the interconnects during use. Numerous researchers have previously shown that the thermal conductivity of thin film dielectrics can be significantly lower than that of bulk materials. As new materials, such as low dielectric constant materials, are considered for use as ILDs, methods are needed for measuring the thermal conductivity of the these materials to determine whether they can adequately conduct heat away from interconnect lines. Many methods reported in the literature use patterned metal lines atop the dielectric on a Si substrate as combination joule heaters and temperature sensors, and extract the thermal conductivity from a model of heat conduction through the dielectric to the substrate. One drawback of these methods is the lack of agreement of the conductivity determined from the different techniques. For example, a thermal conductivity ranging from 0.6 to 1.5 W/m-K was calculated for a 1.25-micron-thick PTEOS oxide using four different methods on the same test structure. In this paper we present a unique combination of test structures, experimental methods, and heat conduction models that highlight the limitations of some of the models and methods. We also show good agreement in the thermal conductivity determined from both an experimental method and a finite element model, and suggest that these two techniques yield an accurate measure of the thermal conductivity of thin film dielectrics.

Chair: Zhigang Suo
Thursday Morning, April 3, 1997
Salon 5/6

10:30 AM *J10.1 
MODELING STRESS EVOLUTION IN ELECTROMIGRATION, Michael Thouless, Univ of Michigan, Dept of Mech Engr & Applied Mechs, Ann Arbor, MI.

Diffusional mechanisms of electromigration and stress relaxation involve the flow of atoms along boundaries or interfaces in response to a gradient in chemical potential. It is well-known that non-homogeneous diffusion of matter along boundaries induce elastic distortions and residual stress gradients which, in turn, influence the diffusion process. The effect of these elastic distortions on the atomic flux have been examined by considering diffusion along a single interface in an elastic medium. Furthermore, prior studies of diffusional cavity growth have established the magnitudes of non-dimensional time-scales over which the deposition of atoms along the grain boundaries can be assumed to be essentially uniform. Such an assumption considerably simplifies analyses for stress distributions in these problems. The appropriate time-scales over which such a simplification can be made for electromigration are discussed in this talk. The gradient in chemical potential that drives diffusion may be provided by the component of the electric field parallel to an interface, or by any normal stresses acting on the interface. However, considerations of continuity of the potential dictate that diffusive flow must also be induced along boundaries that intersect the interface. As an example, a model structure is analyzed in which a diffusional path is assumed to exist parallel to an applied electric field, and which contains grain boundaries normal to this path. While the electric field does not directly induce diffusion along these grain boundaries, it can be shown that a complimentary flux must be induced along them. The effect of this flux will be discussed.

11:00 AM J10.2 
FINITE ELEMENT ANALYSIS OF ELECTROMIGRATION-INDUCED STRESS EVOLUTION IN CONFINED METAL LINES, Yongkun Liu, Clemson Univ, Dept of Matls Science, Clemson, SC; Christopher L. Cox, Clemson Univ, Dept of Mathematics, Clemson, SC; Kelvin Poole, Rajendra Singh, Clemson Univ, Dept of E&CE, Clemson, SC.

Electromigration induced failures of interconnect lines are caused by mass transportation and stress development. The life time of a line strongly depends on geometry of the line and microstructure of the line material. Finite element analysis has been conducted to simulate evolution of the stress and vacancy concentration along confined metal lines. For homogeneous microstructure and uniform geometry, the modeling results are consistent with analytical and finite difference solution. Our results further show that conventional NIST test structure (with two big band pads) may overestimate the life time of a line by more than one order of magnitude. For near bamboo like microstructure with polycrystalline clusters, evolution of stress distribution can be divided into four states: initial transition stage, local steady state stage, global transition stage and global steady state stage. Local steady state stress distribution develops quickly. Breaking of local steady state and developing of global transition start from two ends and gradually propagate into center of the line. Stress distribution in final global steady state is determined by electrical current density and is independent of microstructure. Our results also show, if failures occur during development of local steady state stage, life time of a line is relatively independent of band pads and vias. Stress relaxation phenomenon under pulsed current load is also simulated and its effect on life time is discussed.

11:15 AM J10.3 
ELECTROMIGRATION AND STRESS-INDUCED VOIDING IN SHORT Al(Cu) LINES: A COMPARISON OF EXPERIMENTAL RESULTS WITH THEORETICAL PREDICTIONS, Thomas M. Shaw, IBM T.J. Watson Research Ctr, Yorktown Heights, NY; C.-K. Hu, R. Filippi, Robert Rosenberg, IBM T.J. Watson Research Ctr, Research and Microelectronics Div, Yorktown Heights, NY.

Electromigration experiments on short Al(Cu) lines show evidence of resistance saturation. Saturation in turn implies that, at a given current density, a limited amount of void growth can occur in the line. As a consequence a critical current density is required before a total resistance shift large enough to cause failure is reached. In the paper a comparison between the predictions of continuum models for void growth by electromigration and stress voiding and available data for the kinetics of void growth in short lines will be presented. The comparison shows that while the resistance saturation levels attained are reasonably well predicted, the scaling of the rate of void growth with line length is not. The modeling also indicates void growth by stress voiding can be the dominant cause of resistance change in the shortest (25 m) lines. The experiments indicate that this may not always be the case. Possible causes of these discrepancies and the implications for failure prediction will be discussed.

11:30 AM J10.4 
MODELING THE MECHANISMS OF Cu-ENHANCED MEDIAN TIME TO FAILURE IN Al-Cu INTERCONNECTS UNDER ELECTROMIGRATION, Kia Song Low, A. Ghiti, Univ of Newcastle Upon Tyne, Dept of Elect & Electronic Engr, Newcastle Upon Tyne, UNITED KINGDOM; W. C. Shih, A. L. Greer, Cambridge Univ, Dept of MS&E, Cambridge, UNITED KINGDOM; Anthony O'Neill, Univ of Newcastle Upon Tyne, Dept of Elect & Electronic Engr, Newcastle Upon Tyne, UNITED KINGDOM.

In previous work a finite-element model has been used to obtain self-consistent solutions in 3-D for the thermal and electrical transport in an Al-Cu conductor under electromigration. The model includes atomic flow of both species (along grain boundaries only) under electro- and stress migration, and the resulting development of voids. Failure can be treated in terms of resistance increase or catastrophic local heating. In the present work, we explore in more detail the mechanisms of the well known effect in which Cu in Al-Cu metallization increases the median time to-failure (MTF) by up to 2 orders of magnitude. Issues examined include the evolution of the Cu distribution in the grain-boundary network, the role of Cu concentration in changing atomic diffusivity (taken to be the same for Al and Cu), and the role of Al2Cu precipitates as reservoirs of Cu. The model is used to make predictions of the dependence of MTF on the overall Cu content of the metallization.

11:45 AM J10.5 
NEW PROGRESS IN ATOMISTIC MODELLING OF AL-CU INTERFACIAL DIFFUSION, Xiang-Yang Liu, Univ of Illinois-Urbana, Dept of MS&E, Urbana, IL; Wei Xu, Lawrence Livermore National Laboratory, Dept of Pysics & Space Tech, Livermore, CA; Stephen M. Foiles, Sandia National Laboratories, Livermore, CA; James B. Adams, Arizona State Univ, Dept of Chem Biochem & Matls Engr, Tempe, AZ.

To elucidate the underlying atomic mechanisms of microstructure effect on eletromigration, we have studied the segregation of Cu atoms and diffusion processes at Al[110] and [001] tilt grain boundaries, using a newly developed EAM potential from first-principles calculations. Cu atoms are found to segregate to grain boundaries of Al and dominated by size effects. Cu atoms tend to occupy the diffusion path sites in Al at grain boundaries. This makes the vacancy formation energy at grain boundary raised and diffusion via ``conventional channel'' more difficult to proceed. Consideration of diffusion barriers in phase precipitates at boundary is also given and discussed.

Chair: Oliver Kraft
Thursday Afternoon, April 3, 1997
Salon 5/6

1:30 PM J11.1 
INFLUENCE OF VOID GEOMETRY ON ELECTROMIGRATION FAILURE IN VIA-LINE STRUCTURES, Barbara A. Miner, T. S. Sriram, Aldo Pelillo, Digital Equipment Corp, Hudson, MA; Steven A. Bill, Digital Equipment Corp, Digital Semiconductor, Hudson, MA.

Tungsten-filled vias between fine-etched metal levels pose a significant electromigration risk in deep submicron multilevel interconnection technologies. Via-Aluminum interfaces are sites for flux divergence and consequently sites for electromigration-induced void formation. Failure due to electromigration voiding at these interfaces occurs in the form of a resistance increase. The resistance versus time behavior varies significantly from sample to sample. The present study uses extensive failure analysis using FIB/SEM and TEM to characterize electromigration failure sites and correlate the void geometry to resistance behavior. In longer-lived samples, the via resistance is more immune to failure from void growth. The differences in lifetime between samples cannot be examined by microstructural features of the Al underneath (such as grain orientation or presence of clusters). The main factor that influences lifetime is the size of void that can be sustained without failure. 
Failure in short-lived samples can be caused by very small voids at the tungsten-aluminum interface. It appears that process-induced contamination can make parts of this interface highly resistive. This can cause a large increase in resistance with relatively small amounts of aluminum moved. In long-lived samples, there can be significant void growth without significant change in resistance. In these samples, the failure analysis revealed the presence of TiN antireflection coating used int he interconnect stack and the A intermetallic formed by reaction with the Ti underlayer.

1:45 PM J11.2 
BEHAVIORS OF PRECIPITATES, VOIDS, AND HILLOCKS IN ELECTROMIGRATION-STRESSED Al-2wt%Cu INTERCONNECTS, David E. Grosjean, NEC Corporation, Microelectronics Research Labs, Ibaraki, JAPAN; Hidekazu Okabayashi, NEC Corporation, Research & Development Group, Ibaraki, JAPAN; Masao Komatsu, Hirotaro Mori, Osaka Univ, Center for Ultra-High Voltage Electron Microscopy, Osaka, JAPAN.

We observed the dynamics of AlCu precipitates, voids, and hillocks under electromigration (EM) stress (250 C, <2 MA/cm) in sub-micron wide Al-2wt%Cu lines on a TiN underlayer in a drift velocity measurement structure using in-situ and ex-situ side-view TEM. All identified -phase precipitates (identified by electron diffraction) were based at the Al/TiN interface. Precipitates near the cathode ends of lines shrank under EM, while those at the anode grew. Precipitates that grew at the anode end often did not have clear diffraction patterns, but EPMA measurements verified the accumulation of large amounts of Cu. The crystal orientations of growing precipitates did not change with EM stressing for a limited number of identified precipitates. Voids did not initially grow where precipitates were eroded; Al replaced the difference in volume between -phase and Al matrix. Voids grew at the cathode ends of lines at the interface with the TiN underlayer and at the top away from the interface. In previous experiments at higher temperatures and current densities (300-350C, 7-9 MA/cm), we observed and classified void growth processes based on morphology changes. The void growth processes we observe here under these milder test conditions also fall into those previous categories. Additionally, the transport of Al through a void, along the TiN underlayer and/or along the sides, was observed under these milder test conditions. Virtually all voids grew in faceted ways at the cathode ends of the lines. Hillock growth in the last grain of each line was slower than in the neighboring grains.

2:00 PM J11.3 
EARLY CHANGES IN AL LINES DURING CURRENT STRESSING, Holger Schuehrer, Hubert Brueckl, Guenter Reiss, Inst of Solid State & Materials Research, Desden, GERMANY.

Due to the downscaling of microelectronics devices and the increase of the current density in conductor lines, electro- and thermomigration become more and more important for the reliability. A lot of the methods to analyze failures in lines, however, are destructive and do not have a high structural resolution. Thus it is difficult to obtain information of the initial states of failures. In this paper we will show, that the scanning force mircoscopy is a good tool to observe the microscopic changes in morphology of lines during current stressing with a very high resolution. An atomic force microscope (AFM) was used to image AlSiCu meander structures (1m thick, 4m wide, 44mm long) at room temperature during current stressing. During the current stressing the resistance of the lines was monitored. The structure of the sample (current density : 410 A/cm) showed significant changes already before voiding and hillock growth occured. Growth and reduction of the grain sizes and also grooving and widening of the grain boundaries was observed. Even sometimes whole grains and the boundaries was moving, whereby the resistance of the sample did not change. Additionally the influence of thermomigration (effected through Joule heating) was observed by inspecting a meander parallel to the current stressed line. Some drastic effects in morphological changes in the grains can are detected and compared with the lines where both electro- and thermomigration took place.

2:15 PM J11.4 
IN-SITU TEM-INVESTIGATION OF STRESS AND ELECTROMIGRATION-INDUCED VOID FORMATION AND GROWTH IN PASSIVATED AL-LINES, Dirk Heinen, Herbert Schroeder, Werner Schilling, Forschungszentrum Julich GmbH, Inst fur Festkorperforschung, Julich, GERMANY.

In-situ TEM observations on void formation and growth have been performed in passivated Al-lines in order to collect detailed microstructural data such as void number density, void size distribution and growth rates as a basis for modelling stress relaxation and electromigration effects. The samples were 1 mm long lines of 200 nm thick PVD Al with different widths (0 8, 1.6 and 2.4 m) with two different SiN passivation thicknesses (100 and 200 m). Additional experiment parameters were average gain size (0.4 um to more than 3m, i e., nearly perfect bamboo structure in the lines), relaxation time (0.1 to 50 h) and temperature (20 - 300C), electromigration current density (without current, 1MA/cm). First measurements without current reveal that stress induced voids 
- develop at about 350C during cooling frown 450C; and they start shrinking at 250C and disappear completely at 420C upon heating 
- have an area of at least (100 nm) for t<250C with a wide size distribution 
- have a decreasing number density and total area but a constant mean void size and growth rate with increasing number of temperature cycles (n < 4) 
- show growth rates which are very dependent on time and temperature 
Such data as well as data with electromigration current will lee compared to macroscopic stress relaxation results by wafer curvature and X-ray diffraction and discussed in the light of current models.

2:30 PM J11.5 
IN SITU OBSERVATION OF CURRENT-INDUCED DISLOCATION MOTION, Vladimir T. Volkov, Inst of Microelectronics Technology, Dept of Novel Film Deposition Techniques, Chernogolovka, RUSSIA; Yurii B. Gorbatov, Inst of Microelectronics Technology, Dept of Ion Technologies, Chernogolovka, RUSSIA; Eduard D. Ivanov, Inst of Microelectronics Technology, Dept of Transmission Electron Microscopy, Chernogolovka, RUSSIA.

An electric current can interact with a dislocation so as to cause it to move. Such an interaction might be expected to effect the electromigration behavior of the thin metal conductor lines used as interconnects in integrated circuits. Current-induced dislocation motion was recently observed in microbridges, fabricated from bulk ultra-pure copper single crystal. It was found that dislocation motion had a threshold nature with respect to current density. The value of this threshold is 10-15 MA/cm2. Thin film stripes from pure copper and aluminum were prepared on membranes which are suitable for TEM observations. Films were deposited onto Si3N4 membranes by the self-ion assisted technique. Lines were cut out from the films by focused ion beam and stressed by current in the column of transmission electron microscope. Results of the in situ observations will be discussed in the paper from the view point of electromigration behavior of the lines.

Chairs: Robert R. Keller and Zhigang Suo 
Thursday Afternoon, April 3, 1997
Salon 5/6

3:15 PM J12.1 
MECHANICAL PROPERTIES OF AL-(0-2wt%)CU FILMS WITH VARIOUS HEAT TREATMENTS, Young-Chang Joo, Peter Mullner, Max-Planck-Inst, Inst fur Metallforschung, Stuttgart, GERMANY; Shefford P. Baker, Max-Planck-Inst,; Edward Arzt, Max-Planck-Inst, Inst fur Werkstoffwissenschaft, Stuttgart, GERMANY.

Precipitation and alloy hardening have been studied in Al-(0-2wt)Cu thin films. We have changed the precipitate and dislocation structures of films having different Cu concentrations by varying the heat treatments prior to mechanical testing. Mechanical properties were measured using the substrate curvature method. Pure Al films showed the same values of tensile and compressive yield stresses at a given temperature during stress-temperature cycling. However, Al(Cu) alloys or nominally pure Al with small Fe and Cr impurities showed larger tensile yield stresses than compressive yield stresses. In many cases the heat treatment of the Al(Cu) films resulted in an increase of the compressive flow stress during heating in the curvature experiments. This increase in hardness disappeared by 250C. The fact that this hardening is only observed in films containing Cu suggests it is related to the interaction of dislocations with precipitates. Upon cooling from 480C, solution hardening as well as precipitation hardening is observed in the Al(Cu) films. The solute hardening rate is independent of Cu concentration, but for precipitate hardening, the greater the Cu concentration, the higher the temperature at which hardening begins. TEM observations show heavily curved threading dislocations in the Al(Cu) films but few dislocations In pure Al, which also suggests easy dislocation motion in the pure Al. All of these qualitative and quantitative results clearly show hardening in the Al(Cu) films relative to pure films. The hardening behaviors are discussed based on TEM observation.

3:45 PM J12.3 

Stress voiding is caused by the difference in the thermal expansion coefficients of the metallization lines and the surrounding passivation. Volumes of individual stress voids are measured as a function of stress time at 200C in 1-m-wide AlCu(1wt) integrated circuit metallization lines [1]. Between 30 and 100 days of stress, the total void volume approaches the value of the volume difference between AlCu line and the surrounding passivation at 200C. If the void growth is regarded as an isothermal phase transformation in which voids are formed as precipitates at the void nucleation sites, the void volume growth is accurately described by the Avrami equation with a time power =0.5. Calculations from first principles show that the necessary conditions for =0.5 in the Avrami equation are: void dimensions are limited by the top and the bottom interface of the line; void nucleation sites are gradually exhausted; voids nucleate quickly; void growth is diffusion controlled. First principle calculations are in excellent agreement with the measurements. Data at lower stress temperatures will also be presented. Implications for the integrated circuit manufacturing process yield will be presented.

4:00 PM J12.4 
DEFORMATION OF PASSIVATED METAL LINES ON Si SUBSTRATES, Andrew Gouldstone, MIT, Dept of MS&E, Cambridge, MA; Yu-Lin Shen, Univ of New Mexico, Dept of Mech Engr, Albuquerque, NM; V. T. Srikar, Subra Suresh, MIT, Cambridge, MA; Carl V. Thompson, MIT, Dept of MS&E, cambridge, MA.

We study the elastic, plastic, and thermal responses of patterned metal lines on Si wafers. Passivated and unpassivated pure Al lines with various thicknesses, widths and spacings were etched onto Si substrates, and measurements of the wafer curvatures along and perpendicular to the lines were performed at different temperatures. In parallel with the experiments, detailed numerical simulations of the etching, passivation and subsequent thermal cycling of the specimens were carried out, within the context of a finite element model involving a generalized plane strain formulation. The geometry dependence of the deformation characteristics of the metal lines is extracted by comparing the theory with experiments.

4:15 PM J12.5 
THE EFFECT OF LOW K DIELECTRICS ON THE THERMO-MECHANICAL BEHAVIOR OF DIELECTRIC ENCAPSULATED INTERCONNECT STRUCTURES, Pei-Hua Wang, Univ of Texas-Austin, Austin, TX; Paul S. Ho, Univ of Texas-Austin, Dept of MS&E, Austin, TX; Tze-Wing Poon, Jihperng Leu, Motorola Inc, Austin, TX.

As device scaling continues, signal delay, power dissipation, and crosstalk noise become serious concerns due to the increasing line-to-line capacitance. This has generated considerable interest in developing low dielectric constant materials to replace the existing interlevel dielectric SiO for deep-submicron interconnects. Among potential candidates with 3.0, polymeric dielectrics show promising electric and mechanical properties. However, due to its viscoelastic behavior and chain morphology, the thermomechanical behavior of polymers is distinctly different from that of SiO. The impact of polymer dielectrics on the stress behavior and structural integrity of dielectric/metal structures is not yet fully understood. A finite element analysis was used to study the stress behavior of single level Al and Cu lines under planarized SiO and polymers passivation. Two representative classes of low k materials, namely fluorinated polyimide (high mechanical strength but low thermal expansion) and fluorinated poly(arylene ether) (low mechanical strength but high thermal expansion) were chosen in this study. In oxide/metal structure, we found a near-hydrostatic stress ( +650 MPa) in the passivated submicron lines and its magnitude increases with decreasing linewidth. In contrast, a nonhydrostatic stress (maximum +200 MPa) state with negligible stress in the line normal direction was observed in polymer/metal structure. The large near-hydrostatic stress can induce the void formation and degrade the long-term reliability of deep submicron interconnects. In comparison, the nonhydrostatic stress may induce a high shear stress at metal-polymer interfaces, especially near the corner region. The stress behavior of two representative low k materials in polymer/metal dielectric structure at various aspect ratios and its effect on structural integrity will be also discussed.

4:30 PM J12.6 
COMPARISON OF STRESSES IN Al LINES UNDER VARIOUS PASSIVATONS, Samantha Lee, John C. Bravman, Paul A. Flinn, Stanford Univ, Dept of MS&E, Stanford, CA; Thomas Marieb, Intel Corp, Dept of Components Research, Santa Clara, CA.

Passivation changes the stress state in metallization lines. Previous studies involving both finite element analysis as well as actual stress measurements have been carried out; however, there has been a lack of systematic study on the effect different passivations may have on line stresses. A series of vastly different passivations have been deposited at various temperatures and thicknesses on pure Al lines. Comparisons were made via x-ray measurements and finite element analysis. In addition, a high-voltage scanning electron microscope was used to examine the passivated lines for stress voiding, which can serve as a stress relaxation mechanism. 
Pure Al films 7200 thick were deposited on 250 of Ti on Si wafers. The films were capped with 50 of TiN and patterned into an array of lines 1.0 wide, with 1.0 spacings. After patterning, a 1000 oxide layer was deposited on all lines in order to eliminate chemical effects. 1.0 of ECR oxide, ECR 5fluorinated oxide, ECR 10fluorinated oxide, PTEOS, SiO, SiN, and polymer were deposited at 400C (with the exception of the polymer) to study the effect of passivation composition. ECR oxide and SiN of thicknesses ranging from 0.5 to 2 were deposited at 400 C to study the effect of constraint, and 1.0 thick ECR oxide was deposited at 250C, 325C, and 400C in order to study the effect of deposition temperature.

4:45 PM J12.7 
THE EFFECT OF Ti INTERLAYER ON THE HILLOCK FORMATION OF Al-Cu FILMS ON THE TiN/Ti/SiO/Si MULTILAYER STRUCTURE, Lih-Ping Wang, National Tsing Hua Univ, Dept of MS&E, Hsinchu, Taiwan; A. Chuang, United Microelectronics Co, Process Engr Dept, Hsinchu, TAIWAN; F. S. Feng, National Tsing Hua Univ, Dept of Elect Engr, Hsinchu, TAIWAN; Jenn-Chang Hwang, National Tsing Hua Univ, Dept of MS&E, Hsinchu, TAIWAN.

The hillock formation has been one of the important issues in the reliability of Al-based metallization which may seriously deteriorate IC circuit. Hillocks usually form out of Al-alloy surface plane due to the relaxation of compressive stress during heat treatment. In the past year, the insertion of Ti layer in the Al-Cu/TiN/Ti/SiO/Si multilayer structure ahs been proven able to improve the extent of Al(111) texture and hence improve the electromigration resistance. It is of great interest to investigate how the hillock evolution of the annealed Al-Cu films is influenced by the insertion under TiN layer. The x-ray -scan we applied to determine the degree of texture of Al-Cu layer on TiN(/Ti)/SiO/Si multilayer structure. The degree of Al(111) texture is improved by the insertion of Ti interlayer which was confirmed by the orientation factor in the x-ray -scan and also reflected in the increase of the intensity of normal x-ray by a factor of 810. Two types of hillocks, large and small, were observed for both multilayer structures, with or without Ti interlayer after heat treatment at 400C for 30 minutes. However, the morphologies of hillocks differ due to the insertion of Ti interlayer. With the Ti in the multilayer, the large hillocks are round and high (>200 nm) with a moat around; the small hillocks are round but low without a moat around. While, without the Ti in the multilayer, the large hillocks are round and high with a moat around, the small hillocks exhibit disk-like plateaus. The wedge-like and disk-like plateau features disappear when the Ti layer is inserted into the Al-Cu/TiN(/Ti)/SiO/Si structure. The effect of Ti interlayer on the hillock growth is correlated to the texture of Al-Cu films.

5:00 PM J12.8 
RELIABILITY IMPROVEMENT OF PASSIVATED POWER LINE IN MEMORY DEVICES, Seong-Min Lee, Y. K. Jang, Y. W. Chung, S. M. Sim, K. W. Lee, B. K. Hwang, Samsung Electronics Co Ltd, Dept of Package Development, Suwon, SOUTH KOREA.

In the present study, several different types of amorphous passivation layers such as PECVD-SiN, PECVD-PEOX and PECVD-TEOS were tested to learn how effectively they protect underlying Al interconnection lines. According to the experimental works, a thick monolithic passivation layer composing of PECVD-SiN was found to be highly susceptible to the stress related migration because it does not have sufficient elasticity. Moreover, since it also has a high dielectric-breakdown strength, it exhibits the increased impedance of electric current due to parasitic resistances existing in the path between two passivated metal lines. On the other hand, the passivation thickening by the use of PECVD-TEOS as an initial layer was estimated to be more effective way to improve device reliability because of its good step coverage and small dielectric constant. The FEM simulation explains why the thick multilayer comprising an alternating sequence of mechanically dissimilar layers is an effective way to suppress the stress-induced passivation damage during thermal cycling without causing any significant effect on the IC pattern.