Meetings & Events

Spring 1999 logo1999 MRS Spring Meeting & Exhibit

April 5-9, 1999 | San Francisco
Meeting Chairs: Katayun Barmak, James S. Speck, Raymond T. Tung, Paul D. Calvert



Symposium S—Si Front-End Processing-Physics and Technology of Dopant-Defect Interactions

Chairs

Hans-Joachim Gossmann 
Bell Labs, Lucent Technologies 
Rm 1D-150 
Murray Hill, NJ 07974 
908-582-6217

Tony Haynes
Oak Ridge National Lab
MS 6048 - Bldg 3003
Oak Ridge, TN 37831
423-576-2858

Arne Nylandsted Larsen 
Inst of Physics & Astronomy 
Aarhus Univ 
Aarhus, DK-8000 DENMARK 
45-8942-3720

Mark Law
Dept of E&CE
Univ of Florida
Gainesville, FL 32611
352-392-6459

Shinji Odanaka 
ULSI Process Technology Development Ctr 
Matsushita Electronics Corp 
Kyoto, 601 JAPAN 
81-75-6626137

 

Symposium Support 
*Applied Materials, Inc. 
*Lucent Technologies, Bell Labs, 
*Eaton Semiconductor Equipment Operations 
*Intel Corporation 
*National Electrostatics Corporation 
*Oak Ridge National Laboratory 
*Sematch, Inc. 
*Silvaco Data Systems

1999 Spring Exhibitor 

Proceedings published as Volume 568 
of the Materials Research Society 
Symposium Proceedings Series.

* Invited paper

SESSION S1: ULTRA-SHALLOW JUNCTIONS I 
Chairs: Hans-Joachim L. Gossmann and Shinji Odanaka 
Tuesday Morning, April 6, 1999 
Golden Gate C1 (M)
8:30 AM *S1.1 FUNDAMENTAL ISSUES IN SCALING DOPANT PROFILES FOR DEEP SUBMICRON TRANSISTOR DESIGN. Paul Packan , Intel Corporation Hillsboro, OR. 

As transistor dimensions continue to scale into the deep submicron regime, it is becoming increasingly difficult to maintain current performance trends. The general direction of technology improvement has been based on scaling doping profile junction depths through lowering implant energies and decreasing thermal cycles. Although this has proven to be an effective method for previous technologies, it may not be sufficient for future scaling. More advanced process architectures such as super steep retrograde wells (SSRW) and aggressive lateral channel engineering have been required to maintain performance improvement trends. This talk will discuss the implications of dopant-defect interactions on current process architectures. The effects of implantation, preamorphization and thermal processing will be addressed. In addition, fundamental issues in transistor device scaling will be explored. The effect of source-drain junction depth and lateral underdiffusion on device performance will be analyzed. It will be shown that unlike previous technologies, current device scaling is facing fundamental limits. 

9:00 AM S1.2 
TEMPERATURE- AND TIME-DEPENDENCE OF BORON-ENHANCED-DIFFUSION FROM EVAPORATED AND ULTRA-LOW ENERGY ION-IMPLANTED BORON LAYERS. Aditya Agarwal , Eaton Semiconductor Equipment Operations, Beverly, MA; H.J. Gossmann, Bell Laboratories Lucent Technologies, Murray Hill, NJ. 

We have further characterized the diffusion enhancement mechanism BED (boron-enhanced-diffusion), shown previously to be driven by excess interstitials created in silicon layers containing boron concentrations of few atomic percent. Evaporated-boron as well as ultra-low energy 0.5-keV B-implanted layers were annealed at temperatures from 1100 to 800C for times ranging from 3 to 3000s. Isochronal 10s anneals reveal that the BED effect increases with increasing temperature up to 1050C and then decreases; the enhancement is negligible at 800C, <1.5x at 950C, 2.5x at 1000C, 4x at 1050C, and 3x at 1100C. In contrast, simulations based on interstitial generation via the kick-out mechanism predict a decreasing dependence of diffusivity enhancement on increasing temperature; this disagreement with experimental data leads to the conclusion that the kick-out mechanism is not the dominant source of excess interstitials responsible for BED. The diffusivity enhancement from the combined effects of BED and TED (transient-enhanced diffusion), measured in 2x1015 cm-2, 0.5-keV B implanted samples, shows a similar temperature dependence as seen for evaporated B, during 10s isochronal anneals, except that the maximum enhancement, of 10x, occurs at 1000†C. The temperature dependent behavior of BED is consistent with, and supports, the hypothesis that the source of excess interstitials is the formation of a silicon boride phase in the high boron concentration silicon layer. 

9:15 AM S1.3 
ONSET OF EXTENDED DEFECT FORMATION AND ENHANCED DIFFUSION FOR ULTRA-LOW ENERGY BORON IMPLANTS. Jinning Liu , Daniel F. Downey, Varian Ion Implant Systems, Gloucester, MA; Kevin S. Jones, SWAMP Center, Department of Materials Science and Engineering, University of Florida, Gainesville, FL. 

To meet the challenge of achieving ultra shallow p+/n source/drain extension junction for 0.10m node devices, ultra low energy boron implant and advanced annealing techniques have been explored. In this paper, we report the extended defect and boron diffusion behavior with various implant conditions and annealing ambients. Boron implant was performed at energies from 0.25keV to 1keV and doses of 5e14cm-2 and 1e15cm-2. Rapid thermal anneals were carried out in nitrogen ambient with low concentrations of oxygen ranging from 0-1ppm to 1000ppm. The effect of energy, dose and oxygen concentration on extended defect formation and enhanced dopant diffusion was examined. It was observed that above the defect formation threshold (0.5keV for 1e15cm-2 and 1keV for 5e14cm-2 implant), increasing oxygen concentration results in larger dislocation loops. With optimized oxygen concentration (33ppm) boron diffusion via oxidation, boridation and transient effect is minimized. 

9:30 AM S1.4 
SUB-NM SCREENING LAYER APPROACH FOR ULTRA SHALLOW JUNCTION FORMATION. Mitsuaki Hori , Toshiki Miyake, Ken-ichi Hikazutani, Yoshikazu Kataoka, Manabu Nakamura, Takayuki Wada, and Masataka Kase, Fijitsu Ltd., ULSI Development Division, Mie, JAPAN. 

High performance MOSFET requires both p-type junction characteristics of shallow and low resistivity. The ultra low energy B implantation at sub-keV and spike annealing are the technologies achieving this purpose. The screening oxide is critical issue in such shallow junction, so it is required that appropriate surface layer provides the characteristics to suppress B out-diffusion, to be thin sufficiently and not to diffuse B as oxidation enhanced diffusion (OED). In this study, sheet resistivity () and B profile is investigated depending on sub-nm scr-ox formed by several processes. On <100>-oriented n-type wafers before and/or after ion implantation several types of surface layer, e.g., chemical oxide using wet process, were formed. Ion implantation was performed in conditions of B+ at energy of 0.5 keV with a dose of 2x1015 cm-2. Rapid thermal annealing (RTA) was performed at 1050C and spike condition. Sheet resistivity, thickness of oxide and B depth profile were collected at four point probe measurement, ellipsometry measurement and secondary ions mass spectroscopy (SIMS), respectively. The sample of scr-ox of chemical oxide of HNO3 treatment has the  of 252 /sq. and the junction depth of 64 nm, and the ones of diluted HF (no scr-ox) has 263 /sq. and 54 nm. The thickness of oxide is 0.85 and 0.17 nm after HNO3 and diluted HF treatment, respectively, so the amount of B into the scr-ox is calculated 27 and 7 of implanted B from as-implanted profile. The sample of HNO3 treatment has smaller amount of B in Si than one of diluted HF treatment, however it has a deeper junction and lower sheet resistivity. Thus, we propose the mechanism that during RTA the chemical oxide changes the characteristics, e.g., densification, then it makes the point defect to enhance the B diffusion like as OED. 

9:45 AM S1.5 
EPITAXIAL CoSi2 LAYERS AND DOPANT OUT-DIFFUSION. S. Ohmi, R.T. Tung and H.J. Gossmann, Lucent Technologies Bell Labs., Murray Hill, NJ. 

Silicide as doping source (SADS) has been discussed as a viable method to create ultra-shallow junctions in future sub-100nm ULSI devices. With the down-scaling, the thickness of silicide layers expected to accommodate these implantation and annealing procedures is estimated to be less than 25nm. The uniformity and thermal stability of these silicide layers are therefore of great concern. In this work, 18-40nm thick CoSi2 layers are grown on narrow Si lines by a variety of techniques including oxide mediated epitaxy (OME), high temperature sputtering (HTS), template growth and Ti capped formation. The epitaxial characteristics of these CoSi2 layers vary from single crystal for OME grown layers, to highly 100- and 221-oriented layers, to essentially randomly oriented layers for other processing conditions. In particular, the epitaxial formation of CoSi2 layers by the HTS or template technique is found to vary significantly with details of their processing condition. The thermal stability of these layers is shown by TEM and sheet resistance measurements to depend on the thickness, texture and epitaxial characteristics of the silicide layer. Epitaxial and highly oriented CoSi2 layers are found to remain uniform after anneals at >900C, while polycrystalline CoSi2 layers of comparable thickness began to agglomerate at 850C. Dopant out-diffusion from selected samples implanted with low energy B, BF2 and P is studied as a function of implantation and annealing conditions. Junction formation after rapid thermal anneals at 900C is also discussed for epitaxial and non-epitaxial CoSi2 layers. 

10:30 AM *S1.6 
FORMATION OF ULTRA-SHALLOW JUNCTIONS: RAMP RATE EFFECTS, SPIKE ANNEALS. Aditya Agarwal , Eaton Corporation, Semiconductor Equipment Operations, Beverly, MA. 

Over the last couple of years, rapid thermal annealing (RTA) equipment suppliers have been aggressively developing lamp-based furnaces capable of achieving ramp-up rates on the order of hundreds of degrees per second. One of the driving forces for adopting such a strategy was the experimental demonstration of 30nm p-type junctions by employing a ramp-up rate of 400C/s. It was proposed that the ultra-fast temperature ramp-up was suppressing transient-enhanced diffusion (TED) of boron which results from the interaction of the implantation damage with the dopant. The capability to achieve very high temperature ramp-rates was thus embraced as an essential requirement of the next generation of RTA equipment. Experimental data will be presented which systematically examines the effect of ramp-up rates on enhanced diffusion and shallow junction formation during spike-anneals. A spike-anneal may be characterized by a fast ramp-up to temperature with essentially zero time at temperature. A significant reduction in junction depth is observed with increasing ramp-up rate for only the shallowest, 0.5-keV,ultra-low energy (ULE) B implants, but only a marginal improvement is found for deeper 2- and 5-keV implants. It can be concluded from the data that TED, which dominates diffusion for the deeper implants, is already sufficiently suppressed at ramp-up rates as low as 50C/sec. The observed reduction for 0.5-keV B hence results from a straight-forward decrease in the total thermal budget. The experimental observations will be compared with predictions based on the transient-enhanced and boron-enhanced diffusion mechanisms. 

11:00 AM S1.7 
SHALLOW BORON IMPLANT ACTIVATION. A.T. Fiory , Bell Laboratories Lucent Technologies, Inc., Murray Hill, NJ and K.K. Bourdelle, Bell Laboratories Lucent Technologies, Inc., Orlando, FL. 

Boron implanted into n-type Si with dose in the 1015 cm-2 range and with energies from 500 eV to 5 keV was activated by annealing in nominally pure N2 and in N2 with small admixtures of O2. Various temperature-vs-time heating cycles were examined. The lowest thermal budgets used heating rates up to 150C/sec, cooling rates up to 80C/sec, and minimal dwell time at the maximum temperature. Dopant activation was characterized by sheet electrical measurements. Surface oxidation was characterized by film thickness ellipsometry. Defined p-n junction depths were inferred from analysis of electrical measurements and secondary ion mass spectroscopy profiles. Fractions of activated dopant increase with boron diffusion from the implanted region. Surface oxide serves to retard dopant loss to the ambient for high-temperature anneals. 

11:15 AM S1.8 
SUB-30 nm ABRUPT P+ JUNCTION FORMATION WITH Ge PREAMORPHIZATION AND HIGH ENERGY Si Co-IMPLANTATION. Kam Leung Lee , Ted Zabel, Raman Viswanathan and Kai Chen1, IBM Research Division, Thomas J. Watson Research Center, NY; 1IBM Microelectronics Division, Hopewell Junction, NY. 

Experiments had been carried out to form ultra-shallow (Xj< 50nm) and abrupt(Xjs < 5 nm/decade) P+ junction for sub-50 nm CMOS devices using a combination of shallow implant, Ge preamorphization and high energy Si implant as interstitial getter layer. Various combinations of shallow extension implants (BF2, 1-5 keV, 1E15 dose), Ge preamorphization (range of energies and doses) and Si getter layer (28-1000 keV, 1E14-1E15 doses) were used to determine the optimum conditions for achieving the simultaneous goals of good defects anneal, dopant activation, shallowest Xj and abrupt Xjs. The RTA conditions were fixed at 1000C,1 second with a ramp rate of 125C/sec. A comparison study was also made with other conventional approaches such as shallow extension implant (I/I) alone, shallow I/I+ Si implants and shallow I/I+ Ge preamorphization. Some of the key findings of these studies are summarized as follows: (i) At dose level of 5E14 or above, the Si getter layer essentially stops the transient enhanced diffusion(TED) at the boron tail region. In addition, it was found that the effectiveness of the interstitials gettering process is more sensitive to the Si implant dose than the positioning of the getter layer (500 to 10,000  from the Si surface) relative to the shallow implants.(ii)Experimentally, it was observed that the Si getter layer, in the presence of the Ge preamorphization, not only stops the TED at the boron dopant tail and at the same time promotes enhanced boron diffusion close to the surface boron peak. These unique features have enabled the shallowest and sharpest box-like boron junction yet achieved, i.e. with 1 keV BF2, Xj 23 nm, Xjs 4.8 nm/decade, no Ge end of range damages and good dopant activation at the same time i.e. sheet resistance Rs 1 kohm/sq which is comparable to shallow I/I+ Ge and is better than the shallow I/I alone (Rs 2.38 kohm/sq) or the shallow I/I + Si implant cases (Rs 1.5 kohm/sq). (iii) Device results show that there is no additional junction leakage introduced by the Si getter layer nor its getter action was diminished by the intermediate device well implants. 

11:30 AM S1.9 
ULTRA-LOW ENERGY BORON IMPLANTS IN CRYSTALLINE SILICON FOR ULTRA-SHALLOW JUNCTION FORMATION:ATOMIC TRANSPORT PROPERTIES AND ELECTRICAL ACTIVATION. E. Napolitani , A. Carnera, INFM and Dept of Physics, Padova, ITALY; V. Privitera, A. La Magna, E. Schroer, CNRÑIMETEM, Catania, ITALY; F. Priolo, G. Mannino, INFM and Dept of Physics, Catania, ITALY; S. Moffatt, Applied Materials, Applied Implant Technology Ltd, Horsham, ENGLAND. 

We investigated the atomic transport properties and electrical activation of boron in crystalline silicon after ultra-low energy ion implantation (0.25-1keV) and rapid thermal annealing processes (650-1100C). A wide range of implant doses were investigated (3x1012ñ1x1015/cm2), and both epitaxial and Czochralski silicon layers were implanted. A fast Transient Enhanced Diffusion (TED) pulse is observed involving the tail of the implanted Boron, the profile displacement being dependent on the implant dose and the purity of the material. The excess of interstitials able to promote enhanced diffusion of implanted boron occurs, provided the implant dose is high enough to generate a significant total number of point defects. The Boron diffusion following the fast initial TED pulse can be described by the equilibrium diffusion equations. We studied also the effects of altering the defect population, by performing amorphisation or chemical etching of the near surface region. The former process introduced a source of point defects at the amorphous/crystal interface, which affected the diffusion phenomena relative to the ultra-shallow boron implant. The latter instead removed the densest region in terms of point defects induced by the boron implantation, so showing the influence of the point defects produced by the boron itself on its diffusion. The electrical activation of ultra-shallow implants is hard to achieve, due to the high concentration of dopant and point defects confined in a very shallow layer which significantly contributes to the formation of clusters and complex defects. The amount of active boron was strongly dependent on the annealing temperature and time and was limited by a significant out-diffusion and/or surface trapping occurring during the annealing. Provided a correct combination of annealing temperatures and times for these ultra-shallow implants is chosen, however, a sheet resistance of 500 /square with a junction depth below 0.1m can be obtained, which has a noteworthy technological relevance for the future generations of semiconductor devices. 

11:45 AM S1.10 
DECABORANE AS ION SOURCE MATERIAL FOR BORON IMPLANTATION. Marek Sosnowski , Ravidath Gurudath, John Poate, New Jersey Institute of Technology, Newark, NJ; Anthony Mujsce, Dale Jacobson, Bell Laboratories Lucent Technologies, Murray Hill, NJ. 

Formation of shallow junctions in the future generations of Si devices will require ion implantation of B at very low energies, i.e. below 1 keV, where the beam formation and transport at reasonably high currents are hindered by the ions Coulomb repulsion. An alternative to implantation of monomer ions at very low energy is implantation of large molecular ions at a higher energy. In the latter case, the implantation depth corresponds to a fraction of the beam energy, partitioned between the atoms of a molecule. The molecule of decaborane, which consists of 10 B atoms and 14 H atoms, is of particular interest for implantation of p-type shallow junctions in Si, because each of the B atoms carries only 9% of the molecular beam energy. Experimantal P-MOS devices made using decaborane implantation have been demonstrated recently. It also has been shown that enhanced transient diffusion of B in silicon is the same after decaborane and B implantations of the equivalent energy and dose. Application of decaborane in Si processing will depend on the success of generating sufficiently intense ion beams of this material. The prospects of using decaborane in ion implanters are examined, based on measurements of its ionization properties. 

SESSION S2: ULTRA-SHALLOW JUNCTIONS II 
Chair: Aditya Agarwal 
Tuesday Afternoon, April 6, 1999 
Golden Gate C1 (M)
1:30 PM S2.1 
PRACTICAL ASPECTS OF FORMING ULTRA-SHALLOW JUNCTIONS BY SUB-keV BORON IMPLANTS WITH xR-LEAP AND RTP-CENTURA. M.A. Foad , A.J. Murrell, E.J.H. Collart, G. de Cock, D. Jennings, Applied Materials, Santa Clara, CA. 

As the drive towards production of 100 nm CMOS devices picks up speed, the practical aspects of transistor shallow junction formation, including a large menu of process integration issues, must now be solved in short order. The most direct path to 50 nm junction depths is through the use of sub-keV Boron implantation and rapid thermal annealing. The materials aspects of the process integration agenda centers on: (1) CMOS device requirements for shallow, high-activated and abrupt junctions (involving the choice of ion species [B, BF2, B10H14, BSi2, etc.], substrate material [CZ, Epi, SOI], anneal conditions [ramp rate and soak time, gas ambient], etc.), and (2) Defect-dopant interactions during annealing (including surface reactions of high concentration species [B, F], diffusion and carrier trapping by background and/or co-implanted species [C,O,F,etc.], evolution of point and line defect populations, surface morphology effects [roughness, voids, bubbles], etc). Process data for atomic and electrical activity profiles as well as defect and interface structures will be presented to illustrate progress towards understanding these complex process interactions. A particular focus will be the effects of anneal ambient and rapid temperature rise times approaching the spike anneal ideal. 

1:45 PM S2.2 
CHARACTERIZATION OF ULTRA-SHALLOW BF2 IMPLANTS BY SIMS: A STUDY TO DETERMINE THE MOST ACCURATE PROFILING CONDITIONS. Gary R. Mount , Charles J. Hitzman, Stephen P. Smith and Victor K.F. Chia, Charles Evans & Associates, Redwood City, CA. 

Calibration of process modeling software, characterization of implanters and anneal processes all rely on accurate and reproducible SIMS measurements. SIMS characterization of ultra-shallow boron implants has proven to be very challenging and no single protocol has emerged as the clear method of choice. In this paper, we investigate several analytical approaches to find the conditions that most accurately report profile shape, dose, and junction depth. 500 eV, 1000 eV, and 2500 eV BF2 implants are investigated in both as-implanted and annealed conditions. Much of the ultra-shallow implant is within 20nm of the surface. This is within the depth where the SIMS primary ion beam reaches equilibrium with the substrate at typical primary beam energies. Lowering the primary beam energy to 1 keV or less minimizes but does not eliminate the equilibration zone. Secondary ion yields can be made constant to within a few tenths of a nanometer of the surface by using surface oxidizing conditions. Surface oxidizing conditions can be achieved by flooding the surface with oxygen or by growing oxide from the primary beam. Oxide can be grown using low sputter yield conditions provided by a normally incident oxygen beam. Good depth resolution can be achieved with relatively short analysis times by using low primary beam energy, high angles of incidence, and oxygen flooding. However, under some conditions, crater bottom roughening can degrade depth resolution and cause the sputter rate to change in mid-profile. Normal incidence profiling avoids surface roughening but sputter yields are reduced and ballistic mixing is increased. Even lower beam energies are then needed to recapture depth resolution and sputter rates are reduced further. In this paper we report the conditions where the most accurate profiles were achieved on as-implanted and annealed ultra-shallow BF2 implants. 

2:00 PM S2.3 
FABRICATION OF ULTRASHALLOW JUNCTIONS WITH CONVENTIONAL FURNACE EQUIPTMENT BY USING SILICON PRE-IMPLANTS. Helmut Puchner , Sheldon Aronowitz, Vladimir Zubkov, LSI Logic Corp, Santa Clara, CA. 

Despite the global trend in using ultra-low implant energies for shallow junction creation we present experimental and simulation data for the creation of HDD (Highly Doped Drain) junctions by using moderately low implant energies. Generally, RTP systems are employed during thermal treatments to anneal out the implantation damage and to minimize TED (transient enhanced diffusion) effects which causes broadening of the junctions. Our approach employs the dopant/point-defect interaction mechanism to retard dopant diffusion as well as dopant activation in the tail of the diffusion profiles to achieve suitable shallow junctions. Before the dopant is implanted, silicon is pre-implanted at a sub-amorphizing dose to create a reservoir of excess interstitials in the silicon substrate bulk. During the annealing process these bulk interstitial clusters release a point-defect flow towards the surface and the bulk and therefore reduce the mobility of the dopant-pairs at the surface. The interstitial flow, which is continuous until the excess bulk interstitial reservoirs are completely removed, deactivates the dopants in the tail region. Continuum modeling of such complicated phenomena includes dopant/point-defect interaction mechanisms like kick-out, frank-turnbull recombination, point-defect recombination as well as interstitial clustering. Quantum chemical modeling also was used to examine the energetics on an atomic level of an interstitial dopant competing with an interstitial for a substitutional site. The silicon pre-implant allows fabrication of 90nm arsenic, 150nm phosphorus, and 140nm boron metallurgical junctions for a 40keV arsenic, 20keV phosphorus, and 8keV boron implant. 

2:15 PM S2.4 
COMPARISON OF ULTRA-LOW-ENERGY ION IMPLANTATION OF BORON AND BF2. Jihwan Park and Hyunsang Hwang , KJIST, Kwangji, KOREA.

The scaling of MOSFET device channel length for high-speed application requires the scaling of the junction depth to suppress the short channel effect. It is known that ultra-low-energy ion implantation process is promising because of its compatibility with current semiconductor fabrication technology. In this paper, we have compared an ultra-shallow junction formed by a boron implantation at 0.5 keV and a BF2 implantation at 2.2 keV. The as-implanted SIMS junction depths for both boron and BF2 were approximately 25nm. After rapid thermal annealing at 1000C for 10sec, the junction depth of BF2 and boron was 40nm and 55nm, respectively. The shallow BF2 junction after rapid thermal annealing can be explained by a fluorine incorporation that can reduce the transient-enhanced diffusion. The modeling of the boron profile was performed using the Monte Carlo method for an as-implanted profile and the computationally efficient method for transient-enhanced diffusion.