Orlando Auciello Argonne National Laboratory
Jan Van Houdt IMEC
Rick Carter LSI Logic
Seungbum Hong Samsung Advanced Institute of Technology
G1: Flash Memories
Tuesday PM, April 18, 2006
Room 3010 (Moscone West)
9:30 AM - **G1.1
TwinFlash Charge Trapping Devices and Major Challenges.
Georg Tempel 1 , Thomas Mikolajick 2 , Stephan Riedel 2 Show Abstract
1 IFD TC RM, Infineon, Dresden Germany, 2 IFD TC FL, Infineon, Dresden Germany
Nitride based, localized charge trapping storage flash memory devices with a SONOS stack get increasingly interest due to some advantages like e.g. the ability to store multi bits in one single cell. In the past planar cells with low process complexities and buried bit-lines have been realized. Later on a transistor like structure allowed further shrinkage and performance optimizations. In this cell design the junctions could be well optimized including all state-of-the-art junction formation techniques. To get a further down-scaling of the cell size a new cell concept was mandatory which additionally combines the advantages of both former realizations. In this case the flexible drain-engineering and the robust planar concept have been merged in one process. Electrical results of these 60nm devices will be presented. Further cell shrinkages have been achieved with 3-dimensional FINFET like TwinFlash cells and 20nm working devices have been demonstrated. The general challenge for the 2-bit operation is given by the interaction of both bits, the so called 2nd –bit effect. A threshold voltage shift of bit “1” will also shift the threshold voltage of bit “2” at the identical physical cell. To minimize this effect a charge trapping distributions as sharp as possible is mandatory inside the nitride layer. Therefore a large nitride trap density is obligatory to suppress the lateral spread-out of injected charges and to get distinct threshold voltage shifts. Various simulations and simple experiments confirmed this requirement. In future the engineering of the charge trapping material trap density will be definitely required. In addition deep trap energies are essential for good data-retention.
10:00 AM - G1.2
NROM with Alumina as the Top Oxide in the Memory Stack.
E. Alon 1 , E. Aloni 1 , T. Claasen 5 , R. Edrei 4 , A. Gladkikh 3 , A. Fenigstein 1 , A. Heiman 1 , A. Hoffman 4 , M. Kovler 1 , I. Levin 2 , M. Lisiansky 1 , M. Oksman 3 , Y. Roizin 1 , R. Shima-Edelstein 1 , Y. Shneider 4 Show Abstract
1 , Tower Semiconductor Ltd, Migdal HaEmek Israel, 5 , ASM Europe , Leuven Belgium, 4 , Technion - IIT, Haifa Israel, 3 Wolfson Applied Material Research Center, Tel Aviv University, Tel Aviv Israel, 2 , NIST, Gaithersburg, Maryland, United States
NROM memories have 40-70 Å bottom oxide(BOX) and thus excellent retention parameters. In the last years, NROM attracted much attention due to 2-bit/cell storage and simple technology. Scaling down of ONO stack thickness in advanced NROM technologies is limited. BOX and Nitride that maintain high NROM trapping efficiency and reliability are ~40A. Thus, the only viable solution for ONO thickness decrease involves replacement of the top SiO2 with a high-k material. The high-k top layer also provides: (i) an effective blocking of electron injection from the gate electrode; (ii) improvement of program/erase efficiency including a possibility of Fowler-Nordheim (F-N) erase from the substrate like in standard SONOS devices. Alumina (Al2O3), having k=8-10, is promising for replacing of top SiO2 in ONO. In this paper we report the systematic structural and electrical study of Oxide-Nitride-Alumina (ONA) stacks with emphasis on a) controlled nitride surface preparation prior to Al2O3 deposition; b) post deposition annealing of Al2O3; c) influence of the metal gate electrode on the electrical characteristics of the ONA memory device.The ONA stacks used in this study had a 68 Å BOX and 55 Å nitride layers. Alumina layer was grown on the top of Si3N4 layer by an atomic layer deposition. In some of the specimens Si3N4 was oxidized to a thickness of ~10 Å before the Al2O3 growth. Prior to device fabrication, the samples were annealed at 800-900oC in three different gas environments. Structural/chemical characterization of the alumina layer was performed using HRTEM, EELS, XPS and TOF SIMS techniques. In particular, EELS spectra spatially re-solved across the ONA stack layers were recorded. Electrical measurements were performed with Si-ONA-Metal (SONAM) capacitors having different metal gates and ONA memory transistors (0.18um NROM technology). ONA trapping performance and endurance/retention were analyzed. The results of electrical measurements suggest that the following material aspects of ONA preparation are critical for the device performance: (i) controlled oxidation of silicon nitride prior to Al2O3 growth that ensures ~ 25 Å thickness of the oxynitride layer between silicon nitride and alumina in the final device; (ii) high temperature anneal of alumina in oxygen containing gas; (iii) a proper choice of the metal gate material. A perfect blocking of the parasitic gate electron injection was achieved in the optimized devices. Record values of the memory windows and excellent endurance/ retention (at the level and exceeding the values for standard ONO) were demonstrated in structures with thick BOX programmed and erased by the F-N tunneling. Electrical parameters were correlated with the results of chemical/ structural analysis and peculiarities of device geometry after alumina integration.
10:15 AM - G1.3
Charge Trapping Characteristics of Two-layered Al2O3/SiO2 Stack for Non-volatile Memory Device.
Takashi Nakagawa 1 , Yukishige Saitoh 1 , Ayuka Morioka 1 , Hiroshi Sunamura 1 , Nobuyuki Ikarashi 1 , Makiko Oshida 1 , Shinji Fujieda 1 , Toru Tatsumi 1 , Hirohito Watanabe 1 Show Abstract
1 system devices laboratories, NEC corporation, kanagawa Japan
Using aluminum oxide (Al2O3) has been attempted to improve data retention characteristics of trap memories and to reduce equivalent oxide thickness (EOT) of cell transistors. We investigated the mechanism of trap generation in Al2O3/SiO2 system to achieve a fabrication of highly reliable and scalable memory device. We first examined the charge trapping characteristics of poly-Si/Al2O3/SiO2 stack. The Al2O3 films were deposited on thermally grown SiO2 by atomic layer chemical vapor deposition, followed by post-deposition anneal (PDA) under various conditions. Flatband voltage shift (ΔVfb) caused by charge trapping proved to increase in proportion to Al2O3 thickness. This indicates that carrier traps are located at the interface between Al2O3 and SiO2, not in the Al2O3 bulk. Importantly, the ΔVfb depended on the PDA temperature and ambient, and Vfb did not shift without PDA. Secondary ion mass spectroscopy showed that Al diffused into SiO2 upon PDA, which seems to generate the traps. We investigated the charge trapping characteristics of poly-Si/Al2O3/AlSiOx/SiO2 stack, where we used AlSiOx as a charge trapping layer. This material was confirmed to work as charge trapping layer even without PDA, showing trapping behavior like poly-Si/Al2O3/SiO2 stack. This supports that traps are formed at the Al2O3/SiO2 interface, not within the Al2O3 bulk. Two-layered Al2O3/SiO2 stack is thus capable of storing charges, and this structure is furthermore advantageous in reducing EOT of cell transistors. We then prepared Al2O3/SiO2 stack transistor to assess the feasibility of this two-layered structure. A 15 nm-thick Al2O3 film was deposited on a 5 nm-thick SiO2, followed by PDA. The EOT of the gate stack was 11 nm. Threshold voltage shift (ΔVth) as large as 2 V was obtained by channel hot-electron injection. Complete erasing was also possible by injecting band-to-band tunneling induced hot-hole. By extrapolating the retention data taken at 150oC, ΔVth window after 10 years was estimated to be 1.0 V. However, programming/erasing time turned out to be slower than conventional poly-Si/SiO2/Si3N4/SiO2/Si (SONOS)-type trap memory. Besides, dispersion of ΔVth increased at shorter channel length. It is considered that these problems were caused by influence of plasma damage during etch process and crystallization of Al2O3 upon PDA. Suppressing the crystallization of Al2O3, for example, by optimizing the PDA conditions, would improve the memory characteristics. In conclusion, we found that traps were formed at the Al2O3/SiO2 interface, not within the Al2O3 bulk. Two-layered Al2O3/SiO2 stack was demonstrated to provide non-volatile memory function with an EOT as small as 11nm. Crystallization and plasma damage sensitivity are found to be issues for improving the memory characteristics of Al2O3.
10:30 AM - G1.4
Towards a Viable high-k Interpoly Dielectric for Aggressively Scaled Floating-gate Flash Memory.
Bogdan Govoreanu 1 , David Brunco 2 , Luc Haspeslagh 1 , Joeri De Vos 1 , Daniel Ruiz Aguado 1 , Pieter Blomme 1 , Giuseppina Puzzilli 3 , Koen van der Zanden 4 , Fernanda Irrera 3 , Jan Van Houdt 1 Show Abstract
1 , IMEC, Leuven Belgium, 2 , Intel Corp. c/o IMEC, Leuven Belgium, 3 , University of Rome "La Sapienza", Rome Italy, 4 , Infineon Technologies c/o IMEC, Leuven Belgium
10:45 AM - G1.5
Composition-Property Relationships for New Amorphous Ultra-thin TixAl1-xOy Alloy Oxide Layers for Next Generation of CMOS and Flash Memory Gate Dielectrics
Lijuan Zhong 1 , IL-Seok Kim 1 , M. Nieto 2 , B. Kabius 1 , J. Allain 2 , A. Hassanein 2 , O. Auciello 1 Show Abstract
1 Materials Science Division, Argonne National Lab, Argonne, Illinois, United States, 2 Energy Technology Division, Argonne National Lab, Argonne, Illinois, United States
11:30 AM - **G1.6
Technology Evolution of Semiconductor Devices for Nano Generation.
Kinam Kim 1 Show Abstract
1 Advanced Technology Development Team, Memory Division, Samsung Electronics, Kyunggi-Do Korea (the Republic of)
12:15 PM - G1.8
Studies of Charge Retention in Silicon Nanocrystal Layer for Memory Device Applications: Electrons or Holes?.
Tao Feng 1 , Gerald Miller 1 , Harry Atwater 1 Show Abstract
1 , California Institute of Technology, Pasadena, California, United States
Electrons are commonly selected as stored charges in conventional continuous floating gate memories. By replacing the continuous floating gate with discrete silicon nanocrystals, very thin tunnel oxide can be applied thus making injection and storage of holes also an interesting possibility. We present the nanoscale charge retention characteristics of both electrons and holes in SiO2 layers containing 2~3 nm silicon nanocrystals with very high areal density (4 × 1012 ~ 3 × 1013 cm-2) synthesized under similar ion implantation and thermal annealing conditions as that used for our nanocrystal memory device fabrication. Ultrahigh vacuum (UHV) conductive-tip noncontact atomic force microscopy (nc-AFM) was applied to inject charges into the nanocrystal layer and monitor subsequent charge retention. The results revealed a much longer hole retention time (e.g., > 1 day) than that for electrons (e.g., < 1 hour), which is consistent with our previous charge retention characteristics from electrical characterization of nanocrystal floating gate MOS capacitors [Appl. Phys. Lett. 86, 033103 (2005)] as well as time-resolved photoluminescence measurements. The large difference in charge retention times for electrons and holes is attributed to the difference in tunneling barrier heights: 3.1 eV and 4.7 eV for electrons and holes, respectively. UHV nc-AFM guarantees high detection sensitivity and stability in charge imaging experiments due to a lack of air damping, so a 3D electrostatic model can be developed to provide quantitative information regarding the distribution and evolution of the localized charges. Based on the charge injection and retention characteristics obtained from UHV nc-AFM and nanocrystal floating gate MOS devices, we suggest that hole programming in Si nanocrystal memories is an interesting choice in further device scaling.
12:30 PM - G1.9
Si-nanodot-based Multi-bit Memories Using Hybrid Structures Composed of Electron- and Hole- trap Layers.
Sangjin Park 1 , Young-Kwan Cha 1 , Daigil Cha 1 , Youngsoo Park 1 , In-Kyeong Yoo 1 , Jung-Hyun Lee 2 , Suk-Ho Choi 3 Show Abstract
1 Nano Devices Lab, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of), 2 Nano Fabrication Center, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of), 3 Department of Physics and Applied Physics, Kyung Hee University, Yongin Korea (the Republic of)
Memory capacitors with a structure of SiO2/Si nanodots/SiO2/HfO2 have been prepared by sequential processes: atomic layer deposition (ALD) of amorphous Si on SiO2, thermal oxidation at 900 oC, and another ALD of HfO2. The memory devices offer hybrid type of charge memory: the interface states of Si nanodot/SiO2 tend to act as hole traps resulting in a negative shift of flat band voltage in capacitance-voltage (C-V) curve, and the SiO2/HfO2 interface has dominantly electron trap centers leading to a positive voltage shift. By this hybrid effect, the memory window in C-V curve was observed to be enlarged enough to realize 4-level multi-bit memories. The charge-loss rates measured for each memory level were compared with those of conventional memory structures without HfO2. The improved memory properties in the hybrid structures are discussed with reference to possible charging/discharging mechanisms
12:45 PM - G1.10
Fabrication of Dense Ordered Arrays of Metal Dots for Flash Memory Application
Davood Shahrjerdi 1 , Joy Sarkar 1 , Sanjay Banerjee 1 Show Abstract
1 ECE, Univ of Texas at Austin, Austin, Texas, United States
Future generation of microelectronics demands ever-decreasing physical dimension of electronic components in order to improve the overall performance of integrated circuits. The advent of new photolithography techniques have made it possible to continue the scaling trend at the expense of increasing cost and complexity of lithography tools. In contrast, self-assembly provides a low-cost and simple pathway to define nanostructures with dimensions below photolithography resolution limits. Utilizing copolymers however have been recently demonstrated as an elegant approach to creating ultra dense periodic surface structures. Diblock copolymers consist of two distinct polymer chains with high interaction energy, which cause those two blocks to microphase separate under a certain condition in order to minimize the free energy of the system, thereby forming ordered morphologies with nanometer-scale dimensions. In this work we report a large area fabrication of an ordered array of metal quantum dots with area density of ~10^12/cm2, by using a trilayer pattern-transfer method. The trilayer structure consists of a PS-b-PMMA copolymer top layer, a SiO2 middle layer and a polyimide bottom layer on HfO2-capped Si substrates. Si substrates were cleaned with a 10min piranha etch, 30s HF dip and DI water rinse/spin dry. Reactive Hf sputtering was performed in a DC magnetron sputtering system, followed by a post deposition furnace anneal at 550C. A 50nm thick polyimide bottom layer was spin coated onto the substrate which had been precoated with a very thin layer of adhesion promoter and annealed for 2hrs at 350C in nitrogen ambient to remove the solvent thoroughly. Next, a 200nm thick PECVD SiO2 was deposited at 280C. Prior to the copolymer deposition, a relatively thick layer of random copolymer, P(S-r-MMA), was spin-coated onto the SiO2 layer. Samples then were annealed at 180C under vacuum for 48 hrs to end-anchor polymer chains to the surface. Unanchored random copolymer was washed away by rinsing with toluene, leaving a ~6 nm film. Next, a 1 wt.-% PS-b-PMMA (70:30, PS/PMMA) solution of the copolymer in toluene was spin-cast to produce a film with thickness of ~34 nm. Subsequently, samples were annealed under vacuum at 180C for 3hrs to promote self-assembly into nanometer-scale domains. A 2-minute UV exposure that tends to degrade the integrity of PMMA block, followed by PMMA removal in glacial acetic acid completed the process, leaving behind a PS nano-template of 20nm in diameter pores with the center-to-center spacing of 40nm. Afterwards, CHF3 RIE was used to transfer the pattern into the oxide. An O2 RIE was further performed to continue the pattern-transfer process through the polyimide layer. Finally, Ni dots were produced by e-beam evaporation followed by a lift-off process. AFM and SEM images confirm the feasibility of this method to achieve ordered arrays of metal dots. Currently, the fabrication of NC flash memories with this approach is under way.
G2: Advanced Nanocrystal-Based Gate-Flash Memories
Tuesday PM, April 18, 2006
Room 3010 (Moscone West)
2:30 PM - **G2.1
Silicon Nanocrystal Memory – Physics and Technology.
Ko-Min Chang 1 Show Abstract
1 Technology Solutions Organization, Freescale Semiconductor, Inc., Austin, Texas, United States
3:00 PM - G2.2
Germanium Implantation of Silicon Oxide for Nanocrystal Non-Volatile Memories
Jeong Han 1 , Chanjin Park 1 , Chungwoo Kim 1 , U.-I. Chung 1 , J. T. Moon 1 , B.I. Ryu 1 Show Abstract
1 Process Development Team, Samsung Electronics Co., Ltd., Yongin, Gyeonggi, Korea (the Republic of)
Nanocrystal (nc) memories have garnered much attention as an alternative for next-generation Flash memory. The threshold voltage shift due to charge storage in an nc memory device is directly proportional to the density of nc's. As the gate length of devices continue to scale, it is critical that nc's be formed as small as possible so as to increase density and maximize memory window. A fully compatible process to create nc's with diameters less than 5nm within a SiO2 film was studied. Ge was used, rather than Si, since implantation of a heavier mass ion is more controllable. Also, the energy bandgap for Ge is smaller that for Si. This allows for larger barrier heights between the nc and surrounding oxide, resulting in improved retention.A 30-50 nm thick SiO2 layer was grown on n-type Si substrates in a conventional furnace. The SiO2 layer was then implanted with Ge ions at 15keV at doses of 5×1015-1×1016cm-2 at room temperature. The samples were subsequently annealed at 800-1050°C for 10 min in Ar to enhance the nucleation and growth of Ge nc's and to cure the damage from the implant process.From cross-sectional TEM images, a dark band of Ge nc's formed within the oxide. The Ge nc's are located approximately 5 nm from the SiO2/Si interface, providing a sufficient tunnel oxide. The nc’s are approximately 3-4 nm in diameter. The nc's density is approximately 5×1012cm-2 from plain-view TEM. SIMS results confirmed the distribution of Ge nc's in the oxide, with a peak coinciding at the location seen from TEM pictures. SRPES spectra of selected Si 2p and Ge 3d core levels were studied. A mixture of SiO2 and GeOx exists in the near-surface region of the Ge implanted oxide. With increasing anneal temperature, the GeOx phase decreases and the SiO2 phase increases. This is evidence of improved nc nucleation with higher temperatures.With a large dose amount and thinner oxides, hysteresis of over 21 V was achieved when swept from -20 to 20 V. Hysteresis loops for both dosages widened with lower annealing temperature, but the difference was insignificant. More importantly, hysteresis curves for higher anneal temperatures had a larger slope, which may indirectly convey the quality of the SiO2/Si interface. Program and erase performance via F-N tunneling are reasonable. The erase operation is more efficient since the structures are on n-type Si. The difference between the programmed state and write state was extrapolated to be 0.6 V after ten years.Using DLTS and ODLTS, it was found that the electron traps of an un-implanted sample rapidly shift to lower energies, but saturates at approximately 200 K, depending on the gate bias. From ODLTS spectra with excitation energy of 1.3 eV (wavelength of 950nm), the oxide structures containing nano-crystals had two dominant peaks in the temperature range of 100 to 250 K. From an Arrhenius plot, their respective activation energies are 0.13 and 0.32 eV above the valence band.
3:15 PM - G2.3
Approaches to the Self-assembling of Nanostructures for Charge Storage in Discrete Trap Memories.
Rosaria Puglisi 1 , Piero La Fata 1 , Salvatore Lombardo 1 Show Abstract
1 Istituto per la Microelettronica e Microsistemi, Consiglio Nazionale delle Ricerche, Catania Italy
3:30 PM - G2.4
Temperature Dependence of Hole Retention in Silicon Nanocrystals Embedded in SiO2
Gerald Miller 1 , Tao Feng 1 , Harry Atwater 1 Show Abstract
1 Applied Physics, California Institute of Technology, Pasadena, California, United States
Nanocrystal floating gate nonvolatile memories have now been extensively investigated, but most previous reports have focused on electron programming and retention. In this work we report a strong asymmetry in retention times of electrons and holes, and find hole retention times greatly exceeding electron retention times. We have also explored temperature-dependent charge retention of electrons and holes in programmed Si nanocrystal floating gate layers performed with electrostatic force microscopy in an ultrahigh vacuum environment. The nanocrystals were fabricated using Si ion implantation and annealing in an SiO2 matrix, and were estimated to be 2-3nm in size with an areal density of ~ 4 × 1012 cm-2. Using a conducting tip non-contact AFM system under UHV, holes were injected at a +10V bias into 150 nm x 150 nm regions of the Si nanocrystal/SiO2 samples and charge retention was monitored from 300K-500K. We observed a strongly temperature dependent hole retention time, with room temperature hole retention > 4 x 104 sec. At 400K hole retention times of ~ 1 x 104 sec were observed, while at 500K a hole retention time of 1.2 x 103 sec was measured. A quantitative electrostatic force microscopy model enables the relation of the local charge density to be related to the local electrostatic force on the scanning probe tip. Following programming, the measured charge dissipates in time, and measurements of the dynamics of this dissipation allow leakage current pathways to be characterized. Temperature dependent retention of electrons in Si nanocrystals/SiO2 will also be reported, as will models for charge transport mechanisms that limit electron and hole retention time.
3:45 PM - G2.5
Influence of the Ge Dose in Ion-implanted SiO2 Layers on the Related Nanocrystal-memory Properties.
Sebastien Duguay 1 , Abdelillah Slaoui 1 , Jean-Jacques Grob 1 , Philippe Kern 1 Show Abstract
1 , InESS, STRASBOURG France
4:30 PM - G2.6
Ge Nanocrystals Grown by Pulsed Low-energy Ion-beam Assisted Deposition on SiO2 Films.
Anatoly Dvurechenskii 1 , P. Novikov 1 , Y. Khang 2 , Zh. Smagina 1 , V. Armbrister 1 , Rainer Groetzschel 3 , A. Gutakovskii 1 , V. Kesler 1 Show Abstract
1 Siberian Branch of Russian Academy of Science, Institute of Semiconductor Physics, Novosibirsk Russian Federation, 2 , Material Center, Samsung Advanced Institute of Technology, Yongin-Si Korea (the Republic of), 3 , Institute of Ion Beam Physics and Materials Research, Research Center Rossendorf, Dresden Germany
4:45 PM - G2.7
Core-shell Ge Nanoparticles on Oxide Surfaces for Enhanced Interface Stability.
Scott Stanley 1 , Yueran Liu 2 , Sanjay Banerjee 2 , John Ekerdt 1 Show Abstract
1 Chemical Engineering, University of Texas Austin, Austin, Texas, United States, 2 Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, United States
Germanium films and nanoparticles are increasingly used in microelectronics due to the higher carrier mobility of Ge over Si and enhanced carrier confinement in Ge nanocrystals compared to Si nanocrystals. Non-volatile flash memory, for example, is moving towards a nanocrystals-based architecture with Si or Ge nanoparticles on a HfO2 tunnel dielectric layer in place of a continuous Si floating gate. However, a primary problem with Ge integration is the rapid formation of low-quality, unstable germanium oxides at the Ge surface. We have previously studied the self assembly of Ge nanoparticles on HfO2 surfaces in chemical vapor deposition (CVD) and find that Ge nanoparticles are very prone to oxidation, even with a short exposure to ambient or other oxidizing environment. A method is needed to stabilize the Ge nanoparticle surface that (1) will prevent oxidation (2) be thermally stable for subsequent processing (3) is compatible with Ge and the gate dielectric, and (4) will create an electrically favorable interface, i.e. low fixed charge, low defect density, and low trap density.In this paper, we present the synthesis and oxidation resistant properties of core-shell nanocrystals prepared by CVD. Core-shell nanoparticles are prepared with a Ge core and a Si, C, N, H, or native GeOx shell. Core-shell nanoparticles are characterized with in-situ X-ray photoelectron spectroscopy (XPS) and low energy ion scattering (LEIS) as deposited and after oxidation treatments. Scanning electron microscopy (SEM), atomic force microscopy (AFM), and transmission electron microscopy (TEM) are used to image nanoparticles. The core-shell nanoparticles are then encapsulated in a gate oxide, gate metal is deposited, and metal-oxide-semiconductor (MOS) capacitors are patterned. The interface electrical quality and charge storage characteristics are determined through high-frequency capacitance-voltage (CV) measurements. The shell layers are seen to passivate the Ge core towards oxidation to differing degrees. Beyond applications in flash memory, these core-shell nanoparticles are being studied for their optical properties and for use in multiple or nested quantum well devices.
5:00 PM - G2.8
Formation and Memory Effect of Ru Nanocrystals with High Spatial Density and Small Size Distribution by Controlling Nucleation and Growth Stage of Plasma Enhanced Atomic Layer Deposition.
Sung-Soo Yim 1 , Moon-Sang Lee 1 , Ki-Su Kim 1 , Ki-Bum Kim 1 Show Abstract
1 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Formation of mono-dispersed nanocrystals with high spatial density on dielectric substrates is one of the key processes to achieve a flash type single electron memory device. Although various deposition methods such as sputtering and chemical vapor deposition (CVD) have been used to fabricate nanocrystals on substrate by controlling the initial stage of film formation, these conventional processes have been suffered from uncontrollability of density, size of nanocrystals, and their distribution because the accurate control of nucleation stage is very difficult. In this respect, atomic layer deposition (ALD) process can be a facile route to the formation of discrete nanocrystals due to excellent controllability of digital film growth. Here, we demonstrate that plasma enhanced ALD (PEALD) process of Ru can be used to achieve uniform sizee distribution of nanocrystals on dielectrics. Ru nanocrystals are formed on thermally grown SiO2 substrate at 300oC using (EtCp)2Ru (diethylcyclopentadienyl ruthenium) precursor and NH3 plasma as a reactant. Average growth per cycle and film resistivity of ALD-Ru film is 0.025 nm/cycle and 40 μΩ-cm, respectively. Apparently, nominal thickness of ALD-Ru as a function of ALD cycles has a linearity as measured by atomic force microscopy (AFM). However, TEM analysis reveals that films do not form continuous layer even at 500 ALD cycles, which indicates large process window for island growth mode for this process. Below 200 ALD cycles, discrete and circular nuclei are observed in plan-view TEM, and coalescence of clusters proceeds after 200 ALD cycles. Close examination of plan-view and cross-sectional high resolution TEM reveals that nuclei do not have hemispherical shape, which is the most probable morphology of clusters after undergoing heterogeneous nucleation, but spherical shape. Maximum nuclei density of 9 x 1011 /cm2 is achieved at 200 ALD cycles with nucleation rate of 4.5 x 109 /cycle and the average size of 3.5 nm. After 200 ALD cycles, nucleation density decreases due to coalescence process. Surprisingly, it is found that nuclei have size deviation of less than 20 % at all samples below 200 ALD cycles. The spherical shape of nuclei, small size distribution and relatively large work function make Ru nanocrystals fascinating material for element of single electron device. We will show memory effects of Ru nanocrystals by measuring threshold voltage shift of Al/oxide with Ru nanocrystals/Si (MOS) capacitors caused by charging of electrons in Ru nanocrystals by C-V measurement after pulsing of programming voltage.
5:15 PM - G2.9
Charge Trapping Memory Cell with TANOS (Oxide-SiN-Al2O3-TaN) Structure erased by Fowler-Nordheim tunneling of Hole
Chang-Hyun Lee 1 , Jang-Sik Lee 1 , Juhyung Kim 1 , Jaesung Sim 1 , Sanghun Jeon 1 , Yoocheol Shin 1 , Ki-Tae Park 1 , Jongsun Sel 1 , Younseok Jeong 1 , Byeongin Choi 1 , Viena Kim 1 , Wonseok Jung 1 , Chung-II Hyun 1 , Changseok Kang 1 , Jungdal Choi 1 , Kinam Kim 1 Show Abstract
1 Semiconducor R&D Center, Samsung Electronics, Yongin-City,, Kyungki-Do, Korea (the Republic of)
The thin tunnel oxide is indispensable for erase operation of the conventional SONOS cells using band-to-band direct tunneling of holes due to the backward tunneling. The use of thin tunnel oxide is a road-block for the SONOS device to come into high-density NAND flash memory in terms of data retention. To overcome the fundamental problem, we reported previously the TANOS (SiO2-SiN-Al2O3-TaN) device structure with high-k dielectrics as a blocking layer and higher work function metal gate. In this work, we present the evolved TANOS device which can be erased by Fowler-Nordheim (FN) tunneling of hole even at 40Å-thick tunnel oxide. The fabricated 32-string NAND string has TANOS cell structure with W/WN/TaN/100Å-thick Al2O3/60Å-thick SiN/40Å-thick SiO2. The NAND string was integrated using 63 nm NAND process technology. The NAND cell shows program threshold voltage of 3.84V with program voltage of 17V and time of 100μsec and erase threshold voltage of -1.36V with erase voltage of -19V and time of 10ms. The band-to-band direct tunneling is surpressed completely and electron and hole are transported by Fowler-Nordheim tunneling at the tunnel oxide of 40Å. The effective blocking of the backward tunneling enables erase threshold one to be negative even at the tunnel oxide thickness of 40Å. Through the charge loss measurement, the electron trap energy density of the cell is calculated. The extracted electron trap is revealed to consist of deep trap of 1.30 eV and shallow trap of 0.97 eV. The electrons trapped at the shallow trap. We treat the endurance characteristics with respect to the tunnel oxide thickness. The interface state and oxide trap generation will be shown after cycling stress with respect to the band-to-band direct tunneling, Fowler-Nordheim tunneling, and the coexistence of two tunneling mechanism.
5:30 PM - G2.10
CMOS Compatible Bottom-up Approach of Multi-Dot Floating-Gate Nonvolatile Memory Fabrication.
Karl-Heinz Heinig 1 , Bernd Schmidt 1 , Torsten Mueller 3 1 , Lars Roentzsch 1 , Karl-Heinz Stegemann 2 Show Abstract
1 Inst. of ion beam physics and materials research, Research Center Rossendorf, DRESDEN Germany, 3 Flash Technology Predevelopment, Infineon Technologies Dresden, DRESDEN Germany, 2 , ZMD Analog Mixed Signal Service Company, DRESDEN Germany
Scalability and performance of current FLASH memories could be improved substantially by novel devices based on multi-dot floating gate MOSFETS. Until today, ten years of research effort have been devoted to Tiwari`s idea  to replace the poly-silicon floating-gate of FLASH memories by a layer of Si nanocrystals. Although several groups and companies developed test-devices, a breakthrough was not achieved due to two main reasons: (i) The CMOS compatible fabrication of the layer of nanocrystals remains a great challenge (monolayer of monodisperse Si nanocrystals of high density, which has to be embedded in the gate oxide at a controlled tunnel distance of a few nm above the Si channel). (ii) The retention of the test-devices did not reach the industrial standard.Here, we present a CMOS compatible bottom-up approach of a multi-dot floating-gate non-volatile memory fabrication which is based on ion-beam mixing of Si-SiO_2 interfaces . By energetic Si ion irradiation through the poly-Si gate and the gate oxide into the Si substrate, a SiO_x layer forms in the interface region. During post-irradiation annealing, the flat Si/SiO_2 interface rebuilts rapidly by spinodal decomposition and interface area minimization. However, in the tail of the mixing profile, Si excess nucleates in the gate oxide layer forming Si nanocrystals. These nanocrystals are separated from the substrate by a few nm thin SiO_2 layer which is free of Si excess. Experimental and atomistic computer simulation studies of this bottom-up approach will be presented. Electrical characteristics of devices, which were fabricated in an industrial environment, will be shown. Predictions to overcome the main drawback in view of applicability as memory devices, i.e. the data retention of only a few months at room temperature, will be discussed.[ 1] S. Tiwari et al., IEEE Int. Electron Devices Meeting Technical Digest, 521–524 (1995)[ 2] K.-H. Heinig, T. Müller, B.Schmidt, M. Strobel, W. Möller, Appl. Phys. A 77, 17–25 (2003).
5:45 PM - G2.11
In-situ Characterization of Surfaces and Interfaces at the Nanoscale for Application to Nonvolatile Memory Systems.
Jean Allain 1 , Lijuan Zhong 2 , Martin Nieto 1 , Vladimir Titov 1 , Ahmed Hassanein 1 , Orlando Auciello 2 Show Abstract
1 Energy Technology Division, Argonne National Laboratory, Argonne, Illinois, United States, 2 Materials Science Division, Argonne National Laboratory, Argonne, Illinois, United States
Advanced techniques for synthesis and characterization of thin films and interfaces are critical to study film growth and interface processes at the atomic scale, necessary for the development of the next generation of nonvolatile memories. Surfaces and interfaces of thin films used in the fabrication of advanced nonvolatile memories require the use of sophisticated characterization systems able to adequately diagnose chemical, kinetic and thermodynamic behavior of the thin films and the materials integration strategies required for the development of the next generation devices. The IMPACT (Interaction of Materials with Particles and Components Testing) experimental facility recently developed at Argonne is designed to perform in-situ atomic scale characterization of the time evolution of elemental, chemical, and thermodynamic states of ultra-thin film surface and interfaces using complementary surface-sensitive techniques. The in-situ techniques used include: low-energy ion scattering spectroscopy (LEISS), direct recoil spectroscopy (to study impurity levels in the film), X-ray photoelectron spectroscopy, Auger analysis and extreme ultraviolet photoelectron spectroscopy (EUPS). EUPS combined with LEISS can give chemical state and elemental information at the first 2-3 monolayers, respectively. Both ion and electron spectroscopies are conducted using a highly sensitive hemispherical sector energy multi-channel analyzer. High-resolution depth profiles are obtained by using a unique low-energy ion source delivering 100 eV Xe ions at current densities of 2.5 uA/cm^2. Simultaneously the total erosion flux is measured in-situ using an ultra-sensitive temperature-compensating quartz crystal nanobalance – dual crystal unit (QCN-DCU) with resolution better than 0.005 A/sec. In addition to total erosion measurements, partial sputtering from multi-component surfaces and interfaces is measured using an advanced post-ionization secondary mass neutral spectrometer using 193-nm and 355-nm colors with a pulsed Alexandrite laser system tunable to +/- 40-nm with a spectral bandwidth better than 0.5-nm. Pulses range from 1-50 mJ/pulse at 10 Hz and varied pulse widths between 10-100 nsec/pulse. Results to be discussed include the application of IMPACT to the study of film growth and interfaces critical to nonvolatile memory systems. We will discuss specifically the surface elemental characterization, high-resolution depth profiling and characterization of ultra-thin interfaces both elemental and chemical states for new amorphous Ti-Al-O and HfO2 high-K dielectric layers relevant to the new generation of CMOS and flash memory gates.
Orlando Auciello Argonne National Laboratory
Jan Van Houdt IMEC
Rick Carter LSI Logic
Seungbum Hong Samsung Advanced Institute of Technology
G3: Ferroelectric Random Access Memories (FeRAMs)
Wednesday AM, April 19, 2006
Room 3010 (Moscone West)
9:30 AM - **G3.1
High Density Thin Film Ferroelectric Nonvolatile Memories.
Ramamoorthy Ramesh 1 Show Abstract
1 , University of California, Berkeley, Berkeley, California, United States
The field of ferroelectric nonvolatile memories has made some dramatic progress over the past 5 years. Although the field formally started in the early eighties, it was not until the late eighties and early nineties that a concerted, interdisciplinary approach was taken to solve the critical “show-stoppers” that limited their implementation as the next generation of solid state nonvolatile memories ( FRAMS). Among the key inventions, the use of conducting oxide electrodes to solve polarization fatigue and imprint in PZT based capacitors, the implementation of the SBT process, conducting barriers to create high density architectures, approaches to solve hydrogen damage, etc all have paved the way to the current status of this field. Many large companies are actively involved in designing and manufacturing low and high density IC’s that have been implemented in many applications. In this presentation, I will describe our efforts on exploring a new lead-free ferroelectric material, BiFeO3, as a possible replacement for both PZT and SBT families of ferroelectrics.
10:00 AM - G3.2
Ferroelectric Properties of Bi(4-x)Ce(x)Ti(3)O(12) Thin Films and Quantitative Structure – Spontaneous Polarization Relationship.
Min Ku Jeon 1 2 , Yong-Il Kim 3 , Soon-Gil Yoon 4 2 , Seong Ihl Woo 1 2 Show Abstract
1 Chemical and Biomolecular Engineering, Korea Advanced Institute of Science and Technology, Daejeon Korea (the Republic of), 2 Center for Ultramicrochemical Process Systems, Korea Advanced Institute of Science and Technology, Daejeon Korea (the Republic of), 3 , Korea Research Institute of Standards and Science, Daejeon Korea (the Republic of), 4 Materials Engineering, Chungnam National University, Daejeon Korea (the Republic of)
Ferroelectric Bi(4-x)Ce(x)Ti(3)O(12) (BCT, x = 0.25, 0.5 and 0.75) thin films were prepared by using pulsed laser deposition method. Remnant polarization (Pr) of the BCT thin films exhibited a significant composition dependence. The Pr decreased from 23.5 uC/cm2 to 14.2 uC/cm2 and 9.8 uC/cm2 with increase in the amount of substituted Ce from 0.25 to 0.5 and 0.75, when annealed at 650 oC. The Bi(3.75)Ce(0.25)Ti(3)O(12) thin film showed a fatigue-free behavior during 1.36x10^10 read/write cycles. To understand the composition dependence of BCT thin films, crystal structure was determined by neutron powder diffraction and Raman spectroscopy study. BCT powder of same composition to that of thin films was synthesized by a normal solid state reaction. Bismuth titanate has a crystal structure in which bismuth oxide layers, Bi(2)O(2), are interleaved with perovskite blocks, Bi(2)Ti(3)O(10), along c-axis. Therefore, there are two possible substitution sites of Ce in BCT, the Bi(2)O(2) layers and the perovskite units. In the Raman spectroscopic study, the band appeared at 65 cm-1, which is originated from the Bi atoms in the Bi(2)O(2) layers, showed little variation with increase in the amount of substituted Ce. However, the triple bands at 90, 119 and 148 cm-1, which were assigned to the Bi atoms in the perovskite units, became diffusive and shifted to higher frequencies. It can be concluded that substitution site of Ce was the perovskite units only. Based on the Raman study, crystal structural refinement was carried out by using neutron powder diffraction data, which is a useful method to determine the position of oxygen atoms. BCT of monoclinic crystal structure (space group of B1a1) will show a large spontaneous polarization along the a-axis, but zero and small polarization along the b- and c-axis, respectively. The a- and b-axis lattice parameter decreased with increasing amount of substituted Ce, while c-axis lattice parameter increased. The orthorhombicity, defined as 2(a-b)/(a+b), decreased linearly with increasing substituted Ce. Spontaneous polarization was calculated by summing atomic displacement of constituent atoms along the a-axis from the corresponding position in tetragonal structure. The calculated spontaneous polarization of BCT powder also decreased from 30.4 uC/cm2 to 27.5 uC/cm2 and 16.5 uC/cm2 as in the case of the thin films. It can be concluded that composition of BCT is closely related to orthorhombicity and Ps.
10:15 AM - G3.3
Excellent Room-Temperature Ferroelectricity in Mn-substituted BiFeO3 Thin Films Formed by Chemical Solution Deposition
Sushil Singh 1 , Hiroshi Ishiwara 1 Show Abstract
1 Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama Japan
Multiferroic materials are important for realizing multifunctional devices used in information storage, spintronics and so on. Multiferroic BiFeO3 (BFO) is a suitable candidate to attain the ferroelectric and antiferromagnetic domain coupling at room temperature (RT), due to its high Curie temperature of ~1123 K and Neel temperature of ~643 K. BFO is also advantageous for fabrication of future nonvolatile FeRAMs, because of its large remanent polarization value and its crystallization temperature lower than 823 K. One of the major problems of BFO thin films is low electrical resistivity, which affects the measurement of ferroelectric/antiferromagnetic properties at RT. Mn-substituted BFO thin films were formed by chemical solutions deposition on Pt/Ti/SiO2/Si(100) structures. Electron beam evaporation was used to deposit Pt top electrodes 3.14x10-4 cm2 or 0.79x10-4 cm2 in area through a shadow mask. Effects of the Mn-substitution on the structure and ferroelectricity of BFO films were examined. We found that the lattice structure of the film is sensitive to the Mn-substituting percentage and the secondary phase is appears in 20% Mn-substituted BFO films. The 5% Mn-substituted BFO film shows higher leakage current than undoped BFO films in a lower electric field than 0.5 MV/cm. However, the leakage current density at 1 MV/cm was much lower in the Mn-substituted sample (on the order of 10-4 A/cm2) and saturated P-E hysteresis loops with remanent polarization of 55-75 μC/cm2 were obtained at RT for applied field of 0.8 to 2.4 MV/cm.
10:30 AM - G3.4
Novel Multiferroic Thin Films of Modified BiFeO3 for Non-Volatile Memory Applications.
Vaijayanti Palkar 1 , Anisha Ramesh 2 , Shashank Purandare 1 , Smita Gohil 1 , Richard Pinto 2 , Shobo Bhattacharya 1 Show Abstract
1 Condensed Matter Physics and Materials Science, Tata Institute of Fundamental Research, Mumbai, Maharashtra, India, 2 Electrical Engineering, Indian Institute of Technology, Bombay, Mumbai, Maharashtra, India
Multiferroics are characterized by a coexistence of ferroelectric and ferromagnetic orderings. Discovery of the induction of polarization by a magnetic field and of a magnetization by an electric field created a lot of excitement in the 1960s. The cross-link between magnetic and electric properties opened new degree of freedom for device designing. However, in real life the scarcity of materials exhibiting multiferroic behavior at room temperature restricted their usage in device applications. We have been successful in realizing single phase thin films of Bi0.6Dy0.3La0.1FeO3 on platinized silicon by using pulsed laser deposition technique. Magnetic measurements (M-H) and ferroelectric loop studies carried out on these films confirm co-existence of two order parameters at room temperature. Change in electric polarization value with applied magnetic field indicates coupling between the two parameters. Magnetic Force Microscopic (MFM) study reveals evolution of different magnetic domain patterns with the thickness of the films. The results open up important research front for the material having versatile applications along with non-volatile memories.
10:45 AM - G3.5
Electrical and Magnetic Properties of NiFe2O4 and CoFe2O4 Modified Pb(Zr,Ti)O3 Nanocomposite Thin Films.
Nora Ortega 1 , Pijush Bhattacharya 1 , Ram Katiyar 1 , Prasanta Dutta 2 , Mohindar Seehra 2 Show Abstract
1 Physics, University of PUerto Rico, San Juan, Puerto Rico, United States, 2 Physics, West Virginia University , Morgantown, West Virginia, United States
Multiferroics are novel class of next generation multifunctional materials, with two or more properties, such as ferroelectricity, ferromagnetism, and ferroelasticity occur in same phase. There are few such single-phase materials that exhibit these kind of multifunctional properties. Recently, the syntheses of composite thin films consisting of ferroelectric and ferromagnetic materials have been attracted much attention to enhance magneto-electric (ME) coefficients for potential device application. In this work, we studied Pb(Zr,Ti)O3–CoFe2O4 (PZT-CFO) and Pb(Zr,Ti)O3–NiFe2O4 (PZT-NFO) composite thin films fabricated by pulsed laser deposition. These films were deposited on Pt/TiO2/SiO2/Si substrate at 400 °C and post annealed at 650°C using rapid thermal annealing (RTA). X-ray diffraction and Raman spectra of these composite films revealed that, the perovskite PZT and the spinel (CFO and NFO) grown in two separate phases. Scanning electron micrographs (SEM) showed that the ferrites (CFO, NFO) were grew as a columnar structure inside the PZT matrix in the composite films. The dielectric constant for the PZT-NFO films (~1000) was found to be higher compared to PZT-CFO (~650) films at 100 kHz. The PZT-NFO composite films showed a peak in temperature dependent dielectric constant at 620 K, which was close to the phase transition of PZT (~ 600 K) films. However, no such phase transition was observed in PZT-CFO. In contrast, the dielectric constant was nearly constant in the temperature range of 400 to 650 K. Saturated magnetic hysteresis loops were obtained at room temperature, for both CFO and the NFO modified PZT composite films. The detailed temperature dependent magnetic and electrical characterizations will be presented.
11:30 AM - **G3.6
Status of FeRAM Technology and Commercialization as of 2006.
Carlos Paz de Araujo 1 2 Show Abstract
1 , Symetrix Corporation, Colorado Springs, Colorado, United States, 2 Department of Electrical and Computer Engineering, University of Colorado at Colorado Springs, Colorado Springs, Colorado, United States
Ferroelectric Random Access Memories, branded as FeRAMs, have grown to full maturity in the last few years and are now in production in the technology nodes of 0.6, 0.5, 0.35, 0.18 and 0.16 microns. Circa April 2006, both PZT-based and SBT-based FeRAM have combined sales of over 400 million devices in the field. In the SBT camp, 0.18 and 0.13 micron are in full production and ramping at over 40 per cent per year. These statistics clearly illustrate the maturity of the technology and its placement into unique products in which low power and high write speed are necessary. Now the era of 65nm offers challenges and opportunities to FeRAM to enter the cutting edge of silicon for Systems-On-Chip (SOC). This paper reviews the state of the art technology and product survey of SBT FeRAM and presents a progress report of the 65nm research.
12:00 PM - G3.7
Scaling Potential of pin-type 3-D SBT Ferroelectric Capacitors Integrated in 0.18μm CMOS Technology.
Ludovic Goux 1 , Dirk Wouters 1 , Judit Lisoni 1 , David Maes 1 , Hans Vander Meeren 1 , Vasile Paraschiv 1 , Luc Haspeslagh 1 , Cesare Artoni 2 , Giuseppina Corallo 2 , Raffaele Zambrano 2 Show Abstract
1 SPDT, IMEC, Leuven Belgium, 2 Memory Products Group Stradale Primosole, STMicroelectronics, Catania Italy
12:15 PM - G3.8
Ferroelectric Domain Dynamics in Epitaxial LaxBi1-xFeO3 Films Grown on Different Substrates.
M.P. Cruz 1 2 , F. Zavaliche 2 , Y.H. Chu 2 , T. Zhao 2 , P. Shafer 2 , M. Scullin 2 , R. Ramesh 2 Show Abstract
1 , Centro de Ciencias de la Materia Condensada (CCMC)-UNAM, Ensenada, B.C., Mexico, 2 , University of California, Berkeley, California, United States
Epitaxial LaxBi1-xFeO3 films with x = 0 and 0.1 have been grown by pulsed laser deposition on SrRuO3-buffered SrTiO3(100) and Si(100) substrates. The ferroelectric domain structures have been imaged by piezo-force microscopy (PFM) at ambient conditions as a function of poling bias and the number of poling cycles. The polarization directions and switching processes have been identified by simultaneously imaging the out-of-plane and in-plane piezoresponse signals, and by scanning along different crystallographic directions. In the as-grown state, the films show mainly four polarization variants with the polarization vector oriented towards the bottom SrRuO3 semi-metallic layer. Upon locally poling the film by the application of an electrical bias to the conducting probe, all three polarization switching mechanisms (71ο, 109ο and 180ο) were observed, together with the displacement and creation of ferroelastic domain walls. As a general feature, the propensity towards the formation of large, rectangular-like domains was observed. This is especially relevant for the La-doped films where small domains (tens of nm) were seen in the as grown films, probably because the growth temperature was above the ferroelectric Curie temperature. As the number of poling cycles was increased, the ferroelastic domain walls become pinned, and mainly two variants have been observed. These experimental results are especially important to help us understand the fatigue mechanisms in the BiFeO3 films and improve the films ferroelectric properties via domain engineering.This work has been supported in part by ONR under a MURI program, SRC under a MARCO program, and by LBL-LDRD program.
12:30 PM - G3.9
Fabrication of Ferroelectric Thin Films on Crystalline HfO2/γ-Al2O3/Si(100) Substrates for MFIS-FET Applications.
Takayuki Okada 1 , Daisuke Masunaga 1 , Mikinori Ito 1 , Kazuaki Sawada 1 2 , Makoto Ishida 1 2 Show Abstract
1 Electrical and Electronic Engineering, Toyohashi University of Technology, Toyohashi, Aichi, Japan, 2 Intelligent Sensing System Research Center, Toyohashi University of Technology, Toyohashi, Aichi, Japan
Ferroelectric random access memory (FeRAM) applications with metal-ferroelectric-insulator-semiconductor field effect transistor (MFIS-FET) cell structure have been numerously investigated because of its non-destructive read-out capability, possibility for higher cell density, faster writing speed and lower operating voltage. In order for the realization, much effort has been made to obtain orientation-controlled ferroelectric thin films and insulation layer with higher dielectric capacitance. In this paper, we propose to employ crystalline HfO2/γ-Al2O3 stacked insulation layer for MFIS-FET cells, because its crystallinity is suitable for orientation control and high dielectric constants of both are also useful for device operation. Crystalline γ-Al2O3 films were deposited on p-Si(100) substrates by Al-O2 molecular beam epitaxy, which showed c-axis oriented γ-Al2O3(111) plane with the thickness of 4 nm. 15 nm-thick HfO2 was deposited by electron beam evaporation method using HfO2 tablets in vacuum environment. The deposition was performed at various substrate temperatures (ranging from room temperature to 800°C). In order to reveal the effect of γ-Al2O3 under layer on crystallization of HfO2 films, the HfO2 depositions were also performed on HF-treated and chemically oxidized Si(100) substrates. In addition SrBi2Ta2O9 (SBT) and (Bi,La)Ti3O12 (BLT) ferroelectric thin films preferred for FeRAM applications were deposited by conventional sol-gel spin-coating method on the crystalline and amorphous HfO2/γ-Al2O3/Si(100) substrates. The fabricated films were analyzed by XRD, RHEED and AFM. XRD 2θ-ω scan of HfO2 film deposited on γ-Al2O3/Si substrates at 700°C showed that the HfO2 film was dominated by crystalline phase of monoclinic HfO2(-111) plane. The intensity of attributed diffraction peak at about 28.3° was over 10 times larger than other plane ones. In contrast, that of deposited on HF-treated and chemically oxidized substrates did not show such dominant peaks. The AFM study showed that γ-Al2O3 buffer layer acted as protection layer for substrate etching (deep pin-hole was observed from HfO2 film deposited on without γ-Al2O3 under layer). In addition, XRD patterns of 200 nm-thick SBT and BLT films exhibited that crystalline HfO2/γ-Al2O3 substrates effectively performed for orientating crystallization for BLT(117) and SBT(115) planes. In this study, it has been revealed that crystalline γ-Al2O3 layer was useful for preparation of crystalline HfO2 films. And the crystalline HfO2/γ-Al2O3/Si(100) substrates were also attractive for the fabrication of orientation-controlled ferroelectric thin films.
12:45 PM - G3.10
Simultaneous Measurement of the Piezoelectric, Dielectric and Resistive Current Response of Ferroelectric Capacitors by an Atomic Force Microscopy Based Approach.
Adrian Petraru 2 , Hermann Kohlstedt 1 2 , Valanoor Nagarajan 4 , Ramamoorthy Ramesh 5 , Darrell Schlom 3 , Kristoff Szot 2 , Rainer Waser 2 Show Abstract
2 IFF_IEM, Institut fuer Festkoerperforschung and CNI, Forschungszentrum Juelich GmbH, Juelich Germany, 1 Advanced Light Source, LBNL , Berkeley, California, United States, 4 School of Materials Science and Engineering, University of New South Wales, Sydney, New South Wales, Australia, 5 Department of Materials Science and Engineering and Department of Physics, University of California , Berkeley, California, United States, 3 Department of Materials Science and Engineering, Pennsylvania State University, University Park, Pennsylvania, United States
G4: RRAMs and Scanning Probe Memories
Wednesday PM, April 19, 2006
Room 3010 (Moscone West)
2:30 PM - **G4.1
Resistance Change of NiO and its Memory Applications.
In Yoo 1 Show Abstract
1 Nano Devices Lab, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of)
3:00 PM - G4.2
Oxygen-vacancy Mediated Resistance Switching of Perovskite Oxide Material; First-principles Study.
Sang Ho Jeon 2 , Bora Lee 1 , Bae Ho Park 2 , Seungwu Han 1 Show Abstract
2 Department of Physics, Konkuk University, Seoul Korea (the Republic of), 1 Department of Physics, Ewha Womans University, Seoul Korea (the Republic of)
Reversible resistance switching has been found to occur in perovskite oxides such as SrTiO3 and SrZrO3 sandwiched between two metallic electrodes. Even though many sophisticated experiments favor the interface mechanism of the switching behavior, the microscopic origin is yet to be elucidated. Based on the first-principles study, we propose a switching mechanism where the oxygen vacancy, a most important point defect in oxides, plays an essential role. We calculate on the Schottky barrier between the SrTiO3 and various metal electrodes such as Au, Pt, Ti, and SrRuO3. We find that the Schottky barrier is extremely sensitive to the defect density as well as the position of oxygen vacancies near the interface. Based on the computational results, we propose a model that can explain recent experiments on resistance switching phenomena in Nb- and Cr-doped SrTiO3.
3:15 PM - G4.3
Resistance Switching in Cr-doped SrTiO3. A Candidate for Nonvolatile Memory.
Gerhard Ingmar Meijer 1 , M. Janousch 2 , U. Staub 2 , S. F. Karg 1 , D. Widmer 1 , J. G. Bednorz 1 Show Abstract
1 , IBM Zurich Research Laboratory, CH-8803 Rueschlikon Switzerland, 2 , Swiss Light Source, Paul Scherrer Institut, CH-5232 Villigen Switzerland
3:30 PM - G4.4
Resistive Switching in Pt/TiO2/Pt Thin Film Capacitor – A Candidate for a Resistive Non-volatile Memory.
Doo Seok Jeong 1 , Herbert Schroeder 1 Show Abstract
1 IEM / IFF and CNI, Forschungszentrum Juelich GmbH, Juelich Germany
Non-volatile memory (NVM) devices such as switchable resistors (ReRAM) are discussed for future ultra-large scale-integrated memory chips in cross-bar architecture because of their simple geometry. A large variety of candidates is presently under discussion such as magnetic RAM, phase change materials, single molecules, polymers and other organic insulating materials, and ferroelectric and paraelectric oxides. We have produced metal/insulator/metal (MIM) capacitor structure with thin sputtered TiO2 films between platinum electrodes showing resistive memory switching and investigated the microstructural and electrical properties of these MIM capacitors. Sputtering parameters, which were varied during reactive sputtering of Ti with a mixture of argon/oxygen, were e.g. deposition rate, deposition temperature (up to 500°C), deposition time (film thickness) and ratio of oxygen/argon in the sputter gas. The DC electrical properties were measured in dependence of applied voltage or current, temperature and sample geometry such as oxide film thickness and electrode (capacitor) area. The main results are:a) All produced titanium oxide films are amorphous, they did not show any XRD peaks. The stoichiometry was close to TiO2 as revealed by Rutherford backscattering (RBS).b) After deposition the TiO2 films were insulating. They had to be electroformed to show resistive switching, the forming voltage ranged from 5 V to 8 V. A current compliance had to be applied, which must be larger than 1 mA to induce the electroforming successfully, but smaller than about 10 mA not to degrade the film completely (permanent dielectric breakdown).c) The “Reset” voltage to the higher resistance state (“Off”-state) was 0.7 ± 0.1 V. The resistance ratio between “On”- and “Off”-state was of the order of 1000. The set voltage for inducing the “On”-state again showed larger variations, 1.5 ± 0.25 V with a current compliance as high as that of the electroforming for the same reason.d) The switching curve was completely symmetrical for positive and negative bias. Reading and writing could be applied several times, but a limit for the number of switchings has not been tested yet.The results will be discussed in the light of common mechanisms for resistive switching.
3:45 PM - G4.5
The Interfacial Layer between Pt/PCMO and the Bi-stable Resistive States
Wei Pan 1 , David Evans 1 Show Abstract
1 , Sharp Labs of America, Camas, Washington, United States
Nobel metals, such as Pt, Au, and Ag, in contact with perovskite metal oxides, PrxCa1-xMnO3 (PCMO) for example, have shown switching resistance values upon the stimulation of electrical pulses. In this paper, the Pt/PCMO/Pt structures were made through e-beam evaporation (Pt electrodes) and RF sputtering (PCMO films). The PCMO thin films made through low temperature sputter deposition in this study were stoichiometry (slightly oxygen rich) material containing nano-crystal PCMO. Two distinguished resistance states, a couple of orders of magnitude between high resistance state (HRS) and low resistance state (LRS), were observed by the application of electrical pulses with different pulsing lever and pulse duration. It was noted as uni-polar long-short switching. In order to understand this unique mechanism, extensive electrical characterizations were designed and performed on the Pt/PCMO/Pt structure and the results are presented in the paper.The existence of a contact resistance, or an interfacial layer, between Pt electrodes and PCMO was evident by simply measuring the stack resistance (IV) against PMCO film thickness. Results indicated that the contact resistance contributed a quite portion to the whole stack resistance. Temperature dependence of the IV characteristics indicated the transport mechanism in PCMO was ionic both in the bulk and the interfacial layer, which was also confirmed by the result of the time-bias test done on the Pt/PCMO/Pt stack. The transient characteristics of Pt/PCMO/Pt stack, i.e. the response to the pulsing in the time domain, were characterized in the frequency domain instead, that is, the admittance spectroscopy measurements. Detailed and extensive analysis of the impedance spectra and/or the Cole-Cole plots against temperature, bias, and PCMO film thickness led us to understand that there was a dipolar polarization on the interfaces. This layer of surface dipole polarization located right on the Pt/PCMO interfaces and contributed to the contact resistance. The switching of surface dipole polarization states through ionic jump was also responsible for the so unique uni-polar long-short switching because our calculated relaxation time constants for the surface dipole polarization corresponding to LRS and HRS were long-short and vary close to the experimental values.
4:30 PM - **G4.6
A Scanning-Probe Based Complete Storage System
Evangelos Eleftheriou 1 Show Abstract
1 , IBM Zurich Research Lab, Rueschlikon Switzerland
Ultrahigh storage densities of 1 Tb/in.2 or higher can be achieved by using local-probe techniques to write, read back, and erase data in very thin polymer films. Our thermomechanical scanning-probe-based data-storage system referred to as "millipede", combines ultrahigh density, small form factor, and high data rates. After illustrating the principles of operation of our concept, the 2D cantilever-array and microscanner components are described in detail. The arrangement of these MEMS (micro-electro-mechanical-system) components in an assembly is also elucidated. Moreover, the architecture of data-storage fields as well as dedicated fields for servo and timing control is discussed, and the system aspects related to the read-back process, probe parallelism, synchronization, and the servo mechanism are presented. Finally, results of the first small-scale prototype storage system with servo navigation and parallel read/write/erase capability using our scanning-probe thermomechanical recording technology are presented. This is the first time a scanning-probe recording technology has reached this level of technical maturity, demonstrating the joint operation of all building blocks of a storage device.
5:00 PM - G4.7
Transfer of Si3N4 Cantilever Array on a CMOS Circuit Using New Wafer Level Bonding Method for Probe-Based Nano Data-Storage Applications.
Il-Joo Cho 1 , Caroline Lee 1 2 , Young-Sik Kim 1 , Hyo-Jin Nam 1 , SongSoo Jang 1 , Won-Hyeog Jin 1 , Jong-Uk Bu 1 , Sun-Il Chang 3 , Euisik Yoon 3 Show Abstract
1 Devices and Materials Lab, LG Electronics, Seoul Korea (the Republic of), 2 , Hanyang University, Seoul Korea (the Republic of), 3 , University of Minnesota, Minneapolis, Minnesota, United States
5:15 PM - G4.8
Lead Titanate thin Films Obtained from the Reaction of a TiO2 Precursor Layer with PbO for the Application as Ferroelectric Media in High Density Probe Storage
S. Buhlmann 1 , Y. W. Nam 1 , S. Hong 1 , Y. Kim 2 , K. No 2 Show Abstract
1 Nano Devices Lab, Samsung Advanced Institute of Technology (SAIT), Yongin-Si, Gyeonggi-Do, Korea (the Republic of), 2 Electronic and Optical Materials Lab, Korea Advanced Institute of Science and Technology (KAIST), Daejeon Korea (the Republic of)
Due to their reversible polarization, ferroelectrics are promising materials as information carriers in data storage. We use a modified AFM tip, which serves as a resistive probe to read and write (r/w) data from a ferroelectric media. The probe discriminates between up and down polarization by sensing the direction of the field emanating from the ferroelectric thin film. Because of its high remanent polarization, PbTiO3 is particularly interesting as a media candidate. Its crystalline orientation and grain size are two important material properties which very much affect the quality of the r/w mechanism. In an oriented film having a grain size in the range of the bit size, even few misaligned grains (i.e. one in 10'000) induce severe error levels during r/w. In order to address this issue, we currently investigate nano-grain sized ferroelectric thin films. The grain size in such films has to be smaller than the bit size. This allows to average misalignment and other defects over several grains for one bit to reach uniform properties on the media. Unfortunately, with conventional fabrication processes, the grain size of PZT thin films is usually in the range of about 50nm, which is too large for a target bit size of 25nm (for 1Tbit/in2). This large grain size is a consequence form the nucleation controlled growth of PZT.In this contribution we present a sputtering method, which circumvents the nucleation issue and produces PbTiO3 thin films with grain sizes well below 10nm on Pt/SiO2/Si. We use a TiO2 starting precursor layer on Pt which is then reacted to PbTiO3. For the reaction, Pb is reactively rf-sputtered from a Pb target onto the TiO2 layer at 650C, 10mT oxygen pressure. It is believed that PbO is the reactive species. TEM analysis showed the formation of small PbTiO3 crystals with the correct stoichiometry and grain sizes down to 5nm. No remaining Pb compound other than PbTiO3 was detected at the surface which indicates complete evaporation of PbO. The process allows precise control of the reacted thickness. As such, a 13nm thick PbTiO3 layer with uniform thickness was formed on a 70nm thick TiO2 film. Piezoelectric force microscopy showed that this film was ferroelectric. These findings are promising for the fabrication of a reliable ferroelectric media which is able to provide a data storage density above 1Tbit/in2.
5:30 PM - G4.9
Effect of Pulse Parameters and Scan Speed on Domain Size in Ferroelectric Probe Storage.
Yunseok Kim 1 , Seungbum Hong 2 , Yun-Woo Nam 2 , Seung-Hyun Kim 3 , Kwangsoo No 1 Show Abstract
1 Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon Korea (the Republic of), 2 Nano Device Lab., Samsung Advanced Institute of Technology, Suwon Korea (the Republic of), 3 , Inostek Inc., Ansan-si Korea (the Republic of)
5:45 PM - G4.10
Resistive Probe Storage: R/W Mechanism.
Seungbum Hong 1 , Hyoungsoo Ko 1 , Dong-Ki Min 1 , Juhwan Jung 1 , Yun-Woo Nam 1 , Hongsik Park 1 , Simon Buehlmann 1 , Yong Ho Seo 1 , Jong Youp Shim 1 , Chulmin Park 1 , Yunseok Kim 2 , Kwangsoo No 2 , Junsoo Kim 3 , Hyungcheol Shin 3 , Hyunjung Shin 4 , Seung-Hyun Kim 5 , In Kyeong Yoo 1 Show Abstract
1 Nano Devices Lab, Samsung Advanced Institute of Technology, Suwon, Kyounggi, Korea (the Republic of), 2 Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejon Korea (the Republic of), 3 Nano Systems Institute and School of Electrical Engineering, Seoul National University, Seoul Korea (the Republic of), 4 Nano Materials and System Lab, Kookmin University, Seoul Korea (the Republic of), 5 , INOSTEK, Ansan Korea (the Republic of)
We present the principle of read/write mechanism using the resistive probe accompanied by a servo/tracking concept. We developed a nanoscale field sensor called resistive probe that, in principle, can detect electric charges at the nanoscale (resolution of 75 nm) within nanoseconds (response time of 10 ns). Such resistive probes can be implemented into probe storage device with ferroelectric media development, which shows promising future for the terabit era.
G5: Poster Session: FeRAMs and Other Concepts of Non-Volatile Memories
Thursday AM, April 20, 2006
Salons 8-15 (Marriott)
9:00 PM - G5.1
Influence of Intermediate Layers on the Imprint of PZT Ferroelectric Capacitors
Ulrich Boettger 1 Show Abstract
1 IWE II, RWTH Aachen, Aachen Germany
9:00 PM - G5.10
Predictive Process Simulation of Si Nanocluster Layer Formation by Low-Energy Ion Implantation
Karl-Heinz Heinig 1 , Mueller Torsten 2 1 , Bernd Schmidt 1 Show Abstract
1 Inst. of ion beam physics and materials research, Research Center Rossendorf, DRESDEN Germany, 2 Flash Technology Predevelopment, Infineon Technologies Dresden, DRESDEN Germany
Memory cells consisting of a metal-oxide-semiconductor field-effect transistor (MOSFET) with a charge-storage floating-gate made of silicon nanocrystals (ncs) are promising candidates for high-storage density low-power memory applications. The information is stored in the floating gate that can be charged and discharged either from the control gate or from the channel of the transistor. Floating gates consisting of Si ncs have been fabricated through the use of different deposition techniques.The multi-dot layer in the very thin gate oxide can be fabricated CMOS-compatibly by ion beam synthesis (IBS) . Here, we present theoretical studies on IBS of multi-dot layers consisting of Si nanocrystals (NCs) . The NCs are produced by ultra low energy Si ion implantation, which causes a high Si supersaturation in the shallow implantation region. During post-implantation annealing, this supersaturation leads to phase separation of the excess Si from the SiO_2. Kinetic lattice Monte Carlo simulations of Si phase separation have been performed and compared with EFSTEM images . It has been predicted theoretically that the morphology of the multi-dot Si floating gate changes with increasing ion fluence from isolated, spherical NCs to percolated spinodal Si pattern. These patterns agree remarkably with EFSTEM images. However, the predicted fluence for spinodal pattern is lower than the experimental ones. Because oxidants of the ambient atmosphere penetrate into the as-implanted SiO_2, a substantial fraction of the implanted Si is lost due to oxidation. K.-H. Heinig, T. Müller, B.Schmidt, M. Strobel, W. Möller, Appl. Phys. A 77, 17–25 (2003). T. Müller, K.H. Heinig, and W. Möller, Appl. Phys. Lett. 81, 2373 (2002). T. Müller, K.H. Heinig, W. Möller, C. Bonafos, H. Coffin, N. Cherkashin, G. Assayag, S. Schamm, G. Zanchi, A. Claverie, M. Tencé, C. Colliex, Appl. Phys. Lett. 85, 2373 (2004).
9:00 PM - G5.11
Combinatorial Studies for High Density Si and Ge Nanoparticle Arrays.
Scott Stanley 1 , John Ekerdt 1 Show Abstract
1 Chemical Engineering, University of Texas Austin, Austin, Texas, United States
Optimizing chemical and physical vapor deposition (CVD and PVD) processes to realize a particular film or nanostructure composition with desired properties (such as thickness, particle size distribution, bandgap, etc.) is an arduous task. The parameter space for CVD processes is vast due to the large number of parameters to be investigated, such as growth temperature, precursor material and flux, substrate material and surface treatment, and reaction method (thermal, plasma, catalytic) to name a few. Therefore, combinatorial studies could have a large impact on the efficiency of defining a process and identifying parameter regions of interest for detailed study. Combinatorial methods can be particularly useful in nanoparticle growth studies as discussed in this paper.This paper is divided into two parts. First, the simple design of a combinatorial CVD setup is presented. Methods to controllably generate gradients in composition, growth temperature, and precursor flux all on one surface are discussed and the rich data extracted will also be discussed in general terms. Second, a combinatorial study is presented to identify parameters leading to high density nanoparticle arrays. Silicon and Ge nanoparticle growth on HfO2 is chosen due to the relevance to non-volatile memory applications (i.e. nanocrystal-based flash memory). This approach decreases experimental time by orders of magnitude for examining nanoparticle growth and allows an enormous parameter space to be investigated in a comparatively short time. We are able to extract critical flux and critical temperatures from these studies to “dial in” a desired nanoparticle size and coverage. We identify optimum conditions from the combinatorial study to grow optimal nanoparticle arrays and study electrical properties for flash memory applications.
9:00 PM - G5.13
New Design of Scanning Resistive Microscopy (SRM) Probe for Spatial Resolution Improvement.
Hyoungsoo Ko 1 , Seungbum Hong 1 , Hongsik Park 1 , Chulmin Park 1 , Ding-Ki Min 1 , Yongho Seo 1 , Jongyoup Shim 1 , Yunwoo Nam 1 , Simon Buhlmann 1 , Juhwan Jung 1 , Inkyung Yoo 1 Show Abstract
1 Nano Device Lab, Samsung Advanced Institute of Technology, Yongin-Si, Kyunggi-Do, Korea (the Republic of)
9:00 PM - G5.14
Effect of Oxygen Stoichiometry on Resistive Switching Characteristics of Pr0.7Ca0.3MnO3 Thin Films Grown by Pulsed Laser Deposition.
Young-Hwan Kim 1 , Dong-Soo Kim 1 2 , Sung-Mok Jung 1 3 , Seong-Il Kim 1 , Yong Tae Kim 1 Show Abstract
1 Semiconductor Materials and Devices Laboratory, Korea Institute of Science and Technology, Seoul Korea (the Republic of), 2 Department of Physics, Korea University, Seoul Korea (the Republic of), 3 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Recently, resistive switching in transition metal oxides and perovskite oxides has been widely studied for a possible application to nonvolatile memory devices due to their low power consumption and high-density integration. We have investigated resistive switching characteristics of Pr0.7Ca0.3MnO3 (PCMO) thin films grown on Pt/TiO2/SiO2/Si substrates by using pulsed laser deposition with KrF excimer laser (λ=248nm). The PCMO films were deposited at various substrate temperatures (500~700 oC) and various oxygen pressures (100~300 mTorr). The crystal structures and surface morphologies were examined by x-ray diffraction and scanning electron microscopy, respectively and the I-V characteristics of Au/PCMO/Pt structures were measured by semiconductor parameter analyzer. The PCMO films were crystallized at the substrate temperature above 600 oC. The crystalline films only exhibited hysteretic I-V curves implying that resistive switching between high-resistance state (HRS) and low-resistance state (LRS) occurred in the Au/PCMO/Pt structures. The resistance ratio of HRS and LRS increased with increasing substrate temperature. The resistive switching characteristics were also dependent on oxygen pressure during deposition. The higher oxygen pressure was found to be favorable to increase the ratio of HRS/LRS. This result indicates that the switching behavior of the PCMO films might be strongly related to oxygen stoichiometry. To elucidate the effect of oxygen content of PCMO film on the resistive switching behavior more systematically, the oxygen contents in the PCMO films are controlled by post-annealing at various oxygen partial pressures and the results will be presented.This work is supported by the National Program for 0.1 Terabit NVM Device.
9:00 PM - G5.15
Co/Ru Sandwich Stacks Fabricated for MRAMs by ALD.
Eun Ho Kim 1 , Y. J. Kong 1 , D. H. Lee 1 , H. S. Kim 1 , S. J. Noh 1 , Yongmin Kim 1 Show Abstract
1 Applied Physics, Dankook University, Seoul Korea (the Republic of)
9:00 PM - G5.16
Mechanism of Resistive Memory Switching in NiO Thin Films.
Jung Bin Yun 1 , Hyunjung Shin 1 , Sunae Seo 2 , Myoung-Jae Lee 2 , Seung-Eon Ahn 2 , Dong-Chul Kim 2 , In-Kyeoug Yoo 2 Show Abstract
1 School of Advanced Materials Engineering, kookmin university, seoul Korea (the Republic of), 2 Nano Devices Lab, Samsung Advanced Inst. of Technology, Kyeonggi-do Korea (the Republic of)
Bi-stable memory switching devices based on transition metal oxides (TMO) are now emerging as a candidate for next generation non-volatile memories due to their superior scalability, compatibility with semiconductor processes and low voltage operation. By conducting atomic force microscopy (C-AFM), we demonstrated the mechanism of forming process and bi-stable memory switching in Pt/NiO/Pt structures. We observed the formation of filaments in nanometer scale by applying appropriate electric field – called “forming”. It is also demonstrated that few tens of nanometer (10~30nm in diameter) sized filaments are generated with localized and random fashion by forming process and contribute to the memory switching. In addition, reconstruction of current paths through the formation and rupture of the filaments in random is illustrated after repetitive switching cycle as truly localized phenomena. Also, the filaments are individually switched so large distribution of operating voltage and current values are induced by those. In order to control the maximum current and operating voltage we made an artificial filament using C-AFM. Distribution of current value of high conducting state decreased from 14.74±3.12 mA of Pt/NiO/Pt to 11.92±0.44 mA of Pt/NiO(a filament by C-AFM)/Pt as mean values with the standard deviation. Deviation for the operating voltages decreased also from 1.81±0.23 V to 1.76±0.08 V. We successfully demonstrated improved controllability by an artificial filament. Results validate the feasibility of high density integration by controlling the complete confinement and number density of the filaments.
9:00 PM - G5.2
Effect Of Plt Buffer Layers With Different Lanthanum Concentration On The Pzt Thin Films For Fram Applications.
Li Dong Hua 1 , Lee Sang Yeol 1 Show Abstract
1 Electrical and Electronic Engineering, Yonsei University , Seoul Korea (the Republic of)
9:00 PM - G5.4
Growth of BiFeO3 Thin Films by Radiofrequency Beam Assisted Laser Ablation.
Maria Dinescu 1 , Mitoseriu Liliana 2 , Ianculescu Adelina -Carmen 3 , Dinescu Gheorghe 1 , Constantinescu Catalin 1 , Moldovan Antoniu 1 , Birjega Ruxandra 1 Show Abstract
1 , NILPRP, Bucharest Romania, 2 , University Al. I. Cuza, Iasi Romania, 3 , Polytehnica University, Bucharest Romania
9:00 PM - G5.5
Electrical Properties of Ferroelectric Thin Films on the sol-gel Derived LaNiO3 Bottom Electrode.
Pei-Ying Lai 1 , Yi-Sheng Lai 1 , Jen-Sue Chen 1 Show Abstract
1 Department of Materials Science and Engineering, National Cheng Kung University, Tainan Taiwan
9:00 PM - G5.6
Electrical Characteristics of Ferroelectric Field Effect Transistors (FeFETs) Incorporating Langmuir-Blodgett Films of a Vinylidene Fluoride Ferroelectric Copolymer.
Andreas Gerber 2 , Hermann Kohlstedt 2 1 , Michael Fitsilis 2 , Rainer Waser 2 , Timothy Reece 3 , Stephen Ducharme 3 , E. Rije 4 , Juergen Schubert 4 Show Abstract
2 Research Center Juelich, Institute of Solid State Research (IFF), and CNI Center of Nanoelectronic Systems for Information Technology, Juelich Germany, 1 Lawrence Berlekely National Laboratory, Advanced Light Source, Berkeley, California, United States, 3 University of Nebraska, Lincoln, Department of Physics and Astronomy, Center for Materials, Lincoln, Nebraska, United States, 4 Research Center Juelich, Institute for Thin Films and Interfaces (ISG 1), and CNI Center of Nanoelectronic Systems for Information Technology, Pittsburgh, Pennsylvania, United States
9:00 PM - G5.7
Electrode Influence on the Transport Through Metal-insulator-oxide Conductor Junctions.
Hwan-Soo Lee 1 , Sukwon Choi 2 , Paul Salvador 2 , James Bain 1 Show Abstract
1 Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States, 2 Materials Science and Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States
Perovskite oxides such as Cr-doped SrZrO3 (SZO),1 and Pr0.7Ca0.3MnO3 (PCMO),2 comprising a film of material sandwiched between two metallic electrodes, are of great interest as a cross-point architecture for next generation nonvolatile memory (NVM). Recently, Sawa et al.3 reported on the interface properties between PCMO and different metallic electrodes. In their work, the authors stressed the importance of a Schottky-like barrier which can be altered by trapped charge carriers in the interface states. The resistance variation was explained by a change in the Schottky barrier height at the metal/PCMO interfaces. Using SRO (SrRuO3, bottom electrode)/Cr-doped SZO/metal (top electrode) heterostructures grown on STO (SrTiO3, substrate), we investigated the current transport characteristics by varying the top electrode metals (Pt, Cr, Cu, Mg, and SRO). The observed I-V curves can be well described for all the samples, using a relationship I(V)=aV+bV2 in the voltage ranges (e.g. <3V). The I-V showed that a linear behavior is greater up to a voltage less than 1V while, at higher voltages, a non-linear I-V gets prevailing. It should be noted that near a voltage (5-10V) where switching occurs, the voltage dependency greater than 2 is observed. These linear and non-linear term with square of the voltage dependence are interpreted as thermionic emission limited conduction (TELC) and space charge limited conduction (SCLC), respectively. Additionally, we have found that the coefficient a is well correlated with the metal work function while the coefficient b is not. As voltage was greater than 1V, the measured resistances with respect to metal electrodes were listed from low to high (SRO∠Pt∠Cu∠Cr∠Mg) while work functions were Mg∠(Cu or Cr)∠SRO∠Pt, suggesting that work function would not be a good indicator of the junction resistances. Rather, the transport properties of the device seems to be dominated by the oxygen affinity of the metal electrodes. For instance, Cu and Cr have similar work functions (4.5 eV), but Cr shows much higher resistance. Of the metals used in this study, Mg and Cr have the highest oxygen affinity while Pt the lowest and Cu the second to the lowest. In fact, the coefficient b (A/V2) varied in the ranges between 10-6 to 10-4. A disappearance of the Schottky rectifying characteristics at higher voltages may be due to barrier lowering by image forces or tunneling effects at work. Furthermore, using a widely accepted trap-controlled SCLC model by Rose,.4 the trap density, Nt(/m3) and distance, E(eV) from the valence band were also estimated. For b=10-5 and E=1.1-1.4 eV, the Nt is in the ranges between 1023-1018/m3. Ref)1 A. Beck et al., Appl. Phys. Lett., 77, 139 (2000).2 A. Baikalov et al., Appl. Phys. Lett., 83, 957 (2003).3 A. Sawa et al., Appl. Phys. Lett., 85, 4073 (2004).4 A. Rose, Phys. Rev., 97, 1583 (1955).
9:00 PM - G5.9
Data Storage and Retention in a Polymer-Based Non-Volatile Ferroelectric Capacitor.
Timothy Reece 1 , Andreas Gerber 2 , Chris Othon 1 , Hermann Kohlstedt 2 , Stephen Ducharme 1 Show Abstract
1 Department of Physics and Astronomy, Center for Materials Research and Analysis, University of Nebraska, Lincoln, Nebraska, United States, 2 Institute of Solid State Research (IFF) and CNI-Center of Nanoelectronic Systems for Information Technology, Juelich Research Center, Juelich Germany
Langmuir Blodgett ferroelectric polymer films are promising candidates for use in ferroelectric field effect transistor elements due to their many attractive features, such as, lower processing temperatures and lower fabrication costs . For samples consisting of a 25 monolayer LB film deposited on p-type silicon with a thermally grown oxide (10 nm), Capacitance-Voltage curves with a +/- 3 Volt sweep revealed a 1 Volt memory window and an on/off ratio of 3.2. Memory retention times of only 15-20 minutes were observed after 4 Volt, 1000 sec. polarizing pulses . In this study, we investigate the limited retention. The potential causes include charge leakage, unsaturated polarization, and depolarization fields. Improvements in retention are expected with the use of insulating layers with higher capacitance, by making thinner layers , or by using a high-k dielectric like HfO2.1.S. Ducharme, T.J. Reece, C.M. Othon, R. Rannow IEEE TDMR accepted Oct. 2005.2.A. Gerber, T.J. Reece, H. Kohlstedt, S.Ducharme in preparation.This work was supported by the USA National Science Foundation, the USA Office of Naval Research, the Nebraska Research Initiative, and Volkswagon-Stiftung under project number I/77 737.
Orlando Auciello Argonne National Laboratory
Jan Van Houdt IMEC
Rick Carter LSI Logic
Seungbum Hong Samsung Advanced Institute of Technology
G6/H5: Joint Session: Phase Change Memories I
Thursday AM, April 20, 2006
Room 3010 (Moscone West)
9:00 AM - **G6.1/H5.1
OUM Nonvolatile Semiconductor Memory Technology Overview
Stephen Hudgens 1 Show Abstract
1 , Ovonyx, Inc., Sunnyvale, California, United States
OUM (Ovonic Unified Memory), also called PCRAM (phase-change RAM) or CRAM (chalcogenide RAM) is a nonvolatile semiconductor memory technology being developed by Ovonyx, Inc. in a number of industrial joint development programs. OUM technology is based on an electrically initiated reversible amorphous to crystalline phase change process in multi-component chalcogenide alloy materials similar to those used in rewriteable optical disks. Fundamental processes in OUM devices, manufacturing technology, and progress towards commercialization of the technology will be reviewed.
9:30 AM - G6.2/H5.2
Thermal Analysis and Structural Design of Phase Change Random Access Memory.
Rong Zhao 1 , Ler Ming Lim 1 , Luping Shi 1 , Hock Koon Lee 1 , Hongxin Yang 1 , Tow Chong Chong 1 Show Abstract
1 , Data Storage Institute, Singapore Singapore
9:45 AM - G6.3/H5.3
On the Kinetic Characteristics of the Set Process in a Non-volatile Phase-change Memory.
Dae-Hwan Kang 1 , Byung-ki Cheong 1 , Jeung-hyun Jeong 1 , Taek Lee 1 , In Kim 1 , Won Kim 1 , Ki-Bum Kim 2 Show Abstract
1 Thin Film Materials Research Center, Korea Institute of Science and Technology, Seoul Korea (the Republic of), 2 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Phase-change memory device characteristics concerning reset and set states/processes are liable to have causal relations with the kinetics of these phase changes and the resulting phase structures. Accordingly, characterization and understanding of the relations are supposed to be indispensable to design of materials and device structures for better memory performances. This seems particularly true with regard to the set process that involves more complex and sluggish material responses than the reset, thus representing an arena of important technical and scientific issues in research and development of materials and structures for phase change memory devices. In this study, a time-resolved analysis is carried out on the kinetic nature of the set process in a non-volatile phase-change memory device by combined analyses of set voltage waveforms and low-field resistances. As it turns out, the progress of a set process may be measured in terms of three characteristic times in sequence i.e., threshold switching time t_th, apparent incubation time t_app,inc, and complete set time t_set. These characteristic times are supposed to demarcate, in some measure, different stages of crystallization in the phase-change material during a set process. Based on a qualitative model of the set process, it is suggested that t_th is required to form cold filaments in an amorphous matrix and t_app,inc – t_th and t_set – t_app,inc correspond to true incubation time t_inc for nucleation of crystallites and time for percolation t_per of growing nuclei in the heated filaments, respectively. Each of these times has a strong dependence on input pulse voltage, representing the kinetic nature of threshold switching and crystallization processes correspondingly. t_th is found to have an exponentially decaying dependence and this might be related to the decreasing capacitance of an amorphous phase-change material with approaching threshold switching. Meanwhile, each of t_inc and t_per shows a pseudo-linear dependence but with a decreasing and an increasing tendency with input voltage respectively. These results might be explained by the enhanced tendency toward faster nucleation of a lower density of crystalline nuclei at a higher input voltage (or higher temperature). The methodology advanced in the present work is being developed further for practical use in design of high-speed phase change materials and cell structures of memories with better performances.
10:00 AM - G6.4/H5.4
Multi-level Operation in Multi-layered Structure of Ge2Sb2Te5 and TiN.
Hyun-Goo Jun 1 , Dong-Ho Ahn 1 , Tae-Yon Lee 2 , Dongbok Lee 1 , Ki-Bum Kim 1 Show Abstract
1 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 Nano Systems Institute - National Core Research Center, Seoul National University, Seoul Korea (the Republic of)
Multi-layered structure comprising alternately deposited films of TiN and Ge2Sb2Te5 is investigated. From the multi-layered structure, it is possible to implement the multi-level operation simply by stacking metal, TiN in this case, and Ge2Sb2Te5 in resistive region of phase change random access memory (PRAM). As the metal layer, TiN is selected because of its chemical stability at interface with Ge2Sb2Te5 and relatively high resistivity for Joule heating. PRAM devices of such structure are fabricated by direct current (DC)-sputtering of Ge2Sb2Te5 and TiN layers. DC current-voltage (I-V) curves of the device were measured with the applied current in the range of 0 to 100 mA. The I-V curve on multi-layered structure exhibits several threshold switching, in contrast to the single switching observed in single layered structure. It is found that the number of switching is equal to that of Ge2Sb2Te5 layers. Furthermore I-V characteristic after each threshold switching is preserved. The differences of resistance measured after each switching and before the switching are big enough to realize multi-level device operation. I-V curves are measured on the other asymmetric double-layered structures, whose Ge2Sb2Te5 layers have different thickness. Interestingly, device which has thicker Ge2Sb2Te5 layer toward positive electrode has higher threshold voltage. It implies that electrical conduction behavior in Ge2Sb2Te5 has directional dependence. The high resistive intermediate TiN layers may modify the temperature profile during the set operation, and its interfaces with Ge2Sb2Te5 may serve as heterogeneous nucleation sites for crystallization. Thus, the preserved I-V characteristic after each switching implies that permanent changes like partial crystallization occur sequentially in each Ge2Sb2Te5 layer. As a result, discrete resistance levels are distinguished by the crystallized portion. Detailed discussion on the proposed device structure, the conduction behavior, and relation between the observed I-V characteristics and microstructure will be given.
10:15 AM - G6.5/H5.5
Investigation on Ultra-high Density and High Speed Non-volatile Phase Change Random Access Memory (PCRAM) by Material Engineering.
E.G. Yeo 1 , L.P. Shi 1 , R Zhao 1 , T.C. Chong 1 Show Abstract
1 , Data Storage Institute, Singapore Singapore
11:00 AM - **G6.6/H5.6
Modeling Considerations for Phase Change Electronic Memory Devices.
Guy Wicker 1 Show Abstract
1 , Ovonyx, Inc., Rochester Hills, Michigan, United States
This presentation will review the status of modeling phase change electronic memory devices. Beginning with a historical look at early modeling efforts in optical and electronic phase change memories, recent modeling efforts will be reviewed based on recently published results. Then the difficulties encountered with modeling of these devices will be discussed along with a discussion of the direction modeling needs to take to be useful in improving chalcogenide alloy phase change memory devices, including mechanical properties and alloy phase segregation.
11:30 AM - G6.7/H5.7
An Analysis of the Operation Characteristics of PRAM and Development of a New Multi–bit Structure through 3-D Transient Simulation Modeling.
YoungWook Park 1 , Kyung-Woo Yi 1 Show Abstract
1 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
A simulation model of a PRAM device was developed in order to evaluate the thermal and electric characteristics of its set and reset operations. Using this model, we investigated the effects of unit cell structure, contact area and material properties on the thermal and electric characteristics of memory switching. In addition, time-dependent variations of temperature and electric potential during phase transitions were investigated using a three dimensional transient simulation model. According to our results, the structure and contact area of the unit cell had a decisive influence on the transition volumes of the phase change material. Also, smaller phase transition volumes resulted in more efficient characteristics for the device in terms of power consumption. On the basis of our simulation model, we developed a new conceptual multi-bit structure. Unlike the on and off motions of existing structures, the processes of the multi-bit structure can be divided into three or more operations with multiple states of resistance. This multi-bit system is based on our results showing the contact area’s considerable influence on the thermal and electrical characteristics of PRAM devices.Keywords: PRAM, phase change, SET & RESET, contact area, multi-bit structure
11:45 AM - G6.8/H5.8
Thermal Conductivity of Phase Change Material Ge2Sb2Te5
Ho-Ki Lyeo 1 2 , David Cahill 1 2 , Min-Ho Kwon 5 2 , Bong-Sub Lee 1 3 , John Abelson 1 3 , Stephen Bishop 3 4 , Ki-Bum Kim 5 , Byung-ki Cheong 6 Show Abstract
1 Materials Science and Engineering, University of Illinois, Urbana, Illinois, United States, 2 Frederick-Seitz Materials Research Laboratory, University of Illinois, Urbana, Illinois, United States, 5 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 3 The Coordinated Sciences Laboratory, University of Illinois, Urbana, Illinois, United States, 4 Electrical & Computer Engineering, University of Illinois, Urbana, Illinois, United States, 6 Thin Film Materials Research Center, Korea Institute of Science and Technology, Seoul Korea (the Republic of)
Ge2Sb2Te5 (GST), a material that can change structural phases between an amorphous and two crystalline states, undergoes phase transformations by optical absorption or joule heating. Practical utilization of this material associated with the phase change at a small scale depends crucially on the thermal transport in GST and between GST and surrounding materials. We hereby explore the relationship between the phase transformations and the thermal conductivity of Ge2Sb2Te5 films (ΛGST). The thermal conductivity of GST films is measured using time-domain thermoreflectance. First, we measure the thermal conductivity ΛGST for three films that include an as-deposited amorphous (a-GST) film; the other two films are annealed for 20 min at fixed temperatures of 180 °C and 360 °C to form the cubic f.c.c. (c-GST) and hexagonal (h-GST) phases, respectively. For the three films, we obtain the values of Λa-GST ≈ 0.19 Wm-1K-1, Λc-GST ≈ 0.57 Wm-1K-1, and Λh-GST ≈ 1.58 Wm-1K-1. We then measure the thermal conductivity as a function of the film temperature when the film is heated at a rate of 3 K/min. The measured conductivity ΛGST undergoes a discontinuous increase at T ≈ 130 °C and a smooth change at ≈ 340 °C. The first abrupt change appears upon crystallization, i.e. a- to c-GST transformation, and the second change appears with c- to h-GST transformation. The values of Λc-GST encompass the range of 0.45 - 0.95 Wm-1K-1 at 130 °C < T < 310 °C. Similarly, Λh-GST includes the range of 1.4 - 1.53 Wm-1K-1 at 340 °C < T < 400 °C while the values of Λa-GST are essentially constant. The thermal transport at a- and the early c-GST phases can be explained by a random walk of vibrational energy (minimum thermal conductivity). By contrast, in the h-GST phase, the thermal conduction is largely due to electronic contribution; the contribution deduced from the Wiedemann-Franz law accounts for ~70% of the measured Λh-GST. Finally, we measure the thermal conductivity of spots crystallized by laser processing as functions of the energy density and the number of applied laser pulses. The measured thermal conductivity of the rapidly transformed spots induced by laser pulses is lower and closer to the minimum thermal conductivity than that of the thermally annealed one. This implies that the rapid crystallization leads to a more disordered crystalline structure than the annealed one does.
12:00 PM - G6.9/H5.9
Investigation on the Enhanced Switching Reliability of a Phase Change Memory Device with an Oxidized TiN Electrode.
Dae-Hwan Kang 1 , In Kim 1 , Jeung-hyun Jeong 1 , Byung-ki Cheong 1 , Dong-Ho Ahn 2 , Dongbok Lee 2 , Hyun-Mi Kim 2 , Ki-Bum Kim 2 Show Abstract
1 Thin Film Materials Research Center, Korea Institute of Science and Technology, Seoul Korea (the Republic of), 2 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Fluctuations (or drifts) in switching voltages such as programming set/reset voltages and threshold voltage pose serious obstacles to the reliable operation of electrical phase change memory devices. Using a phase change memory device having a GeSb2Te4 phase change material and TiN electrode, these fluctuations are demonstrated to result from device resistances varying with programming cycles, which appear to be caused by variations in contact resistance at the interface between the phase-change material and the TiN electrode as well as by inhomogeneous phase distribution across the GeSb2Te4 layer due to lack of temperature uniformity. Oxidation of a TiN electrode surface (via thermal annealing at 350^oC under an air environment with N2 gas flow) is very effective in the reduction of fluctuations in device resistances and switching voltages hence the resulting increase in the programming cycles by two orders of magnitude. From a high resolution transmission electron microscopy, the oxidized surface was shown to consist of a TiOx (x~1.5) layer with nm-sized Ti2O3 crystallites which is presumed to yield enhanced stability of the device by the following two effects. Firstly, Ge, Sb, and Te atoms would have stronger bonds to oxygen atoms than to nitrogen atoms by about 0.5 eV, thereby producing more robust interface. Accordingly, both contact resistance and its variation with programming cycles tend to be reduced significantly so as to have little influence on the device resistances and their fluctuations (interface effect). Secondly, thermally and electrically more resistive nature of the TiOx layer would tend to yield, by enhanced generation and confinement of joule heat, more uniform temperature distribution across the