Integrated circuit technology is an enabling force for an ever broadening array of information technology systems. Herein we examine the hypothesis that as feature size scaling continues, integrated circuit technology may morph into integrated system technology at the atomic level. Constraint analysis of extreme microsystems is a useful tool for better understanding of the fundamental limits and potentials of nanodevices in an integrated system. An example of extreme prototypical application of autonomous micron-scale systems is the ‘electronic cell’ (e.g. for bio-medical applications); but many other applications can be envisioned. Imagine that we desire to design and fabricate an active micron-sized system that performs in-vivo sensing and possibly interaction with a single living cell. The technological challenges that must be addressed to develop such a system are daunting and encompass almost every facet of integrated system technology including sensing, information processing, energy, communication, packaging, and possibly actuation. This is a very challenging task with many unknowns, including the impact of scaling on power source options, sensitivity limits for scaled sensors etc. A fundamental physics approach is used to comprehend the allocation of the atoms in the micron-scale devices to achieve the desired functionality for the system.

Spintronics is a concept in which both the charge and the spin of the electron are used to create low-power, radiation-hard, non-volatile devices. In this talk, I describe a spintronic scheme based on ferromagnetic metallic nanostructures in which Boolean states are coded using the direction of magnetisation and information is propagated by magnetic domain walls flowing through networks of magnetic nanowires. A room-temperature NOT-gate, AND-gate and a 1-to-2 fan-out gate are all demonstrated experimentally. Small functioning logic circuits including a variety of shift registeres are also demonstrated [1]. The strengths and weaknesses of nanoscale magnetic logic as a post-CMOS logic primitive are described and a scheme proposed for ultrahigh density non-volatile integrated serial memory which could be fabricated as a BEOL process on top of a CMOS device. [1] Allwood, Cowburn et al. Science 309, 1688 (2005)

We analyze spin wave-based logic circuits as a possible route to building reconfigurable magnetic circuits compatible with conventional electron-based devices. A distinctive feature of the spin wave logic circuits is that a bit of information is encoded into the phase of the spin wave. It makes possible to transmit information as a magnetization signal through magnetic waveguides without the use of an electric current. By exploiting sin wave superposition, a set of logic gates such as AND, OR, and Majority gate can be realized in one circuit. We present experimental data illustrating the performance of a three-terminal micrometer scale spin wave-based logic device fabricated on a silicon platform. The device operates in the GHz frequency range and at room temperature. The output power modulation is achieved via the control of the relative phases of two input spin wave signals. The obtained data shows the possibility of using spin waves for achieving logic functionality. The scalability of the spin wave-based logic devices is defined by the wavelength of the spin wave, which depends on the magnetic material and waveguide geometry. Potentially, a multifunctional spin wave logic gate can be scaled down to 0.1um2. Another potential advantage of the spin wave-based logic circuitry is the ability to implement logic gates with fewer elements as compared to CMOS-based circuits in achieving same functionality. The shortcomings and disadvantages of the spin wave-based devices are also discussed.

One of the big challenges in beyond C-MOS technology is how one can use correlated electrons for information technologies. Apart from semiconductors that treat electron free from other electrons, we always enjoy cooperative phenomena of many electrons residing in oxides. There are numbers of ingredients that makes oxides so interesting. The advances in thin film technology allow us to test our ideas at the interfaces. The many body physics welcome interfaces. Very important question there is that how electron behaves if faced with other ground states. If electrons decide what to do by watching other electrons, giving well-defined boundary condition is an important probe. I will describe how and why the correlated electrons in complex oxides are to be considered to discuss the opportunities in this symposium. The talk will cover magnetic interfaces and tailored multiferroics.

Although a number of alternatives to silicon-based materials have been proposed, silicon remains the stalwart of the electronics industry. Generally, the behavior of silicon is controlled by changing the composition of the active region by impurity doping; while changing the surface (interface) states is also possible. As scaling to the sub-20 nm-size region is pursued, routine impurity doping becomes problematic due to its resultant uncertainty of distribution. Provided back-end processing of future devices could be held to temperatures that are molecularly permissive (300-350°C) and taking advantage of the dramatic increase in the surface-area-to-volume-ratios of small features, it is attractive to seek controllable modulation of device performance through surface modifications. If there is no intervening oxide between the pi-rich molecules and the silicon, sequentially tuned molecular-structure changes can predictably regulate the device performances over a wide range. In this contribution, an electronically controlled series of molecules, from strong pi-electron donors to strong pi-electron acceptors, were prepared and systematically covalently attached as molecular monolayers onto the channel region of pseudo-MOSFETs (back gated), and the device modulation was studied. Changes of >2.5 V could be obtained in the threshold voltages by attaching monolayers atop the active regions of the transistors. Additionally, three-terminal field-effect transistors (FETs) were fabricated using intrinsic Si nanowires. Forming an F-terminated oxide surface significantly decreased the resistivity, increased the mobility, and they had a large hysteresis, enabling their possible use in memory devices. Finally, 2-terminal silicon-graphene nanodevices with highly non-linear I(V) curves provide the basis for 10^7 ON:OFF ratio, non-destructive read, non-volatile memories.

The practical need for new semiconductor technologies is driving the recent surge of interest in single layers of graphite – graphene. This novel material offers the possibility of modulating its electronic behavior and introducing novel functionality by tailoring the morphology. Individual layers can be stacked vertically, resulting in different properties due to interlayer interaction. They can also be carved into smaller structures, for example 2D electron waveguides or quasi-1D channels which dramatically alters their electrical behavior due to confinement of charge carriers. The bandgap of such nanoribbons could be engineered by simply changing their width. Together with very high mobility (more than 15000 cm2/Vs), this makes graphene a promising two-dimensional material for nanoscale electronics. There are however numerous problems related to processing and intrinsic properties of graphene that should be solved. For example, device fabrication is still difficult and impractical at large scales. I will attempt to give an overview of the current state of research in this field and present several strategies for overcoming existing difficulties.

New computing paradigms are sought to go beyond the CMOS roadmap. Nanoscale crossbar architectures offer several interesting opportunities, including ultimate scaling and defect tolerant reconfiguration.[1] Initial demonstrations of stand-alone ultra-dense memory and logic are promising, but it is clear that integration of nano-crossbars with Si CMOS is mandatory both for circuit optimization and technology adoption.Here we demonstrate a 21x21 nano-crossbar switch array at 40 nm half-pitch formed by nanoimprint lithography on top of fully integrated Si MOSFETs. Using these hybrid FET/nano-switch circuits we demonstrate compound logic “AB+CD” operations with FET outputs for signal gain and fanout. The system was then set up with a feedback loop to enable conditional self-programming of nano-switch junctions within the crossbar containing the logic for the circuit. This demonstrates for the first time a switch in an nano-crossbar architecture that is toggled depending on the result of an adjacent nano-crossbar logic operation. These results open new opportunities for self-programmed logic arrays as well as electronic adaptive network type computing. [1] P. J. Kuekes, G. S. Snider, and R. S. Williams 2005, "Crossbar nanocomputers," Scientific American, 293 (5), 72-8

The ability to scale CMOS while keeping power density roughly constant represents a significant limitation to meeting end-of-the-roadmap specifications. Neuronal computational systems such as the human brain require very small amounts of power as compared to binary systems. One fundamental feature of this architecture is the ability to compute in a massively parallel manner, with information being simultaneously propagated to multiple processing units. A single neuron, for example, can form 10^4 synapses, and can send information distances greater than 1 m without loss. Mead and co-workers have previously demonstrated CMOS devices in crystalline silicon that mimic aspects of neural processes at the device level (e.g. Ranvier nodes, synapses). Because speed is not critical in a neuron-inspired architecture and to permit scaling to large area or integrating with CMOS, we investigated the use of non-crystalline, nanowire FET’s to build silicon analogues of Nodes of Ranvier. First, we constructed a SPICE model of polycrystalline, nanowire FET’s using the ASIA2 AIM-SPICE Level 15 amorphous silicon model. The derived model is in agreement with recent work, correctly scaling with different Vds. Next, a simple Node of Ranvier analogue was simulated using CMOS inverters built from the nanowire FET’s. Simulations were performed using an input signal similar to neuronal action potentials, with varying output capacitance loads. We show that a single silicon Node of Ranvier can support 10^3 synapses, with 1% loss in pulse area, while dissipating, on average, 1 nW. It is therefore possible to achieve synaptic fan-out of 10^4 while dissipating only 10 nW from propagation mechanisms.

New generation microelectronic systems embedded in safety-critical hardware or operating in aggressive environments are facing contradictory constraints related to their reliability. On the one hand, applications in domains such as air- and spacecraft flight control, or implanted medical devices demand massive data processing in order to improve their capabilities, throughput, and system accuracy. On the other hand, a constant decrease in manufacturing yield of modern deep-submicron VLSI is observed, and fabrication parameter fluctuations, intrinsic device noise, current leakage, as well as transient failures are starting to play a major role in integrated circuit robustness. Moreover, the integration of novel nanoelectronic devices into “nano-LSI” circuits is predicted to suffer from significantly high defect densities, at least in the first generations, causing a large number of devices to operate outside of their nominal range of electrical characteristics, or be inoperative. Solutions that had been proposed in the early stages of CMOS integration era have re-emerged recently. We believe that an optimal approach to fabricating reliable systems out of unreliable, atomic-scale nano-devices should span across several layers of abstraction. We explore circuits and architectures which are designed according to the principles inspired by the operation of feed-forward artificial neural networks, and which are taking benefit of internal analog computation in order to recover proper operation of Boolean functionalities. The input variables are processed by a small number of redundant units, which in turn feed into a voter consisting of averaging and thresholding functions, thereby forming a binary decision output value. Unlike traditional fault-tolerant systems such as triple modular redundancy, or NAND-multiplexing, our system has been designed to tolerate a large number of defects, still demanding very low redundancy. In specific cases, this system still operates while all redundant units are subject to several non-identical defects. Theoretical analysis has been carried out considering both gate-level, and module-level (<1e5 devices) implementation, to demonstrate the superiority of the proposed approach in terms of fault tolerance. The benefit is obvious at gate-level, where device failure rates of up to 30% can be tolerated without affecting the functionality, and using three redundant units only. Improvement of the probability of correct operation over r-fold modular redundancy of 33% and up to 80% can be achieved using the proposed architecture without and with adaptive thresholding, respectively, at constant probability of failure. The redundancy factor needed to achieve a given probability of failure can be decreased by 35% and 70% using the proposed architecture in replacement of r-fold modular redundancy. These improvements are significant, and directly result in significant area and power savings while ensuring system level robustness.

Thursday, March 27New Abstract *B2.7 @ 4:30 PMSome Current Trends and Future Challenges in Nanoelectronics. Thomas N. Theis, IBM T.J. Watson Research Center, Yorktown Heights, New York.