Jeff Gambino IBM Microelectronics
Sinichi Ogawa Semiconductor Leading Edge Technologies, Inc.
Chee Lip Gan Nanyang Technological University
Zsolt Tokei IMEC vzw
N1: Low-k Dielectrics I
Chee Lip Gan
Tuesday PM, March 25, 2008
Room 2024 (Moscone West)
9:15 AM - **N1.1
Molecular-level Manipulation Technology for Low-k Dielectrics Controlling the Physical and Chemical Structures toward 32nm-node BEOLs.
Yoshihiro Hayashi 1 Show Abstract
1 Device Platforms Research Laboratories, NEC, Sagamihara, Kanagawa, Japan
Low-k materials in advanced BEOL modules are required not only to reduce the parasitic capacitances among interconnects, but also to have mechanical stability with damage-less interfaces in the BEOL modules. By using a sophisticated plasma-co-polymerization process, we have innovated a new molecular-level manipulation technology, which enables us to control the physical and chemical structures in low-k dielectrics continuously. The key feature is the mixing ratio modulation of several kinds of vaporized precursor molecules with unsaturated hydrocarbon side-chains. The low-k film characteristics such as the chemical composition, the porosity, the refractive index, the elastic modulus, and the adhesion strength are controlled continuously in the thickness direction. In this paper, the technology concept and its application to 32nm-node ULSIs will be explained in details. Here, tight chain-type vinyl-siloxane molecules are co-polymerized with ring-type vinyl siloxane molecules having sub-nanometer-scale molecular-pores, achieving a modulated molecular-pore-stack (MPS) SiOCH module with the stabilized interfaces in the 100nm-pitched lines.
9:45 AM - N1.2
Molecular Network Reinforcement of Sol-gel Glasses.
Geraud Dubois 1 , Willi Volksen 1 , Teddie Magbitang 1 , Robert Miller 1 , David Gage 2 , Reinhold Dauskardt 2 Show Abstract
1 Department of Advanced Organic Materials, IBM, San Jose, California, United States, 2 Department of Materials Science and Engineering, Stanford University, Stanford, California, United States
The intrinsic mechanical properties of a given material strongly depend upon its chemical nature: the organics tend to be soft, but tough, while the inorganic materials, on the other hand, are hard but brittle, and are prone to fracture. The later characteristic gets even worse for porous materials and is of major concern in the microelectronics industry as porous organosilicates (mainly inorganic) will constitute the next insulating layers in future electronic devices . In this presentation, we demonstrate that significantly tougher organosilicates glass thin-films prepared by sol-gel process, can be obtained by introducing carbon bridging units between silicon atoms present in the organosilicate network [2,3]. Fracture energy values of 14-16 J/m2 were measured, surprisingly higher than those for dense silicon dioxide (10 J/m2), suggesting mechanical properties that lie somewhere in between those of conventional glasses and organic polymers. We also found that the Young’s modulus follows a linear decay when porosity is introduced, a unique property when compared to traditional organosilicates. As a result, crack resistant films were obtained at high level of porosity, opening potential applications in the field of low-k materials for future integrated circuits, membranes, sensors, waveguides, fuel cells and micro-fluidic channel. G. Dubois, W. Volksen, R.D. Miller, in Dielectric Films for Advanced Microelectronics, (Eds: M. Baklanov, K. Maex, M. Green), Wiley, New-York, 2007, Chap 2. G. Dubois et al. US 7,229,934 B2. G. Dubois et al, Adv. Mater. 2007, Wiley Interscience on line early view.
10:00 AM - N1.3
Zeolite-like Films for Low-k Applications.
Salvador Eslava 1 3 , Mikhail Baklanov 1 , Francesca Iacopi 1 , Jone Urrutia 1 , Abheesh Busawon 1 , Christine Kirschhock 2 , Karen Maex 1 3 , Johan Martens 2 Show Abstract
1 , IMEC, Leuven Belgium, 3 ESAT-INSYS, K. U. Leuven, Leuven Belgium, 2 Centrum voor Oppervlaktechemie en Katalyse, K. U. Leuven, Leuven Belgium
10:15 AM - N1.4
Atomic Layer Deposition of Hybrid or Microporous Low-k Materials.
Ying-Bing Jiang 1 , Zhu Chen 2 , David Kissel 1 2 , Shisheng Xiong 2 , Juewen Liu 2 , Carlee Ashley 1 2 , Eric Carnes 1 2 , Darren Dunphy 1 2 , Robin Swell 1 , Joseph.L. Cecchi 2 , C.Jeffrey. Brinker 1 Show Abstract
1 Dept. 1815, Sandia National Labs, Albuquerque, New Mexico, United States, 2 Center of Microengineered Materials and Dept. ChNE, Univ. of New Mexico, Albuquerque, New Mexico, United States
Atomic layer deposition (ALD) films are precise in thickness control and conformal to complex topographies. Enabling ALD to deposit organic/inorganic hybrid or microporous materials may extend this burgeoning technique to a number of new applications. Several vacuum deposition techniques, such as CVD and PECVD, have been employed to coat hybrid materials for low-k applications, but the layer-by-layer deposition mode in ALD process requires different deposition chemistries. Here we report a successful ALD deposition of silica-based hybrid or microporous low-k materials by using bridged silsesquioxane precursors ((RO)3Si-R’-Si(OR)3)). To improve the deposition rate and material’s rigidness, a second silane precursor such as TMOS (tetramethyl orthosilicate) or SiCl4 was used to replace silsesquioxane intermittently. The compositional and structural information of the as-deposited ALD films was characterized with Fourier transform infrared spectroscopy (FTIR), X-ray induced photoelectron spectroscopy (XPS) and transmission electron microscope with electron energy loss analysis (TEM with EELS). Their surface roughness was investigated by AFM, and their density and the young’s modules were measured by a surface acoustic wave (SAW) device. The organic/inorganic hybrid structure of the as-deposited films has been confirmed by the above characterizations. Upon proper UV treatment, this hybrid structure can be converted into a microporous structure and the pore size determined by gas permeability measurement was found to be in the order of magnitude of ~ 3 angstroms. We have attempted to perform ALD using organosilane precursors with pendant organic groups, such as R’-SiX3, R’-Si(OR)3 and (R’-SiX2)2O, but we found the deposition rate to be practically zero, presumably due to surface passivation by the accumulating pendant organic groups that terminate on the sample surface after each ALD cycle, suggesting that a precursor containing bridging instead of pendant organic groups is important for this hybrid thin film ALD process.
10:30 AM - **N1.5
Porosity Characteristics of Ultralow Dielectric Insulator Films Directly Patterned by Nanoimprint Lithography.
Hyun Wook Ro 1 , Hae-Jeong Lee 1 , Ken-Ichi Nihara 2 , Hiroshi Jinnai 2 , David Gidley 3 , Do Yoon 4 , Christopher Soles 1 Show Abstract
1 Polymers Division, NIST, Gaithersburg, Maryland, United States, 2 Polymer Science and Engineering, Kyoto Institute of Technology, Kyoto Japan, 3 Physics, University of Michigan, Ann Arbor, Michigan, United States, 4 Chemistry, Seoul National University, Seoul Korea (the Republic of)
Directly patterning dielectric insulator materials via nanoimprint lithography has the potential to simplify fabrication processes and significantly reduce the manufacturing costs for semiconductor devices. However, the prospect of mechanically forging these materials, especially in their porous form, into nanoscale patterns raises concerns regarding their physical integrity and pore structure. Recently we demonstrated that an excellent fidelity of the pattern transfer process could be achieved, with minimal pattern shrinkage or distortion, as quantified with critical dimension small angle X-ray scattering and specular X-ray reflectivity. Here we focus on developing the measurement techniques to characterize the porosity characteristics of spin-on organosilicate materials that have been patterned by nanoimprint lithography. X-ray porosimetry (XRP) is used quantify the average density, the porosity, and the wall density of the material between the pores of these imprinted patterns. All of these parameters characterized by XRP can be resolved as a function of vertical height through the pattern. In addition, positron annihilation lifetime spectroscopy measurements are described to quantify the pore size distributions and the degree of pore interconnectivity in the patterned material. Finally, the porosity characteristics determined by XRP and PALS are correlated with high resolution transmission electron microscopy (TEM) images of the pattern cross section to obtain a complete picture of how the imprint process affects the porosity of these materials. Examples will be shown where the porosity level is pushed to over 50 % by volume, well into the ultralow-k regime where the expected dielectric constants will be less than 1.8. In some instances the imprint process can be used to induce a porosity collapse or dense skin that enhances the barrier properties of the imprinted pattern. In other cases the pores inside the patterns remain highly interconnected and open to the external surfaces. The differences in these two situations will be discussed in detail.
11:15 AM - **N1.6
Advanced Bilayer Low-k Dielectric Cap for Reliable High Performance Cu-Low k Interconnects in ULSI Devices.
Son Nguyen 1 2 , Shobha Hosadugra 1 , Alfred Grill 2 , Joshua Herman 1 , Griselda Bonilla 2 , Stephan Cohen 2 , Eva Simonyi 2 , Thomas Shaw 2 , Steven Molis 3 , Chao-Kun Hu 2 , Nancy Klymko 3 , Tien Cheng 3 , Sang Lee 4 , Maggie Le 4 , Li-Qun Xia 4 , Ritwik Bhatia 4 , Steven Reiter 4 Show Abstract
1 IBM at Albany Nano Tech, IBM Research, Albany, New York, United States, 2 Silicon Technology, IBM T.J. Watson Research Center, Yorktown Heights, New York, United States, 3 SRDC, IBM System Technology Group, Hopewell Junction, New York, United States, 4 Blanket CVD, Applied Materials, Santa Clara, California, United States
The metallization of integrated circuits for high performance CMOS devices involves the use of copper with low-k or ultra low-k dielectrics to reduce RC delay and cross talk in devices. For CMOS devices, there is a definite need to reduce the dielectric constant of both the cap and ILD films without sacrificing the reliability of the BEOL device structures. Thus the BEOL dielectrics need to have lower dielectrics constants but still provide high mechanical, electrical, and fabrication integration robustness.This paper presents the development of an advanced bilayer low k Cu diffusion cap having a low dielectric constant (k<= 4.0) while still maintaining equivalent reliability as compared to traditional SiCNx cap materials. A new PECVD SiCNx/SiCNy bilayer film was developed with varying composition to achieve: 1) a high nitrogen content SiCNx bottom layer with robust mechanical properties, good barrier properties ,and excellent interfacial characteristics with Cu. 2) a lower nitrogen content SiCNy top layer with lower dielectric constant, good plasma RIE selectivity, and high chemical mechanical polishing stability. This paper will discuss the development and final results of this advanced bi-layer low-k cap material for use in advanced CMOS devices
11:45 AM - N1.7
Study on the Thermal Stability of Pore Structure in a Porous Low-k in a Copper/Low-k Interconnect Pattern - Correlation with Thermal Stress.
Woong Ho Bang 1 , Choong-Un Kim 1 , Kyu Hwan Oh 2 , Hee Suk Chung 2 , Eun Kyu Her 2 Show Abstract
1 Materials Science and Engineering, University of Texas at Arlington, Arlington, Texas, United States, 2 Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Currently porous low dielectric constant materials (porous low-k) are being introduced into the interconnect structure of microelectronics. One of the most critical issues for this challenging is the stability of pore structure in the low-k, especially during thermal and plasma steps of interconnect integration process. This presentation presents thermal stability of pore structure in a porous low-k embedded in a Cu/low-k pattern. It observes pore structure change after high temperature anneal set at 400C, but also examines samples with different pitch sizes (identical copper width but with different low-k width). Our major findings are following geometry-dependent pore behaviors during anneal: stable pore structure at wide pitch; significant pore collapse and pore structure change at narrow pitch. The pitch-size dependent result indicates that, in interconnect structure, pore behavior is deeply in association with physical-mechanical process such as thermal stress evolution rather than with chemical process. Using finite element method (FEM), thermal stress evolution within low-k material is examined. The correlation between the experimental results and thermal stress suggests that the pore collapse at narrow pitch size is caused by severe compressive stress developed in low-k during anneal. More detailed results and discussion will be given during presentation.
12:00 PM - N1.8
Copper Treatment to Improve Adhesion to Dielectric Barrier.
Raymond Vrtis 1 , Laura Matz 1 , Mark O'Neill 1 Show Abstract
1 Electronics, Air Products and Chemicals Inc., Allentown, Pennsylvania, United States
As device dimensions in the microelectronics industry continue to decrease, more new materials are being integrated than ever before. Critical areas of concern for 45nm nodes and beyond are the resistance increase associated with smaller copper lines and increased electromigration (EM) resistance due to higher current densities required by device designs. To counteract the increase in RC time constant from the line resistance increase, many manufacturers have announced that they will use porous organosilicate glasses such as Air Products PDEMSTM porous dielectrics at the 45 nm technology node for capacitance reduction. There has also been a drive to lower the dielectric constant of the dielectric barrier layer to lower the k-effective for the dielectric stack. As device manufacturers modify their dielectric barrier layers concerns related to adhesion to copper and EM resistance arise. To address the EM needs for 32nm and below, several groups have reported the use of electroless CoWP or the formation of self-aligned copper salicide layers.The self-aligned copper salicide process has been shown to improve the resistance to EM by up to a factor of three. However, this comes at the cost of increasing line resistivity due to rapid diffusion of silicon into copper. In this study, we investigate various adhesion promotion precursors and processes which may provide advantages to improve EM beyond that achieved with the current silane processes.Previous research points to a relationship between the level of adhesion of copper to dielectric barrier and the resistance of that structure to EM, therefore comparisons of EM resistance performance for various precursors and processes will be inferred from 4-point bending methodology. In order to understand the penetration of the silicon species for each chemical exposure, dynamic SIMS and surface XPS will be employed to investigate the copper/nitrogen-doped silicon carbide interface. Using the above procedure, we will investigate 3 chemicals with modified chemical species bonded to silicon to asses the fundamental role that various functional groups have on adhesion, and by inference EM, while not significantly increasing copper line resistance. To further assess the fundamentals of copper adhesion as related to device performance, modifications to the industry standard nitrogen-doped silicon carbide and silicon nitride dielectric barrier processes will be examined to gain insight into the properties that affect copper adhesion.
12:15 PM - N1.9
The Effects of Porosity on the Stiffness and Fracture Toughness of Brittle Organosilicates.
Han Li 1 , Youbo Lin 2 , Joost Vlassak 1 Show Abstract
1 School of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, United States, 2 Department of Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States
Nanoporous organosilicate glass coatings with relative dielectric constants less than 2.5 are considered for use as intra-metal dielectric in future generations of advanced integrated circuits. Their low dielectric constant is achieved by incorporating a substantial fraction of nanometer-sized pores into a hybrid organic-inorganic matrix. While introducing porosity may be beneficial for the dielectric properties of the coatings, porosity does have a negative impact on their mechanical behavior. Increasing the amount of porogen during the deposition process changes the mechanical behavior of the coatings by increasing the pore volume fraction and by altering the network structure of the dielectric matrix. In this paper, we present, for the first time, a generic strategy to separate the effects of porosity on the elastic modulus and fracture toughness from those caused by changes in the matrix structure, with particular application to a series of PECVD-deposited organosilicate glasses of porosities ranging from 7% to 45%. This strategy relies on FTIR and composition measurements to characterize the network bond density of the matrix and on the correlation between network bond density and the mechanical response of the dielectric.We have used nanoindentation to measure the elastic modulus and the double-cantilever beam (DCB) technique to measure the mode I fracture toughness as a function of porosity for a series of porous OSG films. XPS and AFM were used for composition and morphological characterization of the fracture surfaces. After correction for changes in the matrix network structure, the modulus decreases nonlinearly with increasing porosity and is generally much lower than expected for a structure with randomly distributed spherical pores. The stiffness is in good agreement, however, with the solid sphere model proposed by Roberts (J.Am.Ceram.Soc.p3041,2000). The effects of pore shape and interconnection will also be discussed. With similar corrections for changes in the matrix structure, the porosity demonstrates a linear weakening effect on fracture toughness across the porosity range investigated. This observation is consistent with a planar through-pore cracking mechanism. Pore toughening as a result of crack blunting or deviation by individual pores is not observed.
12:30 PM - N1.10
The Mechanical Properties of Organosilicates: Effects of Methyl and Methylene via Theory & Simulations.
Brian Peterson 1 , Mary Haas 1 , Mark O'Neill 1 Show Abstract
1 , Air Products & Chemicals, Inc., Allentown, Pennsylvania, United States
Jeff Gambino IBM Microelectronics
Sinichi Ogawa Semiconductor Leading Edge Technologies, Inc.
Chee Lip Gan Nanyang Technological University
Zsolt Tokei IMEC vzw
N9: Poster Session: Reliability and Packaging II
Thursday PM, March 27, 2008
Salon Level (Marriott)
9:00 PM - N9.1
Using a Flash Process to Reduce RC Delay and Improve Electromigration in Al-Cu/Ti/W Interconnect for High Power Analog and Mixed Signal Applications.
Tom Lee 1 , William Murphy 2 , Daniel Delibac 3 , David Thomas 3 , Daniel Vanslette 4 , Zhong-Xiang He 5 , Stephen Mongeon 6 , Jonathan Chapple-Sokol 7 , Timothy Sullivan 8 , Stephen Luce 9 Show Abstract
1 N65V, IBM, Essex Junction, Vermont, United States, 2 AZQV, IBM, Essex Junction, Vermont, United States, 3 A9UV, IBM, Essex Junction, Vermont, United States, 4 BEVV, IBM, Essex Junction, Vermont, United States, 5 E1AA, IBM, Essex Junction, Vermont, United States, 6 UFYV, IBM, Essex Junction, Vermont, United States, 7 AZZV, IBM, Essex Junction, Vermont, United States, 8 CLVV, IBM, Essex Junction, Vermont, United States, 9 FHFV, IBM, Essex Junction, Vermont, United States
We report the effects of bottom liners on electrical resistance and upstream electromigration of three metallization stacks: (I) Ti/TiN/AlCu/Ti/TiN, (II) Ti/TiN/Ti/AlCu/Ti/TiN (annealed at 400C for 20 minutes), and (III) a flash process/stack I. Bottom Ti/TiN, AlCu, and Top Ti/TiN layers have the same thickness for all these stacks. Metal line and via contact resistances of stack III are the lowest and are closely followed by stack I. Stack II has the highest metal line resistance, which is attributed to Al consumption in the TiAl3 formation during 400C/20minutes annealing. The nominal thickness of AlCu is, therefore, reduced from 370nm to 340nm, and corresponds to a sheet resistance increase of about 15%. For stacks I and II, the bottom 15nm Ti layer serves multiple purposes in the stack, one of which is adhesion to the underlying oxide. However, the Ti also interacts with the oxide layer to form TiOxSiy compounds that decrease the thickness of the conductive part of the Ti layer. Since the Ti does not react with the flash appreciably, adding the flash prior to the 15nm Ti deposition inhibits the reaction between the Ti and the underlying oxide. By keeping the original 15nm Ti intact and adding an extra flash, stack III liner has the lowest nominal sheet and contact resistances. Electromigration evaluations have been carried out on all three metallizations at 250C stress temperature and stress current densities from 10 to 15 mA/um2. For a 20% resistance increase as the failure criterion, the lifetime distributions of all three stacks exhibit bi-modal behavior. Failure analysis suggests that the two modes are differentiated by the void locations. For the early mode, the electromigration voids are located immediately at the cathode end of the test line. In this case, only the bottom redundant liner is left to carry current when the voids grow big enough to pass the edge of the bottom W via. In contrast, the voids of the late mode fails are located somewhat away from the cathode end of the line beyond the via such that both the bottom and the top liners are able to shunt the electrical current after voids of late mode fails have grown to extend over the entire AlCu cross sectional area. The normalized lifetimes of the early modes of three liner stacks are about 1X for stack I, 1.5X for stack II, and 2X stack III. The resistance versus time curves of stack I have more abrupt resistance increases at shorter electromigration stress durations than those of either stack II or stack III. Failure analysis of the fails with abrupt resistance increases shows a thermal runaway signature at the bottom redundant layer. The void characteristics and resistance time behavior of electromigration imply that the bottom liner plays the most critical role. Therefore, it is concluded that stack III liner is most suitable for high power analog and mixed signal circuit applications as well as for high circuit density where minimum pitch, single via layouts are necessary.
9:00 PM - N9.10
Study of Migration in W/TiN/Ti Metal Lines Induced by Extremely High Electrical Current.
Deokkee Kim 1 , Soo-Jung Hwang 1 , Jung-Hun Sung 1 , Sung-Yup Jung 2 , Ha-Young You 2 , Young-Chang Joo 2 , Hyuksoon Choi 1 , Ihun Song 1 , Chan-Hee Lee 1 , Yoondong Park 1 Show Abstract
1 , SAIT, Yongin Korea (the Republic of), 2 Materials Science & Engineering, Seoul National University, Seoul Korea (the Republic of)
9:00 PM - N9.11
Pore Deformation in Porous low-k Dielectrics Induced by Thermal Stress.
Suk Hoon Kang 1 , Seul-Cham Kim 1 , Kyu Hwan Oh 1 , Liangshan Chen 2 , Woong Ho Bang 2 , Choong-Un Kim 2 Show Abstract
1 , School of Materials Science and Engineering, Seoul National University, 56-1 Shillim-Dong, Gwanak-Gu , Seoul Korea (the Republic of), 2 , Materials Science Engineering,The University of Texas at Arlington, Arlington, Texas, United States
9:00 PM - N9.12
Evaluation of Properties for Tantalum and Niobium Solid-electrolyte Capacitors.
Jae Sik Yoon 1 , Yang Soo Kim 1 , Hyung Park 2 , Byung Il Kim 1 Show Abstract
1 , Korea Basic Science Institute, Sunchon, Jeonnam, Korea (the Republic of), 2 , Core Technology Research Center for Fuel Cell, Jeonbuk Korea (the Republic of)
9:00 PM - N9.2
Electromigration of Cu Interconnect Lines Prepared by a Plasma-based Etch Process.
Guojun Liu 1 , Yue Kuo 1 Show Abstract
1 Thin Film Nano & Microelectronics Research Laboratory, Texas A&M University, College Station , Texas, United States
Electromigration (EM) is one of the most critical reliability issues for ultra large scale integrated (ULSI) circuits. In addition to CMP, copper (Cu) lines could be prepared with a plasma-based etch process at room temperature (1,2). Instead of vaporizing the plasma/Cu reaction product formed during plasma exposure, a dilute HCl solution was used to dissolve the reaction product. Although there are many studies on EM of CMP Cu lines (3), there is no information on the EM performance of the Cu lines prepared by this new plasma-based etch process. In this paper, the single level Cu lines with NIST structure were patterned using the Cl2 plasma-based etch process (1). A PECVD SiNx layer was deposited above the Cu lines as the passivation layer. Following the guidelines of JESD61, we carried the isothermal EM lifetime tests on a probe station. Several conclusions can be summarized this study. First, the EM activation energy (Ea ) of 0.6 eV and the current density exponent (n) of 2.7 were obtained for the Cu line. The value is larger than that of the CMP Cu line in the package level tests (e.g., 1~2), which was attributed to the local temperature increase in the vicinity of the voids during the EM tests. The low activation energy value indicated the Cu-SiNx cap layer interfacial diffusion may be the primary transport mechanism. The standard deviations of the log-normal distributions from lifetime tests were between 0.19 and 0.3, which were comparable to those of the single level CMP Cu test structure (4). Second, SEM pictures of the failed line showed that the void was initiated from the triple junction point of the grain boundaries, which was attributed to the flux divergence. When the Cu atoms were depleted from the grain boundary or the inner free surface of the void that intersected the top Cu surface, the void grew in a “v” shape. For grain thinning, the surface atoms on the upstream grain diffused to the void boundary, and then moved up the step to feed the atoms that flowed at the Cu/dielectric interface (3). The EM induced stress caused the cap layer crack and led to the Cu extrusion, which shortened the EM lifetime. Third, when the sample was mechanically bended, the cap layer cracking was accelerated and the voids aligned perpendicular to the current flow. Both phenomena shortened of the lifetime and lowered the value to 0.5 eV.In summary, EM tests were carried out on Cu lines prepared from the plasma-based etch process. The value of 0.6 eV was obtained, which was consistent with various diffusion mechanisms such as interfacial and grain boundary diffusion. The externally applied stress shortened the lifetime and lowered the value. 1. S. Lee and Y. Kuo, J. Electrochem. Soc., 148, G524 (2001).2. Y. Kuo and S. Lee, Appl. Phys. Lett., 78, 1002 (2001).3. C.-K. Hu, L. Gignac and R. Rosenberg, Microelectronics Reliability, 46, 213 (2006).4. C.-K. Hu and J. M. E. Harper, Mater. Chem. Phys., 52, 5 (1998).
9:00 PM - N9.3
Semiconductor Film Bonding Technology and Application in Two-axis Hall Sensor Fabrication.
Keishin Koh 1 , Takashi Matushida 1 , Koji Hohkawa 1 Show Abstract
1 , Kanagawa Institute of Technology, Atsugi Japan
9:00 PM - N9.4
Formation and Electrical Characterization of Cu Through-Vias for Chip Stack Packages with Variations of Electrodeposition Parameters.
Kwang-Yong Lee 1 , Teck-Su Oh 1 , Tae-Sung Oh 1 Show Abstract
1 Materials Science and Engineering, Hongik University, Seoul Korea (the Republic of)
Chip stack packages have been developed for smaller, lighter, and thinner electronic products. Besides significant size and weight reductions, chip stack packages have advantages of high electrical performance and reduced processing cost. Chip stack packages have been processed by assembling Si chips in stack and wire-bonding I/O pads of each Si chip to substrate pads. However, wire-bonding deteriorates high frequency characteristics and hinder further size reduction. To overcome such limitations caused by wire-bonding, three-dimensional interconnection between stacked Si chips has been proposed with Cu filling into through-via holes by electrodeposition. In this study, Cu via filling behavior and electrical characteristics of Cu through-vias have been investigated for applications to chip stack packages. To facilitate the observation for Cu filling behavior, trench vias of 75~10um width were filled with variations of electrodeposition current mode and rotating speed of the rotating disc electrode. With pulse-reverse pulse electroplating, via-holes of 75um diameter and 150um depth were filled with Cu without formation of a large defect such as a seam. When flip-chip bonded at 270C for 2 minutes, the contact resistance of a Cu/Sn bump joint of 100umx100um size was 6.74 mΩ, and the resistance of a Cu via of 75um diameter and 90um height was 2.31 mΩ. With rotating disc electrode, almost complete Cu filling could be achieved for trench-vias with widths down to 35um even at DC electroplating mode.
9:00 PM - N9.5
Modelling and Characterization of Ultrasonic Consolidation Process of Aluminium Alloys.
Elaheh Ghassemieh 1 , Amir Siddiq 1 Show Abstract
1 Mechanical Engineering, University of Sheffield, Sheffiled United Kingdom
9:00 PM - N9.6
Estimating Thermal Resistance of Solder Joints in Light Emitting Diode (LED) Packages.
Jin-Woo Park 2 , Young-Bok Yoon 1 Show Abstract
2 Materials Science and Engineering, Yonsei University, Seoul Korea (the Republic of), 1 Fundamental Technology Center, Samsung Electro-Mechanics, Suwon Korea (the Republic of)
9:00 PM - N9.7
Effect of Cu Doping on Thermal Stability Improvement of Silver Metallization.
Gwan Ho Jung 1 , Jun Ho Son 1 , Jong-Lam Lee 1 Show Abstract
1 Materials Science and Engineering, POSTECH, Pohang, Gyungbuk, Korea (the Republic of)
9:00 PM - N9.8
Interfacial Behavior between Au Deposits and Electronic Substrates by Utilizing Au Nanoparticle Suspension.
Tzu Hsuan Kao 1 4 , Jenn Ming Song 2 , In Gann Chen 1 4 , Teng Yuan Dong 3 , Weng Sing Hwang 1 4 Show Abstract
1 Materials Science and Engineering, National Cheng Kung University, Tainan Taiwan, 4 Frontier Material and Micro/Nano Science and Technology Center and Center for Micro/Nano Science and Technology, National Cheng Kung University, Tainan Taiwan, 2 Department of Materials Science and Engineering, National Dong Hwa University, Hualien Taiwan, 3 Department of Chemistry, National Sun Yat-Sen University, Kaohsiung Taiwan
9:00 PM - N9.9
Numerical Analysis of Packaging-Induced Failures in Cu/Low-k Interconnects
Aditya Karmarkar 1 , Xiaopeng Xu 2 , Xiao Lin 2 , Greg Rollins 2 , Victor Moroz 2 , Xi-Wei Lin 2 Show Abstract
1 TCAD DFM Solutions, Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh, India, 2 TCAD DFM Solutions, Synopsys, Inc., Mountain View, California, United States
The current industry trends demand smaller feature sizes and greater integration density at every technology node. This requirement leads to multi-level metallization schemes with Cu interconnects and low-k dielectrics. The mechanical stresses generated in the Cu/low-k structures during packaging pose significant reliability challenges due to chip-package interaction. The packaging process generates global level stresses that permeate to the Cu/low-k level and are responsible for interconnect failures and yield loss. Therefore, it is essential to understand the impact of chip-package interaction on the mechanical reliability of Cu/Low-k interconnects. In this paper, advanced simulation techniques are used to assess the impact of the packaging process on the Cu/low-k interconnect reliability. The mechanical reliability is examined at both the package level and the interconnect level. At the package level, the reliability is determined by the thermomechanical stresses and the interfacial defects generated during packaging. At the interconnect level, the mechanical stresses, and hence reliability, are determined by the dielectric mechanical properties. Since the package behavior at the global level affects the interconnect behavior at the local level, and vice versa, the reliability impact of the chip-package interaction needs to be examined in detail. Here, an advanced simulator is used to examine interface delamination in the package and mechanical failures in interconnects, along with the interaction between these phenomena. The simulator can account for the viscoelastic behavior of various materials at the processing conditions. The viscoelastic models are used instead of linear elastic models in order to improve the simulation accuracy. The J-integral method and cohesive zone model are used to determine the effects of various global and local factors affecting the formation and propagation of interface defects and cracks. Moreover, initial defect simulations are performed to predict the behavior of an initial crack and cohesive zone simulations are performed to predict the probability of crack formation. The multi-level multi-scale submodeling technique is used to study the propagation of mechanical stress from the package level to the interconnect level and to assess the reliability impact of chip-package interaction.In the full paper, various failure mechanisms at the package and the interconnect level are discussed. The multi-level multi-scale submodeling technique along with the J-integral method and cohesive zone model is used to study the chip-package interaction and its impact on interconnect failure. Also, the effects of material property variation on the interaction between the package and the interconnect structure are analyzed. The simulation results are used to develop comprehensive strategies to reduce cracking/delamination due to chip-package interaction and to improve packaging yield and reliability.