Rong Zhao, Singapore University of Technology and Design
Ilya Karpov, Intel Corporation
Barbara De Salvo, Leti, CED-TECH
Luping Shi, Tsinghua University
ED2.1: Neuromorphic System I
Tuesday AM, April 18, 2017
PCC North, 100 Level, Room 126 A
10:30 AM - *ED2.1.01
A Hybrid Neuromorphic Computing System with Advanced Learning Capabilities
Karlheinz Meier 1 Show Abstract
1 , Heidelberg University, Heidelberg Germany
We present a new hybrid neuromorphic computer architecture based on local analog implementations of neurons and synapses, binary asynchronnous and continuous time spike communication and an on-chip microprocessor to execute local learning rules. The system is the successor of the BrainScaleS machine which is currently operated in the framework of the EU Human Brain Project (HBP).
The system features an anlog implementation of a non-linear neuron model (AdEx) with parameters stored in local capacitive memory cells. Network architectures can be freely configured via physical links established by cross-bar switches and through analog synapses. Synapse parameters are stored in local SRAM cells and each synapse features local short term (STP) and long term plasticity (STDP). The analog parameters of neurons and synapses are set to operate the system in an accelerated mode 1000 times faster than biological realtime. An on-chip SIMD Power PC based plasticity microprocessor has access to the STDP correlation measurements and can modify the STDP response function. The plasticity processor can also perform other measurements on the chip and control cell and network parameters allowing for flexible implementations of synaptic, neuronal ans structural plasticity under user control. External input signals can emulate rewards and other external controls.
With access to electronic time constants from nanoseconds to hours the new systems is especially suited to implement and study mechanisms of plasticty, learning and evelopement that range from milliseconds to years in neurobiology. It is also a model case for the self calibration of imperfect analogue systems with potential applications in future systems based on non-CMOS nanodevices.
Results of measurements performed with the the system will be described and an outlook for scaling up to wafer-scale implementations will be given. Special emphasis will be given to the effect of device variability and means to compensate or to exploit it during computation.
11:00 AM - ED2.1.02
HfO2-Based Devices for Neuromorphic Network with Real-Time Operation
Jacopo Frascaroli 1 , Stefano Brivio 1 , Erika Covi 1 , Paolo Lorenzi 2 , Manu Nair 3 , Fernanda Irrera 2 , Giacomo Indiveri 3 , Sabina Spiga 1 Show Abstract
1 , IMM-CNR, Agrate Brianza Italy, 2 Department of Information Engineering, Electronics and Telecommunication, “Sapienza” University of Rome, Rome Italy, 3 Institute of Neuroinformatics, University of Zürich and ETH Zürich, Zurich Switzerland
Bio-inspired neural processing systems have the ability to treat ill-posed problems in a very robust and efficient way. Though software implementations of deep neural networks have already achieved impressive results, they are not suitable for real-time and low power applications required by embedded devices interacting with human beings and open environment. On the other hand, hardware implementations of neural networks appear to be stuck by the unsatisfied need of nanoscale low-power electronic devices able to emulate the dense synaptic connectivity among neurons, which is at the basis of learning and adaptation.
Memristive technologies are considered the picklock to open new opportunities for hardware neuromorphic systems. Indeed recently many proposals of networks employing memristive devices as synapses have appeared:[1,2] literature reports may be distinguished on the base of (a) the functionality of the electronic synapses, e.g. single binary, compound binary synapses, or analog synapses; (b) the treatment of synapse non-idealities,[1,5] which are significant because used out of their window of deterministic behavior; (c) the learning rule the network operates (e.g. spike timing dependent plasticity with pulse overlap,[1-5] with handshaking neurons,).
In this context, we perform an investigation of operation of Pt/HfO2/TiN devices that can hold several intermediate states for both resistance increase, RESET and decrease, SET;[6,7] the simulation of the device behavior together with its non-idealities; the simulation of a highly connected neuromorphic network. The network operates a semi-supervised learning through a version of the well-known Spike timing Dependent Plasticity (STDP) that is modified to emulate a biological plausible Ca dynamics together with possible real-time operation. On one hand, there is a limited number of works dealing with the use a realistic simulation of both average behavior and variability of a device displaying a high density of resistive state that can be reached through stimulation with identical pulses SET and RESET pulses. On the other hand, the employment of this semi-supervised STDP circuit in combination with the description of neuromorphic silicon neurons  and memristive devices and the test of the network performance on the MNIST dataset is unpreceded.
Thus, this work allows the study of the network performance in relation to the specific device and circuit properties and a generalization of the results through the comparison with networks with different synaptic elements or STDP versions.
 Covi et al 2016 Front Neuros doi: 10.3389/fnins.2016.00482
 Covi et al 2016 ISCAS 393
 Ambrogio et al 2016 Trans Elect Dev 63 1508
 Garbin et al 2015 Trans Elect Dev 62 2494
 Querlioz et al 2015 Proc IEEE 103 1398
 Brivio et al 2016 Appl Phys Lett 109 133504
 Covi et al 2015 Microel Eng. 147 41
 Fusi et al 2002 Biol Cybern 87 459
 Chicca et al 2014 Proc IEEE 102 1367
11:15 AM - ED2.1.03
Organic and Organic-Inorganic Hybrid Artificial Synapses
Wentao Xu 1 , Sung-Yong Min 2 , Himchan Cho 1 , Young-Hoon Kim 1 , Yeongjun Lee 2 , Hyunsang Hwang 2 , Tae-Woo Lee 1 Show Abstract
1 , Seoul National University, Seoul Korea (the Republic of), 2 , Pohang University of Science and Technology (POSTECH), Pohang Korea (the Republic of)
We present our recent research on the fabrication of artificial synapses using organic and organic-inorganic hybrid materials. Both two-terminal and three-terminal structures are discussed. Important synaptic working principles have been emulated, including short-term plasticity (STP), long-term plasticity (LTP) and spike-timing dependent plasticity (STDP). Using our home-built electrohydrodynamic nanowire (e-NW) printer, digitally aligned semiconducting nanofibers were printed for synaptic transistor arrays, which will allow nano feature size. High-quality organic-inorganic hybrid perovskite thin film facilitated the fabrication of two-terminal artificial synapses, which is essential for high-density cross-bar electrode architectures. These properties are essential for brain-inspired computation, nano-circuit integration and represent an important step towards the future building up neuromorphic electronics.
ED2.2: Neuromorphic System II
Tuesday PM, April 18, 2017
PCC North, 100 Level, Room 126 A
1:30 PM - *ED2.2.01
Designing Oxide Architectures and Charge Transfer Processes for Resistive Switching Memory and Computing Operations
Jennifer Rupp 1 Show Abstract
1 Electrochemical Materials, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States
The next generation of information memories and neuromorphic computer logics in electronics rely largely on solving fundamental questions of mass and charge transport of oxygen ionic defects in materials and their structures. Here, understanding the defect kinetics in the solid state material building blocks and their interfaces with respect to lattice, charge carrier types and interfacial strains are the prerequisite to design new material properties beyond classic doping. Through this presentation basic theory1 and model experiments for solid state oxides their impedances and memristance2, electro-chemo-mechanics and lattice strain3-5 modulations is being discussed as a new route for tuning material and properties in ionic conducting oxide film structures up to new device prototypes based on resistive switching. Central are the making of new oxide film materials components, and manipulation of the charge carrier transfer and defect chemistry (based on ionic, electronic and protonic carriers)1-2, 5-6, which alter directly the resistive switching property and future computing performances. A careful study on the influence of microstructure and defect states vs. the materials` diffusion characteristics is in focus. For this, we suggest novel oxide heterostructure building blocks and show in-situ spectroscopic and microscopic techniques coupled with electrochemical micro-measurements to probe near order structural bond strength changes relative to ionic and electronic diffusion kinetics and the materials integration to new optimized device architectures and computing operation schemes.
1)Memristor Kinetics and Diffusion Characteristics for Mixed Anionic-Electronic SrTiO3-δ: The Memristor-based Cottrell Analysis Connecting Material to Device Performance
F Messerschmitt, M Kubicek, S Schweiger, JLM Rupp
Advanced Functional Materials, 24, 47, 7448 (2014)
2)Uncovering Two Competing Switching Mechanisms for Epitaxial and Ultra-Thin Strontium Titanate-based Resistive Switching Bits
M Kubicek, R Schmitt, F Messerschmitt, JLM Rupp
ACS Nano 9, 11, 10737 (2015)
3)Designing Strained Ionic Heterostructures for Resistive Swicthing Devices
S Schweiger, R Pfenninger, W Bowman, U Aschauer, JLM Rupp
Advanced Materials, in press (2016)
4) The Effect of Mechanical Twisting on Oxygen Ionic Transport in Solid State Energy Conversion Membranes
Y Shi, AH Bork, S Schweiger, JLM Rupp
Nature Materials, 14, 721 (2015)
5) A Micro-Dot Multilayer Oxide Device: Let’s Tune the Strain-Ionic Transport Interaction
S. Schweiger, M. Kubicek, F. Messerschmitt, C. Murer, J.L.M. Rupp
ACS Nano, 8, 5, 5032 (2014)
6) How does Moisture affect the Physical propert of Memristance for Anionic-Electronic Resistive Switching Memories?
F Messerschmitt, M Kubicek, JLM Rupp
Advanced Functional Materials, 25, 32, 5117 (2015)
2:00 PM - ED2.2.02
Pulse Characterization of HfOx-Based RRAM for Resistive Processing Unit Application
Seyoung Kim 1 , Tayfun Gokmen 1 , Takashi Ando 1 , Marwan Khater 1 , Hiroyuki Miyazoe 1 , Wilfried Haensch 1 Show Abstract
1 TJ Watson Research Center, IBM, Yorktown Heights, New York, United States
Advances in machine learning (ML) software and Big Data analytics have enabled otherwise conventional computing hardware to deliver impressive learning, reasoning, and human-machine interaction capabilities – thus launching the Cognitive Computing era. In a recent publication  we have introduced an ensemble of Resistive Processing Unit (RPU) devices that can simultaneously store and process data locally and in parallel, thus providing significant acceleration for deep neural network (DNN) training. Performance analysis of various system designs based on the RPU array concept shows that it can potentially provide four orders of magnitude acceleration of DNN training while significantly decreasing the required power and compute resources. Our analysis shows that conventional non-volatile memory elements (PCM, RRAM, etc.) do not meet the requirements needed for optimal RPU operation. In particular we find that the optimal switching behavior is analog in nature and that symmetric resistance switching under pulse stimulation is required.
We fabricate a HfOx-based resistive memory device and explore switching characteristics using various pulse voltage amplitudes and pulse widths down to 5 ns in order to test the feasibility of resistive memory devices for RPU application. Pulse measurement results indicate that the range of device resistance decreases and the up/down change symmetry in device resistance improves as the pulse width decreases. To test the fidelity of the measured switching characteristic for DNN applications we perform an RPU model simulation on the MNIST handwritten digit recognition task with the experimentally determined switching characteristics of our RRAM samples and achieve 91% of classification accuracy. Further analysis reveals the correlation between the DNN training accuracy and resistance update symmetry in RRAM devices.
 T. Gokmen et al., Frontiers in Neuroscience, 2016
2:15 PM - ED2.2.03
Pattern Recognition with “Materials that Compute”
Yan Fang 1 , Victor Yashin 1 , Anna Balazs 1 Show Abstract
1 , University of Pittsburgh, Pittsburgh, Pennsylvania, United States
Driven by advances in materials and computer science, researchers are attempting to design systems where the computer and material are one and the same entity. Using theoretical and computational modeling, we design a hybrid material system that can autonomously transduce chemical, mechanical, and electrical energy to perform a computational task in a self-organized manner, without the need for external electrical power sources. Each unit in this system integrates a self-oscillating gel, which undergoes the Belousov-Zhabotinsky (BZ) reaction, with an overlaying piezoelectric (PZ) cantilever. The chemomechanical oscillations of the BZ gels deflect the PZ layer, which consequently generates a voltage across the material. When these BZ-PZ units are connected in series by electrical wires, the oscillations of these units become synchronized across the network, where the mode of synchronization depends on the polarity of the PZ. We show that the network of coupled, synchronizing BZ-PZ oscillators can perform pattern recognition. The “stored” patterns are set of polarities of the individual BZ-PZ units, and the “input” patterns are coded through the initial phase of the oscillations imposed on these units. The results of the modeling show that the input pattern closest to the stored pattern exhibits the fastest convergence time to stable synchronization behavior. In this way, networks of coupled BZ-PZ oscillators achieve pattern recognition. Further, we show that the convergence time to stable synchronization provides a robust measure of the degree of match between the input and stored patterns. Through these studies, we establish experimentally realizable design rules for creating “materials that compute.”
2:30 PM - *ED2.2.04
Challenges and Solutions for Memristors Used for Memory and Neuromorphic Computing
Rivu Midya 1 , Zhongrui Wang 1 , Saumil Joshi 1 , Hao Jiang 1 , Peng Lin 1 , Qiangfei Xia 1 , J. Yang 1 Show Abstract
1 , University of Massachusetts Amherst, Amherst, Massachusetts, United States
Numerous perspective applications have been proposed for memristive devices. However, each application emphasizes on different merits of device properties and imposes different challenges on device performance. A practical solution to those challenges is to add an auxiliary device to each of the memristor. For memory applications, this device is often called “selector”, mainly employed to enable large memristor crossbar arrays by mitigating the so-called “sneak path current” issue with its nonlinear current-voltage characteristic. We have obtained over 1E10 nonlinearity by using engineered materials for such devices. In neuromorphic computing the accumulation and extrusion of Ca2+ in the pre- and postsynaptic compartments play a critical role in initiating plastic changes in biological synapses. To emulate this fundamental synaptic dynamic process in electronic devices, we developed diffusive Ag-in-oxide memristors with a temporal response during and after stimulation similar to that of the synaptic Ca2+ dynamics. The diffusive memristor and its dynamics enable a direct emulation of both short- and long-term plasticity of biological synapses and provide a viable solution for the crucial synaptic dynamics in neuromorphic computing.
3:30 PM - *ED2.2.05
Bioinspired Programming of Resistive Memory Devices for Implementing Embedded Neuromorphic Circuits
Elisa Vianello 1 , Thilo Werner 1 , Olivier Bichler 1 Show Abstract
1 , CEA Leti, Grenoble France
One of the most striking properties of biological systems is plasticity, their ability to make physical changes in its structure as a result of learning and experience. Plasticity typically operates on very long time scale, ranging from millisecond to days or more. Biological synapses exhibit both short-term plasticity (STP) and long-term plasticity (LTP). LTP produces stable modifications of the synapses according to the timing of pre- and postsynaptic spike events, also known as spike-timing-dependent plasticity. Along with LTP, cortical synapses undergo STP which is the dynamic modulation of the synaptic strength as a function of input stimulations and shows retrievable dynamics in short time scales (typically in the range of milliseconds).
Resistive RAM cells are a promising candidate to emulate the behavior of real synapses in artificial Neural Networks, and in particular to reproduce their learning abilities. They are a key element to enable the implementation of unsupervised learning with minimal hardware footprint and low power consumption. Embedding neuromorphic learning into low-power devices could enable the design of future sensory processing or autonomous systems. An autonomous system can be a simple one, such as a sensory processing system based on environmental sensors or biosensors; or more complex ones, such as a Brain-Machine Interface making decisions based on real-time on-line processing of in-vivo recorded biological signals, or such as humanoid robot making decisions and producing behaviors based on the outcome of sophisticated auditory or visual processing.
In this work, a simple circuit architecture and a reading/programming strategy able to emulate both Short and Long Term Plasticity (STP, LTP) rules using non-volatile RRAM cells is presented. We demonstrated that short-term plasticity allows to improve signal detection in highly noisy input data.
4:00 PM - ED2.2.06
Li-Ion Synaptic Transistor for Low Power Analogue Computing (LISTA)
Elliot Fuller 1 , Farid El Gabaly 1 , Francois Leonard 1 , Sapan Agarwal 1 , Steven Plimpton 2 , Robin Jacobs-Gedrim 2 , Conrad James 2 , Matthew Marinella 2 , Alec Talin 1 Show Abstract
1 , Sandia National Laboratories, Livermore, California, United States, 2 , Sandia National Laboratories, Albuquerque, New Mexico, United States
The exponential increase in data in the last decade has generated growing interest in low-power neuromorphic networks that are capable of learning, image recognition and real-time processing of unstructured data. The building blocks of neuromorphic networks are artificial synapses that store the synaptic weights used for learning. CMOS can be used to store synaptic weights and carry out neuromorphic algorithms, however, the volatility, high supply voltages, and the number of transistors required per synapse limit the energy efficiency and information density. Alternatively, new types of analog resistive memory are being explored to replace CMOS for low power neuromorphic computing. Here, we present a Li-ion synaptic transistor for analog computation (LISTA). LISTA is a solid-state, non-volatile electrochemical transistor (NVET) with resistance switching mechanism based upon the intercalation of Li-ion dopants into a channel of Li1-xCoO2. A NVET, such as LISTA, differs from ‘volatile’ electrochemical transistors in that dopants cannot diffuse out of the channel after the relaxation of an applied bias. NVET has two key advantages compared to two-terminal resistive memory such as phase change memory (PCM) or filament forming metal oxides (FFMO): (1) NVET utilizes the low energy process of ion insertion/extraction into a channel for resistance switching enabling extremely low voltage (< 10 mV) switching. In contrast, two-terminal devices cannot reduce switching voltages below ~0.3 V (~10 kT) and retain memory; (2) that resistance switching occurs without inducing large structural transformations that are typical for memristive devices. For LISTA, the intercalation of Li dopants does not lead to filament formation or amorphous-to-crystalline phase transformation that occurs in FFMO and PCM, respectively. The structurally stable switching mechanism allows LISTA to operate with a high signal-to-noise ratio (>80), a linear response to write operations, and orders of magnitude lower switching voltages and currents than existing devices. Simulations of backpropagation using the experimentally measured noise, linearity and conductance levels achieves the highest classification accuracy that has been demonstrated using resistive memory. Experimentally validated simulations of the device physics predict an energy cost per write operation of <10 aJ after scaling to dimensions of 200×200 nm, the lowest predicted energy cost for a resistive memory device to date .
 Elliot J. Fuller, Farid El Gabaly, François Léonard, Sapan Agarwal, Steven J. Plimpton, Robin B. Jacobs-Gedrim, Conrad D. James, Matthew J. Marinella and A. Alec Talin, Advanced Materials (in press)
4:15 PM - ED2.2.07
Spatial Summation of Organic Artificial Synapses
Fei Zeng 1 , Yuandong Hu 1 Show Abstract
1 , Tsinghua University, Beijing China
Recent studies discover short-term and long-term frequency selectivity in organic polymer/electrolyte system. The short-term plasticity has been regarded to relate with signal handling and computing in the neural system so that its spatial summation rule is commonly interested. In this study, Pt/Mg-doped polyethylene oxide (PEO)/Pt and Pt/Mg-doped PEO/poly(3-hexylthiophene-2,5-diyl) (P3HT)/Pt devices were fabricated for the studying of the spatial summation of short-term plasticity (STP). The charging peaks behaved short-term depression but the discharging peaks behaved short-term facilitate (STF) for the former. However, both the charging and discharging peaks displayed STF for the latter. Frequency selectivity in the weight modification of the charging peaks appeared for a simple integration of parallel connection, i.e., the parallel connected devices facilitates below a frequency threshold but depresses at a higher frequency. In contrast, only STF was observed in the weight modifications of the discharging peaks for the parallel connection protocol. Importantly, the weight modification could be linearly summed from those of the source devices though the absolute peak currents. This might be a calculation rule in the neural system, which need to be checked in more systems. Our study suggests that bi-directional signal transfer and synaptic computation are feasible for such a parallel connection system, which depend on both frequency and linear summation of weight modifications.
4:30 PM - *ED2.2.08
Oxide-Based Electric-Double-Layer Transistors for Neuromorphic Systems
Qing Wan 1 Show Abstract
1 , Nanjing University, Nanjing China
Our brain can perform a simple cognitive task by consuming only ~20 W of power because it processes information using energy efficient, highly parallel, event-driven architectures as opposed to clocked serial processing. The fundamental building block of every nervous system is the single neuron. Neurons have intricate dendritic morphologies and receive thousands of excitatory and inhibitory synaptic inputs arriving at different dendritic locations. Hardware implementation of neuron by individual ionic/electronic coupled device is of great importance for enhancing our understanding of the brain and building brain-inspired intelligent computer. Here, we provide a proof-of-principle artificial neuron based on a field-configurable oxide-based electric-double-layer transistor with multiple laterally-coupled input gates. Temporal summation (paired-pulse facilitation and high-pass filtering) is realized due to the dynamic process of the proton modulation. Regulation of dendritic summation was successfully mimicked by changing the voltage applied on the modulatory terminal. Additionally, neuronal gain control (neuronal arithmetic) in the scheme of temporal-correlated coding is also realized. Our results provide a new-concept approach for brain-inspired neuromorphic systems.
ED2.3: Poster Session
Tuesday PM, April 18, 2017
Sheraton, Third Level, Phoenix Ballroom
8:00 PM - ED2.3.01
Cause of RRAM Device Switching Variability and Its Impact on use in Neural Network Arrays
Karsten Beckmann 1 , Wilkie Olin-Ammentorp 1 , Joseph Van Nostrand 2 , Garrett Rose 3 , Nathaniel Cady 1 Show Abstract
1 , State University of New York Polytechnic Institute, Albany, New York, United States, 2 , Air Force Research Laboratory/RITB, Rome, New York, United States, 3 Department of Electrical Engineering & Computer Science, University of Tennessee Knoxville, Knoxville, Tennessee, United States
Resistive Random Access Memory (RRAM) is a novel form of non-volatile memory, and is making its entry into the field of neuromorphic or neuro-inspired circuit architectures. One requirement for neuro-inspired circuitry is the need for a two-terminal device whose resistance can be precisely manipulated by the means of an applied voltage or current. RRAM devices fulfill this by enabling an incremental change in resistance after passing a current. For this purpose, we developed a 1 transistor 1 RRAM (1T1R) structure integrated with the IBM 65nm 10LPe process, based on a 300mm wafer platform. The RRAM device was integrated into a custom layer between metal 1 (M1) and metal 2 (M2), where the M1 material was changed from copper to tungsten, and an additional tungsten via was introduced, to serve as the bottom electrode for the RRAM device. This change allows for the use of atomic layer deposition tools for the HfO2 switching layer from the frond-end-of-the-line (FEOL). A subsequent deposition of titanium and titanium nitride creates the oxygen scavenger layer and the top electrode, respectively. This device stack shows excellent performance with respect to switching parameters such as set/reset voltages, which are below 2 V (set) / -1.5 V (reset), and an excellent endurance exceeding 200 million cycles. In addition, incremental resistance changes were shown during the reset operation by applying 10ns short pulses. For further improvement and understanding of these devices, better insight into the magnitude and causes of variability is needed. In particular, the high-resistance state (HRS) of RRAM devices based on a Ti oxygen scavenger layer has a large variance. In part, this is believed to be caused by the dependency of the resistance with respect to the crystallographic direction. A change of the nanoscale grain structure might be induced by a redox reaction at the HfO2-Ti interface, causing a significant local resistance change. The pulse response of the reset operation of our devices, and in particular the variability observed during incremental resets, should give further insight about the thresholds necessary for such changes to occur. In addition, most neural network array designs rely on stable incremental switching of the RRAM devices to gain the desired synaptic weight. Simulations with synaptic weights incorporating the variability gained via the experimental pulse response are underway to identify the impact on the performance of neural network implementation using RRAM.
8:00 PM - ED2.3.02
A Universal Logic-in-Memory Methodology to Implement Boolean Logic Based on Memristor
Yaxiong Zhou 1 , Zhuorui Wang 1 , Yi Li 1 , Long Cheng 1 , Xiangshui Miao 1 Show Abstract
1 , Wuhan National Laboratory for Optoelectronics, School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan China
Memristor, or memristive devices exhibit reversible resistive switching behaviors are being exploited for various IoT applications, including digital memory, brain-inspired neuromorphic computing and nonvolatile logic circuits. Especially, memristor based in-memory computing provides a promising route to break the traditional von Neumann bottleneck and then build novel energy-efficient parallel computing architecture. Based on a functionally complete logic algebra described as:L=AB'C'D'+(A'+B)C'D+A'BCD+(A+B')CD', we proposed a universal logic-in-memory methodology which is applicable to different memristive devices, structures and architectures. Four mathematical variables (A, B, C, D) are assigned to corresponding physical quantities, such as the device initial resistance, voltage potential, voltage polarity. We experimentally verified our method in three cases: one complementary device, one 1T1R structure, and one single bipolar device in crossbar array. Functionally complete 16 binary Boolean logic could be achieved in three steps: logic state initialization, state input and optional read-out. Moreover, reconfigurable Boolean logic operations were executed in 1T1R configuration by inducing the gate-control signal as a variable. In architecture level, logic function could be determined by control signal in crossbar arrays, which means arbitrary logic could be implemented in a general architecture. In short, through adequately exploiting the logic function, in-memory computing could be realized in device, array and architecture level, which may greatly promote the development of memristor based non Von Neumann computation.
8:00 PM - ED2.3.03
Mimicking Synaptic Processing from Ion Gel-Gated IGZO Transistors with Au Trapping Layers
Jaemok Koo 1 , Seunghan Kim 1 , Hojin Lee 2 , Moon Sung Kang 1 Show Abstract
1 Department of Chemical Engineering, Soonsil University, Seoul Korea (the Republic of), 2 School of Electronic Engineering, Soonsil University, Seoul Korea (the Republic of)
We demonstrate synaptic functions from ion gel-gated indium-gallium-zinc-oxide (IGZO) transistors equipped with Au nanoparticles (NPs) trapping layers. The Au NPs layer is placed on top of the IGZO channel and serves as nanosize capacitors near the channel. When a voltage is applied to the gate electrode, electric double layer is formed at ion gel/IGZO interface and induce electrons in the IGZO channel. By controlling the trapping of these electrons into the Au NPs these devices by themselves can serve as non-volatile transistor memories that yield programmed/erased signal margin larger than 103 for more than 103 sec at low operation voltages below 10 V. Such an ion driven signal storing process can be harnessed to mimic the synaptic functions between neurons; the voltage applied to the gate serve as the presynaptic signal, the ions in the ion gel serve as the neurotransmitters, and the channel current between the source and drain electrodes serves as the postsynaptic signal. Because the memory behavior of the devices varies with the size and density of the Au NPs as well as through the applied voltage, the synaptic weight is highly tunable. Using these devices, the basic synaptic behaviors, such as paired-pulse facilitation (PPF) short-term plasticity (STP), and self-tuning behavior are successfully mimicked.
8:00 PM - ED2.3.04
Design of the Insulator-to-Metal Transition Properties in Vanadium Oxides for the Joule-Heating Devices
Jianqiang Lin 1 2 , Sushant Sonde 1 2 , Anil Annadi 1 2 , Changyao Chen 1 , Liliana Stan 1 , Shriram Ramanathan 3 , Narayan Achari 3 , Supratik Guha 1 2 Show Abstract
1 Center for Nanoscale Materials, Argonne National Laboratory, Lemont, Illinois, United States, 2 Institute for Molecular Engineering, University of Chicago, Chicago, Illinois, United States, 3 School of Materials Engineering, Purdue University, West Lafayette, Indiana, United States
The Insulator-to-Metal (IMT) phase transition materials have been recently investigated for the applications for post-CMOS electronic switches and neuromorhpic devices. In these devices, the operating mechanism involves Joule heating through an applied voltage or current. The Joule-heat-induced temperature changes result in abrupt switches in electrical characteristics. In this paper, we use the coupled electrical-thermal model and experiments to discuss the material aspects of the IMT Joule-heating devices, including the impact of the high-state resistivity (ρH), low-state resistivity (ρL) and the ratio of ρH/ρL.
ρH strongly affects the critical voltages at which an insulation-to-metal transition can occur. Our simulations show that ρH reduction allows the device to operate at lower voltages. Simulations also show that the combination of ρH reduction, dimensional scaling, and heat insulation can lead to a sub-200 mV switching in Joule-heating VO2 devices. Our fabricated VO2 devices show good agreement with the model, and achieve 800 mV IMT switching. For ρL, our experiment and simulation both indicate that a series resistance is mandatory to protect the typical VO2 devices from excess heating after insulator-to-metal transition. Otherwise, the VO2 temperature could go up to thousand degree Celsius in simulation, and device breakdown occurs in experiment. In this paper, we show that one can avoid such breakdown by increasing the value of ρL in VO2.
Based on the above two considerations respectively for ρH and ρL, the values of ρH and ρL should be properly engineered in the VO2 growth to achieve low voltage operation and overheat protection. The critical voltage for insulator-to-metal transition can be used as the guide for designing ρH and ρL. With everything else being the same, the critical voltage increases when ρH increases. Consequently, Joule heating in the post-IMT state will increase. To address this problem, one can increase ρL to reduce the post-IMT Joule heating. In this regards, the optimized IMT properties in the Joule-heating VO2 device is the one with a narrow ρH/ρL ratio as opposite to the large ρH/ρL ratio in conventional IMT applications. Our VO2 synthesis experiments show the approach to control the ρH and ρL for it to be used as Joule-heating devices. By varying the oxygen partial pressures during the VO2 growth, one can control the value of ρH and ρL. Following this optimization, we demonstrate a Joule-heating VO2 device with 800 mV switching and a self-heating protection without connecting to external resistors.
Rong Zhao, Singapore University of Technology and Design
Ilya Karpov, Intel Corporation
Barbara De Salvo, Leti, CED-TECH
Luping Shi, Tsinghua University
ED2.4: Electronic Synapse Design and Characterization
Wednesday AM, April 19, 2017
PCC North, 100 Level, Room 126 A
9:00 AM - *ED2.4.01
Electro-Thermal Motion of Ions and Electronic Switching in Transition-Metal-Oxide Memristors
R. Stan Williams 1 Show Abstract
1 , Hewlett Packard Enterprise, Palo Alto, California, United States
Since 2008, research on memristors has become a field in its own right. Thousands of papers have been published in multiple disciplines citing some aspect of the properties of a memristor, and various products are appearing on the market. Here I examine the chemical and physical properties of different types of memristors. I distinguish between passive (or synaptic) memristors that are suitable for nonvolatile memories, and locally active (or neuronic) memristors that can be used to build sinusoidal and chaotic oscillators, amplifiers and spiking neuristors, which are potentially capable of performing brain-like or neuromorphic computation. The electrical behavior of both types of memristors depend on nano-scale physico-chemical processes that we have been analyzing using an array of spectro-microscopic techniques to understand the coupled heat, ionic and electronic transport in these devices. A good understanding of the physical mechanisms involved in resistance switching contributes substantially to the formulation of compact models that are used for circuit simulation and design.
9:30 AM - ED2.4.02
Interplay of Different Synaptic Plasticity Features in Electro-Chemical Metallization Cells
Fabien Alibart 1 , Selina La Barbera 1 2 , Adrien Vincent 3 , Dominique Vuillaume 1 , Damien Querlioz 3 Show Abstract
1 , IEMN-CNRS, Villeneuve d'ascq France, 2 , CEA-LETI, Grenoble France, 3 , C2N, Orsay France
Bio-inspired computing represents today a major challenge at different levels ranging from material science for the design of innovative devices and circuits to computer science for the understanding of the key features required for processing of natural data. In this paper, we propose a detail analysis of resistive switching dynamics in electrochemical metallization cells for synaptic plasticity implementation. We show how filament stability associated to joule effect during switching can be used to emulate key synaptic features such as short term to long term plasticity transition and spike timing dependent plasticity. Furthermore, an interplay between these different synaptic features is demonstrated for object motion detection in a spike-based neuromorphic circuit. System level simulation presents robust learning and promising synaptic operation paving the way to complex bio-inspired computing systems composed of innovative memory devices.
10:15 AM - *ED2.4.03
Neuromorphic Computing Based on Synaptic Device of Bi-Directional Analog Behavior
Huaqiang Wu 1 , Peng Yao 1 , Bin Gao 1 , Ning-Qin Deng 1 , He Qian 1 Show Abstract
1 , Tsinghua University, Beijing China
Transition metal oxides memristor devices exhibit promising potential as the electronic synapse because they have high operation speed while keeping low energy consumption. They are compatible with CMOS fabrication process and can be scaled down remarkably to reach density as high as 1011 synapses per cm2. Such devices usually show analog switching during RESET process but abrupt switching for SET process which is due to the positive feedback of oxygen vacancy generation. This hinders the application of transition metal oxides memristor for neuromorphic computing.
To emulate the synapse performance using memristor, we proposed a new transition metal oxide RRAM structure as TE/CMO/TMO/BE stacks, which has bi-directional stable analog conductance modulation behavior. The TMO layer works as the resistive switching layer and CMO layer serves as the interface modulation layer and oxygen reservoir. We further fabricated a uniform 1K bit 1T1R array to demonstrate a perceptron network to classify patterns experimentally. The 1T1R synapse cell is supposed to improve the bidirectional analog switching performance and the uniformity as the compliance current could be controlled by the transistor’s gate voltage and the sneak path is eliminated by cutting off the conductance. With the optimized operation scheme, the hardware system based on RRAM cells has shown great advantages on speed and energy consumption.
10:45 AM - ED2.4.04
Transition between Short-Term Memory and Long-Term Memory in Artificial Electronic Synapses
Yishu Zhang 1 , Rong Zhao 1 Show Abstract
1 , Singapore University of Technology and Design, Singapore Singapore
Brain-inspired computing has attracted significant attention recently due to its potential superior performance. It is believed that memory in biological brains has two phases: short-term memory (STM) and long-term memory (LTM)1. Usually STM with weak stimulation can hold information within seconds and then forget quickly, and the information in LTM can last for much longer time depending on the stimulation strength. With different stimulations, STM can be transferred to LTM, and vice versa. Developing devices that can emulate such human memory functionalities is important for developing brain-inspired computing system. Recently several researches have been reported on mimicking these two phases of memory, and the transition from STM to LTM has been demonstrated based on memristive switching devices2,3. However, systematic analysis of the programming conditions on the STM and LTM and their transition is still lacking.
In this work, we design iron oxide based memristors to investigate the STM and LTM functionalities. When low frequency and weak intensity stimulation is applied, the devices are able to switch to a metastable low resistance state and then return to the original high resistance state within several seconds, which behaves as a STM. After repeated and frequent stimulation, the low resistance state can be maintained for a longer time, varying from hours to days and even years, which demonstrates the STM to LTM transition process. The stimulation conditions could significantly affect the duration of LTM. By properly designing the stimulation frequency and intensity, the duration of LTM can be modulated and the transition from LTM to STM was achieved. Various characterizations have been conducted to investigate the mechanism, including XPS, XRD and TEM. The experimental results reveal that the combination of metal atom diffusion and spontaneous nanoparticle formation is the possible cause for this behavior4.
1. Bliss, T. V. & Collingridge, G. L. A synaptic model of memory: long-term potentiation in the hippocampus. Nature 361, 31–39 (1993).
2. Chang, T., Jo, S.-H. & Lu, W. Short-term memory to long-term memory transition in a nanoscale memristor. ACS Nano 5, 7669–7676 (2011).
3. Ohno, T. et al. Short-term plasticity and long-term potentiation mimicked in single inorganic synapses. Nat. Mater. 10, 591–595 (2011).
4. Wang, Z. et al. Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing. Nat. Mater. (2016). doi:10.1038/nmat4756
11:00 AM - ED2.4.05
Analog Resistive Switching Emulating Biological Synaptic Behaviors in a Pt/CeO2/Pt Structures
Hyung Jun Kim 1 , Hong Zheng 1 , Paul Yang 1 , Jong-Sung Park 1 , Chi Jung Kang 1 , Tae-Sik Yoon 1 Show Abstract
1 , Myongji University, Yongin Korea (the Republic of)
An artificial synaptic device emulating the functions of biological synapse is one of the most attractive research subjects to overcome the limitations of von-Neumann computing scheme and to realize the neuromorphic systems with benefits of adaptivity as learning and memory features, high energy efficiency in computing, visual image processing, auditory recognition and so on, in complex situations. Until now, the resistive switching-based synaptic devices have been reported with the resistance change in response to applied voltage or current. Most of them employed the digital-type resistance change while the actual biological synapse operates with an analog modulation of synaptic strength. In this study, we report the analog resistive switching characteristics emulating biological synaptic behaviors in a Pt/CeO2/Pt structure, which was deposited as thin film by sputtering process. The resistive switching associates the internal changes in the oxide such as redistribution of oxygen ions (or vacancies) in order to either form the conducting filament, modulate the oxide/electrode interfaces, or alter the defect states, and so on. In this regard, the oxygen ionic conductor would be a good candidate for the switching material. Among various metal-oxide materials, a cerium oxide has a multivalence state of cerium, i.e. Ce3+ and Ce4+, and a good oxygen ionic conductivity associating the redistribution of oxygen vacancies. Thus, the CeO2 is thought to be a promising switching material for digital and analog switching devices. In this study, the Pt/CeO2/Pt structure exhibited the analog resistive switching with reversible and gradual resistance change depending on the polarity of applied voltage. In addition the gradual increase and decrease of resistance by orders of magnitude as repeating voltage pulses emulated the synaptic potentiation and depression motions, respectively, as well as the fair memory retention like biological synapse. These results demonstrate the potential for the application to artificial synaptic devices. In this presentation, the detailed analog resistive switching characteristics of the CeO2 layer as an artificial synapse will be discussed.
This research was supported by Nano×Material Technology Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (NRF-2011-0030228).
11:15 AM - *ED2.4.06
Oscillation Neuron Device Design Considerations
Shimeng Yu 1 , Ligang Gao 1 , Bin Dong 1 , Pai-Yu Chen 1 Show Abstract
1 , Arizona State University, Tempe, Arizona, United States
A radical shift in computing paradigm towards the neuro-inspired computing is attractive for performing data-intensive applications. The neuro-inspired architecture leverages the distributed computing in the neuron nodes and the localized storage in the synaptic elements. The research community used to focus on engineering the emerging resistive memories (RRAM) for implementing the analog synaptic weights in the neural networks. However, limited advances have been achieved on the neuron node design. The neuron node is still generally implemented by tens of CMOS transistors. Compared to the resistive crossbar array, the CMOS neuron is not only power-hungry and area-inefficient, but also causes the column pitch matching problem (multiple columns have to share one neuron, thereby reducing the parallelism of the neuro-inspired architecture). How to design a single device that can efficiently emulate the neuronal behavior (e.g. integrate-and-fire) is critical to the neuromorphic hardware design. Very recently, there are reports on using the threshold switching (with I-V hysteresis) phenomenon in oxides and chalcogenides to function as an oscillation neuron node. Material systems of the interests include the metal-insulator-transition (MIT) phenomenon in strongly correlated oxide materials (VO2, and NbO2), as well as Ovonic threshold switching (OTS) phenomenon in chalcogenide materials (GeTe, and SiTe). When such oscillation device is connected with a series resistor whose resistance is within the on/off dynamic range of the oscillation device, the node voltage between the oscillation device and the resistor will start self-oscillation. In this work, we explore the design space of using such oscillation neuron when it connects to a synaptic array. We propose using this oscillation device to emulate the rectified linear unit (ReLU) activation function of the neuron node. The oscillation frequency is designed to be proportional to the weighted sum current from the array above the threshold, and the input signal time window can tune the threshold of the ReLU. Preliminary results have experimentally shown the self-oscillation in the NbO2 device that can naturally emulate the integrate-and-fire neuronal behavior. In addition, the circuit-level analysis and demonstrate significant improvement in area and energy consumption of the proposed oscillation neuron over the conventional CMOS neuron.
ED2.5: Memristive Device and Its Material Fabrication/Characterization for Brain-Inspired Ccomputing I
Wednesday PM, April 19, 2017
PCC North, 100 Level, Room 126 A
1:30 PM - *ED2.5.01
Memristor-Based Spiking Neuromorphic Networks
Dmitri Strukov 1 Show Abstract
1 , University of California, Santa Barbara, California, United States
Most studies of neuromorphic networks and their hardware implementations have been focused on the firing-rate models, in which neuron spiking activity is represented only by its average rate. However, there is a general consensus that an explicit modeling of spiking activity increases the signal information contents, improves the energy efficiency, and enables coordinated processing of spatial and temporal information. This is especially important in large-scale networks, which may be implemented in hardware based on hybrid CMOS/memristor crossbar circuits. A necessary step in the adaptive spiking network development is an efficient implementation of spike-time-dependent plasticity (STDP), i.e. of the synaptic weight (memristor conductance) change, properly dependent on the time interval between the pre- and post-synaptic spikes.
In my talk I will review recent work on memristor-based spiking neuromorphic networks. I start with the discussion of the recent experimental demonstration of several most biology-plausible STDP windows in integrated metal-oxide memristors and, for the first time, the observed self-adaptive STDP, which may be crucial for spiking neural network applications. I will then discuss recent theoretical work in which an analytical, data-verified STDP model was used to simulate operation of a spiking classifier of spatial-temporal patterns, and the capacity-to-fidelity tradeoff and noise immunity of spiking spatial-temporal associative memories with local and global recording.
2:00 PM - ED2.5.02
Effect of Material Deposition Parameters on the Switching Dynamics of HfO2-Based Memristive Synapses
Stefano Brivio 1 , Jacopo Frascaroli 1 , Erika Covi 1 , Sabina Spiga 1 Show Abstract
1 , Laboratorio MDM, IMM - CNR, Agrate Brianza Italy
Two-terminal memristive devices based on transition metal oxides have been the subject of a renewed interest as functional devices for brain-inspired computing, following their historical mainstream application in the field of non-volatile memories. Their non-volatile resistance variation as a function of electric stimuli can serve as synaptic weight coupling among artificial neurons [1,2]. Oxide-based memristive devices can be highly scaled and integrated in compact structures , and their implementation in neuromorphic circuits can boost performance and promise to greatly reduce the silicon footprint of these circuits. Furthermore, they are capable of the low energy dissipation per operation required for effective computing systems. Several literature reports highlight the importance of the use of memristive devices out of the deterministic binary operation, usually optimized for memory applications . Indeed, either stochastic or multilevel programming can be exploited in specific windows of operation . However, the integration of devices with synaptic functionality poses new challenges in terms of material and structural optimization, and a detailed analysis and understanding at the device level is required in order to satisfy the requirements of low power operation, device yield, and reliable operation with a particular focus on the specific neuromorphic implementation.
In this context, we propose an investigation of the effect of water and ozone oxygen precursors in the ALD deposition of amorphous HfO2 films and of the role of metal/oxide interfaces  in connection with DC and pulsed electrical characterization in filamentary-type memristive devices. We employ electrical characterization to identify the different switching regimes for analog or stochastic programming. Moreover, we find a connection between the variability of resistance values and switching parameters and the device structure. Based on the study of the resistance evolution as a function of the programming mode, we build a compact model which includes the variability for repeated pulses and among devices with the aim of device integration in large networks. Furthermore, we combine material characterization with phenomenological filamentary models  in order to establish a connection between material properties and experimental electrical operation. In conclusion, our analysis provides a guidance about the stability of analog and stochastic switching regimes and the role of fabrication aspects on the device performance for a future integration of memristive devices in neuromorphic computing architectures.
 Covi et al 2015 Microelectron Eng 147 41
 Covi et al 2016 Front Neurosci doi: 10.3389/fnins.2016.00482
 Frascaroli et al 2015 ACS Nano 9 2518
 Garbin et al 2015 NANOARCH
 Brivio et al 2016 Appl Phys Lett 109 133504
 Brivio et al 2015 Appl Phys Lett 107 023504
 Brivio et al 2015 MEMRISYS
2:15 PM - ED2.5.03
MBE Grown Volatile and Non-Volatile Memristors for Neuromorphic Computing
Marshall Tellekamp 1 , Joshua Shank 1 2 , William Doolittle 1 Show Abstract
1 , Georgia Institute of Technology, Atlanta, Georgia, United States, 2 , Sandia National Laboratory, Albuquerque, New Mexico, United States
Memristors are considered a key enabling technology for neuromorphic computing due to their applications as synaptic analogues and signal propagation elements. Current memristor technology focuses on high resistance binary state resistive switches which succeed in basic synaptic weighting processes, but often provide no pathway for more intricate biological mechanisms without complex programming circuitry. Examples of these mechanisms are short and long term potentiation (STP and LTP) effects and spike-timing dependent plasticity (STDP) which are strictly analog processes linked to basic brain functions such as learning and memory. These processes occur on biological timescales from milliseconds to minutes in the case of STP and multiple minutes to months for LTP. In order to recreate these neural functions it is critical that any synaptic enabling technology exhibit plasticity (conductivity modulation), STP (volatility), and LTP (non-volatility) with variable decay constants in realistic time scales. For this reason lithium niobite (not the more common lithium niobate) is explored as an enabling technology to accomplish these biologically realistic goals. LiNbO2 is a lithium intercalated sub-oxide which is difficult to synthesize epitaxially due to the complicated phase space and number of possible competing phases. However, using the stoichiometry control of MBE LiNbO2 can be epitaxially grown using a previously described lithium controlled NbCl5 chemistry. In this growth chemistry lithium getters chlorine from the metal-halide precursor on the hot substrate, controlling the niobium concentration on the substrate surface and therefore the niobium to oxygen ratio. LiNbO2 films are grown at 975 °C on sapphire and cooled under oxygen flow. Devices are fabricated by evaporation and liftoff in isolated concentric ring-dot structures. It is shown that the contact metal choice dramatically affects the device characteristics and can enable both volatile and non-volatile devices. Volatile devices show figure of merit changes of ΔR/R = 20% and decay on the order of 300 ms. Non-volatile devices show varying resistance modulation based on the previous history of the device, applied voltage, and device size. Resistance modification occurs by incremental pulse response and is bipolar emulating both potentiation and depression. Smaller devices show a larger response for the same stimuli with a maximum achieved instantaneous resistance change (2V stimulus) of ΔR/R|2V ~ 1900% and stable value of ΔR/R ~ 500%. Long term potentiation is shown for a non-volatile device which decays linearly at 0.06 % per second, and it is also shown that above a certain threshold non-volatile devices enter a stable higher resistance state. In this way LiNbO2 memristors are shown to span the range of biologically realistic decay times providing a platform for hardware based implementation of important neural pulse response behaviors such as STDP, STP, and LTP.
ED2.6/ED11.8: Joint Session: Devices for Neuromorphic Computation
Wednesday PM, April 19, 2017
PCC North, 100 Level, Room 131 C
3:30 PM - *ED2.6.01/ED11.8.01
The N3XT Technology for Brain-Inspired Computing
S. Burc Eryilmaz 1 , Haitong Li 1 , Weier Wan 1 , H.-S. Philip Wong 1 Show Abstract
1 Department of Electrical Engineering and Stanford SystemX Alliance, Stanford University, Stanford, California, United States
Advances in brain-inspired computing are making rapid progress to meet the demands of abundant-data processing using a variety of techniques, including spiking neural networks, hyperdimensional computing using sparse vectors, deep neural nets, deep belief nets, restricted Boltzmann machines, and their variants. It is therefore crucial to create a scalable and flexible brain-inspired technology platform that can support all the essential elements, and can be adapted for a wide variety of neural computational model.
The key elements of a scalable, fast, and energy-efficient computation platform that may provide another 1,000× in computing performance (energy-execution time product) for future computing workloads are : massive on-chip memory co-located with highly energy-efficient computation, enabled by monolithic 3D integration using ultra-dense and fine-grained massive connectivity. There will be multiple layers of analog and digital memories interleaved with computing logic, sensors, and application-specific devices. We call this technology platform N3XT – Nanoengineered Computing Systems Technology. N3XT will support computing architectures that embrace sparsity, stochasticity, and device variability.
In this talk, I will give an overview of nanoscale memory and logic technologies for implementing N3XT. In particular, I give an overview of the use of nanoscale analog non-volatile memory devices for implementing brain-inspired computing . Phase change memory (PCM) and resistive switching memory (RRAM) are used as examples to illustrate the need to co-design, co-optimize the device technology, circuit design, system architecture, and learning algorithms .
Acknowledgements: Supported in part by Stanford Non-Volatile Memory Technology Research Initiative (NMTRI), Stanford SystemX Alliance, the National Science Foundation (E2CDA, Expedition in Computing), and STARnet SONIC.
 M.M. Sabry Aly, M. Gao, G. Hills, C.-S. Lee, G. Pitner, M.M. Shulaker, T.F. Wu, M. Asheghi, J. Bokor, F. Franchetti, K.E. Goodson, C. Kozyrakis, I. Markov, K. Olukotun, L. Pileggi, E. Pop, J. Rabaey, C. Re, H.-S. P. Wong, S. Mitra, "Energy-Efficient Abundant-Data Computing: The N3XT 1,000X," IEEE Computer, pp. 24 – 33, December 2015
 S. B. Eryilmaz, D. Kuzum, S. Yu, H.-S. P. Wong, “Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures,” invited paper, IEEE International Electron Devices Meeting (IEDM), paper 4.1, pp. 64 – 67, 2015.
 H. Li, T.F. Wu, A. Rahimi. K.-S. Li, M. Rusch, C.-H. Lin, J.-L. Hsu, M.M. Sabry, S.B. Eryilmaz. J. Sohn, W.-C. Chiu, M.-C. Chen, T.-T. Wu, J.-M. Shieh, W.-K. Yeh, J. M. Rabaey, S. Mitra, and H.-S. P. Wong, “Hyperdimensional Computing with 3D VRRAM In-Memory Kernels: Device-Architecture Co-Design for Energy-Efficient, Error-Resilient Language Recognition,” IEEE International Electron Devices Meeting (IEDM), paper 16.1, 2016.
4:00 PM - ED2.6.02/ED11.8.02
Low Voltage Nano-Ionics Based Selector Devices Using Doped HfO2 for Application in 3D Crosspoint Memories
Sushant Sonde 1 2 , Kiran Sasikumar 2 , Yuzi Liu 2 , Jianqiang Lin 2 , Anil Annadi 1 2 , Daniel Rosenmann 2 , Subramanian Sankaranarayanan 2 , Matt Jerry 3 , Nikhil Shukla 3 , Suman Datta 3 , Supratik Guha 1 2 Show Abstract
1 , Institute for Molecular Engineering, University of Chicago, Chicago, Illinois, United States, 2 Center for Nanoscale Materials, Argonne National Laboratory, Lemont, Illinois, United States, 3 , University of Notre Dame, Notre Dame, Indiana, United States
Metal oxides have been explored for applications such as in resistive RAM , electronic synaptic devices for neuromorphic computation  etc. Recently, enhanced nonlinearity in metal oxide stacks was proposed for possible application as selectors in cross-point memory arrays  where they are essential in suppressing sneak leakage currents. Such structures have been studied before from a device performance point of view, with a goal towards low voltage operation . Much, however remains to be understood regarding the underlying materials phenomena and microstructural changes that dictate the operation voltage, the variability and the cycling behavior of these devices.
In this study, we have fabricated and demonstrated low voltage bi-directional selectors using atomic layer deposited HfO2 thin films. The fabricated selectors consist of a cross-bar array with a HfO2 thin film sandwiched between inert (Pt) and electrochemically active (Cu or Ag) electrodes. Filamentary conduction beyond a threshold voltage was verified by varying device areas. It is understood that the switching effect is facilitated by the HfO2 playing the role of a cation conductor for redox active species e. g. Cu+ and Ag+. Through detailed studies of a large set of different samples under different annealing conditions, HfO2 thickness and device structures, we show that it is possible to achieve very low switching voltages of ~0.5 V, tune the hysteresis and ON/OFF ratio, and observe the following key phenomena: (i) the devices can be switched at temperatures down to 20 K, indicating the presence of athermal effects in the field driven microstructural changes; (ii) repeated cycling results in a leaky device that can then be surprisingly restored to initial conditions by driving current through it and (iii) device to device variability is an important issue. We will describe these results and—combined with results from our ongoing molecular dynamic simulations of HfO2:Cu structures, identify the underlying materials phenomena driving these observations related to the cation conduction paths, diffusion mechanism of Cu and Ag in HfO2, time dependent response of the conducting filament to electric field, and lifetime and stability of conduction filaments. We will also describe a simple model for variability for the case of this class of diffusion mediated filamentary breakdown devices, such as threshold switches and resistive random access memory (RRAM) devices that demonstrates that the operating voltage of these devices – related to the energy required to create the resistive state forming “defect” – is inversely proportional to the device to device variability which will fundamentally increase the variability of these devices.
 Sawa, A. Mater. Today 2008, 11, 28–36.
 Yu S. et al., IEEE TED 2011, 58, 2729-2737.
 Alimardani, N., Conley, J.F. Appl. Phys. Lett. 2013, 102, 143501:1–143501:3.
 Luo Q. et al., IEEE IEDM, Washington DC, 2015 253-256.
4:15 PM - ED2.6.03/ED11.8.03
Finite Element Modeling of Ovonic Threshold Switch Controlled Phase Change Memory Devices
Jake Scoggin 1 , Zachary Woods 1 , Helena Silva 1 , Ali Gokirmak 1 Show Abstract
1 , University of Connecticut, Storrs, Connecticut, United States
Phase change memory (PCM) is a high-speed high-density resistive memory technology that utilizes the resistance contrast between amorphous and crystalline phases in phase change materials such as Ge2Sb2Te5 (GST) . PCM can reach 2F2 density when integrated into a crosspoint architecture; however, crosspoint arrays are prone to current sneak paths. Integration of access devices with nonlinear current-voltage characteristics in series with PCM storage elements is therefore necessary for successful crosspoint implementation. Ovonic threshold switches (OTSs)  are promising nonlinear access devices for PCM cells . OTSs utilize the threshold switching phenomenon in chalcogenide materials to limit undesired current in PCM devices. Integration of an OTS into a phase change process flow is relatively simple due to the wide use of chalcogenide materials in phase change devices.
We extend our finite element electrothermal model of phase change materials ,  to model OTSs. We then simulate an OTS as an access device for a crossbar-like PCM cell and analyze the affects of the OTS on PCM operation using COMSOL Multiphysics. Analysis includes read/write waveforms, thermal crosstalk between devices, and energy consumption. We find that an OTS in series with a phase change cell provides stable, repeatable switching, and thermal crosstalk between such OTS-PCM cells is low enough to allow for the maximum 2F2 packing of memory elements in a crosspoint architecture.
 H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, “Phase Change Memory,” Proc. IEEE, vol. 98, no. 12, pp. 2201–2227, 2010.
 R. R. Shanks, “Ovonic threshold switching characteristics,” J. Non. Cryst. Solids, vol. 2, pp. 504–514, 1970.
 DerChang Kau, S. Tang, I. V. Karpov, R. Dodge, B. Klehn, J. A. Kalb, J. Strand, A. Diaz, N. Leung, J. Wu, Sean Lee, T. Langtry, Kuo-wei Chang, C. Papagianni, Jinwook Lee, J. Hirst, S. Erra, E. Flores, N. Righos, H. Castro, and G. Spadini, “A stackable cross point Phase Change Memory,” in 2009 IEEE International Electron Devices Meeting (IEDM), 2009, pp. 1–4.
 A. Faraclas, G. Bakan, H. Adnane, F. Dirisaglik, N. E. Williams, A. Gokirmak, and H. Silva, “Modeling of Thermoelectric Effects in Phase Change Memory Cells,” IEEE Trans. Electron Devices, vol. 61, no. 2, 2014.
 F. Dirisaglik, G. Bakan, A. Faraclas, A. Gokirmak, and H. Silva, “Numerical Modeling of Thermoelectric Thomson Effect in Phase Change Memory Bridge Structures,” Int. J. High Speed Electron. Syst., vol. 23, no. 01n02, p. 1450004, Mar. 2014.
Rong Zhao, Singapore University of Technology and Design
Ilya Karpov, Intel Corporation
Barbara De Salvo, Leti, CED-TECH
Luping Shi, Tsinghua University
ED2.7: Memristive Device and Its Material Fabrication/Characterization for Brain-Inspired Computing II
Barbara De Salvo
R. Stan Williams
Thursday AM, April 20, 2017
PCC North, 100 Level, Room 126 A
8:30 AM - *ED2.7.01
Image Analysis Using Memristor Networks
Wei Lu 1 Show Abstract
1 , University of Michigan, Ann Arbor, Michigan, United States
Memristors crossbar networks have been widely considered as promising candidates for neuromorphic hardware systems due to their ability to both store synaptic weights and process information at the same physical locations, e.g. by performing vector-matrix multiplications naturally in physics. Here I will discuss our approach towards image analysis using memristor networks based on a sparse-coding algorithm. The lateral inhibition among neurons in the network allows the system to settle on a more optimal, sparse solution from many possible solutions. This capability enables the network to identify the hidden features that constitute the input image. Natural images have been successfully reconstructed from learned feature vectors in a fabricated 32x32 memristor array. Effects of device variability during experimental image reconstruction was also analyzed, including device variability during online and offline training, along with device failures including SA0 and SA1. SA1 failure was found to significantly affect image reconstruction results, and a practical approach was developed to mitigate the effects of SA1 failure in memristor crossbars.
9:00 AM - ED2.7.02
Ferroelectric HfO2 for CMOS-Compatible Synaptic Devices
Martin Frank 1 , Takashi Ando 1 , Xiao Sun 1 , Eduard Cartier 1 , John Bruley 1 , Cheng-Wei Cheng 1 , Adam Pyzyna 1 , Adra Carr 2 , Jean Jordan-Sweet 1 , Christian Lavoie 1 , David Muir 3 , Beatriz Moreno 3 , Jin-Ping Han 1 , Vijay Narayanan 1 Show Abstract
1 , IBM T. J. Watson Research Center, Yorktown Heights, New York, United States, 2 , IBM Research, Albany, New York, United States, 3 , Canadian Light Source, Saskatoon, Saskatchewan, Canada
The realization of a synaptic element is of interest for hardware implementation of deep learning networks. Weights are modified and stored by modulating the conductivity of non-volatile memory array elements. Proposals to use the adjustable channel conductance of ferroelectric (FE) field-effect transistors (FET) as a synaptic weight date back to the early 1990s . Significant progress has been made using perovskite ferroelectrics such as Pb(Zr,Ti)O3 , yet implementation on a silicon complementary metal-oxide-semiconductor (CMOS) platform remains challenging due to incompatibilities with CMOS processing. The recent discovery of a previously unknown FE phase of HfO2 (FE-HfO2) [3,4], likely orthorhombic (orth-III) HfO2 with space group Pca21, has the potential to remove the integration challenges of the traditional perovskite-based FE materials. This phase can be stabilized in TiN-HfO2-TiN and TiN-HfO2-Si stacks. Ferroelectric two-terminal (capacitor or resistor) and three-terminal (transistor) devices can thus be built from conventional high-k/metal gate materials used in commercial CMOS logic FETs. This opens up the possibility of implementing a variety of tunable solutions on a CMOS platform. For example, ferroelectric FETs, FE capacitors controlling conventional FET gates, or metal-FE-metal (MFM) ferroelectric tunnel junctions (FTJ)  might be useful as synaptic devices.
Herein, we describe our development of tunable FE-HfO2 materials. First, we optimize FE phase stabilization in MFM with TiN electrodes subjected to CMOS front-end (~1000°C) and back-end (400-450°C) thermal budgets. We achieve this through suitable doping/alloying with cations that raise (e.g. Si, Al) or reduce (e.g. Zr) the HfO2 crystallization temperature . We monitor phase formation and stability in real time via temperature-dependent X-ray diffraction (TD-XRD). High synchrotron photon flux permits fast measurements during anneals at rates up to 60°C/sec, where fast rates are thought to aid FE phase formation.
Basic electrical properties of optimized TiN/FE-HfO2/TiN and TiN/FE-HfO2/Si stacks are evaluated using current-voltage (C-V) and polarization loop (P-E) measurements. We then demonstrate stepwise and reversible pulsed polarization updates down to ~5 ns, e.g. for Al-doped HfO2 (Al:HfO2), using a modified Sawyer-Tower circuit. In synaptic devices, such polarization updates can be used to tune resistance, or alternatively threshold voltage, and thus source-drain current.
 H. Ishiwara, Jpn. J. Appl. Phys. 32, 442 (1993)
 Y. Kaneko et al., IEEE Trans. Electron Devices 81, 2827 (2014)
 T. S. Böscke et al., Appl. Phys. Lett. 99, 102903 (2011)
 M. H. Park et al., Adv. Mater. 27, 1811 (2015)
 A. Chanthbouala et al., Nat. Mater. 11, 860 (2012)
9:15 AM - ED2.7.03
Imaging Dynamic Oxygen Vacancy Behaviour in a Memeristive Device
Huajun Liu 2 3 , Hua Zhou 1 , Yongqi Dong 2 4 , Mathew Cherukara 1 , Kiran Sasikumar 5 , Badri Narayanan 5 , Zhonghou Cai 1 , Barry Lai 1 , Liliana Stan 5 , Seungbum Hong 2 6 , Maria Chan 5 , Subramanian Sankaranarayanan 5 , Dillon Fong 2 Show Abstract
2 Materials Science Division, Argonne National Laboratory, Lemont, Illinois, United States, 3 Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology and Research), Singapore Singapore, 1 X-ray Science Division, Argonne National Laboratory, Lemont, Illinois, United States, 4 National Synchrotron Radiation Laboratory, University of Science and Technology of China, Hefei China, 5 Center for Nanoscale Materials, Argonne National Laboratory, Lemont, Illinois, United States, 6 Department of Materials Science and Engineering, KAIST, Daejeon Korea (the Republic of)
Crystalline defects are essential to materials properties, and understanding how to control them has helped lay the groundwork for much of modern technologies. Although this has been most apparent for silicon-based electronics, the influence of point defects can be far greater in more ionic materials like the transition metal oxides. Here, defects are not merely dopants but can be used to create entirely new functionalities, and their charged nature can lead to the rapid and reversible formation of large-scale defect structures under an applied electric field. In resistive-switching memories, or memristive devices, electrically conducting channels comprised of oxygen vacancies either grow and propagate across the device or dissolve into the insulating matrix, thereby switching the memory state. Although this process is central to the operation of the device, a microscopic picture of how this occurs remains elusive, as oxygen vacancies are not easily imaged especially under working conditions. In this poster, we will present the development of a powerful X-ray technique capable of quantitatively imaging oxygen vacancy profiles in situ, exploiting both chemical and structural contrast mechanisms. Focusing on model heterostructures of WO3-x/SrTiO3(001), we find that memristive behaviour originates from a local phase transition as the oxygen concentration is modulated above and below a threshold stoichiometry, which is quantitatively observed by X-ray imaging and substantiated by ab initio-based simulations. This threshold behaviour is analogous to the threshold potential necessary for signal transmission through synapses in human brain.
The results clearly demonstrate how distinct electrical states can arise from local changes in oxygen stoichiometry and suggest a strategy exploiting the collective behaviour of functional ion defects for the creation of dynamic, field-controlled phases in neuromorphic computing and adaptive electronics.
ED2.8: Neuromorphic Devices, Sensors and Materials I
Thursday AM, April 20, 2017
PCC North, 100 Level, Room 126 A
10:00 AM - *ED2.8.01
Experimental Demonstration of Image Learning in a Memristive Synaptic Network
Giacomo Pedretti 1 , Valerio Milo 1 , Stefano Ambrogio 1 , Daniele Ielmini 1 Show Abstract
1 , Politecnico di Milano, Milano Italy
The progress in computing speed and memory density has made possible artificially-intelligent computing systems, capable to learn tasks such as recognizing patterns, navigating new environments, and even playing videogames. These achievements are however obtained at the cost of complicated software, advanced multicore computers, and a huge power consumption. Low power, inexpensive artificial intelligence requires to overcome the von Neumann paradigm by adopting brain-inspired architectures, such as the neural networks. In this networks, neurons can be realized by the CMOS technology, while resistive (or memristive) switching devices are ideal for synaptic connections providing both communication and reconfigurability, or plasticity. Developing high density neuromorphic systems capable of human-brain functions requires the demonstration of prototypical networks with memristive synapses at both simulation and hardware levels.
This work presents the experimental demonstration of neural networks with memristive synapses capable of online unsupervised learning of image patterns and their classification based on spike-timing dependent plasticity (STDP) as the weight update rule. The synapses consist of hybrid CMOS-memristive circuit blocks with one-transistor/one-resistor (1T1R) structure, where the memristor device has a Ti/HfO2/TiN stack. In the 1T1R synapse, STDP is achieved by the overlap between a positive pre-synaptic spike stimulating the transistor gate and a bipolar post-synaptic spike resulting from the fire event and applied to the top electrode of the memristor. Potentiation and depression are achieved by set and reset transition via nanoscale ion migration in the metal oxide layer. For full-hardware demonstration, 16 synapses were connected to one post-synaptic integrate-and-fire neuron realized in a Arduino microcontroller. Pre-synaptic spikes were also provided by the microcontroller in a stochastic mode, where image patterns and random noise patterns were randomly submitted to the synapses. We provide evidence for potentiation generally taking place in correspondence of fire following the submitted pattern spikes, whereas depression takes place most frequently in correspondence of random noise spikes following a fire event. Time-dependent potentiation/depression allow for self-adaptation of synaptic weights to the submitted image pattern. We demonstrate learning of individual patterns from any arbitrary initial weight configuration, thus capable of on-line change of the synapses during training. Recognition and multiple-pattern learning are also demonstrated. These results provide a robust architecture/technology platform for up-scaled neuromorphic networks capable of unsupervised learning and adaptation with high repeatability and reliability.
10:30 AM - ED2.8.02
Electrical Self-Oscillation in NbOx Film Devices for Neuromorphic Computing
Xinjun Liu 1 , Shuai Li 1 , Sanjoy Nandi 1 , Robert Elliman 1 Show Abstract
1 Department of Electronic Materials Engineering, The Australian National University, Canberra, Australian Capital Territory, Australia
Threshold switching devices and self-sustained electrical oscillators have attracted particular attention due to their potential for the applications as selector elements in emerging non-volatile memory and as building blocks for bio-inspired neuromorphic computing, respectively. Among these, devices based on metal-oxide-metal structures offer the advantage of device simplicity and scalability, and have been used to realize systems of nano-crossbar array memory and coupled nano-oscillators. Niobium dioxide (NbO2) is one of several materials that exhibit reliable threshold switching and associated current-controlled negative differential resistance (CC-NDR). Our previous studies have demonstrated electrical self-oscillation with a frequency of tens of MHz in a Ti/NbOx NDR device with low operation voltages, large frequency control range, and long endurance.
However, the threshold switching mechanism in amorphous NbOx films remains unclear. Recent discussion center around two mechanisms: one based on the thermally-induced insulator-metal transition (IMT) in crystalline t-NbO2; and the other, a purely electronic model, based on the temperature dependence of Poole-Frenkel conduction. Both models assume that switching occurs along a filamentary path created during electroforming and results from a reduction in electrical conductivity with increasing temperature due to local Joule heating. Since the IMT is specific to crystalline NbO2, it has been speculated that a polycrystalline NbO2 zone or filament is created by the electroforming process and that this is responsible for the IMT response. It is interesting to note that the limited number of transition metal oxides that exhibit reliable threshold switching (e.g. TiOx, VOx, and NbOx) also have crystalline phases that exibibit thermally-induced IMTs. Various combined phase structures of NbO, NbO2, and Nb2O5–δ have been proposed to result from electroforming, including structures comprised of a NbO/NbO2 current channel. The threshold switching response will clearly be influenced by such microstructure.
In this work, we experimentally explore voltage-controlled oscillations in NbOx devices with a particular focus on understanding how the frequency and waveform are influenced by circuit parameters. We also report results from a finite element model of the device based on a Joule-heating induced insulator-metal transition. In this case the electroformed device structure is represented by a cylindrical conductive channel (filament) comprised of NbO/NbO2 zones and surrounded by an Nb2O5–δ matrix. The model is shown to reproduce the current-controlled negative differential resistance observed in measured current-voltage curves, and is combined with circuit elements to simulate the waveforms and dynamics of isolated and coupled Pearson–Anson oscillators. Such modeling is shown to provide considerable insight into the relationship between the material response and device and circuit characteristics.
10:45 AM - ED2.8.03
Development of Empirical Charge Transfer Interatomic Potential to Simulate Switching Processes in HfO2-Based Devices
Kiran Sasikumar 1 , Badri Narayanan 1 , Henry Chan 1 , Sushant Sonde 1 , Supratik Guha 1 , Subramanian Sankaranarayanan 1 Show Abstract
1 , Argonne National Laboratory, Lemont, Illinois, United States
Manipulating ionic transport behavior in electrochemical devices is important in emerging technologies for both energy and information processing. Here, it is desirable to control the flow of ionic defects under an applied electric field. It is the ionic transport in such systems that results in memristive switching, devices based of which are candidates for next-generation fast, scalable, non-volatile, low-power memories. HfO2 based memristive switching devices have attracted significant attention of late. Recent experimental studies on an HfO2 thin film sandwiched between inert (Pt) and electrochemically active (Cu) electrodes reveal that the switching effect is facilitated by the oxide film acting as a cation (Cu+) conductor. However, the exact mechanisms of ionic transport and filament formation are lacking. Here, understanding the switching phenomena is important for reducing device variance .
Molecular dynamics (MD) simulations represent a powerful tool to provide a microscopic view into how electrode material and oxide film thickness affect the switching properties and to investigate the atomistic origin of the resistance switching mechanisms at play [2, 3]. The key to a reliable MD simulation is the underlying empirical force field (FF) that describes the interatomic interactions. While robust reactive interatomic potentials have been developed for several metal oxides [4-8], there is no available reactive FF to simulate the resistive switching behavior of Copper-Hafnia interfaces. To address this, we have utilized supervised machine learning technique such as genetic algorithm in conjunction with local optimization such as Simplex to develop the first reactive FF for Cu/Hafnia interface, based on the charge-transfer ionic potential formalism . Our FF is rigorously trained against a first principles based training data set comprising of structure, cohesive energies and elastic properties for the various experimentally observed Hafnia polymorphs, copper oxides, metallic copper and Hafnium. Our model correctly reproduces the various defect (e.g. oxygen vacancy) formation energies as predicted from density functional theory (DFT) calculations. We, subsequently, use the optimized FF parameters to carry out electric field assisted simulations of Cu/Hafnia interfaces and understand the mechanism of field assisted ion transport that lead to formation of metallic filaments.
 J. J. Yang et. al., Nat. Nanotech. 8, 13 (2012).
 N. Onoforio et. al., Nat. Mat. 14, 440-446 (2015).
 N. Onoforio et. al., Nanoscale 8, 14037-14047 (2016).
 F. H. Streitz and J. W. Mintmire, Phys. Rev. B 50 (16), 11996-12003 (1994).
 X. W. Zhou et. al., Phys. Rev. B 69, 035402 (2004).
 M. Matsuui and M. Akaogi, J. Mol. Sim. 6, 239-244 (1991).
 V. Swamy and J. D. Gale, Phys. Rev. B 62, 5406 (2000).
 F. G. Sen et. al., J. Mat. Chem. A 37, 18970-18982 (2015).
11:00 AM - ED2.8.04
Integrated Photonics and Superconducting Electronics for Massively Scaled Neuromorphic Computing
Jeffrey Shainline 1 , Sonia Buckley 1 , Adam McCaughan 1 , Richard Mirin 1 , Sae Woo Nam 1 Show Abstract
1 , National Institute of Standards and Technology, Boulder, Colorado, United States
We present a hybrid semiconductor-superconductor hardware platform for the implementation of neural networks and large-scale neuromorphic computing. The platform combines semiconducting few-photon light-emitting diodes with superconducting-nanowire single-photon detectors to behave as spiking neurons. These processing units are connected via a network of optical waveguides, and variable weights of connection can be implemented using several approaches. The use of light as a signaling mechanism enables massive scaling by overcoming fanout challenges and communication bottlenecks, and the use of superconduting electronics enables massive scaling by providing detection of few-photon signals and extreme power efficiency. The processing units achieve an energy efficiency of 20 aJ per synapse event, an improvement of roughly six orders of magnitude over recent CMOS demonstrations. The proposed processing units can operate at 20 MHz with fully asynchronous activity, light-speed-limited latency, and power densities on the order of 1 mW/cm^2 for neurons with 700 connections operating at full speed at 2K. By leveraging multilayer photonics with low-temperature-deposited waveguides and superconductors with feature sizes > 100 nm, this approach could scale to massive interconnectivity near that of the human brain, and could surpass the brain in speed and efficiency.
11:15 AM - *ED2.8.05
Bio-Inspired Computing Leveraging the Non-Linearity of Magnetic Nano-Oscillators
Julie Grollier 1 Show Abstract
1 , CNRS/Thales, Palaiseau France
The brain displays many features typical of non-linear dynamical networks, such as synchronization or chaotic behaviour. These observations have inspired a whole class of models that harness the power of complex non-linear dynamical networks for computing. In this framework, neurons are modeled as non-linear oscillators, and synapses as the coupling between oscillators. These abstract models are very good at processing waveforms for pattern recognition or at generating precise time sequences useful for robotic motion. However there are very few hardware implementations of these systems, because large numbers of interacting non-linear oscillators are indeed. In this talk, I will explain why coupled magnetic nano-oscillators are very promising for realizing cognitive computing at the nanometer and nanosecond scale. Then, I will present our experimental results. In particular, I will show how we can perform speech recognition using the transient dynamics and the synchronization of a few oscillators.
ED2.9: Neuromorphic Devices, Sensors and Materials II
Thursday PM, April 20, 2017
PCC North, 100 Level, Room 126 A
1:30 PM - *ED2.9.01
Programming Synaptic Devices for Computational Efficiency and Robustness in Neuromorphic Systems
Yuhan Shi 1 , Aansh Malik 1 , Duygu Kuzum 1 Show Abstract
1 , University of California, San Diego, La Jolla, California, United States
The biological brain has capability of learning, recognizing, and processing imprecisely defined data and execute extremely complex computational tasks with incredible computational efficiency. Inspired from biological counterparts, synaptic devices have been developed to enable new computational paradigms inspired from the unique features of the biological brain. The question of how to design and build compact synaptic devices for energy-efficient and robust neuromorphic architecture has been a challenge for industry and academia. Here we will describe desired device characteristics for the synaptic devices and potential programing techniques for system-level robustness and efficiency. Then we will discuss recent advances in phase change memory based synaptic devices focusing on device level improvements and array level neuromorphic computing demonstrations. We will also discuss future directions towards building computational systems with brain-like parallelism, computational efficiency and learning capability.
2:00 PM - ED2.9.02
Light-Sensitive Quantum Dot Memristor with Bi-Directional and Wavelength-Dependent Conductance Control
Fabian Hartmann 1 , Patrick Maier 1 , Mariama Rebello Sousa Dias 2 3 , Monika Emmerling 1 , Christian Schneider 1 , Leonardo Kleber Castelano 2 , Martin Kamp 1 , Gilmar E. Marques 2 , Victor Lopez-Richard 2 , Sven Höfling 1 4 , Lukas Worschech 1 Show Abstract
1 Physikalisches Institut, Technische Physik, Universität Würzburg, Würzburg Germany, 2 Departamento de Fisica, Universidade Federal de São Carlos, Sao Carlos Brazil, 3 Institute for Research in Electronics and Applied Physics, University of Maryland, College Park, Maryland, United States, 4 SUPA, School of Physics and Astronomy, University of St. Andrews, St. Andrews United Kingdom
Passive circuit elements with inherent memory functionality, such as memristors, have opened new perspectives in hardware implementations of brain inspired computing architectures. The memristor theory was first outlined in 1971 by the nonlinear circuit theorist Leon Chua. With their time- and state-dependent resistance, memristors are suitable to emulate synaptic functionalities [3,4] and more complex computing tasks as object detection and classification have recently been reported with memristor networks.
We present the realization of a memristor based on the mature III-V-semiconductor platform and the memristance of the device is controlled by charge localized on site-controlled InAs quantum dots. Interband absorption processes in the quantum dot barrier matrix lead to photo-generated electron-hole-pairs that, depending on the applied bias voltage, charge or discharge the quantum dots and hence decrease or increase the memristance. Wavelength-dependent conductance control is observed by illumination with red and infrared light, which leads to charging via interband and discharging via intraband absorption, respectively. The presented memristor enables optical conductance control and may thus be considered for sensory applications in artificial neural networks as light-sensitive synapses or optically tunable memories.
 L. Chua. IEEE Trans. Circuit Theory 18, 507 (1971).
 D. B. Strukov, G. S. Snider, D. R. Stewart, R. S. Williams, Nature 453, 80 (2008).
 S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, W. Lu, Nano Letters 10, 1297 (2010).
 M. Prezioso, F. Merrikh-Bayat, B. D. Hoskins, K. Likharev, D. B. Strukov, Scientific Reports 6, 21331 (2016).
 M. Prezioso, F. Merrikh-Bayat, B. D. Hoskins, G. C. Adam, K. K. Likharev, D. B. Strukov, Nature 521, 61 (2015).
2:15 PM - ED2.9.04
Mixed Conductor Memristor for Accelerated Neural Net Training
Kevin Brew 1 , Dennis Newns 1 , Seyoung Kim 1 , Wilfried Haensch 1 Show Abstract
1 , IBM, Yorktown Heights, New York, United States
The advent of the Cognitive Computing era has galvanized the research and development of devices and materials for machine learning. Recently, a cross-bar array of Resistive Processing Units (RPU) - analog devices that can locally process and store data in parallel - showed potential for accelerated neural net training . Symmetric switching between resistance states is necessary for RPU operation; however, this requirement is uncharacteristic of conventional non-volatile memory elements (e.g. RRAM, PCM, etc). Thus, it is necessary to develop a new bipolar, non-volatile memristive element, capable of symmetric analog switching.
To accomplish this goal, we propose a solid-state device comprised of lithium ion intercalated mixed conductors: Pt/LixCoO2 (LCO) anode/Li4Ti5O12 (LTO) barrier/ LixCoO2 (LCO) cathode/Pt. In this device structure, we theoretically demonstrate that reversible transfer of lithium between the x = 0.95 (insulating) and x = 0.75 (metallic) metastable phases is possible using a regular solution model. The reversible transfer of Li+ from one LCO film to another induces a disproportionate resistance change in each LCO film, allowing for symmetric modulation of total device resistance. We fabricated LCO films and performed ICPMS elemental analysis of chemically delithiated LCO thin film devices to show the increasing conductivity of LCO as lithium is removed. The volatile memristive properties are electrically observed via voltage pulse and sweep experiments in both spinel (LT-LCO) and layered (HT-LCO) lithium cobalt oxide thin films. Use of an LTO barrier layer and manganese doping LCO helps improve non-volatility and control base level device resistance respectively.