Rinus Lee, GlobalFoundries
Kah-Wee Ang, National University of Singapore
Catherine Dubourdieu, Helmholtz-Zentrum Berlin / Freie Universität Berlin
John Robertson, Cambridge University
Applied Materials, Inc.
EP09.01: Ferroelectric HfO2
Tuesday AM, April 23, 2019
PCC North, 200 Level, Room 224 B
10:30 AM - *EP09.01.01
Steep-Slope Devices with New Operation Mechanisms for Ultra-Low-Power Applications
Qianqian Huang1,Ru Huang1,Huimin Wang1,Yang Zhao1,Cheng Chen1,Yangyuan Wang1
Peking University1Show Abstract
Standby power becomes much more serious than dynamic power with the technology scaling and becomesone critical issue of IC development, particularly for the power constrained applications, such as Internet of things (IoT) and implantable chips which have stringent ultra-low-standby-power requirements. Different from conventional MOSFET, novel device concepts with new operation mechanisms which can achieve ultra-steep subthreshold slope, free from the conventional thermal limitation of subthreshold slope (SS), have attracted immense attention for ultra-low-voltage and ultra-low-power applications. Among all kinds of steep-slope devices, Tunnel FET (TFET) utilizing band-to-band tunneling (BTBT) mechanism and Negative Capacitance FET (NCFET) with ferroelectric (FE) gate are the two of the most promising candidates, with reported demonstrations of their capability of sub-60mV/dec SS at room temperature. However besides the steep SS, the devices need further comprehensive investigation as well as further physical clarification for device design optimization and future circuit applications.
TFET devices with the gated p-i-n structure can theoretically achieve steep SS and ultralow off-state leakage current. However, they face the fundamental low on-current issue due to the relatively low tunneling efficiency. Moreover, it is difficult to obtain high on-current, steep SS and ultralow off-current simultaneously, even adopting narrow bandgap materials. From the perspective of mechanism engineering, a new kind of hybrid operation mechanism of Schottky injection and BTBT is presented, fundamentally addressing the issue of low drive current in conventional TFETs and obtaininghigher on-current and lower SS while maintaining ultralow off-current. The proposed multi-finger-gate Schottky barrier TFET (MFSB-TFET) exhibits superior performance with the steep SS of 29mV/decade and large on-off current ratio of >108. The ON-current is improved by 2.5 decades compared with conventional TFET. In addition, the MFSB-TFET also experimentally demonstrates comprehensive electrical properties enhancement in terms of output behavior, capacitance, delay, gain, noise, variability and reliability, showing its great potential for ultralow-power digital and analog circuits applications.
The other possible solution for sub-60mV/dec SS isNCFET. Integrating the FE layer into the gate stack of conventional FET, the voltage amplification effect induced by the NC of FE can lead to the steeper SS than conventional FET without on-current penalty. However, the FE film usually exhibits hysteretic loops of polarization-voltage, and most NCFETs experimentallydemonstrate the confliction between SS and hysteresis. Besides, the theoretical explanations of NC effect and hysteresis in NCFETs are still controversial. We presentthe first direct experimental observation of NC effect in a standalone FE capacitor, proving that the NC is generated from the dynamic polarization switching instead of steadyswitching of FE. A new dynamic polarization matching condition is derived and provides new understanding of the steep-slope in the NCFETs. In addition, the physical origin of hysteresis behavior in NCFETs is analyzed, theoretically explaining the SS and hysteresis optimization confliction, which indicates a big challenge for logic applications of NCFETs.
Due to the voltage amplification effect of NC, by further integrating NC to TFET, NC-TFET devices are expected to obtain higher on-current and steeper SS without off-current degradation. A novel NC-TFET design with striped gate configuration is proposed and experimentally demonstrated with sub-60mV SS and nearly non-hysteresis behavior. Benefiting from the hybrid modulation of NC effect and junction depleted-modulation effect, the proposed new NC-TFET design shows great potentials for some standby-power constrained applications.
11:00 AM - *EP09.01.02
Negative Capacitance in Ferroelectric Hafnium Oxide
Thomas Mikolajick1,2,Uwe Schroeder1,Michael Hoffmann1,Benjamin Max2,Stefan Slesazeck1
NaMLab1,Technische Universität Dresden2Show Abstract
More than ten years ago, ferroelectric negative capacitance has been proposed  to overcome the basic limitations of the voltage scalability in complementary metal oxide semiconductor circuits (CMOS) imposed by the fact that the subthreshold swing cannot be reduced below 60 mV/dec. However, to realize this proposal it was necessary to overcome the massive issues associated with integrating a ferroelectric into a CMOS process . The first report on ferroelectricity in doped hafnium oxide in 2011  therefore quickly turned this idea into a possibly mass manufactural option for future CMOS scaling. However, although the benefits of voltage amplification achieved by the integration of the ferroelectric into the gate stack can be easily shown using fundamental Landau theory, the possibility of a practical implementation of the effect into CMOS devices is still under discussion in the scientific community. When measuring ferroelectric properties, in general the voltage is forced and therefore the negative capacitance region cannot be observed. Using a series resistor, first indications of negative capacitance could be observed in doped HfO2 . Recently, a pulse measurement technique together with dielectric layer in direct contact to the ferroelectric, finally made it possible to extract the S-shaped curve predicted by Landau theory [5,6]. Already in  the idea of introducing a suitable dielectric capacitor in series has been described and used as the basis for subsequent investigations by many groups. However, an important feature of ferroelectrics, namely domain formation, is often neglected in basic simulation work, where Landau theory is used in a way that implies a single domain state . When introducing domains into the theory, it still seems possible to stabilize the negative capacitance region . However, the metal electrode introduced between the dielectric and the ferroelectric in many experimental demonstrations will be detrimental and limit the stabilization to extremely small devices. Coming from the practical side, encouraging data on hafnium oxide based ferroelectrics integrated into state of the art devices have been shown , but the connection to the basic material work and theory is often missing. In this presentation the authors will give an overview on their own findings of negative capacitance in hafnium oxide and connect these to literature results on fully integrated devices.
 S. Salahuddin and S. Datta, Nano Lett. 8 (2008), pp. 405-410
 C.-U. Pinnow and T. Mikolajick, J. Electrochem. Soc. 151 (2004), pp. K13-K19
 T. S. Böscke et al., Appl. Phys. Lett. 99 (2011), p. 102903
 M. Hoffmann et al., Adv. Funct. Mater. 26 (2016), pp. 8643-8649.
 M. Hoffmann et al., IEDM (2018)
 M. Hoffmann et al. Nature (accepted for publication).
 H. Ota et al., IEDM (2016), pp. 12.4.1-12.4.4.
 M. Hoffmann et al., Nanoscale 10, 23 (2017), pp. 10891-10899
 Z. Krivokapic et al., IEDM (2017), pp. 357-360
11:30 AM - *EP09.01.03
A Ferroelectric Semiconductor Field-Effect Transistor
Purdue University1Show Abstract
A ferroelectric semiconductor field-effect transistor (FeS-FET) was proposed and experimentally demonstrated for the first time. In this novel FeS-FET, a 2D ferroelectric semiconductor α-In2Se3 is used to replace conventional semiconductor as channel. α-In2Se3 is identified due to its proper bandgap, room temperature ferroelectricity, the ability to maintain ferroelectricity down to a few atomic layers and the feasibility for large-area growth. An atomic layer deposited (ALD) Al2O3 passivation method was developed to protect and enhance the performance of the α-In2Se3 FeS-FETs. The fabricated FeS-FETs exhibit high performance with a large memory window, a high on/off ratio over 108, a maximum on-current of 671 μA/μm, high electron field-effect mobility with μFE= 312 cm2/Vs in forward sweep and μFE= 488 cm2/Vs in reverse sweep, and the potential to exceed the existing Fe-FETs for non-volatile memory applications.
EP09.02: 2D Materials
Tuesday PM, April 23, 2019
PCC North, 200 Level, Room 224 B
1:45 PM - *EP09.02.01
Prospects and Challenges of 2D Materials and Devices
Won Jong Yoo1
Sungkyunkwan University1Show Abstract
Two dimensional (2D) materials are being investigated very intensively, some of them holding great promise as emerging semiconducting materials for future nano-electronics, beyond current semiconductor technology which faces hard limitation in performance enhancement due to excessive power dissipation during high frequency operation, while they present ultra-thin body and short channel effect-free state with efficient electrostatic control. These properties enable 2D materials to be very promising candidates that can meet major requirements for high performance memory and logic applications using CMOS and also for electronic and photonic devices operated in emerging future mobile and IoT environment. However, research towards the realization of the 2D materials based CMOS semiconductor devices faces serious challenges which require various innovative technical breakthroughs. In this talk, I would like to firstly address prospects of 2D devices for the future semiconductor applications. Then, I would like to address challenges from the semiconductor device point of view, mainly on crystalline growth of large scale 2D materials, doping of charge carriers into 2D substrates, strong Fermi level pinning from surface defects sensitive material properties, high contact resistance at the interfaces with metal electrodes, and inefficient power dissipation along ultra-thin 2D structures leading to early breakdown.
Acknowledgments: This work was supported by the Global Research Laboratory (GRL) Program (2016K1A1A2912707) and Global Frontier R&D Program (2013M3A6B1078873), both funded by the Ministry of Science, ICT & Future Planning via the National Research Foundation of Korea.
 F. Ahmed et al. “Impact ionization by hot carriers in a black phosphorus field effect transistor” Nature Communications 9, 3414 (2018)
 M. Huang et al. “Highly Oriented Monolayer Graphene Grown on a Cu/Ni (111) Alloy Foil” ACS Nano 12, 6177 (2018)
 C. Kim et al. “Fermi Level Pinning at Electrical Metal Contacts of Monolayer Molybdenum Dichalcogenides” ACS Nano 11, 1588 (2017)
 M. S. Choi et al. “Electrically Driven Reversible Phase Changes in Layered In2Se3 Crystalline Film” Advanced Materials, 29, 1703568 (2017)
 D. Qu et al. “Carrier Type Modulation and Mobility Improvement of Thin MoTe2” Advanced Materials, 29, 1606433 (2017)
 X. Liu et al. “Modulation of Quantum Tunneling via a Vertical Two-Dimensional Black Phosphorus and Molybdenum Disulfide p–n Junction” ACS Nano 11, 9143-9150 (2017)
2:15 PM - *EP09.02.02
Theoretical Exploration of Energy Efficient Spin Transduction and Switching
University of Minnesota1Show Abstract
There is an intense search for materials that enables energy efficient schemes for charge-to-spin conversion and magnetization switching. I will discuss various proposals in relying on topological effects for the realization of efficient charge-to-spin conversion, such as the Rashba Edelstein effect in topological insulator and the intrinsic spin-Hall effect in topological materials. Next, I will discuss the possibility of maganetization switching via voltage controlled magnetization anisotropy, in ultrathin ferromagnetic layers stacks.
2:45 PM - EP09.02.03
STM Investigation of Graphene/Few-Layer Molybdenum Disulfide Memristor Devices
Jesse Thompson1,Tania Roy1,Masa Ishigami1
University of Central Florida1Show Abstract
Nanoscale mechanisms of memristors and electronic synapses fabricated from vertical graphene/MoS2 van der Waals heterostructures remain largely unexplored. We used scanning tunneling microscopy (STM) and spectroscopy (STS) to investigate the electronic properties of these devices at the atomic scale. We were able to resolve the contributions from defects, specifically to the formation of atomic-scale conductive regions during switching events in these devices. We were also able to induce switching through these devices using the STM tip and to tune the performance of memristors and electronic synapses. We will discuss these results along with theoretical calculations.
3:30 PM - *EP09.02.04
2D Semiconductor Electronics—Advances, Challenges and Opportunities
University of California, Berkeley1Show Abstract
Two-dimensional (2-D) semiconductors exhibit excellent device characteristics, as well as novel optical, electrical, and optoelectronic characteristics. In this talk, I will present our recent advancements in defect passivation, contact engineering, surface charge transfer doping, ultrashort transistors, and heterostructure devices of layered chalcogenides. We have developed a defect passivation technique that allows for observation of near-unity photoluminescence quantum yield in monolayer MoS2. The work presents the first demonstration of an optoelectronically perfect monolayer. Forming Ohmic contacts for both electrons and holes is necessary in order to exploit the performance limits of enabled devices while shedding light on the intrinsic properties of a material system. In this regard, we have developed different strategies, including the use of surface charge transfer doping at the contacts to thin down the Schottky barriers, thereby, enabling efficient injection of electrons or holes. We have been able to show high performance n- and p-FETs with various 2D materials, including the demonstration of a FET with 1nm physical gate length exhibiting near ideal switching characteristics. Additionally, I will discuss the use of layered chalcogenides for various heterostructure device applications, exploiting charge transfer at the van der Waals heterointerfaces.
4:00 PM - *EP09.02.05
Contact Engineering for 2D Field-Effect Transistors
Po-Wen Chiu1,2,Chun-Hao Chu1,Chao-Hui Yeh1
National Tsing Hua University1,Academia Sinica2Show Abstract
Moving beyond the limits of silicon transistors requires both a high-performance channel and high-quality electrical contacts. The type of barrier at a metal/TMD junction is one of the key issues in TMD field-effect transistors (FETs). It is important to design contacts such that the transmission is dictated by intrinsic properties of the TMD channel rather than by details of the contacts. In this work, we report a systematic study of metal/TMD contacts, with monolayer channel materials WSe2 and MoS2 grown by chemical vapor deposition. We show how the contact barrier can be modulated by the work function of contact metals, defects, and contact geometry on “clean” surface of TMD. The Fermi level pinning can be effectively mitigated or eliminated through the proper contact engineering. The end-bonded contact, formed through the reaction of transition metals with the TMD channel, exhibited no Schottky barrier and holds great promise for high-performance TMD FETs, enabling future ultimately scaled device technologies.
4:30 PM - EP09.02.06
Reducing Contact Resistances, Unpinning Femi Levels and Understanding Schottky Barriers
John Robertson2,Yuzheng Guo1
Swansea University1,Cambridge University2Show Abstract
A major factor limiting the performance of devices is their contact resistances which depend on Schottky barrier heights (SBHs). Fermi level pinning (FLP) by a high density of states in the semiconductor band gap generally limits the ability to vary the contact work function to minimize the SBH. Recently, it was found that contacts with Bi or Sb between the main contact metal and Si  would be less strongly pinned than those with direct contact to Si. To understand the cause of this effect, the SBH of metals on Sb were calculated by DFT. It was found that the low density of states at EF allows a SB pinning factor S of 0.2 - 0.4, depending on Sb thickness. This suggests that the SBH follows the MIGS /Cowley-Sze  model where only the density of states at EF matters. On the other hand, the SBHs of silicides on Si are easier to interpret in terms of the polarization of interfacial bonds (‘Tung model ’). This indicates how the control of Schottky barriers, critical to one of the simplest limits to device performance, are still not well understood.
 T Nishimura et al, SSDM K1-05 (2017)
 A M Cowley, S Sze, J App Phys 36 4212 (1965)
 R T Tung, App Phys Rev 1 011304 (2014)
 H Li, Y Guo, J Robertson, Sci Rep 7 16669 (2017)
EP09.03: Poster Session: Devices and Materials to Extend the CMOS Roadmap for Logic and Memory Applications
Tuesday PM, April 23, 2019
PCC North, 300 Level, Exhibit Hall C-E
5:00 PM - EP09.03.01
MEMS Process and Characterization for Strain-Engineered 2D Materials
Edgar Acosta1,Mariana Martinez1,Aldo Vidaña1,Sergio Almeida2,Jose Mireles3,David Zubia1
University of Texas at El Paso1,University of California, Berkeley2,Universidad Autónoma de Ciudad Juárez3Show Abstract
In recent years, an incredible increase in the number of transistors per chip has been observed, which has led to an increasing demand for more power efficient electronics. Additionally, recent studies of two layered materials such as graphene and some transition-metal dichalcogenides (TMDs) have shown strong potential for future use in electronics. One useful property of TMDs is that their electrical and optical properties are highly sensitive to strain. Furthermore, Micro-Electro-Mechanical System (MEMS) can be designed to provide a high level of stress. A low-power switch was recently proposed using a MEMS actuator to strain a MoS2 bilayer with switching energies as low as E = 1.0733 aJ .
In this work, we present the design and fabrication process of a MEMS-TMD switch designed to provide strain up to 6%. A comb-drive architecture is used for the MEMS actuator. A fabrication process for the MEMS is developed using SiGe technology. Finally, a process to transfer and clamp the TMD onto the MEMS is presented.
A. Vidana et al., (2018) "Conductivity Modulation in Strained Transition-Metal-Dichalcogenides via Micro-Electro-Mechanical Actuation", Manuscript submitted for publication.
5:00 PM - EP09.03.02
Application-Driven Perovskite Thin Films with Oxygen Vacancies Controlled
Pratheek Gopalakrishnan1,Nikoleta Theodoropoulou2,Ethan Ahn1
The University of Texas at San Antonio1,Texas State University2Show Abstract
Crystalline metal-oxide thin films are an attractive group of materials for a wide variety of device applications. Among these, the perovskite family of complex oxides have experienced extensive research and development efforts due to their unique multifunctional properties. Despite numerous advances in the field, it is still a challenging task to create a high-quality epitaxial heterostructure on silicon where the intrinsic properties and functionalities of the perovskite oxides are preserved. Additionally, the practical, application-driven methodology to best tune their properties remain relatively unexplored. In this work, these two challenges are addressed by adopting an advanced oxide-MBE technique and controlling the amount or density of the oxygen vacancies, respectively. The flagship perovskite oxide, STO (SrTiO3),was grown directly on top of silicon in an oxide-MBE chamber by co-deposition of Sr, Ti, and molecular O2, and our preliminary analysis indicates that formation of an amorphous SiO2layer at the interface was well suppressed (ensuring the epitaxy) and oxygen deficiencies (defects) were created inside the STO layer (ensuring tunability). Thetwo-step annealing process was applied to control both the crystallinity and oxygen vacancy of the 8.6 nm-thick perovskite thin film. Based on the structural and electrical testing results on the STO/Si heterostructure thin films prepared by oxide-MBE, we propose that STO has great potential to advance the next-generation memory and storage device applications. Its ultra-high dielectric constant (100 to 300) that can be accomplished by eliminating the oxygen vacancies inside the STO layer can significantly improve the EOT for the purpose of developing a high-capacity DRAM. The hysteretic resistance change in the very low operating current regime (a few to a few hundred amperes) suggests that the STO thin film can also contribute to the development of low-power memristor devices.
5:00 PM - EP09.03.03
Single- and Double-Gate Synaptic Transistor with a TaOx Gate Insulator and an IGZO Semiconductor Channel Layer
Keonwon Beom1,Paul Yang1,Daehoon Park1,Minju Kim1,Sunki Kim1,Hyung Jun Kim1,Chi Jung Kang1,Tae-Sik Yoon1
Myongji University1Show Abstract
To develop brain-inspired neuromorphic computing systems, the artificial synaptic devices were investigated using synaptic transistors with single- and double-gate thin-film transistor (TFT) structures. Distinguishable from a two-terminal memristor-synapse, the synaptic transistor enables the synaptic weight to be tuned and then updated by gate biasing during signal processing by drain biasing at the same time. In this study, we demonstrated various synaptic motions with single- and double-gate TFT consisting of an oxygen-deficient TaOx gate insulator and an indium-gallium-zinc oxide (IGZO) semiconductor channel layer, i.e., an Al-top-gate/SiOx/TaOx/n-IGZO on a SiO2/n+-Si-bottom-gate substrate through concurrent changes in gate oxide capacitance, channel mobility, and threshold voltage. This synaptic TFT exhibited the tunable drain current, corresponding to synaptic weight modulation in biological synapse, upon repeatedly applying gate and drain voltages. The drain current modulation features to be analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (~104), as a consequence of the changes in mobility of IGZO channel and gate oxide capacitance, and threshold voltage. The drain current modulation responsive to timing of voltage application emulates synaptic potentiation, depression, paired-pulse facilitation, and memory transition behaviors depending on the voltage pulse amplitude, width, repetition number, and interval between pulses. The synaptic motions could be realized also by double-gate operation that separately tuned the drain current by top-gate biasing and sensing it by bottom-gate biasing. It provided the modulated synaptic weight with wide level of synaptic weight with respect to read condition using bottom-gate stack without read-disturbance. It demonstrated an operation scheme that the signal processing can be performed using the bottom-gate biasing during simultaneous updating of synaptic weight with the top-gate biasing. In addition to the application of this synaptic TFT to artificial synapse for neuromorphic system, its analog, reversible, and nonvolatile changes in drain current as a result of gate biasing can be applied to the operation for nonvolatile memory and field-programmable logic devices.
5:00 PM - EP09.03.04
Multiscale Modeling Framework for 2D-Material MOS Transistors
Madhuchhanda Brahma1,Santanu Mahapatra1
Indian Institute of Science, Bangalore1Show Abstract
Atomically thin 2D materials have ushered in a new era in the field of materials science and has been translated to notable advancements in the design of sensors, optoelectronic devices, flexible electronics . These atomically thin materials are predicted to replace conventional bulk materials, Si and Ge, for transistor channels and extend the complementary metal oxide semiconductor technology road-map beyond the ultimate scaling limit . Constant efforts are being made to synthesize devices based on some of the recently discovered van der Waal's materials such as graphene, hexagonal boron nitride, MoS2, phosphorene [3,4,5]. Density functional theory (DFT) calculations have suggested a large number of 2D materials and their derivatives for device applications . In order to narrow down the material and design selection space for time- and cost-heavy experimental device fabrication, atomic level DFT calculations need to be coupled with device-level physics models. Thus, starting from first principles DFT calculations, we propose a multiscale computational framework to extract important electronic parameters, such as effective mass, band gap, real and complex band dispersion, and phonon spectrum, which are then used to construct the material Hamiltonian. A self-consistent solution of the Schrodinger and the Poisson's equations through the non-equilibrium Green’s function approach  is then obtained to describe the complex, spatially heterogeneous intrinsic carrier transport and resulting device performance in both ballistic and dissipative regimes. Modeling studies on three devices: (i) monolayer germanane metal oxide semiconductor field effect transistors (MOSFETs), (ii) monolayer GeSe based tunneling field effect transistor (TFET), and (iii) phosphorene based MOSFET and TFET, will be presented and their design and performance limits will be evaluated to guide future material selection and device fabrication.
 S. Das, R. Gulotty, A. V. Sumant, and A. Roelofs "All two-dimensional, flexible, transparent, and thinnest thin film transistor.", Nano Lett., vol. 14, no. 5, pp: 2861-2866, 2014.
 S. Thiele, W. Kinberger, R. Granzner, G. Fiori and F.Schwierz "The prospects of transition metal dichalcogenides for ultimately scaled CMOS." Solid State Electron., vol. 143, pp: 2-9, 2018.
 C. R. Dean, A. F. Young, I. Meric, C. Lee, L. Wang, S. Sorgenfrei, K. Watanabe, T. Taniguchi, P. Kim, K. L. Shepard and J. Hone "Boron nitride substrates for high-quality graphene electronics." Nat. Nanotechnol., vol. 5, no. 10, pp: 722-726, 2010.
 B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti and A. Kis "Single-layer MoS 2 transistors." Nat. Nanotechnol., vol. 6., no. 3, pp: 147-150, 2011.
 L. Li, Y. Yu, G. J. Ye, Q. Ge, X. Ou, H. Wu, D. Feng, X. H. Chen and Y. Zhang "Black phosphorus field-effect transistors." Nat. Nanotechnol., vol. 9, no. 5, pp: 372-377, 2014.
 N. Mounet, M. Gibertini, P. Schwaller, D. Campi, A. Merkys, A. Marrazzo, T. Sohier, I. E. Castelli, A. Cepellotti, G. Pizzi and N. Marzari "Two-dimensional materials from high-throughput computational exfoliation of experimentally known compounds." Nat. Nanotechnol., vol. 13, no. 3, pp: 246-252, 2018.
 S. Datta " Quantum transport: atom to transistor". Cambridge university press, 2005.
5:00 PM - EP09.03.05
Suppression of Defects at High-K/SiGe Interface with Monolayer Si ALD Deposition
Harshil Kashyap1,Mahmut Kavrik1,Victor Wang1,Andrew Kummel1
University of California, San Diego1Show Abstract
High mobility SiGe is promising for p channels in CMOS. Successful integration of SiGe into CMOS necessitate low defect SiGe/gate oxide interfaces for practical device operation. The existence of Ge on SiGe surface is problematic as it forms GeOx during gate oxide deposition and induces defects at the interface. Selective oxidation of Si is challenging especially during ALD deposition at elevated temperatures. In this study, a novel method to form low defect interface is demonstrated to deposit monolayers of Si on SiGe with plasma assisted ALD. In this method, HF cleaned SiGe wafer is subjected to 2 super cycles of SiCl4(g) and Ar/H2 downstream plasma at high temperature (350C). Hydrogen atoms from the Ar/H2 plasma interact with SiClx(s) on the SiGe producing Si(s) and HCl(s). HCl desorbs from the surface at high temperature and is purged out. This leaves behind one monolayer of Si(S). This step is followed by N2/H2 downstream plasma to help passivate the interface. The downstream plasma operates at high pressure (> 1 torr) which ensures negligible ions flux thereby preventing ion induced defect formation. It is hypothesize that N2/H2 downstream plasma results in Si-N, Si-H, and N-H bond formation and SixNy prevents outdiffusion of Ge while Si-H and N-H forms a good nucleation layer for subsequent gate oxide ALD. Experiments with Al2O3, HfO2 and ZrO2 ALD gate oxide deposition after this Si monolayer deposition and N2/H2 downstream plasma passivation show up to 50% decrease in interface defect density; for example with approximate 5 nm ZrO2 gate oxide deposition, the Dit = 1.0 x 1012 eV-1cm-2 compared to samples with monolayer of Si (~ Dit = 1.9 x 1012 eV-1cm-2) and compared to samples with just HF treatment (~Dit: 3.6 x 1012 eV-1cm-2).
5:00 PM - EP09.03.06
Development of a Hierarchical Process for Optimization of the Design for MEMS Vibrating Ring Gyroscope for Miniaturized Space Attitude Control System
Daniel Choi1,Ibrahim Elfadel1,Muneera Al Shaibah1,Wajih Syed1
Khalifa University of Science and Technology1Show Abstract
Micro-electromechaical systems (MEMS) inertial sensors are expected to enable so many emerging military and commercial applications that they are becoming too numerous to list. MEMS is probably the most exciting new inertial sensor technology ever and development is a worldwide effort. Apart from size reduction, MEMS technology offers many benefits such as batch production and cost reduction, power (voltage) reduction, ruggedness, and design flexibility, within limits. However, the reduction in size of the sensing elements creates challenges for attaining good performance. In general, as size decreases, then sensitivity (scale factor) decreases, noise increases, and driving force decreases. Currently, the performance of MEMS IMUs continues to be limited by gyro performance, which is now around 5-30°/h, rather than by accelerometer performance, which has demonstrated tens of μg or better.
In this study, we develop an innovative, affordable, miniature, low-power, navigation-grade integrated gyroscope for the attitude control system that applies MEMS technology to achieve the performance, size, power, sensitivity, and cost objectives of space and other commercial applications.
We have been using MEMS+ to simulate and settle on the VRG design of choice. We iterated the design choices manually. MEMS+ does allow parameterization of some geometric properties, but it does not allow varying number of components and their order on the fly using a script. We developed to create a model construction and simulation script that would encode the design in a hierarchical data structure and use this structure to execute model construction, model simulation and analysis, and layout creation tasks in a hierarchical manner.
5:00 PM - EP09.03.07
Influence of Intermixing on Perpendicular Magnetic Anisotropy of Ion-Beam-Deposited CoFeB
MTJs for STT-RAM
Tania Henry1,Narasimhan Srinivasan1,Katrina Pietruski1,Vincent Ip1,Frank Cerio1
Veeco Instruments Inc1Show Abstract
The interface of CoFeB with MgO that forms a Magnetic Tunnel Junction (MTJ) is a critical element of Perpendicular Magnetic Anisotropy (PMA) in STT-RAM devices. The TMR and RA product, which is a key figure of merit for these devices, is very sensitive to the quality of this interface. Intermixing and wettability of the CoFeB on MgO are two critical parameters that are of interest in evaluating this interface. In this work we report the fabrication of MTJ stacks and characterization of this interface. Ion Beam Sputtering (IBS), a very low rate deposition process in which one can control both energy and angle of deposition, is used to fabricate these MTJ structures. We probe intermixing by estimating the magnetic dead layer (MDL) of a stack using magnetic measurements and report a MDL of 0.2 nm after annealing the MTJ stacks at a temperature greater than 300 °C. We also report the impact of some key IBS process parameters on the value of MDL.
5:00 PM - EP09.03.08
Role of Hypochlorous Acid in Solution-Processed P-Type Oxide Thin-Film Transistors for Oxide Semiconductor-Based CMOS Logic
Jusung Chung1,Tae Soo Jung1,Heesoo Lee1,Hee Jun Kim1,Jin Hyeok Lee1,Hyun Jae Kim1
Yonsei University1Show Abstract
Amorphous oxide semiconductor thin-film transistors (TFTs) have achieved enough technological advances to be applied to mass-produced display products. However, the technological development of the oxide TFTs is limited to n-type, and only a few researches on p-type oxide TFTs have been reported due to the lack of p-type oxide materials and rigorous fabrication conditions. Furthermore, since p-type oxides have many localized states near the valence band maximum, it makes control of the amount of metal vacancy, which is the origin of the hole carrier, difficult.1 Due to the above issues, researches on p-type oxide TFTs have become increasingly challenging. Nevertheless, researches on p-type oxide TFTs are essential due to a demand on all oxide semiconductor-based complementary metal oxide semiconductor (CMOS) logic circuits.
Herein, we propose a simple method to enhance the switching characteristic of the p-type copper oxide (CuOx) TFTs via the oxidation effect of hypochlorous acid (HClO). HClO is a relatively inexpensive material to manufacture by reacting chlorine gas with water, and a useful oxidant because of generating oxygen radical (O*), one of the strong reactive oxygen species with heat or light conditions.2 Because of this radical-generating property, HClO is widely used in the fields of sterilization, disinfection, and bleaching in industry. In this study, the HClO treatment was carried out to optimize the hole carrier concentration through the suppression of the copper vacancy (VCu) in the CuOx thin film. Also, we investigated the effects of O* on the CuOx thin film generated from HClO, and the variations of chemical composition were verified by chemical analysis. Through the robust oxidation by HClO, the amount of Cu-O bonds increased and the amount of VCu acting as the origin of hole carriers decreased within the CuOx. In the modified CuOx TFT, the superior switching characteristic was achieved with the subthreshold swing of 0.70 V/dec., the on/off current ratio of 4.86 x 104, and the field-effect mobility of 2.83 x 10-3 cm2/Vs, while pristine CuOx TFT did not show switching characteristic.
 O. Porat and I. Riess, Solid State Ionics 81, 29-41 (1955).
 J. Fan, H. Mu, H. Zhu, J. Du, N. Jiang, J. Wang, and X. Peng, Industrial & Engineering Chemistry Research 54, 8842-8846 (2015).
5:00 PM - EP09.03.09
Ge2Se3/Ge2Se3-M (M = Sn, Al, Ti, W, Cr, Pb, Cu, C)-Based Optically-Gated Transistor—M Influence on Optical and Electrical Properties
Md Faisal Kabir1,Randall Bassine1,Kristy Campbell1
Boise State University1Show Abstract
Electronic devices made with alternating layers of undoped and doped chalcogenide materials, Ge2Se3/Ge2Se3-M (M = Sn, Al, Ti, W, Cr, Pb, Cu, C) exhibit transistor-like current-voltage (I-V) curves when illuminated. These devices, referred to as optically-gated transistors (OGTs), have two electrodes: a source and drain. Current is measured between the source and drain electrodes when the chalcogenide material (which acts as a ‘gate’) is illuminated. In this work, the effect of the metal dopant on the transistor characteristics are measured. The transistor materials are characterized using UV-Vis to explore the band gap and electronic structure. Raman spectroscopy is used to verify incorporation of M into the Ge2Se3 material. Photoconduction is investigated using electrical characterization as a function of wavelength, light intensity, and temperature. The devices were tested from 385 to 1260 nm and were operational over that entire range.
The metal dopant is shown to clearly influence the transistor optical responsivity, maximum current, threshold voltage, electrical switching speed, and optical band gap. A transistor fabricated with M = Al is demonstrated in three applications: as an access transistor to a memristor memory element for cross point array element isolation; as an optical amplifier; and in an optical wavelength converter circuit.
5:00 PM - EP09.03.10
MoTe2 p-n Junction Formed via Edge Contact and Oxidation
Changsik Kim1,Won Jong Yoo1
Sungkyunkwan University1Show Abstract
MoTe2 is a promising two dimensional material due to phase transition and ambipolar transport with a band gap of 1.0 eV. But MoTe2 is sensitive to environment and easy to oxidize. Here, we demonstrated one-dimensional edge contact to MoTe2 covered with h-BN passivation layer and etched by SF6/O2 plasma. The Schottky barrier height of edge contact is found to be 0.01-0.03 eV for various metals (titanium, chromium and palladium). Additionally, MoTe2 edge contact with h-BN passivation shows good stability under ambient environment and oxygen plasma. But MoTe2 without h-BN passivation layer is oxidized and changed to strong p-type. Based on the n-type characteristics from edge contact and p-type characteristics from oxidization, we were able to fabricate MoTe2 p-n junction with a rectifying ratio of 104.
 S. Cho, S. Kim, J. H. Kim, J. Zhao, J. Seok, D. H. Keum, J. Baik, D.-H. Choe, K. J. Chang, K. Suenaga, S. W. Kim, Y. H. Lee, H. Yang, Science (80-. ). 2015, 349, 625.
 B. Chen, H. Sahin, A. Suslu, L. Ding, M. I. Bertoni, F. M. Peeters, S. Tongay, ACS Nano 2015, 9, 5326.
This work was supported by the Global Frontier R&D Program (2013M3A6B1078873) at the Center for Hybrid Interface Materials (HIM), both funded by the Ministry of Science, ICT & Future Planning via the National Research Foundation of Korea (NRF).
5:00 PM - EP09.03.11
Nonvolatile Capacitance Changes in Metal-Oxide-Semiconductor Device with Resistive Switching Floating-Gate Structure for Nonvolatile Memory and Programmable Logic Device Application
Minju Kim1,Daehoon Park1,Keonwon Beom1,Paul Yang1,Sunki Kim1,Hyung Jun Kim1,Tae-Sik Yoon1
Myongji University1Show Abstract
Nonvolatile capacitance changes in metal-oxide-semiconductor (MOS) device with floating-gate structure by resistive switching through filament formation were investigated for the application to nonvolatile memory and programmable logic devices. In general, the electrical charging of the floating-gate located inside the gate oxide has been utilized to shift the threshold voltage for nonvolatile memory and programmable logic devices. However, the approach to use the threshold voltage shift by electrical charging has faced difficulties in further scaling due to undesirable cell-to-cell crosstalk. Instead of using the electrical charging of floating-gate, the device performance such as drain current, threshold voltage, and transconductance can be altered by changing the capacitance of gate oxide. In this study, we demonstrated the change of gate oxide capacitance in MOS device with floating-gate structure, i.e., an Ag-control-gate/CeO2/Pt-floating-gate/HfO2/n-Si substrate, where the formation of conducting filament in Ag-control-gate/CeO2/Pt-floating-gate stack by voltage application increased the gate oxide capacitance as reducing the effective oxide thickness. For example, the accumulation capacitance corresponding to the serial capacitance of CeO2 and HfO2 was increased considerably from ~40 pF before applying positive programming voltage in Ag-control-gate to ~55 pF after applying the voltage while preserving the typical shape of capacitance-voltage curve. The increase of capacitance was induced by the voltage-driven migration of Ag ions through CeO2 layer, leading to the formation of filament between Ag-control-gate and Pt-floating-gate and subsequent reduction of effective thickness of gate oxide. In contrast, the reference device with a structure of an Al-control-gate/CeO2/Pt-floating-gate/HfO2/n-Si did not exhibit the increase of capacitance because Al atoms did not migrate through CeO2 layer. Rather, it showed little decreased capacitance as increasing voltage possibly due to the migration of oxygen ions from CeO2 to Al-control-gate that reduced the relative permittivity of CeO2. Since the gate oxide capacitance could be changed by programming voltage applied to control-gate, which subsequently changes the threshold voltage and drain current, it could be applied for nonvolatile memory and programmable logic devices without the use of electrical charging in floating-gate. These results demonstrated the novel scheme of memory and logic device operations through the change of gate oxide capacitance through resistive switching by filament formation in floating-gate MOS device structure.
5:00 PM - EP09.03.14
Influence of the Type of Chalcogen (Ch) Atom on the Electrical Properties of a Ge2Se3/Sn-Ch Memristive Device
Pradeep Kumar Kumaravadivel1,Kristy Campbell1
Boise State University1Show Abstract
In this work, self-directed channel (SDC) memristor devices  with a Sn-Ch layer (Ch = O, S, or Se) were fabricated and electrically characterized in order to determine the role of the chalcogen atom in the Sn-Ch layer on the memristor properties. The SDC device structure is a sandwich structure consisting of the following layers (from bottom to top electrode): W/Ge40Se60/Sn-Ch//Ge40Se60/Ag//Ge40Se60/W. The device is fabricated by depositing all layers via in-situ sputtering. The final W electrode layer effectively caps the device.
Current-voltage (I-V) curves of the devices were obtained. The I-V curves were analyzed to study the conduction mechanisms of each device type. This includes the analysis of Schottky emission, Space-charge limited Conduction , and Poole-Frenkel emission . In addition, the first and second write threshold voltage of these devices are compared. The response of each device type to a sinusoidal input signal was also measured and used to classify the memristor type .
 K.A. Campbell, Microelectronics J. 59, 10 (2017).
 H. Sun, Q. Liu, S. Long, H. Lv, W. Banerjee, and M. Liu, J. Appl. Phys. 116, 1 (2014).
 J. Frenkel, Phys. Rev. 54, 647 (1938).
 L. Chua, Semicond. Sci. Technol. 29, 104001 (2014),
5:00 PM - EP09.03.15
Enhancement of Electrical Properties for Black Phosphorus Using the via Contacts Embedded in h-BN
Myeongjin Lee1,Won Jong Yoo1
Sungkyunkwan University1Show Abstract
Black phosphorus (BP), one of the allotropes of phosphorus, is a promising candidate for future nano-electronics and nano-photoelectronics. Unlike conventional two dimensional semiconducting materials which show n-type property and high electron mobility, BP shows p-type property and high hole mobility . However, BP faces limitations in application to future electrical devices since BP is easily degraded in air atmosphere, and therefore studies to prevent BP from being oxidized in air atmosphere are required. Here, we suggested a via method for suppressing degradation of BP, which uses metal embedded hexagonal boron nitride (hBN) on BP. The fabricated devices showed good electrical properties because of the suppression of degradation of BP. The devices also showed low contact resistance since ultra clean surface between metal and BP was formed. Furthermore, through the applying force on contact between metal and BP by atomic force microscopy (AFM) probes, the performance of the devices were increased because contact between metal BP become better.
 Likai Li, Yijun Yu, Guo Jun Ye, Qingqin Ge, Xuedong Ou, Hua Wu, Donglai Feng, Xian Hui Chen, and Yuanbo Zhang, Black phosphorus field-effect transistors, Nature Nanotechnology, 9, 372-377, 2014
This work was supported by the Global Research Laboratory (GRL) Program (2016K1A1A2912707) and Global Frontier R&D Program (2013M3A6B1078873), both funded by the Ministry of Science, ICT&Future Planning via the National Research Foundation of Korea (NRF).
5:00 PM - EP09.03.16
Giant Electroresistance Effect in Single-Crystalline Lithium Niobate Thin Films Enabled by Domain Wall Control
Haidong Lu1,J.P.V. McConville2,P. Chaudhary1,A. Lipatov3,Alexander Sinitskii3,Ursel Bangert4,Michele Conroy4,Kalani Moore4,Alexei Gruverman1,Marty Gregg2
University of Nebraska–Lincoln1,Queen’s University Belfast2,University of Nebraska-Lincoln3,University of Limerick4Show Abstract
One of the most prominent features of the ferroelectric domain walls (DWs) is their electrical conductivity, which was observed in a number of ferroelectric materials, such as BiFeO3, Pb(Zr,Ti)O3, ErMnO3. Here, we combine scanning transmission electron microscopy (STEM) and local probe techniques to investigate the conducting properties of the charged DW in the ion-sliced single-crystalline LiNbO3 thin films with sub-µm thickness. STEM shows large inclination of the electrically-generated 180° DWs away from the polar z-axis (with inclination angles reaching 16°) suggesting that these DWs are strongly charged. Atomic column STEM imaging reveals the dipolar-kinked configuration of the Nb atoms along the inclined DWs. By using piezoresponse force microscopy (PFM) in combination with conductive atomic force microscopy (CAFM) performed both on z- and x-cut surfaces, it was shown that head-to-head DWs exhibit much higher conductivity than the tail-to-tail DWs, suggesting an electronic type of conductance. One of the most important findings is a possibility of DW conductivity modulation by an external voltage. It is demonstrated that the resistance of the LiNbO3 thin film capacitors can be changed continuously by 5 to 9 orders of magnitude by controlling the DW perimeter allowing development of multi-level resistive switching devices. Resistance states can be altered by exposure to cumulative voltage pulses (resistance plasticity), suggesting that these domain wall memristors might be useful in the context of artificial synapses.
5:00 PM - EP09.03.17
Transport Analysis of 4H-SiC Power Devices Using Full-Band Ensemble Monte Carlo Method
Chi-Yin Cheng1,Dragica Vasileska1
Arizona State University1Show Abstract
Energy issue is one of the most important things for us humankind. To reduce the energy waste and decrease the emission of greenhouse gases, people try to develop high energy efficiency units for power supply systems, for example, for EV and HEV. Therefore, we need an accurate and reliable model to help us develop and design the power devices. For this purpose, being one of the most promising materials for high power applications, 4H-SiC will be investigated in detail for improving performance of existing technology using in-house full-band Monte Carlo device simulator that is a subject of this work. The commercial TCAD tools are always based on effective mass approximation, however, most of the power electronic devices are operated under high electric field, so the non-parabolic band approximation cannot hold anymore. Hence, we need full-band analysis.
First ingredient in the process of building a device simulator is calculation of the band structure. In that respect, the empirical pseudopotential method (EPM) provides an effective way to get the band structure since we can adjust parameters to fit measurements (optical gaps). Here we refer to findings of G. Ng et al. to re-build the band structure. 205 eV cut-off energy was adopted; hence 527 plane waves were considered. The first Brillouin zone in reciprocal space of 4H-SiC is hexagonal. The full band structure of 4H-SiC is calculated, the indirect band gap is found to be 3.2464 eV and is between Γ point and M point. It is quite close to the commonly known value of 3.26 eV.
Next task in the sequence is calculation of the scattering rates for which a Density of States (DOS) function is needed. The most widely used method for DOS calculation was proposed by Gilat and Raubenheimer in 1966. They extended the original method in 1967 also to hexagonal close-packed crystals. The first step in the DOS calculation is to discretize the k-space into smaller volumes. We only consider the irreducible wedge, which is 1/24 of the first Brillouin zone, because of symmetry. The wedge can be discretized into rectangular meshes and smaller wedge meshes. If we assume that linear extrapolation works good in every mesh, then the intersections of constant energy surfaces inside meshes are replaced by parallel planes S(kc,n) which are perpendicular to the gradient ▽kE(kc,n). If w is the distance of a particular energy plane from kc inside a mesh, the range w determines the possible cross-section area S(w). λm are defined as λm=lmαm. We rearrange them in a decreasing sequence λ1 ≥ λ2 ≥ λ3 ≥ 0. All possible S(w) for both rectangular meshes and smaller wedge meshes are found. After calculating all cross-section area and relating equations, we obtain the DOS function.
Once the DOS function is calculated, to analyze 4H-SiC devices, we have to consider acoustic, non-polar optical and polar optical phonon scattering. Thus, we create a scattering table using the information from the DOS. For the typical doping level in 4H-SiC device applications, the Brooks-Herring model is not valid. Hence, both electron-electron and electron-ion interactions are calculated. To save the runtime, we use the particle-particle-particle-mesh (P3M) method to get an efficient analysis procedure. The P3M divides the Coulomb force into two parts, the short-range force and long-range force (mesh force). We only need to consider the short-range forces for the carriers and ions close to the carrier we are tracing during each time step; the long-range force will be included via the solution of the 3D Poisson's solver.
We present at the conference simulation results of a N+-n-N+ resistor from where we extract the results for the low-field electron mobility dependence upon Coulomb scattering in 4H-SiC devices, and the high-field electrons behavior where band structure effects are important.
5:00 PM - EP09.03.19
Manipulating the Electrochemical Metallization Cell Kinetics by the Anion Electrode and Tunable Electrolyte
Ziyang Zhang1,Yaoyuan Wang1,Huanglong Li1,Luping Shi1
Tsinghua University1Show Abstract
Electrochemical metallization (ECM) memories have the potential to replace today's technology, enabling novel memory and computing architectures circumventing the von Neumann bottleneck. Typically, the operation of ECM cell is based on the electrochemical redox reactions of the cation supplying active electrode. However, the possibility of utilizing new materials for the active electrode remains largely undiscussed. In addition, the ECM cell kinetics are strongly determined by the electrolyte, which can hardly be altered after the cell has been fabricated. Therefore, it is necessary to investigate the influence of the electrode and electrolyte on the ECM cell kinetics. In this work, we engineers the anion supplying active electrode and tunable electrolyte into the electrochemical metallization cell. First, to investigate the electrode dependent switching characteristics of the ECM cells, we fabricates the ECM cell with Te active electrode. It is found that the SET operation of the device occurs under negative voltage on the active electrode. This behavior is opposite to that of the device with Ag electrode, indicating that Te supplies anions by the ECM mechanism. Different modes of switching between the two types of cells, namely, unipolar switching for Pt/GeS/Te cell and bipolar switching for Pt/Ge2Sb2Te5(GST)/Te cell are observed. These phenomena can be attributed to the rupture of the filament by Joule heating for the former and by ECM for the latter in the RESET process. Next, we fabricate the ECM cell with solid phase tunable GST electrolyte to investigate the electrolyte dependent switching characteristics of the ECM cells. The resistive switching characteristics of the cells with different GST phases are examined. The magnitude of the high resistance, the SET voltage and the on/off ratio are found to be considerably affected by the solid phase of GST, whereas the magnitude of the low resistance is least affected. Moreover, a transition from volatile to nonvolatile SET switching is only observed for crystalline GST based cell under prolonged voltage sweep, but not for amorphous GST based cell. This work provides a springboard for more studies on the manipulation of the ECM cell kinetics by tunable electrode/electrolyte and the resulting unprecedented device functionalities.
5:00 PM - EP09.03.20
Bidirectional and Multilevel Threshold Switching of Ag-Dielectrics Diffusive Devices for Neuromorphic Computing Applications
Yaoyuan Wang1,Ziyang Zhang1,Shuang Wu1,Lei Tian1,Huanglong Li1,Luping Shi1
Tsinghua University1Show Abstract
Non-volatile memristor crossbar arrays have great potential in brain inspired computing and next generation high-density memories. Diffusive devices with volatile threshold switching (TS) behavior, which are based on the phenomenon of spontaneous rupture of filaments in dielectrics, are of importance in selector applications to suppress the sneak current issue of memristor arrays. Besides, their rich synaptic dynamical behaviors can also enable novel designs in neuromorphic computing to extend the circuits based on the complementary metal-oxide-semiconductor. In this work, we have realized reproducible bidirectional and multilevel TS behavior on Ag-dielectrics diffusive devices. The ON/OFF ratio and the OFF current of the device TS behavior are ~ 107 and ~ 10-12 A, respectively, which are suitable for selector applications. And we also realize stochastic and multilevel TS by optimizing the device structures. For neuromorphic applications, we integrate the stochastic TS into the stochastic learning process of deep neural networks, and demonstrate the multilevel TS into short-term and long-term plasticity for electronic synapses. Simulations of nanoparticles diffusion are also carried out to study the mechanism of this bidirectional and multilevel TS process. The simulations show that these phenomena are mainly caused by the diffusion and redistribution of Ag nanoparticles. This work illustrates that Ag-dielectrics diffusive devices are promising candidates for neuromorphic computing applications.
5:00 PM - EP09.03.21
Optoelectronic CMOS Transistors—Performance Advantages for Sub-7nm ULSI, RF ASIC, Memories and Power MOSFETs
Advanced Enterprise and License Company1Show Abstract
Substantial increase of output current, and Ion / Ioff ratio, for sub-7nm low power CMOS transistors can be accomplished using a novel optoelectronic technology, which is 100% compatible to existing CMOS process flow. For RF or mixed signal ASICs, adding photonic components may improve the cut-off frequency, and reduce series resistance. Products that utilize power regulating devices, such as power MOSFETs, will benefit from the optoelectronic configuration to achieve much lower Rdson and high avalabche breakdown voltage at the same time. For semiconductor memories, including DRAM or FLASH, the photonic technique may reduce the ERASE / WRITE / access time and improve the reliability.
Photon generating and sensing devices can be integrated in the drain region of a MOSFET, FINFET or power MOSFET as one transistor. The laser diode is turned on only when the MOSFET is switched to on. The laser is off when the MOSFET is switched off. When both laser and MOSFET are on, light is absorbed by the APD (Avalanche Photo Diode), which is fabricated in the drain / well regions of the MOSFET, and generates avalanche breakdown currents as part of the output drain current. In this paper we will discuss how to implement this optoelectronic technique for low power, high speed sub-7nm CMOS, memories (DRAM, SRAM, FLASH), and high power MOSFETs.
Sub-7nm CMOS Transistors. Process integration of a laser in the drain region of a MOSFET or FINFET may be simplified. Cross section of an optoelectronic MOSFET shows device configuration, where part of the drain is etched and redeposited with lasing films. An equivalent circuit of the device provide step-by-step detailed operatons. Please notice that if the substrate is silicon, the lasing films (direct band gap materils) can be deposited selectively on silicon through low temperature epitaxy. If the substrate is GaAs, or other compound semiconductors, a thin silicon film may be deposited on the compound substrate. MOSFET is build in the top thin silicon film, and laser is formed on the compound substrate after selective etching of silicon.
Similar integration techniques can be applied to FINFETs, with low temperature selective epitaxy of lasing semiconductor films in the drain area of a FINFET. The fin can be silicon or GaAs. If the fin is GaAs, a thin silicon epi layer needs to be deposited on GaAs, then selectively removed right before the lasing films are deposited.
In order to further simply the process integration, it is feasible to integrate the laser in the contact 1 or via between metal 1 and silicide.
Improvement of MOSFET output current depends on laser external quantum efficiency and the APD absorption rate. To achieve optimized CMOS drive current, high laser quantum efficiency and APD absorption rate are needed.
Power MOSFETs. Cross section of a discrete vertical power MOSFET illustrates how a laser diode is integrated. For this type of devices, the drain is located in the back side of the chip. Source is on the top of the chip. Deposition of compound lasing semiconductor films in the back side of the chip creates a laser. When a high voltage is applied to the drain, a large depletion region is formed along the drain junction in order to sustain a high breakdown voltage. High-intensity light is produced from the laser in the backside, and absorbed in the depletion region to produce light current, which reduces Rdson.
Nonvolatile Memories: SRAM, DRAM, FLASH, SONOS, EEPROM – Light Assisted Very High Speed Operations. An optoelectronic Flash memory is a SONOS memory (NOR Flash) with a laser integrated in the drain area. For the Write operation, typically with hot carrier injection, a gate voltage is applied to turn on the word line transistor, and a drain voltage is applied to turn on the laser – light is produced and absorbed in the depletion regions in the channel and drain. Hot carrier injection is enhanced by the light current, and the Write operation is much faster.
5:00 PM - EP09.03.22
Atomic Force High Frequency Phonons Nonvolatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology
Advanced Enterprise and License Company (AELC)1Show Abstract
This paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and CMOS-based magnetic devices. Random access is accomplished with the magnetic fields generated from ring-gate MOSFETs. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.
A fast non-volatile dynamic random access memory is different from NAND Flash, for which random access is not possible, and NOR Flash, which is relatively slow and high operation voltages are required. Traditional MRAM (Magnetic Random-Access Memory) uses the material properties of magnetic films, which might not be reliable after many operational cycles. A magnetic nonvolatile DRAM (MNV-DRAM) consists of a main gate on top of a silicon substrate with implanted source and drain regions, a floating phonon gate above the main gate, and a control gate above the phonon gate. In between the gates there are vacuum gaps of a few Å. The floating phonon gate consists of polarized ferromagnetic thin films. The control gate is made of a conducting layer on top of a ferromagnetic thin film. The main gate is made of a ferromagnetic thin film on top of a conducting layer. The ferromagnetic films in the phonon gate are implanted with positive or negative charges. As the result, there is an electro-magnetic field with dual quantum wells in between the control and main gates from atomic forces, where the floating phonon gate switches from one quantum well to the other with very high frequency. The layout design of the 3 gates may be rectangular, or circular (3 loops on top of each other), in order to achieve random access with magnetic fields from the currents in the loops. Due to the currents flowing in the loops, magnetic fields from each loop couple with each other, forming two magnetic dipoles. Motions of the loops depend on the polarity of the dipoles. When currents flow in the same direction, there is an attracting force between the two loops. If currents flow in opposite directions, there is a repelling force. The channel length of the ring gate MOSFET is approximately the length of the ring, as described by a cross section (cut along the ring). If the device is cut across the ring, this shows the width of the MOSFET.
Conclusion: A novel atomic force magnetic nonvolatile memory is presented in this paper. Nonvolatile functions are achieved by high frequency phonons and quantum wells. Random access is accomplished with coupling of magnetic dipoles. This type of memory requires very low voltages for Write / Erase / Read operations and no Refresh is necessary. The speed is much higher than traditional FLASH memories. Manufacturing of the memory is low cost, without exotic materials, and compatible to deep nanometers CMOS technology. Access time vs. current and memory device dimensions are presented in this paper.
5:00 PM - EP09.03.23
Generic 2D Schrödinger-3D Poisson Solver for AlGaN/GaN Nanowire FinFETs
Viswanathan Naveen Kumar1,Dragica Vasileska1
Arizona State University1Show Abstract
AlGaN/GaN heterojunction FETs (HFETs) possess unique properties such as a wide band-gap, high drift velocity and high critical electric field which make them uniquely suitable for high voltage power devices. Unique properties of Gallium nitride (GaN) such as a wide band gap significantly reduces band to band tunneling making it suitable for sub-10 nm transistors. Ballistic transport is also possible in GaN devices because of the high optical phonon energy. Presence of a 2DEG at the AlGaN/GaN hetero-interface contributes to a high sheet charge density, and subsequently high mobility. However, this very presence of polarization-induced charge density leads to poor turn-off characteristics. In the past decade, 3D FETs, such as FinFETs and Gate-all-around (GAA) FETs, have been developed as viable alternatives to traditional planar transistors. Recent works demonstrate such an approach to AlGaN/GaN HFETs as well. Introduction of non-planarity such as a fin has shown to improve off-state characteristics and push the threshold voltage into the positive. Previous works have shown experimentally the dependence of threshold voltage and the electron density on the width of the nanowire channel. The focus of this work is to develop a generic 2D Schrödinger-3D Poisson solver for GaN Nanowire FETs. A 3D Poisson solver coupled with a 2D Schrödinger solver allows us to accurately map the charge density in the channel. The solver can also help us model the dependence of electron density in 2DEG and sidewalls on geometry of the nanowire channel. The electron wavefunctions generated by the solver is used to compute overlap integrals in the Ensemble Monte Carlo (EMC) algorithm. Three scattering mechanisms: acoustic phonon scattering, polar optical phonon scattering, and piezoelectric scattering are considered to account for the electron phonon interactions in the system. The EMC solver is then used to determine the low field electron mobility and drift velocity in the channel.
5:00 PM - EP09.03.24
Observation of Threshold and Resistive Switching Behaviors in Epitaxially Regrown GaN p-n Diodes by MOCVD
Tsung-Han Yang1,Houqiang Fu1,Kai Fu1,Xuanqi Huang1,Hong Chen1,Jossue Montes1,Chen Yang1,Jingan Zhou1,Yuji Zhao1
Arizona State University1Show Abstract
Resistive random access memory (RRAM) has been extensively investigated due to its great potential in synaptic and neuromorphic computing applications. In the crossbar array of RRAM architecture, threshold switching selector devices are one of the crucial components to cut off the sneak current path of the unselected cells. This work reported the first observation of threshold and resistive switching behaviors in epitaxially regrown vertical GaN p-n diodes by MOCVD. They showed excellent thermal reliability up to 300 °C, which is a significant improvement over traditional oxide-based devices. The device can be integrated with mature III-nitride high electron mobility transistors (HEMTs) technology and facilitate the development of GaN-based integrated circuits, especially for harsh environments.
The epilayers were grown homoepitaxially on bulk n+-GaN substrates by MOCVD. The device structure consists of a 0.5 µm n+-GaN buffer layer, a 7 µm unintentionally doped (UID) GaN drift layer, 1 µm n+-GaN contact layer, 0.3 µm regrown UID-GaN and 1 µm regrown p-GaN after the etching of 1.5-µm-deep trenches in the UID-GaN drift layer and n+-GaN contact layer. The regrown layers on top of the n+-GaN contact layer were removed to form the top n-contact. The top p-contact was formed on the regrown p-GaN, and the bottom n-contact was on the backside of the substrate. The forming process was completed by the soft breakdown of either lateral p-n diode between the top n- and p-contact or the vertical p-n diode between the top p-contact and bottom n-contact. After the forming process, we observed the threshold switching process in the vertical diodes with a high resistance state (HRS) and a low resistance state (LRS). Reliability study showed that the devices can operate stably up to 1000 cycles at both room temperature and 300 °C, indicating the excellent thermal stability of the threshold switching behaviors.
The I-V characteristics of the devices was analyzed in log-log scale to explain the operation mechanism. At the LRS, the I-V curve was similar to that of a conventional p-n diode. At the HRS, there are two regions, which follow the trap-assisted space charge limited current (SCLC) theory. At low voltage region, it is dominated by the ohmic law where I V; at high voltage region, it is dominated by the Child’s square law with defects where I V2.3. As shown by the TEM study, the regrowth interface was highly disordered with defects. We hypothesized that after the soft breakdown, the regrowth interface layer may behave like a thin insulating layer with trap states which leads to the HRS. It’s reported that these traps can form/rupture a conductive path by trapping/detrapping carriers. From 0 V to the set voltage, the traps at the interface will be filled with carriers to form a conductive path, resulting in the transition from HRS to LRS. carriers. From the reset voltage to 0 V, the traps will be depleted of carriers to cut off the conductive path, and the devices change from LRS to HRS. We also observed an increase in set voltage with increasing temperature, which can be explained by the enhanced detrapping effect at high temperatures. Furthermore, the memory behavior can also be observed if the voltage is large than the turn-on voltage of the p-n diode. This is analogous to a diode and a RRAM cell connected in series.
In summary, we demonstrated threshold switching and memory behaviors in epitaxially regrown GaN vertical p-n diodes. This physical mechanism was attributed to the forming/rupturing of the conductive path formed by traps through trapping/detrapping carriers at the regrowth interface. The device showed excellent reliability up to 1000 cycles and thermal stability up to 300 °C. In addition, memory behaviors can be observed when the reset voltage was higher than the turn-on voltage. These results open up opportunities for the development of GaN-based memory devices and integrated circuits.
5:00 PM - EP09.03.26
Non-Volatile Discrete Memristive and Memcapacitive States Enabled by Electric Field Controlled Charge Disproportionate Redox
Sreetosh Goswami1,Thirumalai Venkatesan1
National University of Singapore1Show Abstract
Handling ‘big data’ is one of the biggest problems for next-generation computing. This calls for major breakthroughs in digital electronics, the backbone of modern computing, where emerging technologies like artificial intelligence is being implemented. For this, memristors are considered an important building block since they facilitate two key strategies for big data handling, viz. (i) increasing data density and (ii) reducing the asymptotically increasing demand for computing power. The main challenge in increasing data density is that the existing non-volatile memristors consist of many analog states, suitable for neuromorphic computing but not optimized for a digital platform. We report here a memristor, based on a molecular film of a Ru-complex of an azo-aromatic ligand, having 3 discrete, non-volatile states with conductance values separated by >3 orders of magnitude that are temporally and thermally stable – an ideal candidate for high-density digital electronics. Formation of these discrete states is enabled by field-driven transitions between three different molecular redox states in the film resulting in significant changes in conductance. Of these redox states, the ground state of the film is characterised by charge disproportionation (CD), the formation and disruption of which can be reversibly controlled by an external bias at room temperature. Based on electrical and spectroscopic measurements and quantum mechanical calculations, we conclude that the applied field displaces the counterions w.r.t. the molecules, making or breaking the coulombic symmetry and stabilizing the CD and non-CD states. The resulting CD results in a binary memcapacitance concurrent with the ternary memristance and could lead to ultra-low energy computing. In contrast to the highly correlated electronic systems, where only specific physical conditions (like high or low temperature or ultra-high pressure) can cause a broken electronic symmetry (i.e. CD), in our molecular films electronic symmetry/asymmetry (i.e. non-CD and CD states) can be reversibly controlled by external voltage at ambient conditions – one of the Holy Grails in condensed matter physics.
5:00 PM - EP09.03.27
Self-Purification of the Highly Pure Semiconducting Carbon Nanotube Arrays
Zhenxing Zhu1,Nan Wei2,Weijun Cheng3,Fei Wei1
Beijing Key Laboratory of Green Chemical Reaction Engineering and Technology1,Aalto University2,Tsinghua University3Show Abstract
Carbon nanotubes (CNTs) are the promising candidates for the novel integrated electronics. Whereas, it’s a challenge to obtain perfect semiconducting CNT (s-CNT) arrays with a high purity. Here, we demonstrate the self-purified 99.9999% s-CNT arrays based on an interlocking between the atomic assembly rate and bandgap of CNTs. Rate analysis verified the Schulz-Flory (SF) distribution for both metallic (m-) and s-CNTs, indicating their different decay rates as length increased. Furthermore, s-CNTs exhibited an averaged ten-fold slower decay rate than that of m-CNTs, causing the self-purification of 99.9999% s-CNTs with diameters centered around 2.40 nm when the length exceeded 154 mm. Transistors fabricated on them delivered a high current of 1.4 mA/µm with an on/off ratio around 108 and mobility over 4000 cm2/Vs. Our self-purification strategy offers more degrees of freedom to in-situ control the s-CNT purity, exhibiting significant potential in scale-up production and applications of highly pure s-CNTs.
5:00 PM - EP09.03.28
Performance Degradation Due to Nonlocal Heating Effects in Resistive ReRAM Memory Arrays
Marius Orlowski1,Mohammad Al-Mamun1
Virginia Tech1Show Abstract
Conventionally, resistive RAM memory is manufactured in a cross-point architecture. A cross-point at which a memory cell is located, is an intersection of vertical and lateral metal lines for the active and inert electrodes of the resistive memory cell. Here, we investigate the thermally induced degradation of Cu/TaOx/Pt/Ti ReRAM devices. When one cell is repeatedly switched on and off, a certain amount of heat is being deposited in the cell. The local temperature to rupture a Cu filament has been estimated to be 600-800oC. The lingering heat affects not only the device itself, but the heat dissipated along the electrode metal lines causes performance degradation of the neighboring cells. To monitor the cell degradation we choose specific set condition to form a marginal, i.e. weak, highly resistive Cu filament by imposing low Icc of 10μA and ramp rate rr=1.2V/s, while the reset is performed at low rr=0.1V/s with no Icc imposed in order to maximize the Joules heating. Such a fragile Cu filament acts as a canary in the coal mine with respect to ambient heat. The heat deposited in a stressed device leads to a limited number of switching cycles, usually 11-14. When the device is preheated, the maximum number of cycles may decrease to zero and thus serves as a measure for performance degradation of the neighboring cell. Within 3-4 minutes, after reaching maximal cycles for a given device, we test the switching behavior of the neighboring cells, one at a time. We find that only the cells that share either metal line of the heated device, suffer performance degradation. Direct neighbors (like a cell at the intersection of the adjacent Cu and Pt line) to the heated cell thus not sharing any the electrode of the heated device, are not affected at all by the heat, provided that the intermediate cells are in off-state. However, when the intermediate cells are programmed to the on-state and provide thus a direct heat conduction path to the heated device via copper line, Cu filament of the intermediate cell, and the Pt line, the diagonal neighbors suffers performance degradation. We find that the neighbors along the common Cu electrode line are affected more than the neighboring cells along the Pt electrode line. The heat transport along the Cu layer line is more effective and reaches further neighbors than for Pt line. Although the heat conductivity of Cu is roughly 5 higher than of Pt and the Cu metal line is 150 nm while the Pt line is 50 nm thick, we found this result surprising because it challenges the conventional assumption that the shape of the Cu filament is that of a sharply tipped cone with a broad base forming an interface with the Pt line and the tip of the cone touching the Cu line. This shape would imply very small contact of the filament with Cu and large contact with Pt, favoring heat transfer to the Pt line rather than to the Cu line. The observed more efficient heat transfer from the filament to Cu than to Pt line implies that the shape of the Cu filament appears to be more likely that of hour glass rather than a cone. When the tested neighboring cells are allowed to cool off for sufficiently long time (20 min or more) they return to the original performance levels of 11-14 cycles. We find also that the minimum cooling off period is shorter for cells disposed along the Cu lines rather than along the Pt lines.
The width of Cu and Pt lines in our arrays varies between 5 μm and 35 μm and the distance between the lines is ca 150 μm. We find more pronounced degradation of the neighboring cells along the Pt lines, for 35 μm wide Pt lines than for 5 μm wide Pt lines, indicating that metal lines with smaller cross-section are less effective in heat dissipation to the surroundings. In commercial arrays, the thickness, width, and line pitch of the electrode metal lines are of the order of couple 10s of nm. We therefore expect much more pronounced heating effects and over a longer time period in commercial memory arrays.
5:00 PM - EP09.03.29
Suppression of Gate-Induced Drain Leakage in Single-Gate Feedback Field Effect Transistors
Doohyeok Lim1,Sangsig Kim1
Korea University1Show Abstract
In this work, we demonstrate single-gate feedback field-effect transistors (FBFETs) consisting of p+-n+-i-n+ silicon nanowires (SiNWs). SiNWs were derived from a bulk-Si wafer including ion implantation and crystallographic wet etching processes, and the SiNWs were then transferred onto a plastic substrate. The SiNWs had a diameter of 100 nm. BF2+ and As+ ions were implanted for the formation of p+ and n+ regions in the p+-n+-i-n+ SiNWs, respectively. The aluminum electrodes were formed on top of the SiNW in p+-drain and n+-source regions. The i-regions of the channels were covered with Al2O3 high-κ dielectric layers. Tungsten top-gate electrodes with widths of 2 μm were also formed via photolithography and thermal evaporation processes. The SiNW FBFET exhibits good switching characteristics in terms of an on/off current ratio, a subthreshold swing, and gate-induced drain leakage (GIDL) current. Specifically, the GIDL can be effectively suppressed because the p+ potential barrier in p+-n+-i-n+ silicon nanowires can block the injection of tunneling electrons, unlike the conventional metal oxide semiconductor FETs (MOSFETs).
5:00 PM - EP09.03.30
Introducing a Single MOF Crystal into a Micro CBRAM Device by a Selective Growth Method of MOF
Atsushi Shimizu1,Kentaro Kinoshita1,Yusuke Nakaune1,Hisashi Shima2,Makoto Takahashi2,Yasuhisa Naitoh2,Hiro Akinaga2
Tokyo University of Science1,National Institute of Advanced Industrial Science and Technology2Show Abstract
Conducting-bridge resistive random access memory (CBRAM) is attracting attention thanks to its advantages such as low power consumption and high applicability to multi-bit data storage. However, CBRAM has issues to be solved, ex., large deviation of switching voltage and resistance, for putting it into practical use. Above all, semiconductor technology is facing a miniaturization limit that prevents the density of memory devices higher. Metal organic frameworks inherently have periodically and densely aligned subnano-scale pores due to self assembled phenomena. We propose replacing a metal oxide film in a CBRAM cell that works as a memory layer with MOF. This is because we expect that the subnano-scale pores of MOF enhance ionic diffusion and the directionality of the diffusion along the pores, leading to superior performance including the improvement of the deviations of a switching voltage and resistance. In this paper, to introduce MOF into actual CBRAM devices, we established a method to grow a single MOF crystal selectively at a via. We also show resistive switching behavior observed in the MOF-CBRAM.
SiO2 was deposited on a Cu(50nm)/Pt(20nm)/TiN(20nm)/SiO2/Si substrate, followed by the formation of vias with the diameter of 100 nm, through which the surface of the Cu layer was exposed to the solution, using electron beam lithography. 1,3,5-Benzenetricarboxylic acid (BTC) of 1.8 g was dissolved into the mixed solution of ethanol of 15 ml and dimethylformamide (DMF) of 15 ml. The processed substrate was soaked into the solution to synthesize HKUST-1  that is one of most popular MOF due to its high stability in the atmosphere. Finally, we fabricated top electrodes of Au(20nm)/Ti(20nm), filling the vias, by EB evaporation. Electric characteristics were measured using a semiconductor parameter analyzer (B1500A, Keysight).
In our proposed method, HKUST-1 synthesis advances by dissolving Cu from the Cu layer of the processed substrate into the solution through the vias. Since no Cu is contained in the synthesis solution, HKUST-1 can be synthesized only at the via region, at which Cu ions and BTCs encounter. To keep the concentration of dissolved Cu around the via high, another substrate was placed facing the processed substrate through thin glass sheets that works as a spacer. In fact, we confirmed by SEM that a single HKUST-1 crystal was selectively synthesized at the via region. As for electric characteristics, our MOF-CBRAM showed relatively low resistance in an initial state. This may be attributed to the presence of residual Cu ions that were not incorporated into the crystal and were left in the pores. Accordingly, electrical preparation process similar to reset, which is resistive switching from a low to high resistance state, is necessary for the development of resistive switching phenomena. After the preparation process, bi-polar resistive switching, which means that bias voltages with different bias polarities are necessary to cause set and reset switching, respectively, was confirmed. Therefore, resistive switching phenomena in a single MOF crystal was achieved as a microfabricated electric device, for the first time.
In conclusion, we newly developed a method that enables a selective synthesis of MOF crystal accurately at desired points. Combining this method with conventional microfabrication technic that is familiar with silicon process, micro CBRAM cells containing a single MOF crystal each as a memory layer could be fabricated successfully. In addition, our result strongly indicates MOF crystal can be introduced widely into CMOS process.
 A. S. Münch and F. O. R. L. Mertens, J. Mater. Chem. 22, 10228 (2012).
5:00 PM - EP09.03.31
Functional Demonstration of In-Memory Arithmetic Logic Unit in Memristive Crossbar for Software-Defined Memprocessor
Yi Li1,Long Cheng1,Xiangshui Miao1
Huazhong University of Science and Technology1Show Abstract
Abstract: Software-defined microprocessor in computing systems provides the convenience for users to execute the wanted functions in intelligent terminals. In the microprocessor, arithmetic logic unit (ALU) with the information processing ability is the kernel. In this work, the in-memory ALU functions are demonstrated in the memristive crossbar with implementing nonvolatile Boolean logic functions and arithmetic computing. For logic implementation, stateful IMP, OR and NOR logic are reconfigured within three devices in one step. Based on them, other logic functions are constructed within five devices in five steps at most. The program voltage amplitude is decreased at a relatively low standard under “±VP” mode. For arithmetic computing, the fundamental functions including n-bit full adder with high parallelism, efficient increment, decrement and shift operations are designed and demonstrated for building other arithmetic blocks, such as subtraction, multiplication and division. Furthermore, the energy comsumption is estimated and the design of the peripheral circuit is discussed to evaluate the practiability. This work may pave the way for memristor-based logic and arithmetic computing.
5:00 PM - EP09.03.32
CBRAM Based on Single Crystalline Si Thin Films Grown by Solid Phase Epitaxy
Inho Kim1,Jong-keuk Park1,Beomsic Jung1,Gun-hee Kim1
Korea Institute of Science and Technology1Show Abstract
Low dimensional defects such as dislocation in single crystal Si serve as fast diffusion path of Ag ions. Recently, efforts have been made to employ dislocations in single crystal based oxide and silicon as reliable Ag filaments in CBRAM (Conductive Bridging Random Access Memory). Conductive Ag filaments are reported to be well confined in one dimensional dislocation defects in nanometer scale and exhibit promising device performances in terms of retention time, endurance, linearity and on/off ratio. However, there has been a rare study of controlling the location of the low dimensional defect formation, which is a key factor to device production. In this study, we performed research to create the low dimensional defects on the active region of the epitaxially grown Si thin films for CBRAM by our proposed approach. The single crystal Si thin films were grown by solid phase epitaxy. We fabricated CBRAM devices by sandwiching the epitaxial Si thin films between the active metal of Ag and highly conductive Si substrate. We investigated the device performance of CBRAM including intentionally controlled defects in the epitaxial Si thin films and discuss the effect of the low dimensional defects on the resistive memory device performances. Furthermore, we performed the feasibility study on the use of the epitaxial Si based CBRAM for artificial synapse for neuromorphic computing. The fundamental device parameters of the epitaxial Si CBRAM were extracted, and we propose the future research direction to optimize the device parameters for the artificial synaptic device applications.
5:00 PM - EP09.03.33
Nanoscale Electronics Realization with a Prospectives from Devices Architecture and Interconnect Circuits Theory
National Institute of Technology1Show Abstract
Nanoelectronics is a natural consequence of the earlier successes of microelectronics. However, this realization is likely to continue provided, all new elements fetched by nanometer era of technologies [P. Meher, et al. IEEE Microelectronics and Electronics, 2012, 229]. The primary interest of this investigation is to raise the level of awareness of the IC design community [P. Meher, et al. Journal of The Institution of Engineers (India), 96 (2015) 391] that design for cost minimization is likely to emerge as a high priority action item on IC design plans [P. Meher, et al. International Journal of Circuit Theory and Applications, 2018]. Few basic important parameters have been formulated for cost minimization via cost objective function and performance via design density (very large scale integration) and yield concurrently. This understanding helps us to realize the CMOS logic gate with simple model developments for delay and power dissipation estimation [S. R. Ghimiray, et al.International Journal of Circuit theory and Applications, Wiley, 46 (2018) 1953]. These analysis permit us to understand the mechanisms that control the performance, particularly the power dissipation, of a logic circuit [IEEE Region 10 Annual International Conference, Proceedings/TENCON, 2017]. Several CMOS design styles are attempted with a circuit variations of the static complementary CMOS, which are suitable for low-power applications [S. R. Ghimiray, et al.IOP Conference Series: Materials Science and Engineering- Institute of Physics, 2017].
Rinus Lee, GlobalFoundries
Kah-Wee Ang, National University of Singapore
Catherine Dubourdieu, Helmholtz-Zentrum Berlin / Freie Universität Berlin
John Robertson, Cambridge University
Applied Materials, Inc.
Wednesday AM, April 24, 2019
PCC North, 200 Level, Room 224 B
8:00 AM - EP09.04.01
Current Density and Electric Field Decomposition During Nonlinear Electronic Instabilities
Suhas Kumar1,R. Stanley Williams1
HP Labs1Show Abstract
What physical quantities determine behavior of multistable electronic devices and circuits, especially when multiple stable configurations exhibit identical current, voltage, power input and heat output? This question has been discussed in different forms over several decades. For instance, in 1963 Ridley postulated that under certain bias conditions circuit elements exhibiting a current- or voltage-controlled negative differential resistance will separate into coexisting domains with different current densities or electric fields, respectively. Landauer then postulated that all circuit theorems are in essence heat-generation theorems. These debates were never resolved because of the lack of analytical and experimental techniques to resolve the underlying issues. These issues now assume vast importance especialy with the tapering down of Moore's law and the concurrent interest in nonlinear electronic devices such as memristors.
We address these issues by using thermal and chemical spectro-microscopy to directly imaged signatures of current-density and electric-field domains in several metal oxides. The local activity theorem successfully predicts initiation and occurrence of spontaneous electronic decomposition, accompanied by a reduction in internal energy, despite identical power input and heat output. This is a process similar to spinodal decomposition of a homogeneous liquid or disproportionation of a metastable chemical compound. This result reveals a thermodynamic constraint required to properly model all nonlinear circuit elements. Our results explain the electroforming process that initiates information storage via resistance switching in metal oxides and has significant implications for improving neuromorphic computing based on nonlinear dynamical devices.
Reference: Kumar and Williams, Nature Communications, 9, 2030 (2018)
8:15 AM - EP09.04.02
Bi-Directional Analog Synaptic Behavior of SiOx:Ag-Based Diffusive Memristor
Nasir Ilyas1,Dongyang Li1,Yuhan Yuan1,Xiangdong Jiang1,Wei Li1
University of Electronic Science and Technology of China1Show Abstract
Besides conventional digital von Neumann computing system, the brain-inspired neuromorphic system has been proposed as a new computing paradigm considering effective information processing and memorizing simultaneously. Artificial electronic synapses mimicking biological synaptic functions are required for the realization of highly efficient neuromorphic architectures. Therefore, a two terminal memristor based on electromigration of cations (e.g., Ag+) has attracted considerable interests due to its similar behavior with a bio-synapse (e.g., the flux of Ca++ and Na+) at an ionic level. The memristor working on Ag diffusion dynamics in an ionic conductor matrix (i.e., SiOx:Nx , Ag2S and biopolymer i-carrageenan) has successfully emulated the Ca++ and Na+ dynamics of bio-synapse. HfOx- or TaOx-based memristors exhibiting gradual resets are also proposed for the adaptive learning to mimic the bio-synapse inhibition process based on the electromigration of the oxygen ions/vacancies under voltage pulses. It is challenging to implement bi-directional analog resistance modulation, i.e., many memristors possess gradual conductance changes only under 1V polarity and cannot dutifully mimic bio-synaptic functions of potentiation and depression. Moreover, bi-directional analog resistive random-access memory (RRAM) is suitable for running more complex deep neural networks. There is no doubt that innovation in the design of a memristor both in materials and electrodes is one of the efficient way to realize this goal.
In a memristor, bi-directional analog resistive switching behavior is crucial to adjust the conduction continuously and to mimic various bio-synaptic functions faithfully. The silver-nanoclusters dispersed silicon oxide thin film is an attractive material to fabricate the RRAM devices. It is well-known that in SiOx:Ag-based RRAM devices, the switching mechanism is closely correlated to the formation/dissolution of Ag filaments under an electrical field. Therefore, developing a method to control the filament formation/dissolution is necessary for performance enhancement. Recently, we have proposed a Pt/SiOx:Ag/Ti/Pt memristor which possesses an excellent bi-directional analog resistive switching behavior. We have observed that the formation of a non-stoichiometric high-k TiOx interfacial layer during device fabrication process presents a good barrier property for Ag diffusion under a relatively high electric field. The device has shown a gradual increase and decrease of conductance under positive and negative pulse trains without setting compliance current (ICC). The results of the bi-directional gradual set/reset are a benefit to obtain a reliable “analog” switching for the corresponding synaptic characteristics. Moreover, the short- and long-term plasticity, paired-pulse facilitation (PPF) and transition from short-term memory (STM) to long-term memory (LTM) have also been realized.
In our Pt/SiOx:Ag/Ti/Pt memristor architecture, a stack of pure Ti-layer and SiOx:Ag composite film was deposited on Pt bottom electrode using DC sputtering and RF co-sputtering, respectively. Subsequently, by using the lithography process, 100-nm-thick Pt top electrodes of 200 nm in diameter were patterned. XPS, XRD and SEM were used to demonstrate the formation of TiOx interfacial layer during device fabrication process. The resistance switching characteristics have been determined by modulating the interfacial resistance under 0→±1.5V pulse trains using a digital power source (Keithley 2636B) hooked with a probe system.
In short, we have successfully demonstrated a bi-directional analog synaptic behavior based on Pt/SiOx:Ag/Ti/Pt memristor and proposed a new way for the design of multi-functional resistive switching devices which are promising for future memory and neuromorphic computing applications.
8:30 AM - *EP09.04.03
Reliable Integrated HfO2 RRAM—Material Insights and Filaments Confinement
Gang Niu1,Pauline Calka2,Eduardo Perez2,Markus Andreas Schubert2,Wei Ren1,Zuo-Guang Ye1,Lambert Alff3,Christian Wenger2,Thomas Schroeder2
Xi'an Jiaotong University1,IHP2,Technische Universität Darmstadt3Show Abstract
HfO2-based resistance switching random access memory (RRAM) with 1 transistor-1 resistor (1T1R) architecture represents a strong candidate for future non-volatile memories to compete with NAND Flash as well as for the wireless sensor networks and neuromorphic computation applications. HfO2-RRAM possess various advantages including the compatibility with complementary metal oxide semiconductor (CMOS) processing, fast and low power switching and excellent scaling capability [2-6] etc. The resistive switching (RS) in HfO2 RRAM is widely accepted to be related to nanometer-sized conductive filaments (CFs) in the metal-insulator-metal structure and the electrode/HfO2 interface is also considered as a significant factor to severely impact RS. With the continuous scaling of RRAM devices, in-depth understanding of material issues including the interface, the filament nature and other factors like carbon contamination, become more and more important to further improve the device performances. It will also be highly valuable to directly study integrated cells and arrays in a statistic way to unambiguously clarify material effects on scaled device performances. Moreover, it is urgent to identify solutions to confine the nanoscale filament in order to possibly further increase the device reliability.
In this report, we will show our recent progress in understanding the materials insights and in improving the device performance of HfO2 based RRAM devices. We will demonstrate firstly a detailed study on TiN/Ti/HfO2/TiN/Si 1T1R RRAM (single devices and 4kbit arrays processed in a standard 0.25 μm CMOS process line) with the combination of statistic electrical measurements in pulse mode and a systematic materials characterization to correlate key material factors (nano-crystallites and carbon impurities) with the filament type RS behaviour. It is found that, while the crystallites and grain boundaries could influence the forming/set/reset voltage, carbon residues play a key role to determine the RS property particularly the programming characteristics. Subsequently, by using synchrotron radiation based bulk sensitive synchrotron photoemission spectroscopy (HAXPES), we report an operando diagnostic detection of the oxygen “breathing” behavior at the oxide/metal interface, namely, oxygen migration between HfO2 and TiN during different RS periods. This highlight the significance of oxide/metal interfaces in RRAM, even in filament type devices. Finally, we developed a RRAM device with geometric confinement of the oxygen vacancy distribution and nanofilament location. The nanotip based devices show good RS properties including forming-free, stable endurance and retention. This demonstrates a route to CMOS compatible devices and an effective way to control cycle-to-cycle resistance switching in RRAM technology.
Our progress in understanding the materials issues and RS mechanism, as well as the development of filament confinement solutions, will certainly facilitate the possible regulation of RS modes and thus the further optimization of RRAM device performances.
 K.Zhang, Embedded Memories for Nano-Scale VLSIs (2009, Springer).
 R.Waser, Nanoelectronics and Information Technology 3rd edn, 692 (2012, Wiley-VCH).
 G.Niu et al. Sci. Rep. 6 (2016) 25757.
 G.Niu et al. Sci. Rep. 6 (2016) 28155.
 G.Niu et al. J.Phys. Chem. C, 121 (2017),7005–7014.
 G.Niu et al. Nanotechnology, 28(2017),215702.
9:00 AM - *EP09.04.04
Device and Material Considerations of Ovonic Threshold Switch (OTS) for Cross-Point Memory Technology
Shimeng Yu1,Jiyong Woo1
Georgia Institute of Technology1Show Abstract
As the physical limitations of Si material are faced, the performance improvement of charge storage memories enabled by conventional scaling rules is noticeably slowing. In the meantime, emerging memories that are theoretically advantageous for device scaling based on resistance changes in oxides and chalcogenides driven by spin orientation, phase change, and atomic filament formation have begun to be implemented for a storage class memory, which is a newly introduced technology in the traditional memory hierarchy. Particularly, by employing a cross-point architecture, the memory is sandwiched by perpendicularly located word line and bit line. This passive array allows the highest memory density at the smallest cell size, but is inherently affected by unwanted sneak-path currents generated from adjacent cells, causing read errors. Therefore, a two-terminal threshold selector (TS) that can prevent the sneak-path current below a threshold voltage (Vth) and provide a sufficient current instantly above the Vth is required for each memory (1TS-1R) in the cross-point array.
From a material perspective, the TS can be realized using certain transition-metal oxides such as VO2 and NbO2. Applying electrical stimulus accompanied by heat drives an insulating crystal structure of the material to be converted to another metallic crystal structure. However, a small on/off ratio of about 102 is achieved by this structural phase transition mechanism, which is insufficient to prevent the sneak-path current. Instead, the combination of Cu or Ag electrode and oxide allows a large on/off ratio of greater than 1010 due to the formation of metallic Cu or Ag filament across the oxide, which can be rapidly dissolved with removing bias. However, improvements of reliability and uniformity relevant to the repeatedly formed and ruptured filament remain a primary concern. For these reasons, ovonic threshold switches (OTS) in chalcogenides, which are believed to be related with intrinsic properties of chemical bonding in chalcogen atoms such as Se or Te, have recently gained considerable attention. Based on the understanding of the role of each element in multicomponent chalcogenides, excellent switching and reliability characteristics of the OTS have been demonstrated. Therefore, we aim to present design guidelines of the OTS that vary depending on the memory technology to be used through array level analysis performed in SPICE simulations.
Specifically, when a magnetic RAM (MRAM) generally exhibiting a set voltage (Vset) of about 0.5 V is used with the OTS, the Vth of the OTS less than 0.5 V should be used to achieve a reasonable read voltage (Vread) margin between Vth and Vset for reading a memory window. However, most of the OTSs showed non-linear current-voltage (I-V) relation in a sub-threshold regime due to trap-related conduction mechanisms. Thus, as the Vth is appropriately adjusted to the smaller value, an off-current in the sub-threshold regime directly relevant to the sneak-path current is inversely increased. We therefore examine how the parameters of the OTS affect the maximum allowable array size.
Meanwhile, since a resistive switching memory (RRAM) or phase change memory (PCM) has usually the Vset greater than 1 V, the Vread is boosted in the 1TS-1R. The memory showing robust endurance under a small Vread of 0.1 V may be disturbed by the boosted Vread. Thus, instead of the conventional read operation, a recently proposed sub-threshold read operation enabled by the OTS having Vth much greater than the Vset of 1 V and strong I-V non-linearity in the sub-threshold regime is alternatively taken into account. Here, it is an important to read the memory window at the voltage where the OTS has not yet been turned on in the 1TS-1R, which helps minimize the disturbance. By analyzing how large scale cross-point array can be built, we show a particular circumstance, where the sub-threshold read operation is favorable.
EP09.05/EP08.06: Joint Session: Neuromorphic Devices
Wednesday AM, April 24, 2019
PCC North, 200 Level, Room 224 B
10:00 AM - *EP09.05.01/EP08.06.01
Device and Materials Requirements for Neuromorphic Computing
Raisul Islam1,Haitong Li1,Pai-Yu Chen2,Weier Wan1,Hong-Yu Chen3,Bin Gao4,Huaqiang Wu4,Shimeng Yu5,Krishna Saraswat1,H.S. Philip Wong1
Stanford University1,Arizona State University2,GigaDevice Semiconductor Inc.3,Tsinghua University4,Georgia Institute of Technology5Show Abstract
In today’s data-centric world, where some of the most useful computing tasks are to extract meaningful information from massive amount of unstructured data, neuromorphic computing can provide low-energy high throughput computing. The challenge in data-centric computing with the conventional computing architecture lies in the energy and latency bottleneck of off-chip memory access (i.e. “memory wall”) which do not scale down with the scaling of the technology node.
Deep neural network (DNN) is a class of artificial neural networks (ANNs) that benefits from both the availability of big data (large amount of multi-media data for model training) and the continual performance improvement of semiconductor technologies in the past decade. However, the memory hiararchy of today’s computing architectures is not specifically designed to leverage the predictable dataflow and potential data reuse of DNN processing, resulting in longer latency and insufficient energy-efficiency for memory access. To reduce these expensive memory access, hardware accelerators for DNNs are designed to employ more fine-grained local memory hiararchy and more specialized dataflow design, which improves the energy efficiency and throughput while maintaining DNN’s inference accuracy. However, the "memory bottleneck" in modern DNNs may not be fully addressed by the acceleration architectures alone. Emerging memory technologies have the potential to play an important and unique role. As these technologies can potentially offer up to tera-bytes of on-chip data storage with a wide range of energy-delay optimization opportunities, they may complement SRAM and DRAM for more efficient DNN inference acceleration. A possible application of the emerging non-volatile memory (NVM) devices is to serve as in-memory computing element where multi-level resistance response of an NVM can store the analog synaptic weights of a DNN on-chip. In another in-memory computing scheme, a crossbar array of non-volatile memory devices can perform the multiply-and-accumulate (MAC) operation at a lower energy cost when the input vector is encoded as an analog voltage and the weight matrix is encoded as analog resistance (conductance) values stored in the memory devices. The ability of the NVMs like RRAM, PCM, CBRAM to change its resistance values gradually as a function of the applied voltage pulse across its electrode is the key to performing analog in-memory MAC operation.
This paper provides an overview of the current state-of-the-art non-volatile memory devices used for neuromorphic hardwares in applications ranging from biology based learning models to conventional machine learning algorithms solved using neural networks. Furthermore, a more focused overview of the device-level trade-offs required for hardware acceleration of neural network architectures using analog in-memory MAC operation is presented. In general, larger conductance range, more intermediate states, and higher resistance are desirable for both inference and traning. For inference, an ideal device should also have linear I-V relationship and long retention time. For training, symmetric and linear pulse response, small device-to-device and cycle-to-cyle variation, and good endurance are crucial.
Our review reveals that controlling the oxygen ion movement during pulsed switching in RRAM can be a promising way to achieve the aforementioned performance goals. Placing an oxygen ion barrier to make a bilayer RRAM and confinement of the generated heat during switching have shown significant improvement in analog switching. Better thermal management in RRAM can also provide filament stability that could improve reliability like retention and endurance. If the ideal device can be achieved, the MAC array using NVMs can provide ultra-low energy, high throughput computing without compromising bit precision that is currently missing in the neural network accelerator landscape.
10:30 AM - EP09.05.02/EP08.06.02
Emulating Biological Synaptic Behavior for Ultra-Low Power Neuromorphic Applications Using MoS2/Graphene Heterojunctions
Adithi Pandrahally Krishnaprasad Sharada1,Nitin Choudhary1,Sonali Das1,Durjoy Dev1,Hirokjyothi Kalita1,Hee-Suk Chung2,YeonWoong Jung1,Tania Roy1
University of Central Florida1,Korea Basic Science Institute2Show Abstract
The conventional computing systems based on the von Neumann architecture have reached limits in terms of computational time and power dissipation due to increasing computational complexity.1 To circumvent these issues, new computational architectures are explored, among which neuromorphic computing based on emulating the human brain stands out. It is known that the human brain supercedes a supercomputer by 6-9 orders of magnitude in power dissipation. The superior features of the brain, such as ultra-high density, low-energy consumption, parallelism, robustness, plasticity, and fault-tolerant operation need to be emulated by computing systems for perception and learning.1 These qualities are enabled by the brain’s synapses which form a highly complex and efficient interconnection between neurons in the brain. Therefore, a nano-electronic device which emulates the synaptic properties is a crucial building block for brain-inspired computational systems.
It is observed that the programming current in a memristor is decreased by using 2D materials2-3 as the switching medium, and by using graphene electrode instead of conventional metals.4,5 However, these ultra-low power memristors are realized by exfoliated 2D materials which makes large-scale production implausible.2-3 In this work, we use MoS2 as the switching medium to fabricate a memristive synapse. MoS2 is grown on monolayer graphene forming a vertical heterojunction by the sulfurization of Mo film. Graphene (Gr) is used as the bottom electrode while Ni/Au contact on MoS2 is the top electrode.
The MoS2/Gr memristors exhibit forming-free non-volatile switching behaviour with a low programming current of 1 nA. In addition, these devices exhibit sub-nW reset power and low energy consumption of ~2 pJ/spiking event which makes them highly energy-efficient. Synaptic characteristics such as multiple conductance states between 1 nA and 1 μA with a minimum reset current of 16 pA is also observed. Furthermore, the MoS2/Gr memristors exhibit excellent data retention characteristic of 104 s at multiple conductance states viz., 1 nA and 1 μA. Also, MoS2/Gr memristors exhibit biological synaptic characteristics like plasticity, multi-state conductance tuning, short and long-term potentiation, long term depression and spike timing dependent plasticity rule. Additionally, sustained switching at 1 nA and 100 nA programming currents is observed in these devices for 100 DC cycles indicating their robustness. Filamentary switching with low programming reset power observed in these devices unravel the prospects of developing nano-scale crossbar arrays of energy-efficient synaptic devices for neuromorphic applications.
1. Kuzum, D.; Jeyasingh, R. G.; Lee, B.; Wong, H.-S. P., Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing. Nano Lett. 2011, 12 (5), 2179-2186.
2. Tian, H.; Zhao, L.; Wang, X.; Yeh, Y.-W.; Yao, N.; Rand, B. P.; Ren, T.-L., Extremely Low Operating Current Resistive Memory Based on Exfoliated 2D Perovskite Single Crystals for Neuromorphic Computing. ACS Nano 2017, 11 (12), 12247-12256.
3. Zhao, H.; Dong, Z.; Tian, H.; DiMarzi, D.; Han, M. G.; Zhang, L.; Yan, X.; Liu, F.; Shen, L.; Han, S. J., Atomically Thin Femtojoule Memristive Device. Adv. Mater. 2017, 29 (47).
4. Tian, H.; Chen, H.-Y.; Gao, B.; Yu, S.; Liang, J.; Yang, Y.; Xie, D.; Kang, J.; Ren, T.-L.; Zhang, Y., Monitoring oxygen movement by Raman spectroscopy of resistive random access memory with a graphene-inserted electrode. Nano Lett. 2013, 13 (2), 651-657.
5. Chakrabarti, B.; Roy, T.; Vogel, E. M., Nonlinear Switching With Ultralow Reset Power in Graphene-Insulator-Graphene Forming-Free Resistive Memories. IEEE Electron Device Letters 2014, 35 (7), 750-752.
10:45 AM - EP09.05.03/EP08.06.03
Ferroelectric Spiking Neurons for Unsupervised Clustering
Zheng Wang1,Brian Crafton1,Jorge Gomez2,Ruijuan Xu3,Aileen Luo3,Zoran Krivokapic4,Lane W. Martin3,Suman Datta2,Arijit Raychowdhury1,Asif Khan1
Georgia Institute of Technology1,University of Notre Dame2,University of California, Berkeley3,Consultant4Show Abstract
Ferroelectrics as phase-transition materials have promising applications in both logic and memory technologies beyond CMOS. Neuromorphic architectures, such as neural networks and artificial brains , requires synergy among neurons and synapses to achieve cognition and classification functionalities. In spite of the fact that traditional CMOS technologies provide cumbersome topologies to achieve these functionalities, emerging devices, such as ferroelectrics field-effect-transistors (FEFETs), offer significant benefits in terms of power, performance, and area as physical platform for implementing neural networks due to their unique properties—hysteresis, non-volatility, multi-state, and etc. In the past a few years, FEFETs have demonstrated great potential in implementing artificial synaptic devices -; however, the demonstration of artificial neurons built on ferroelectric devices is still pending. In this talk, we will present experimental demonstration of ferroelectric spiking neuron based on a compact 1T-1FEFET structure and projected performance of spiking neural network based on ferroelectric neurons for unsupervised clustering on MINST dataset . Ferroelectric spiking neurons utilize abrupt hysteretic transition feature of ferroelectrics such that there are unstable states in the current-voltage characteristics of FEFETs . FEFET hysteresis can be dynamically tuned by bias conditions which allows for inhibition functionality. Artificial neurons based on other emerging devices, such as metal-insulator-transition (MIT) devices , suffer from a fundamental shortcoming--all these neurons are excitatory. In contrast, ferroelectric spiking neurons have built-in excitatory and inhibitory input connections, which are essential to enable high accuracy in unsupervised learning, increases sparsity in spiking, and efficient implementation of synaptic weights.
In summary, spiking neurons based on FEFETs provide compact and efficient implementation of artificial neurons and have great potential in developing spiking neural networks and other neuromorphic applications.
 A. Merolla, et al. Science, vol. 345, no. 6197, pp. 668-673, 2014.
 C. Eliasmith, et al. Science, vol. 338, no. 6111, pp. 1202-1205, 2012.
 Y. Nishitani, et al. J. Appl. Phys., vol. 111, no. 12, pp. 124108, 2012.
 M. Jerry, et al. 2017 IEEE International Electron Devices Meeting, 2017.
 S. Oh, et al. IEEE Electron Device Lett. Vol. 38, no. 6, pp. 732-735, 2017.
 Z. Wang, et al. 2018 IEEE International Electron Devices Meeting, 2018.
 Z. Wang, et al. IEEE Electron Device. Lett., vol. 38, no. 11, pp. 1614–1617, 2017.
 M. Jerry, et al. Proc. 2017 Symp. on VLSI Tech., pp. T186-T187, 2017.
11:00 AM - EP09.05.04/EP08.06.04
Parallel Programming of an Ionic Floating-Gate Memory Array for Scalable Neuromorphic Computing
Elliot Fuller1,Scott Keene2,Armantas Melianas2,Zhongrui Wang3,Sapan Agarwal1,Yiyang Li1,Yaakov Tuchman2,Conrad James1,Matthew Marinella1,Joshua Yang3,Alberto Salleo2,Alec Talin1
Sandia National Laboratories1,Stanford University2,University of Massachusetts Amherst3Show Abstract
When executing neural algorithms, neuromorphic computers can overcome efficiency bottlenecks inherent to digital computers by parallel processing of synaptic weights in memory. Despite the possibility of improved efficiency, accurate and parallel programming is challenging to realize due to strict requirements for high write linearity and low write current. Redox transistors based upon lithium-intercalation oxides or semiconducting polymers combine linear programming and low write current in a single device. However, programming at the array level requires an additional selector device. Here, we demonstrate that the sharp ON threshold and high OFF resistance of a Ag-based selector enables addressable programming of redox transistors and state retention. Combined, these two devices comprise an ionic floating-gate memory (IFG) similar to flash but with electrochemical mechanisms for charge injection and memory storage. With an IFG crossbar array we demonstrate accurate and parallel synaptic weight updates that are "blind" and therefore require no feedback mechanisms or multi-pulse schemes. Prototype IFG devices exhibit >1 MHz switching rates, >109 write-read endurance and read currents of 5-10 nA that could enable scaling to crossbars with > 1000×1000 elements. Architectural analysis projects a hybrid IFG-CMOS accelerator to have an energy, latency, and area advantage of 476×, 16×, and 9.5×, respectively, compared to an optimized 8-bit digital accelerator.
 E. J. Fuller, et al., Advanced Materials, 2017
 Y. van de Burgt, et al., Nature Materials, 2017
 Midya, et al., Advanced Materials, 2017
11:15 AM - EP09.05.05/EP08.06.05
Correlation Between Traps Jumping Distance and Gradual Conductance Change Under Different Conductance Update Schemes in HfOx-based Memristive Devices
Putu Dananjaya1,Desmond Loy1,Xiao Liang Hong1,Wen Siang Lew1
Nanyang Technological University1Show Abstract
We demonstrated gradual conductance update during the RESET process of Ti/HfO2/TiN memristive device under different device conductance update schemes. These schemes include varying voltage pulse amplitudes and pulse widths. The reported devices exhibited ~50 dynamic ratio of conductance with switching speeds of 100ns and 400ns for SET and RESET processes respectively. 7 different voltage amplitudes were used to switch the devices from their highest conductance to lower conductance at 1000 cycles each. It was observed that the distribution of these 7 conductance states overlapped with one another, owing to the stochasticity nature of device switching dynamics. One of the most critical stochasticity aspects of memristive devices is the presence of random telegraph signal (RTS), in the form of either bimodal or multilevel current fluctuation during read operations. Despite its undesired properties resulting in conductance instability during read operation, bimodal RTS generated from the back and forth movement of an electron between one electrode to an intrinsic oxide trap has been proven useful in characterizing traps behaviour and location in oxide-based memristive devices. Based on classical theory, the electron capture and emission time of this specific RTS have opposite bias polarity dependence. In the capture of this RTS, the measurement was performed by varying the read voltage from ±0.02V to ±0.20V in steps of ±0.01V under different sampling rates, i.e. 8 ksps, 80 ksps, and 800 ksps for each of the write sequence. The measured signals were investigated by analyzing its time lag plot and bias dependence polarity of capture/emission time constants. It was observed that at higher read voltages, the probability of multilevel RTS occurrences increased (from ±0.15V to ±0.20V), hence the read voltage was optimized in the lower regime rather than the higher regime. The absolute value of RTS amplitude was found to increase as the read voltage increased, while its relative percentage to the mean current decreased. The bimodal signal with opposite polarity dependence is further analyzed to extract the defects location in the oxide structure. The estimated defects location before and after the writing process indicated the movement of the defects within the oxide region, resulting in the conductance change of the device. Different jump distances were extracted from the two conductance update schemes to provide an insight on its correlation with gradual conductance change in Ti/HfO2/TiN memristive device.
11:30 AM - EP09.05.06/EP08.06.06
Memristive Behavior in Core-Shell Nanowire Networks for Neuromorphic Architectures
Shangradhanva Eswara Vasisth1,Jadie Palenzuela1,Hiraku Maruyama1,Juan Nino1
University of Florida1Show Abstract
Continuous enhancement of performance and processing powers of computing devices will soon reach a technological and physical limit and to overcome this, systems emulating the human brain are being developed. Presently, mathematical models known as artificial neural networks (ANNs) are designed to simulate the computational abilities of the brain. Due to large simulation times, the current digital ANNs cannot be efficiently scaled. By contrast, analog (ad opposed to digital) neuromorphic devices with dedicated and adaptable synapses are expected to rival the scale and efficiency of the brain. Phase change materials (PCMs) enables us to fabricate synapses through their memristive behavior. Memristors are two-terminal electrical component where the resistance is a function of the amount and direction of current. Here, we discuss memristive behavior of W/WO3/Ag, Cu/CuWO4/W, and Ti/HFO2/Pt systems for neuromorphic architectures and their potential application as ANNs. In prior studies, memristive architectures for neuromorphic computing are connected through a crossbar array of neurons. With a limit on the number of neurons and regular connectivity, the networks lack sparsity and randomness. As a result, they have high wiring cost and poor functional connectivity. To address such limitations, we have fabricated a random array of core-shell memristive wires to form the connectivity matrix for neuromorphic hardware. In the systems listed above, the conductive core (W or Ti) serves as the bottom electrode with a memristive shell (WO3 or HfO2) that can be electroformed with a set of top electrodes (Ag or Pt) deposited on the surface. Prior to miniaturization, the core-shell wire networks were fabricated using 20 μm tungsten fibers as conductive cores with tungsten oxide as memristive shells. After imprinting of top silver electrodes and electroforming, IV measurements revealed memristive behavior with switching between resistive states (i.e., LRS-HRS) at ±1 V. Subsequently, nanowire networks based on the Ti/HFO2/Pt system were fabricated using electron beam lithography (EBL). Over 90 overlapping core (40 nm)-shell (5 nm) nanowires were written on a 200 μm × 200 μm write field. To complete the connectivity matrix, 64 nodes and individual vias connecting the resulting network to electrode pads were written and deposited. Network quantifying simulations revealed a small-world coefficient of 2.89, shortest path length of 3.61 and clustering coefficient of 0.057. When electroformed, this system exhibited switching between LRS and HRS at ±7 V. To investigate the role of electrode-memristor interfaces, copper tungstate films were deposited on copper substrates using chemical solution deposition. After sputtering top tungsten electrodes and electroforming, IV measurements revealed memristive behavior and exhibited switching between LRS and HRS at ±0.7 V. In this presentation, the fabrication process and the memristive characteristics (endurance, resistance retention, pulse measurements, etc.) of the above listed systems will be discussed in detail.
11:45 AM - EP09.05.07/EP08.06.07
Ultralow Power Dual Gated Sub-Threshold Oxide Neuristors—An Enabler for Higher Order Neuronal Temporal Correlations
Rohit John1,Nidhi Tiwari1,Anh Chien Nguyen1,Arindam Basu1,Nripan Mathews1
Nanyang Technological University1Show Abstract
Inspired by neural computing, the pursuit of ultralow power neuromorphic architectures with highly distributed memory and parallel processing capability has recently gained more traction. However, emulation of biological signal processing via artificial neuromorphic architectures does not exploit the immense interplay between local activities and global neuromodulations observed in biological neural networks, and hence are unable to mimic complex biologically plausible adaptive functions like heterosynaptic plasticity and homeostasis. Here, we demonstrate emulation of complex neuronal behaviours like heterosynaptic plasticity, homeostasis, association, correlation and coincidence in a single neuristor via a novel dual-gated architecture. This multiple gating approach allows one gate to capture the effect of local activity correlations and the second gate to represent global neuromodulations, allowing additional modulations which augment their plasticity and enabling higher order temporal correlations at a unitary level. Moreover, the dual-gate operation extends the available dynamic range of synaptic conductance while maintaining symmetry in the weight-update operation, expanding the number of accessible memory states. Finally, operating neuristors in the sub-threshold regime enables synaptic weight changes with high gain, while maintaining ultralow power consumption of the order of femto-Joules.
Wednesday PM, April 24, 2019
PCC North, 200 Level, Room 224 B
1:30 PM - *EP09.06.01
Excitons in Two-Dimensional Semiconductors “Talking” to Their Environment
Freie Universitaet Berlin1Show Abstract
Every atom in two-dimensional semiconductors from the group of Transition Metal Dichalcogenides (TMDs) belongs to the surface. Because of that, TMDs are strongly affected by their microenvironment. In this talk we show that excitons, bound electron/hole pairs, in TMDs can serve as exquisite probes of the physical and chemical properties of that microenvironment.
First, we show that TMD excitons are strongly screened by nearby dielectrics. In suspended TMD, the behavior of pristine material is approached. We also examine frequency-dependent screening of excitons in TMDC and show that the frequency-dependent dielectric function of the environment can be effectively “sampled” by examining spectral shifts and intensity redistribution between neutral, charged, and defect-bound excitons. Second, we examine near-field energy transfer between TMDs and nanoscale quantum emitters (semiconductor quantum dots or dye molecules) near it. We show that such energy transfer is very efficient, and that its rate can be controlled through electrical gating. Finally, we examine binding of excitons in TMDs to charged molecules on their surface. We demonstrate new molecule-specific excitionic species produced by such binding.
2:00 PM - EP09.06.02
Near-Ideal 2D/2D and 2D/High-Κ Dielectric Interfaces Extracted Using the Conductance Method
Durjoy Dev1,Adithi Pandrahally Krishnaprasad Sharada1,Tania Roy1
University of Central Florida1Show Abstract
Two-dimensional transition metal dichalcogenides (TMDs) are expected to have significant contributions to the future electronic and optoelectronic devices due to their unique features, such as sizable bandgaps, uniform thickness, absence of dangling bonds, lower interface trap density, reduced short channel effects, etc. Molybdenum disulfide (MoS2), one well-known TMD, has drawn interest for high speed, flexible, low power electronic devices since it has a tunable bandgap, reasonable carrier mobility, excellent strength and large surface to volume ratio. One of the key reasons for dominance of silicon over all other semiconductors is the high quality interface between Si and SiO2. Any semiconductor system should possess an interface comparable in quality with the Si/SiO2 interface for its reliable application in electronic and optoelectronic devices.
In this work, we studied the interface quality of 2D/2D and 2D/3D interfaces by developing MoS2 based field effect transistors (FET) having hexagonal boron nitride (h-BN) and high-k top gate dielectrics (Al2O3 and ZrO2). For the 2D/2D MoS2/h-BN FET, 13 nm h-BN flake was dry transferred over exfoliated MoS2. For the MoS2/high k gate dielectric structure, two different nucleation layers SiOx and AlOx were e-beam evaporated over exfoliated MoS2, prior to atomic layer deposition of high k gate dielectrics Al2O3 and ZrO2. One of the most direct, precise and sensitive techniques called the conductance method is adopted for extraction of the interface trap density (Dit) . The subthreshold swing for the devices are in the range of 95 mv/decade to 160 mV/decade. In this comparative study, transistors with the MoS2/h-BN 2D/2D interface exhibited lowest trap density in the range of 7×1010 states/cm2-eV at midgap. This superior quality interface is attributed to the absence of dangling bonds at 2D/2D interface . The interface between MoS2 and Al2O3 exhibited lower trap densities compared to MoS2/ZrO2 interfaces. In the mid gap, the highest trap density (1.35×1012 states/cm2-eV) is obtained for ZrO2 gate dielectric with AlOx nucleation layer, while the lowest one (7×1010 states/cm2-eV near valence band) is obtained for Al2O3 gate dielectric with SiOx nucleation layer. For both Al2O3 and ZrO2 gate dielectrics, the SiOx nucleation layer offered lower Dit compared to the AlOx nucleation layer. The interface trap densities obtained by the conductance method are compared with the numbers obtained using other Dit extraction techniques, such as the Terman method and high-low frequency methods. This study shows that the MoS2/h-BN and MoS2/SiOx/Al2O3 interfaces are at par with the state-of-the-art Si/high-k interface, extending the promise of 2D materials for future high-performance electronics.
1. Nicollia. Eh, and Goetzber. A. Bell System Technical JournaL 46.6 (1967): 1055-+
2. Dev, Durjoy, et al. Applied Physics Letters 112.23 (2018): 232101.
2:15 PM - EP09.06.03
Effect of Dose Rate on Interstitial-Vacancy Recombination in Silicon During Helium Implantation
Katherine Haynes1,Xunxiang Hu2,Brian Wirth2,3,Christopher Hatem4,Kevin Jones1
University of Florida1,Oak Ridge National Laboratory2,The University of Tennessee, Knoxville3,Applied Materials, Inc.4Show Abstract
One outstanding issue for state-of-the-art silicon devices is achieving high levels of dopant activation for shallow junctions, particularly for 3D device architectures in which processes like solid-phase epitaxial regrowth cannot be easily integrated. Helium ion implantation offers an intriguing potential method of vacancy engineering that is made possible by the stabilizing effect of helium on vacancy clusters, as well as the ability to subsequently desorb the implanted helium upon low-temperature annealing. However, much is still unknown about the dynamic interactions between helium, vacancies, and self-interstitials in silicon during implantation. In this study, these interactions were investigated by systematically varying the dose rate of an elevated temperature helium implant. 10 keV He+ was implanted into (100) Si at a dose of 4 x 1016 cm-2 and an implant temperature of 450°C. Beam currents were varied from 2.6 to 10.4 mA. Transmission electron microscopy studies show that extended defects are present in the as-implanted state, and the density of these defects decreases with decreasing dose rate, which is unusual for non-amorphizing implants. In addition, cavities are present and their size and density vary systematically with dose rate as well. Thermal helium desorption spectrometry