Wafer Scale Spatially Selective Transfer of 2D Materials and Heterostructures

Nov 29, 2017 - 8:00 PM -  NM04.09.46
Hynes, Level 1, Hall B
Nikolaos Aspiotis 1 , Ioannis Zeimpekis 1 , Omar Abbas 1 , Sakellaris Mailis 1 , Pier Sazio 1 , Chung Che Huang 1 , Daniel Hewak 1
1 Optoelectronics Research Center, University of Southampton, Southampton United Kingdom
The boom in interest in two dimensional materials has led to intense research, increasingly towards the commercialization of this family of materials. Results to date have proved the viability of wafer scale production of 2D materials, nevertheless no technique for controllable large scale 2D heterostructures, which would seamlessly integrate with existing fabrication lines, has been presented. This is however essential for the production of wafer scale photodiodes, pn-diodes, diode logic gates, and other emerging devices.
There are currently two main approaches for creating heterostructures, i) the sequentially epitaxial growth of 2D materials that results in random spatial growth, rendering this approach non-viable for commercial applications [1] and ii) the mechanical assembly technique, where a 2D flake is transferred and aligned to another flake to form just one heterostructure [2].
Here we report a novel method that can achieve wafer scale fabrication of 2D material-based devices. The method is using a lift-off technique for the micro-patterning of TMDCs and graphene layers that are combined to form heterostructures. The low thermal budget of this process makes this method substrate-agnostic hence suitable for fabrication of devices on temperature sensitive materials such as polymers.
The method uses Atomic Layer Deposition (ALD)-grown metal oxides converted by annealing protocols to 2D TMDCs and copper foil CVD - grown graphene as starting materials. The films are transferred to substrates covered with a pre-patterned photoresist layer. Lift off of the photoresist allows the spatially controllable transfer of the 2D materials allowing for sequential steps to produce aligned heterostructures over large areas.
An overview of the process flow will be presented alongside with a examples of 2D heterostructures such as MoS2 field effect transistors, using graphene source and drain contacts. The deposited microstructures are characterized and furthermore analyzed via Raman mapping, SEM, AFM and XPS measurements.


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[2] W. J. Yu, Z. Li, H. Zhou, Y. Chen, Y. Wang, Y. Huang, and X. Duan, “Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters.,” Nat. Mater., vol. 12, no. 3, pp. 246–52, 2013