Symposium Organizers
David Gracias Johns Hopkins University
Ritesh Agarwal University of Pennsylvania
Pavle Radovanovic University of Waterloo
Joerg Ackermann Universite de la Mediterranee
JJ1: Nanowire Growth
Session Chairs
Monday PM, November 26, 2007
Room 306 (Hynes)
9:30 AM - **JJ1.1
Epitaxial Silicon and Silicon/Germanium Nanowires.
Ulrich Goesele 1 , Stefan Senz 1 , Volker Schmidt 1 , Peter Werner 1 , Alexeij Milenin 1 , Yewu Wang 1 , Tomohiru Shimizu 1
1 , Max Planck Institure of Microstructure Physics, Halle Germany
Show AbstractVarious methods of fabricating epitaxial silicon nanowires and silicon/germanium heterostructure nanowires will be described and compared including VLS and VSS growth and various kinds of plasma and chemical etching. The use of various templates such as nanoporous alumina to grow nanowires in <100> direction will be discussed as well as the use of a solid catalyst such as aluminum to grow silicon nanowires. Varous promising approaches to grow epitaxial heterostructure Si/Ge nanowires with sharp interfaces will be presented.
10:00 AM - JJ1.2
Using pn Junction Depletion Regions to Position Epitaxial Nanowires.
Nate Quitoriano 1 , Ted Kamins 1
1 , HP Laboratories, Palo Alto, California, United States
Show AbstractSemiconductor nanowires have promising properties to possibly augment or replace top-down, lithographically defined Si MOSFET (metal oxide semiconductor field effect transistor) channels because of their small, bottom-up-defined diameters. [1,2] One major difficulty in using nano-scale structures is controlling their location. It is possible to demonstrate ten, or even 100, devices by individually manipulating and connecting them, a technique which has demonstrated the promising device properties of nano structures. [3,4,5] However, to utilize nano structures to their full capability, thousands or millions of individual nano structures must be used in each system. To this end, we present a technique that shows promising results for controlling the location of nanowires by controlling the location of Au catalyst nanoparticles, which are necessary for nanowire formation using the vapor-liquid-solid (VLS) method.In this work, we use the negative charge on citrate stabilized Au nanoparticles to aid in placing them along a specific line. The line is defined close to the metallurgical junction between a lightly-doped, p-type Si substrate and a heavily doped, n-type region. Near the metallurgical pn junction, an electric field is formed by the positive and negative charge of the depletion region. Since the Au nanoparticles have a negative charge, they are attracted to the positively charged depletion region of the n-type material and repelled by the depletion region of the negatively charged, p-type material. We study the effects of different structures and applied voltages in positioning Au nanoparticles along this junction and then use these nanoparticles as catalysts for Si nanowire growth. Vertical {111} surfaces were formed by etching a (110) Si substrate covered with an epitaxial layer of the opposite conductivity type and catalyst nanoparticles were positioned as described above. We find that highly-doped, n-type material forming a junction with lightly-doped, p-type material is the best structure to use to focus the Au particles. Also, applying a reverse bias across the junction increases the positive charge in the n-type material’s depletion region, thereby enhancing the electric field and better focusing the nanoparticles along the line on the vertical surface.Si nanowires were then grown horizontally from the vertical {111} surfaces using these catalyst nanoparticles and the VLS method. Substantial alignment of the nanowires was achieved.[1] V. Schmidt, H. Riel, S. Senz, S. Karg, W. Riess, and U. Gosele, Small 2, (2006).[2] J. Goldberger, A. I. Hochbaum, R. Fan, and P. Yang, Nano Letters 6, (2006).[3] X. Duan, Y. Huang, Y. Cui, J. Wang, and C. M. Lieber, Nature 409, 681 (2001).[4] Y. Huang, X. Duan, Q. Wei, and C. M. Lieber, Science 291, 550 (2001).[5] Y. Cui, L. J. Lauhon, M. S. Gudiksen, J. Wang, and C. M. Lieber, Appl. Phys. Lett. 78, 1 (2001).
10:15 AM - JJ1.3
Fabrication of Oriented and Ordered GaAs Nanowire Arrays on GaAs(111)B and Si(111) Substrates Using Metal-organic Chemical Vapor Deposition.
Jeff Cederberg 1 , A. Talin 2 , Doug Nelson 1 , Karen Cross 1
1 , Sandia National Laboratories, Albuquerque, New Mexico, United States, 2 , Sandia National Laboratories, Livermore, California, United States
Show AbstractSemiconductor nanowires are being investigated intensively, motivated by a desire to discover and manipulate physics at nanometer dimensions. The result of these investigations may be electronics and optoelectronics with characteristics superior to what is currently available. These fundamental and applied interests drive the materials research and development of nanowires for all types of materials. An issue that remains under investigation is the formation of dense arrays of nanowires with uniform dimensions. We are investigating the formation of ordered GaAs nanowire arrays. Our approach utilizes the controversial vapor liquid solid/vapor solid solid (VLS/VSS) technique using Au to “catalyze” nanowire growth. The first technique forms a template by having Au films, 0.5 to 3.0 nm in thickness, deposited on GaAs(111)B and Si(111) substrates. The template was then annealed under AsH3 at 650°C to disperse the Au prior to cooling to 450°C. A metal-organic chemical vapor deposition system was used to control the growth. Our work has been able to compare trimethylgallium to triethylgallium as group III sources. Growth was performed for times ranging from 10 to 50 minutes. This technique forms a large distribution of diameters, but generates large (5 cm) arrays that are preferentially oriented normal to the growth surface. We have discovered that a small thickness of Au (1 nm and under) leads to a higher fraction of oriented nanowires. As the nanowires get longer than 2 µm, a larger fraction of them kink and deviate from the (111) orientation. Oriented nanowires are only part of the picture. Techniques to control the diameter and placement of these structures are needed. To address this need, we are investigating nano-imprint lithography to form arrays of nanowires. Nano-imprint lithography allows features that are tens of nanometers to be generated in a fixed pattern. Au seeds with a 200 nm diameter on a 600 nm pitch were deposited by metal lift-off. Square arrays approximately 2.5 cm on a side were fabricated. Using the conditions established from planar Au film experiments, we have shown it is possible to form localized nanowires with high fidelity. This result indicates that patterned-substrates represent a route to controlled density and placement of nanowires. Nano-imprint lithography is especially well suited to fabrication of large nanowire arrays with the desired geometrical control. Sandia is a multiprogram laboratory operated by Sandia Corporation , a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under Contract DE-AC04-94AL85000.
10:30 AM - JJ1.4
Ion Implanted GaAs Nanowire Pn-junctions.
Gutsche Christoph 2 , Werner Prost 2 , Franz-Josef Tegude 2 , Daniel Stichtenoth 1 , Carsten Ronning 1
2 Institute of Semiconductor Technology, University of Duisburg-Essen, Duisburg Germany, 1 II. Institute of Physics, University of Goettingen, Goettingen Germany
Show AbstractIon beam doping of materials offers advantages in comparison to doping during growth or by diffusion. First, the impurity concentrations as well as the lateral and depth distribution of the dopants are precisely controllable, and secondly, almost all elements can be implanted with sufficient high purity even beyond any solubility limit. However, doping by ion implantation is hampered by the created radiation damage, but this can be removed by thermal treatment.Here, we will report on studies in order to fabricate GaAs nanowires pn-junctions. Nominal undoped GaAs nanowires were grown according to the VLS mechanism using Au nanoparticles on top of Si(100) substrates. Zinc as an acceptor was implanted with different ion energies in such samples in order to create a box-like implantation profile matching the diameter of the GaAs nanowires. Subsequently, the samples were re-insert into the MOCVD system and the growth of the nanowires was continued, but with the addition of Si donors. This growth at high temperatures not only resulted into n-type material, but also also in annealing of the implantation defects of the first section of the nanowires. Finally, the pn nanowires were cut of the growth substrate, and processed with contacts on top of new insulating substrates. First results on the electrical characterization will be presented and discussed in this presentation.
10:45 AM - JJ1.5
Silicon / Nickel-silicide Axial Nanowire Heterostructures for High Performance Electronics.
Walter Weber 1 2 , Lutz Geelhaar 1 , Eugen Unger 3 , Caroline Cheze 1 , Franz Kreupl 3 , Henning Riechert 1 , Paolo Lugli 2
1 , Qimonda Dresden and NaMLab, Dresden Germany, 2 Institute for Nanoelectronics, Technische Universitaet Muenchen, Munich Germany, 3 , Qimonda AG, Munich Germany
Show AbstractSemiconducting and metallic nanowires (NW) are widely investigated as potential building blocks for future electronic devices. Silicon and nickel silicide NWs are particularly interesting, because these materials are currently used as bulk materials in the volume production of highly integrated circuits. In this work, intrinsic Si and NiSi2 NWs as well as NiSi2/Si/NiSi2 axial NW heterostructures are fabricated and investigated electrically. Si NWs are grown by Au-catalyzed chemical vapor deposition. Axial segments of the Si-NWs are transformed into metallic ones by a longitudinal silicidation process. To this end, Si-NWs are contacted with a Ni reservoir at one of their ends. Annealing leads to longitudinal Ni diffusion inside the NWs for lengths of up to several micrometers. Along the diffusion path, single crystalline NiSi2 NW segments are formed in a solid-state reaction [1]. The interface between the NiSi2 and the pristine Si segment has a sharpness on the nanometer scale. This axial silicidation reaction is different from previous NW silicidation findings, since those ones only observed radial Ni diffusion [2]. Fully Ni-silicided NWs have an ohmic behavior and a resistivity of at most 98 μΩ-cm as determined by two point IV measurements. Moreover, NiSi2 NWs conduct current densities of up to 205 MA/cm2 before breakdown. This high value is within the same order of magnitude as that of metallic carbon nanotubes and higher than that of Cu nano-interconnects. Schottky barrier (SB) field effect transistors (FET) are fabricated by a controlled NiSi2 formation from both NW-ends, leaving a pristine Si segment in the middle which constitutes the active region. Gate control is performed by a common back gate stack. The NiSi2 NW-segments extend the source and drain contacts, reducing the length of the active region, e.g. from 1 µm to 20 nm. Hence, this method gives simple access to fabricate nanoscale Si regions by only employing a single and coarse optical lithography step to structure the Ni reservoirs. Although undoped, the FETs exhibit unipolar p-type behaviour if the NW diameter is below 30 nm. For thicker NWs, the behavior is increasingly ambipolar. Such a NW heterostructure SB-FET has the advantage over a common SB-FET contacted by a large pad; that for geometrical reasons the gate field is enhanced at the needle-like Schottky contacts. Therefore, gate control over SB-width and carrier transmission is optimized as shown by electrostatic calculations. Consequently, modulation of over 10^7 and subthreshold slopes as low as 110 mV/dec are achieved. Moreover, these SB-FETs exhibit the highest current densities in the on-state reported up to date for intrinsic Si-NW FETs, amounting to 0.8 MA/cm2 at 1 V bias. These results reflect the performance improvement of one dimensional metal to semiconductor heterostructures in comparison to bulk devices. [1] W. M. Weber et al. Nano Lett. 6, 2660 (2006)[2] Y. Wu, et al. Nature 430, 61 (2004)
11:30 AM - **JJ1.6
Abstract Not Available
Charles Lieber 1
1 Department of Chemistry & Chemical Biology, Harvard University, Cambridge, Massachusetts, United States
Show Abstract12:00 PM - JJ1.7
Using Real Time Microscopy to Quantitatively Determine NucleationMechanisms and Kinetics during the Growth of Si Nanowires on Si3N4Substrates.
Bong Joong Kim 1 , Jerry Tersoff 2 , Suneel Kodambaka 3 , Frances Ross 2 , Eric Stach 1
1 School of Materials Engineering & BIrck Nanotechnology Center, Purdue University, West Lafayette, Indiana, United States, 2 , IBM T.J. Watson Research Center, Yorktown Heights, New York, United States, 3 Department of Materials Science & Engineering, University of California, Los Angeles, Los Angeles, California, United States
Show AbstractA comprehensive understanding of vapor-liquid-solid (VLS) nanowiregrowth mechanisms and kinetics is of considerable importance for structuraloptimization of nanoscale wires with desired properties. Despite over 40years of research, little has been reported on nanowire nucleation. Here, wereport, for the first time, real time transmission electron microscopy (TEM)measurements of the nucleation kinetics of Au-catalyzed Si nanowires. Ourdirect observations of Au mediated Si nanowire nucleation span from initialobservations of the pure solid Au catalyst to final nanowire nucleation. Ourmeasurements show that the nucleation time is linearly proportional to thediameter of the AuSi alloy drop – contrary to behavior expected from theGibbs-Thomson effect – and that the nucleation rate linearly increases withdisilane pressure. These two observations indicate that the rate limiting stepthroughout the processs is the thermally activated dissociative adsorptionof disilane on the catalyst surface. Furthermore, we classify the subsequentnucleus growth process of Si nanowires into three regimes: an initial rapidgrowth of the nucleus, a subsequent slow growth of the nucleus, followedby axial growth of the nanowires away from the AuSi drop. We show thatfor the initial growth, the growth rate (dr/dt) is simply proportional to thecritical supersaturation required to nucleate the nanowire. Additionally,during the slow growth regime and final nanowire growth, the growth rate isproportional to the ratio between the surface area of the AuSi alloy and the Sinucleus. These observations are in an excellent agreement with a theoreticalmodel we have proposed for nanowire nucleation kinetics. Finally, using thismodel we are working to extract the critical supersaturation of Si at which nanowire nucleation occurs, leading to the determination of an effective, kinetically controlled liquidus line in the binary phase diagram. These quantiative measurements yield critical data needed for controlling nanowire nucleation during the fabrication of high performance nano-electronic devices based on these structures.
12:15 PM - JJ1.8
Synthesis of Epitaxially-Aligned Ge/Si Core-Shell Nanowires.
Irene Goldthorpe 1 , Paul McIntyre 1
1 Department of Materials Science, Stanford University, Stanford, California, United States
Show AbstractDepositing a Si or SiGe film around a Ge nanowire (NW) creates a structure which may have additional advantageous properties beyond that of a single-element Si or Ge NW. A heteroepitaxially grown shell may allow for engineering of strain in both the shell and the inner core. Moreover, the valence band offset may allow confinement of holes to the core, reducing the influence of surface defects on carrier scattering in p-type NWs. The Ge-core/Si or SiGe-shell arrangement is desirable for the higher carrier mobilities of Ge and the superior properties of SiO2 passivation.In this work, vertically aligned arrays of Ge/Si and Ge/SiGe core-shell NWs have been synthesized by CVD. First, <111> Ge NWs were heteroepitaxially grown on Si (111) substrates; the NW diameter was controlled through the use of monodisperse Au nanoparticles as the catalysts. Silane, with or without germane, was then used to deposit the shell. The Au remaining on the Ge NW tips is problematic since (i) the Au can catalyze unwanted Si NW growth and (ii) the Au particles at the NW tips diffuse into the structure at the temperatures required to obtain single crystalline shells. We have found that Ge NWs dissolve in commercially available wet chemical Au etchants. We will present a KI/I2-based wet etching procedure for Au removal from Ge NWs that does not significantly etch the Ge so that a heteroepitaxial Si or SiGe shell can subsequently be deposited. The resulting core-shell NWs were characterized with transmission electron microscopy to determine their defect and stress states.
12:30 PM - JJ1.9
Failure and Formation of Axial Nanowire Heterostructures in Vapor-Liquid-Solid Growth.
Mohanchand Paladugu 1 , Jin Zou 1 2 , Ya-Nan Guo 1 , Graeme J. Auchterlonie 2 , Hannah J. Joyce 3 , Qiang Gao 3 , H. Hoe Tan 3 , Chennupati Jagadish 3 , Yong Kim 4
1 School of Engineering, The University of Queensland, Brisbane, Queensland, Australia, 2 Centre for Microscopy and Microanalysis, The University of Queensland, Brisbane, Queensland, Australia, 3 Department of Electronic Material Engineering, Research School of Physical Sciences and Engineering, The Australian National University, Canberra, Australian Capital Territory, Australia, 4 Department of Physics, Dong-A University, Busan Korea (the Republic of)
Show AbstractSemiconductor nanowires and their associated heterostructures have many potential applications in nanoelectronic and nano-optoelectronic devices owing to their unique physical properties, which have drawn extensive research attention in the past decade. The vapor-liquid-solid (VLS) mechanism has been a widely used mechanism for the growth of semiconductor nanowires and their heterostructures. In typical VLS growth, metal nanoparticles are deposited on a substrate surface and heated to the growth temperature under the vapor species of growing material. Nano-sized metal liquid droplets form and then catalyze nanowires growth, so that the nanowires have metal particles at their growth fronts. Au nanoparticles have been widely used to catalyze the nanowires and nanowire heterostructures growth. Axial nanowire heterostructures can be grown by altering the chemical composition of vapor species during the nanowires growth and subsequent achievement of respective compositional alteration along the nanowire growth axis.Successful axial growth of GaAs on InAs nanowires using Au nanoparticles have been reported in the literature. In this work, InAs nanowire sections were grown on GaAs nanowire sections through VLS mechanism using Au nanoparticles. Axial growth failure of InAs on GaAs nanowires was observed through transmission electron microscopy (TEM) characterizations with a sequence of : (i) the initial InAs clustering at an edge of the Au/GaAs interface displaces the Au droplet with respect to its underlying GaAs nanowire; (ii) the Au droplets move sidewards and then downwards with further growth of InAs by preserving an interface with the GaAs sidewalls. The fundamental reason for this failure of InAs axial growth on GaAs nanowires and feasibility of GaAs axial growth on InAs nanowires has been determined by quantifying the interfacial energies between Au-InAs, Au-GaAs and InAs-GaAs at equilibrium. This quantification is done by adopting the model proposed for description of heterogeneous nucleation of a solid from liquid metal along a solid wall of a mold. We use this model because, in our case, the Au particles are in the liquid form during the nanowire growth and GaAs and InAs can act as the wall of the mold and nucleated solid, respectively. Through this quantification, we found that the axial growth failure of InAs on GaAs nanowires is due to higher interfacial energy between Au-InAs than that between Au-GaAs.Thermodynamically, following conclusion can be drawn from this work. When a nanowire axial heterostructure is to be grown with two materials combination “A” and “B” using catalyst particle “C”, and if the interfacial energy between A and C-droplet is higher than that between B and C-droplet, the axial growth of A on B fails, whereas axial growth of B on A is feasible.
12:45 PM - JJ1.10
InAs/InP Radial Nanowire Heterostructures: Rational Design, Controlled Synthesis and High Performance Devices.
Xiaocheng Jiang 1 , Qihua Xiong 1 , Sungwoo Nam 2 , Fang Qian 1 , Yat Li 1 , Charles Lieber 1 2
1 Department of Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States, 2 School of Engineering and Applied Science, Harvard University, Cambridge, Massachusetts, United States
Show AbstractRadial core/shell nanowire heterostructures represent important one-dimensional building blocks with substantial potential for tuning materials electronic and photonic properties. Specifically, it is possible to create structures with novel properties through the rational choice of core/shell materials coupled with highly-controlled synthesis. Here, we report the rational design, synthesis and properties of InAs/InP core/shell nanowires as a new one-dimensional electron gas (1DEG) system. Transmission electron microscopy studies revealed uniform, crystalline InP shell growth and clean, epitaxial interfaces between InAs core and InP shell. In addition, energy-dispersive X-ray spectroscopy analysis further confirmed the composition of the designed core/shell nanowire heterostructure. Room-temperature electrical measurements on InAs/InP nanowire field-effect transistors (FETs) showed significant improvement of the on-current and transconductance compared with InAs nanowire FETs fabricated in parallel. Notably, analysis of these transport data yield an electron mobility of 11,500 cm2/V-s that exceeds substantially values previously reported for n-channel nanowire and nanotube devices. In addition, high-performance FET devices were fabricated by incorporating a high-κ dielectric and top-gate geometry. Studies of these top-gated InAs/InP nanowire FET structures yielded a scaled on-current value of 3.2 mA/μm at a bias of 0.5 V, which is larger than any other n-channel electronic devices up to date. The designed 1DEG in InAs/InP core/shell nanowires opens up opportunities for exploring our fundamental knowledge of nanoscale building blocks, and also the development of quantum coherent transport devices and high-speed, low-power nanoelectronic circuits.
JJ2: Nanowire Device Integration
Session Chairs
Monday PM, November 26, 2007
Room 306 (Hynes)
2:30 PM - **JJ2.1
CMOL: A Challenge For Nanowire Technology.
Konstantin Likharev 1
1 , Stony Brook University, Stony Brook, New York, United States
Show AbstractI will review the recent work on devices, circuits and architectures for possible hybrid semiconductor/nanodevice integrated circuits based on nanowire crossbars, with similar, simple, two-terminal devices (with the functionality of programmable diodes) formed at each crosspoint [1-5]. Special attention will be given to the d “CMOL" variety of the hybrids, in which the crossbar is connected to the underlying CMOS circuit with an area-distributed interface [3-5]. Such interface allows the CMOS subsystem to address each and every of the crosspoint devices, even with no nanoscale alignment between the CMOS and crossbar subsystems. Recent detailed studies have shown CMOL may enable (at least) the following applications:(i) terabit-scale memories with access time below 100 ns and defect tolerance up to 10% [6],(ii) FPGA-like reconfigurable logic circuits with the area-by-delay product at least two orders of magnitude lower than that of CMOS FPGAs [5, 7, 8], and(iii) mixed-signal neuromorphic networks (“CrossNets”) [9] which may provide unparalleled performance for some important information processing tasks including pattern classification [10], and in future may become the first hardware basis for challenging the human cerebral cortex. Recently, the hybrid circuit concept has received a strong boost from the announcement of reproducible fabrication of the necessary crosspoint devices (programmable diodes) using copper oxide [11] and the demonstrations of nanowire crossbars with 15-nm-scale half-pitch [12, 13].In order to fight with advanced nanolithography for their application in CMOL circuits, nanowire technologies face tough challenges including low specific and interface resistances, tight chirality control, and (most importantly) a nm-scale placement accuracy. The work has been supported in part by AFOSR, MARCO via FENA Center, and NSF.[1] K. K. Likharev, in: Nano and Giga Challenges for Microelectronics, Springer, Berlin, 2003, pp. 27-68.[2] P. J. Kuekes, G. S. Snider, and R. S. Williams, Sci. American., vol. 293, pp. 72-76, Nov. 2005.[3] K. K. Likharev and D. B. Strukov, in: Introducing Molecular Electronics, Springer, Berlin, 2005, pp. 447-477.[4] G. Snider, and R. S. Williams, Nanotechnology, vol. 18, art. 035204, Jan. 2007.[5] D. Tu et al., preprint, Feb. 2007.[6] D. B. Strukov and K. K. Likharev, J. of Nanoscience and Nanotechnology, vol. 7, pp. 151-167 , Jan. 2007. [7] D. B. Strukov and K. K. Likharev, Nanotechnology, vol. 16, pp. 888-900, June 2005.[8] D. B. Strukov and K. K. Likharev, in: Proc. FPGA’06, pp. 131-140.[9] Ö. Türel et al., Int. J. of Circ. Theor. Appl., vol. 32, pp. 277-302, Sep./Oct. 2004.[10] J. H. Lee and K. K. Likharev, Int. J. of Circuit Theory and Applications, vol. 35, pp. 239-264, Jan. 2007.[11] A. Chen et al., in IEDM’05 Tech. Digest, Report 31.3. [12] G. Y. Jung et al., Nano Letters, vol. 6, pp. 351-356, Jan. 2006.[13] J. E. Green et al., Nature, vol. 445, pp. 414-418, Jan. 2007.
3:00 PM - **JJ2.2
Nanowire-based Architectures for High-Density Memory and Logic.
Andre DeHon 1
1 Electrical and System Engineering, University of Pennsylvania, Philadelphia, Pennsylvania, United States
Show AbstractHow can we exploit the new capabilities offered by nanowires to build large-scale, high-density electronic systems, and how can we cope with the high rates of variation, defects, and faults expected for these components?Nanowires are emerging as powerful nanoscale building blocks which can be synthesized using bottom-up self-assembly techniques and which offer engineering control over material properties and access to nanometer-scalefeatures. Device structures can be integrated into nanowires along with low-resistance interconnect. In this talk, we describe architectures for memory and logic constructed from these nanowire building blocks,highlighting the nanowire properties and features which make these architectures feasible as well as the challenges they raise. We show how our architectures can exploit statistical assembly to differentiate nanowires and post-fabrication configuration to avoid defects, mitigatevariation effects, and allow deterministic construction of reliable memory and logic. We further estimate system-level characteristics (e.g. memory and logic density, performance, and energy) from lower-level nanowireproperties (e.g. resistivity, junction defect rates, variation).
3:30 PM - JJ2.3
Titanium Nanowires Interspersed With Tens of Zeptofarad Tunnel Junctions for High Density Single Electron Circuit Fabrication.
Arnaud Beaumont 1 , Christian Dubuc 1 , Jacques Beauvais 1 , Dominique Drouin 1
1 Department of Computer and Electrical Engineering, Universite de Sherbrooke, Sherbrooke, Quebec, Canada
Show AbstractIn the late 80’s, the Coulomb blockade (CB) theory of electron tunnelling has been favourably evaluated to provide highly integrated logic devices. Many processes have since been proposed to take advantage of this theory but most do not operate above cryogenic temperatures. This limitation is directly related to the CB principle, involving an “island” (i.e. conductive particle) isolated between two electrodes. If the bias does not enable electrons to overcome the charging energy of the island (Ec) no current flows. In analogy with CMOS transistors, a third electrode may lift the blockade but thermal fluctuations may wash this effect if Ec is not widely superior to kT, with k Boltzmann’s constant and T temperature. Recently, a “nanodamascene” process showing CB up to 130°Cwas reported [1]. This process enables one to build metallic nano-wires interspersed with low-capacitance tunnel junctions. The high temperature operation is related to the capacitance of the tunnel junctions, which is as low as 60-80zF (1zf=1E-21 F), i.e. two orders of magnitude below typical values reported in the literature. We present here the steps we took to demonstrate the feasibility of single electron circuits (SEC) by the nanodamascene process. First, individual control gates were patterned next to the double tunnel junctions. Their presence increases the total capacitance of the islands, decreasing in turn Ec and thus the temperature of operation. However, we successfully fabricated single electron transistors (SETs) with room temperature operation by developing the process to achieve sub-50zF tunnel junctions. These ultra-low-capacitance junctions increased the voltage gain (Gv) of the SETs. Indeed, Gv is given by the ratio Cg/Cd, where Cg and Cd are the gate and the drain capacitances. For a given Cg, low values of Cd increase Gv and this explains that we were able to obtain values of Gv reproducibly superior to unity from electrical characteristics. This is very important, since the Gv>1 criterion is a sine qua non condition for SETs to be combined in circuits, and is rarely met in the literature. We also compared the characteristics of unique devices with those of SETs placed at few tens of nm from each other. Indeed, since CB is an electrostatic effect, the coupling between adjacent devices is of high concern for high density SECs. In these conditions, the bias of the gates influenced the surrounding SETs, depending not only on the inter-SET distance but also on the spatial arrangement of SETs. The impact of these two parameters was also successfully modelled by a finite element analysis of the electric field distribution, which was used to determine the best architectures for low-coupling integration of SETs. We conclude that the nanodamascene process is in good position to become the standard technique for the fabrication of high density room temperature SECs.[1] C. Dubuc, J. Beauvais, D. Drouin, Appl. Phys. Lett., vol. 90, p. 113104 (2007).
3:45 PM - JJ2.4
Infiltration of Microstructured Optical Fibers with Crystalline Semiconductors and Metals: A Novel Integration of Optics and Electronics.
Neil Baril 1 , John Badding 1 , Jacob Calkins 1 , Venkatraman Gopalan 2 , Pier Sazio 3 , Anna Peacock 3 , Adrian Amezcua-Correa 3 , Dong-Jin Won 2
1 Chemistry, Pennsylvania State University, University Park, Pennsylvania, United States, 2 Materials Science and Engineering, Pennsylvania State University, University Park, Pennsylvania, United States, 3 Optoelectronics Research Centre, University of Southampton, Highfield, Southampton, United Kingdom
Show AbstractThe infiltration of a platform designed to transmit light, such as microstructured optical fibers (MOFs), with optoelectronic materials would open the door to numerous new and exciting devices and device architectures. We have developed a high pressure chemical vapor deposition (CVD) technique capable of introducing metals, semiconductors, and insulators into the capillaries of MOFs. MOFs are versatile templates capable of producing high density arrays of capillaries with diameters ranging from tens of microns down to tens of nanometers. Pressures of 20-35 MPa are used to force precursors through the capillaries of the MOFs enabling deposition within nanoscale capillaries. Greater complexity can be introduced by sequential deposition, in this manner radial heterojunctions can be fabricated within the capillaries. The ability to utilize the present knowledge base of CVD chemistry and adapt it to high pressure will further enable the introduction of structural complexity within each capillary. There is tremendous potential within this integrated platform for the development of in-fiber optoelectronic devices with potential applications including light modulation, generation, and amplification.
4:30 PM - **JJ2.5
Integration of Semiconductor and Metal Nanowires.
Ted Kamins 1
1 Quantum Science Research, Hewlett-Packard, Palo Alto, California, United States
Show AbstractNanowires of many different semiconductors and metals have been grown over the past decade, following earlier work as much as 4 decades ago, and interest has continued to increase. However, using nanowires requires that they be positioned to interface with other components of an electrical, optical, sensing, or other system. The nanowires can either be grown in the location where they are to be used, or they can be positioned after growth. Each technique has advantages and drawbacks. Growing the nanowires in place allows the position of the nanowire and its ends to be accurately known. Advanced techniques, such as nanoimprint lithography, can be used to position a catalyst nanoparticle and, consequently, determine where the nanowire will be subsequently grown. Electric fields can also be used to position the catalyst nanoparticle. Some examples will be discussed. On the other hand, decoupling the nanowire growth from the substrate where it is to be used allows a wider range of deposition conditions for nanowire growth without being limited by the devices already formed in the substrate.Semiconductor device and sensing applications have been discussed in most detail, and the needed characteristics of the nanowires are known. However, forming a useful device from the nanowire requires attention to electrical contacts and connections to the remainder of the system. For some applications, such as field-effect sensors, forming a number of nanowires in a specific region provides the needed large surface area with a small volume, but the exact number of nanowires is not critical. In other applications, such as electronic devices, the number of nanowires (generally one) and its properties must be well controlled. Metal nanowires are being discussed as potential interconnections and vias in advanced CMOS, and are likely to be included in the 2007 edition of the International Technology Roadmap for Semiconductors (ITRS). Some of the requirements for this application will be discussed, along with related data from the literature. The importance of specular (elastic) scattering from the sides of the nanowires will be considered.
5:00 PM - JJ2.6
Selective Barrier Layer Perforation in Nanoporous Anodic Alumina for Templated Growth of Electrically Connected Nanowires.
Jihun Oh 1 , Carl Thompson 1
1 Materials Science and Technology, MIT, Cambridge, Massachusetts, United States
Show AbstractOrdered Porous Alumina (OPA) is a nano-structured material that self-orders with domains and can be templated for pore ordering over arbitrarily large areas [1]. Thin films of OPA have been used as templates for growth of metallic and semi-conducting nano-dots, and as both templates and scaffolds for growth of nano-wires and nano-tubes. To incorporate these nanostructures in electrically active devices and systems, it is necessary to have two electrodes at top and bottom of each nanowire. However, OPA has thin insulating barrier oxide and it is desirable to remove the thin barrier oxide at the base of the pores. This barrier oxide is normally removed by chemical etching, by barrier thinning technique, or by reverse bias techniques [2-3]. However, these methods have side effects such as pore widening and difficult implementation for OPA on substrates, with difficulties increasing for small-diameter pores and pores with small spacings.A new method for perforation of the OPA barrier layer has been developed, based on anodization of Al/W multilayer films on substrates. When Al/W multilayer films are anodized and pores approach the Al/W interface, tungsten oxide forms and penetrates the alumina barrier oxide. By selectively etching the tungsten oxide, the barrier oxide can be removed and the base of the pores opened, without etching of the OPA. Using this technique, we demonstrate that it is possible to perforate OPA barrier layers for porous structures with small-diameter pores at small spacings. We also demonstrate use of this approach for templated growth of nanodots and for growth of nanowires in an OPA scaffold but electrically connected to conducting underlayers.[1] R. Krishnan and C. V. Thompson, Adv. Mater 19, 998 (2007).[2] K. Nielsch et al, Advanced Materials 12, 582 (2000).[3] M. Tian et al., Nano Letters 5, 697 (2005)
5:15 PM - JJ2.7
Arrays of Dense sub-10 nm Gold Nanowires for Electronics.
Vaida Auzelyte 1 , Harun Solak 1 , Yasin Ekinci 1 , Robert MacKenzie 2 , Janos Voros 2 , Sven Olliges 3 , Ralph Spolenak 3
1 Laboratory for Micro and Nanotechnology, Paul Scherrer Institut, Villigen Switzerland, 2 Laboratory of Biosensors and Bioelectronics,Institute for Biomedical Engineering, ETH, Zürich Switzerland, 3 Laboratory for Nanometallurgy, Department of Materials, ETH, Zürich Switzerland
Show AbstractLarge arrays of extremely small metal nanowires have tremendous potential for use in nanotechnology applications. Regular nanowire arrays can serve as nanoelectrodes to apply electronic control to address and functionalize selected nanowires with receptor molecules for biosensing applications or for computing and storage in a cross-bar geometry arrangement. Fabrication of the required periodic nanostructures for these and other applications with the required resolution, quality and quantity is a challenge for conventional fabrication techniques. We present novel nanowire fabrication processes that utilize Extreme Ultraviolet Interference Lithography (EUV-IL), shadow evaporation and lift-off techniques. EUV-IL provides large area, dense and uniform resist patterns with periodicity down to 25 nm and high throughput [1]. The line patterns were first created in a photoresist. Perpendicular thermal evaporation of gold and a liftoff process were used to create the nanowire arrays. We obtained lines with widths in the 20-70 nm range through this method. In a modified process, additional shadow evaporation of another metal on top of the resist lines was used to modify the width and profile of the resist lines in order to decrease the spacing between the lines. A lift-off process using these modified line patterns led to the creation of 7 nm wide gold lines with a period of 35 nm. The grain size of evaporated gold defines the roughness of nanowires when the linewidth goes below 10-15 nm. The roughness of these extremely thin gold nanowires becomes a limiting factor in achieving even narrower lines. As many as 5000 regular 1 mm long gold nanowires were fabricated. EUV-IL technique in combination with novel processing techniques has enabled the production of large area nanowire arrays with high throughput. Experimental results on characterization of the electrical and mechanical properties of the nanowires with various linewidth and thicknesses will be presented. 1. H. H. Solak, J.Phys.D: Appl.Phys. 39 (2006) R171
5:30 PM - JJ2.8
A First Step Toward a New Architecture for Li-ion Batteries.
Timothy Arthur 1 , James Mosby 1 , Amy Prieto 1
1 Chemistry, Colorado State University, Fort Collins, Colorado, United States
Show AbstractSecondary lithium-ion batteries are the current power source of choice for portable electronics. However, there are two main limitations to the rate of charging and discharging in these batteries: slow diffusion of Li+ into the anode and the cathode, as well as slow diffusion between the two electrodes. The fabrication of nanowire arrays of both carbon based anodes and several common cathode materials has been shown to dramatically enhance electrode performance because reducing the particle size of the electrode materials, while maintaining electrical contact from grain to grain, reduces the distance the Li+ ions have to diffuse. We will show preliminary results on a battery architecture designed to reduce the Li+ diffusion length from cathode to anode. This architecture is based on a geometry predicted by Long et al. and is designed around a nanowire array of anodes, electrochemically coated with a polymer electrolyte, then surrounded by a cathode matrix. Preliminary electrical measurements on this architecture will be discussed.
5:45 PM - JJ2.9
Vertical Si Nanowire Crossbar Arrays for Electronic-Based Sensing.
E. Akhadov 1 , S. Chikkannanavar 1 , S. Choi 1 , K. Cha 1 , S. Picraux 1
1 , Los Alamos National Laboratory, Los Alamos, New Mexico, United States
Show AbstractWe report on the fabrication and characterization of crossbar arrays containing vertical Si nanowires (NWs) that can be individually addressed electrically. Semiconductor NW arrays with the acuity of a dog’s nose for chemical and biomolecular sensing have the potential for revolutionary impact on detection technology in both commercial and national security applications. However, a roadblock to development of such electronic-based sensors systems has been the realization of practical methods to fabricate electrically connected NW arrays. In our approach we integrate top-down and bottom-up processing to create crossbar arrays of electrically connected, addressable, vertical Si NWs with lateral access for gas/liquid sensing. The bottom layer of the crossbar consists of patterned SOI. Au seeds for subsequent Si NW growth are deposited in patterned arrays (both smaller EBL and larger optical patterned openings are used). Intermediate steps to protect the Au seeds and introduce Si oxide support bars and pads for the top crossbar will be discussed. The Si NWs are grown by the vapor-liquid-solid method (400-600C, silane in an LPCVD system) with NW densities ranging from 1 to several 10’s of NWs in each discrete element. The top metal crossbar (Ni) is then deposited after polymer fill, chemical-mechanical polishing and light plasma etching to planarize the structure and expose the NWs. The polymer fill is subsequently removed to expose the Si NWs. Processing issues include seeded vertical NW growth, control of the number and uniformity of NW density in each element, and formation of the top electrical contact with the NWs. We will report on the processing issues and on preliminary electrical characterization results for 25 element (5 x 5) undoped and p-doped NW arrays.
JJ3: Poster Session I
Session Chairs
Tuesday AM, November 27, 2007
Exhibition Hall D (Hynes)
9:00 PM - JJ3.1
Homoepitaxial Growth of Vertical Si Nanowires on Si(100) Substrate using Anodic Aluminum Oxide Template.
Tomohiro Shimizu 1 , Tian Xie 1 , Volker Schmidt 1 , Jo Nishikawa 2 , Shoso Shingubara 2 , Stephan Senz 1 , Ulrich Goesele 1
1 Microstructure physics, Max Planck Institute, Halle, Weinberg 2, Germany, 2 Graduate Scool of Engineering, Kansai University, Osaka Japan
Show AbstractHomo-epitaxial growth of Si nanowires on Si (100) substrate was accomplished using a combination of anodic aluminum oxide (AAO) template and Vapor-Liquid-Solid (VLS) growth. At first an AAO template was formed on Si substrates, and the alumina barrier layer that existed at the bottom of nanoholes and native oxide on Si substrate was removed by chemical etching without loosing the connection between the AAO template and the Si substrate. Subsequently, catalytic gold nanoparticles for VLS growth of Si nanowires were deposited directly onto the Si substrate at the bottom of AAO nanopores by electrolerss plating. The Si nanowires were synthesized by an ultra high vacuum chemical vapor deposition (UHV-CVD) facility using silane gas as a precursor. Morphology and crystallographic analysis for the nanowires were carried out by scanning electron microscope (SEM) and transmission electron microscopy (TEM). We observed vertically grown epitaxial Si (100) nanowires in the AAO template. In addition, after leaving filled pores, Si nanowires changed their growth direction from [100] to <111>. This result shows that the walls of the pores forced the growth direction of Si nanowires parallel to the direction of the pores, and after filling, the growth direction changes to that of the Si nanowires on an unpatterned Si substrate. This method allows preparing various diameters of nanowires by changing the pore diameter of the AAO templates and synthesizing various crystal orientations of nanowires by changing the crystal orientation of the substrate.
9:00 PM - JJ3.10
Synthesis and Characterization of GaSb/GaAs Heterostructured Nanowires.
Yanan Guo 1 2 , Jin Zou 1 2 , Mohanchand Paladugu 1 2 , Qiang Gao 3 , Hoe Tan 3 , Chennupati Jagadish 3
1 School of Engineering, University of Queensland, Brisbane, Queensland, Australia, 2 Center for Microscopy and Microanalysis, University of Queensland, Brisbane, Queensland, Australia, 3 Department of Electronic Materials Engineering, Australian National University, Canberra, Australian Capital Territory, Australia
Show AbstractTo extend potential applications of semiconductor nanowires (NWs), axial heterostructured NWs have shown their advantages. In fact, the fabrication of heterostructured semiconductor NWs suitable for device applications has been a current challenge. This is particularly true for fabricating lattice mismatched heterostructured NWs, such as GaAs NWs on Si. GaSb-based III-V semiconductors are of great interest for near- and mid-infrared optoelectronic devices. However, it is very challenging to grow high quality GaSb epilayer on large areas, especially on GaAs due to the large lattice mismatch (~7.8%). In our work, all GaAs/GaSb heterostructured NWs were grown on {111}B GaAs substrates with Au particles as nucleation sites with sizes of 10 - 50 nm in a horizontal flow MOCVD reactor at a pressure of 76 Torrs. The substrate coated with Au particles was firstly annealed at 600°C under AsH3 flow for 10 min to desorb surface contaminants and form the eutectic alloy between Au and Ga from the substrate. After cooling down to 450°C, Ga source, trimethylgallium (TMG), was switched on to initiate GaAs NW growth. After 15 mins, TMG was switched off and the reactor cell was cooled down to 425°C under the AsH3 flow. AsH3 was then switched off, and, simultaneously, Sb source (trimethylantimony) and TMG were switched on to initiate the GaSb NW growth. The growth time for GaSb was 120 mins. The molar flow rate of TMG remains the same for both growths. SEM images show that the GaAs/GaSb heterostructured NWs are all well aligned, and each individual NW has a tapered body with a thick column shaped head. In terms of TEM investigation, HRTEM and SAED were employed. SAED patterns were taken from the interfacial regions of the heterostructure. Two sets of <110> diffraction patterns can be clearly distinguished with one set being GaAs and the other being GaSb. By delicate measurements of corresponding atomic planes for GaAs and GaSb, a 7.5±0.3% lattice mismatch was determined, which is consistent with the lattice mismatch between GaAs and GaSb (~7.8%). To understand the fundamental mechanism of the growth of GaSb on the GaAs NW, we noticed the fact that The growth of GaSb is significantly slow. The growth rate for GaSb NWs is about 2% of that for GaAs NWs. Additionally, in all the NWs being investigated, GaSb regions are defect-free. It has been suggested that the planar defects such as twins can cost energy (although very small). This indicates that the growth of GaSb part is governed by thermodynamics, in which case, each growth step requires the system to reach a minimum energy state. Each building atoms (Ga and Sb atoms from the decomposed precursors) finally adopted the most energetically preferable sites. For this reason, the slow nature of the GaSb NW growth is the fundamental mechanism for achieving thermodynamically grown defect-free GaSb NWs.
9:00 PM - JJ3.11
Hyperbranched and Complex Heterostructured Nanowires of PbS and PbSe.
Song Jin 1 , Matthew Bierman 1 , Y. K. Albert Lau 1
1 , University of Wisconsin-Madison, Madison, Wisconsin, United States
Show AbstractThe discovery of multiple exciton generation in nanocrystals of semiconducting PbS and PbSe promises a 800% quantum efficiency limit and 65% theoretical photovoltaic conversion efficiency. We report a chemical vapor deposition synthesis and the structural characterization of hyperbranched single-crystal nanowires of PbS and PbSe. Multiple levels of nanowires grow perpendicularly from the previous generation of nanowires in an epitaxial fashion to produce a dense cluster structure of a complex nanowire network. The flow rate and duration of the hydrogen co-flow in the argon carrier gas during the CVD reactions are found to have significant effect on the morphology of PbS/PbSe grown, from hyperbranched nanowires to micron-sized cubes. No intentional catalyst was employed for the nanowire synthesis, but it is suggested that lead itself might serve as a vapor-liquid-solid (VLS) catalysts for the anisotropic growth of PbS/PbSe. We also discuss the formation of other complex heterostructured nanowires of these materials and conclusively explain the formation mechanism of these intricate and exotic PbS/PbSe network or other complex nanostructures. We will explore these nanostructures in high performance photovoltaic applications and as integrated device architectures.
9:00 PM - JJ3.12
Three-Dimensional Gold Nanobridge Based on Au Nanoparticles.
Shih-Hsien Chao 1 , Chia-Ling Chen 1 , Selvapraba Selvarasah 1 , Mehmet Dokmeci 1
1 , Northeastern University, Boston, Massachusetts, United States
Show AbstractNanoscale materials with their attractive properties such as large surface to volume ratio, high packaging density and long-range order are the building blocks of the burgeoning field of nanotechnology. Moreover, approaches to control the precise location of these materials and to be able to integrate them on to microscale devices are needed to fully exploit the attractive properties of these materials. Several nanoscale manipulation techniques, such as the use of nanomanipulators, nanorobotic systems and pick and place tools have various limitations to serve as high rate large scale assembly methods. In this paper, we present an approach using alternating electric field for the fabrication of three-dimensional (3D) gold nanobridges. Utilizing a micromachined platform built using a 2 mask process and dielectrophoretic (DEP) force, we assemble gold nanoparticles (~10nm) to form 3D nanoscale structures. During assembly, conductive nanostructures can easily be damaged due to high current passing through nanobridges. To prevent this damage, we have designed and incorporated a resistance (1-2K Ohms) in series and hence avoided melting. In addition, the height of the micromachined platform can be adjusted by varying the height of the insulator layer (parylene) and hence can be engineered for other nanomaterials. The assembly process is achieved at room temperature and is compatible with conventional semiconductor fabrication and large scale nanoassembly. Due to the attractive properties of gold nanoparticles, this 3D nanobridge can find potential applications in nanomedicine, nanobiosensors and for in-line characterization of manufactured conductive nanoelements.
9:00 PM - JJ3.13
Synthesis and Characterization of Silver Nanowires Mediated by DNA.
Enrique Samano 1 , Mariana Oviedo 1
1 , CCMC-UNAM, San Ysidro, California, United States
Show AbstractThere is an increase interest in nanotechnology in looking for alternatives for the conventional top-down methods used nowadays in electronics devices, like lithography. One of these bottom-up approaches for designing devices in the micrometer and nanometer scale is based on organic molecules like DNA. The first living cells emerged 3.5 billion years ago. Cells house nanoscale biomachis that perform such specific task as manipulating genetic material by means of DNA. The building block of a nanodevice is a semi-conducting and/or conducting nanowire. This work shows a scheme based on sequence-specific molecular lithography on a DNA substrate to synthesize a wire with a diameter similar to the DNA itself. The method is supported by homologous recombination by RecA protein harnessed on lambda-DNA. The lambda-DNA is digested by the Hind III enzyme. They are purified with a kit of invitrogen to obtain the band corresponding to 2027bp and 2322bp. The homologues recombination with RecA and a dsDNA forms a nucleoprotein. The nucleoprotein is incubated with the dsDNA in a solution of AgNO3 to grow metallic islands which coalesce along of specifics sites of the dsDNA created by the protein to form a continuos silver nanowire. One metallization processing on Si wafers is performed to fabricate nanowires, in contrast to recent published results. The morphology of the nanowire is observed by AFM and SEM. Elementary chemical analysis is done by EDS.
9:00 PM - JJ3.14
Si Nanowires with Diamond Cubic / Diamond Hexagonal Heterostructures Using Cu as Catalyst.
Jordi Arbiol 1 2 , Sonia Estrade 2 , Francesca Peiro 2 , Joan Ramon Morante 2 , Anna Fontcuberta i Morral 3
1 TEM-MAT, Serveis Cientificotecnics, Universitat de Barcelona, Barcelona, CAT, Spain, 2 EME/CeRMAE/IN2UB, Dept. d'Electronica, Universitat de Barcelona, Barcelona, CAT, Spain, 3 Walter Schottky Institute, Technical University of Munich, Garching Germany
Show AbstractOne of most common method for the synthesis of nanowires is the Vapor-Liquid-Solid method (VLS), in which a metal seed catalyst is required to nucleate the growth of nanowires. Different metals have been proposed in literature, and it has been found that silicon crystallization is strongly influenced by which metal is used. Al, In and Au have been claimed to form eutectics with Si, whereas Pd and Ni are accepted to form various silicides with Si which enhance the incorporated Si atoms in a crystallized structure. Many efforts have been centered to find other appropriate metal catalyst compatible with device processing. Among different candidates, copper has been reported to interact in a different way with silicon atoms than those other metals catalysts forming eutectics (gold) and silicides (nickel). As during the process of metal-induced recrystallization of amorphous silicon, the metal atoms appear to enhance crystallization of amorphous silicon. It is believed that the metal atoms are repelled by the c-Si whereas Si atoms from the a-Si migrate into the c-Si side resulting in crystallization. When using Cu as a metal, higher crystallization rates are obtained, in comparison to other commonly used metals, such as Ni and Au. Within this logic, we have recently successfully synthesized silicon nanowires by using Cu as catalyst.In the present work we present a detailed study on the structural defects that silicon nanowires present when synthesized with Cu as a catalyst and discuss the relation with the growth mechanism. Initially, High Resolution Transmission Electron Microscopy measurements that indicate the presence of lamellar twinning along the growth direction are presented. Secondly, the experimental results are analyzed showing that the multiplicity of <111> twinning can generate local changes in the stacking sequence of the diamond structure, leading to a Si diamond cubic / hexagonal heterostructure, which is a complete new result in the case of Si NWs. Finally, a detailed study of the structural properties between both semiconductor phases (cubic and hexagonal) and nanowire morphology are reported and plausible growth models discussed.
9:00 PM - JJ3.15
Synthesis of the Bi doped ZnO Nanowires and its Electrical Properties.
JungHwan Chun 1 , DongEon Kim 1
1 physics, POSTECH, Pohang, kyungbuk, Korea (the Republic of)
Show AbstractBi doped ZnO nanowires were obtained through a vapor transport route at temperatures as low as around 250 °C. The electrical transport of Bi-ZnO nanowires shows n-type semiconducting behavior with a carrier concentration of ~3.5 × 108 cm-1 and an electron mobility of 1.5 cm2/V s. The carrier concentration is one order of magnitude larger than that of undoped ZnO nanowires, indicating that Bi acts as donor rather than the usual acceptor in ZnO films. Near band edge emission in photoluminescence spectrum of Bi-ZnO nanowires is redshifted relative to undoped ZnO nanorods as a result of enhanced carrier concentration. The donor-acceptor pair transition associated with Bi was also observed at 3.241 eV.
9:00 PM - JJ3.16
Preparation and Characterization of Highly Ordered Defect-free Nanowire-inorganic Salt Composites.
Vladimir Novikov 1 , Stanislav Khomich 2 , Alla Stetsik 1 , Sveta Filipovich 1
1 , Joined Institute of Solid State and Semiconductor Physics, National Academy of Sciences of Belarus, Minsk Belarus, 2 , Belarus State Medicine University, Minsk Belarus
Show AbstractNanowires (NWs) are among the key objects in nanotechnology. It was reported that various NWs have been used as components in composite materials and as elements of matrices for electron emitters, catalysts and electrodes for biophysical investigations. In view of broad prospects for the technological application of NWs, methods for the synthesis of NWs and related structures are extensively developed. A novel method of ordered metal nanowire–inorganic salt composites formation was proposed in this work. The method is based on a new phenomenon accompanying the electrolysis of salts, whereby an ordered composite is formed under certain conditions. NWs/salt composite have been synthesized using nonaqueous solutions and under galvanostatic regime of electrolysis. Using this method we obtained the following types of composite: Cu / Cu4 P2O7; Fe / FeCl2; FexCoy / FeCl2* Co Cl2 and Ag/Ca3(PO4)2 Scanning electron microscopy (SEM ) and X-ray diffraction (XRD) were used to characterize the topography and crystalloid structure of these materials .The diameter of nanowires in such types of composites was ranged of 50-500 nm and practically unlimited length (in our experiments the length of wires was abut 10 mm). It is worth to notice that the diameter of wires decrease with current density of deposition process and concentration of surfactant as well . The formation of a spatial order in this system can be explained by minimization of the total interfacial energy of elastic stresses in the growing composite and the surface energy of this structure. We successfully tested these composites as materials for supercapacitors (Fe / FeCl2; FexCoy / FeCl2* Co Cl2 ) and also as material for implanted ceramics - Ag/Ca3(PO4)2
9:00 PM - JJ3.17
Measurement of Silicon Nanorod Carrier Concentrations and Diffusion Lengths.
Michael Kelzenberg 1 , Michael Filler 2 , Brendan Kayes 2 , Morgan Putnam 3 , Harry Atwater 2
1 Electrical Engineering, California Institute of Technology, Pasadena, California, United States, 2 Applied Physics, California Institute of Technology, Pasadena, California, United States, 3 Chemical Engineering, California Institute of Technology, Pasadena, California, United States
Show AbstractSilicon nanowire arrays have the potential to enable low-cost, high efficiency solar cells via efficient radial minority carrier collection in an optically thick layer of vertically-oriented nanowires [1]. Optimal photovoltaic performance enhancement for low-minority carrier-lifetime materials is predicted to occur when nanowire diameter is less than or equal to minority carrier diffusion length, and when surfaces and junctions are well passivated.Silicon nanowires for photovoltaic applications were grown on silicon substrates by a vapor-liquid-solid (VLS) chemical vapor deposition (CVD) process from SiCl4 or SiH4 diluted in argon using gold catalyst particles. Straight, single-crystalline silicon nanowires were grown with diameters of 300 nm to 1.2 μm and lengths of 1 to 100 μm. Individual nanowires were deposited onto an insulating substrate and contacted using optical lithography and metal evaporation. Ohmic contacts, verified by four-probe measurements, were obtained using annealed Al contacts. Scanning photocurrent microscopy (SPCM) was performed on unintentionally-doped single nanowires using confocal and near-field optical microscopy (NSOM) laser excitation at 488 and 650 nm.Current-voltage measurements performed in a four point probe configuration on individual nanowires indicate that bulk resistivities from 0.04 Ω-cm to 7 kΩ-cm can be obtained by the introduction or omission of dopant gasses during nanowire growth, or by conventional dopant deposition and diffusion following growth. These correspond to electrically-active doping concentrations from approximately 1012 cm-3 to 1018 cm-3. Back-gated measurements were performed to determine the carrier type for unintentionally doped nanowires. Photocurrent collection was found to be influenced by photovoltaic carrier collection due to band bending at either contact. A one-dimensional charge transport model of drift, diffusion, and single-τ recombination is fit to the measured photocurrent profiles to extract effective carrier diffusion lengths, which are on the order of microns, corresponding to effective carrier lifetimes of a few nanoseconds. Effective diffusion lengths are approximately equal to nanowire diameter, indicating that carrier lifetimes are dominated by surface recombination. This result is supported by photoluminescence (PL) data, in which silicon band-edge emission is observed only following surface passivation by HF etch and dry thermal oxidation, and where carrier lifetimes are less than 10 ns.[1] Kayes, Atwater, and Lewis, J. Appl. Phys., 97, 114302 (2005).
9:00 PM - JJ3.18
Colloidal Synthesis of In/InP Nanoneedles and Their Use as Schottky Diodes.
Christian Klinke 1 , Tim Strupeit 1 , Andreas Kornowski 1 , Horst Weller 1
1 Institute of Physical Chemistry, University of Hamburg, Hamburg Germany
Show AbstractSemiconducting nanostructures are promising candidates for future electronic devices, not least due to their ability to accommodate whole device structures in one nano-object. Additionally, the electronic properties of those nanostructures can be tailored by means of size and dimensionality due to quantum confinement effects. The evolution of the confinement has been demonstrated by means of optical spectroscopy for colloidal zero- and one-dimensional CdSe quantum structures. The one-dimensionality of nanorods affords new properties like the polarized emission under photoexitation and electroluminescence. Their non-linear properties, their bandgap in the visible range, their easy integratability into device structures make InP nanowires ideal candidates as building blocks for novel types of nanowire-based photodevices.In II-VI semiconductor nanowire syntheses (e.g. CdSe) the growth is controlled by the amount and type of added ligand molecules - the proper choice allows the synthesis of rods, dots, or tetrapots. Unlike the preferential growth in wurtzite-like nanoparticles III-V semiconductors, however, possess a cubic zincblende lattice structure, i.e. the required chemically different surfaces are not given. Instead, another growth mechanism, the solution-liquid-solid (SLS) mechanism, can be exploited. A liquid metal droplet acts as seed and catalyst for the crystal growth. This mechanism was found for a few systems establishing III-V semiconductor rods and wires. The used seeds are gold, bismuth, silver or indium. Usually such methods are two-step syntheses. In a first step the metal seeds are produced by decomposing an organometallic precusor. The second step is a dehalosylation reaction of a metal salt (InCl3, InAc3) with tristrimethylsillyl phosphine in presence of the metal seeds in a high-boiling coordinating solvent like trioctyl phosphine (TOP) or trioctylphosphin oxide (TOPO). With this reaction it is possible to synthesize nanowires and nanorods of some microns in length. Recent publications focused on the control of the diameter of the metal seeds, since the diameter of the semiconductor nanowires is determined by the diameter of the metal seeds. Thus, the optical properties of InP nanowires can be adjusted by manipulating the seed size allowing the growth of InP with dimensions in a size range below the exciton Bohr radius.In the presented work we demonstrate a new reaction route for the synthesis of InP nanowires of several micrometers in length. We discuss two different growth mechanisms which depend on the reaction temperature. The length of the wires is tunable by the reaction time. We characterize the items by electron-microscopical and spectroscopical means. Their specific design with an In head and an InP tail represents a ready-made electrical device and allowed using them as Schottky diodes. The electrical analysis rendered the typical asymmetric diode characteristic.
9:00 PM - JJ3.19
Horizontal Porous Alumina Finger Arrays as Growth Templates for Large Area Single Nanowire Devices.
Ying Xiang 1 , Woo Lee 2 , Kornelius Nielsch 2 , Gerhard Abstreiter 1 , Anna Fontcuberta i Morral 1
1 , Walter Schottky Institut, Garching Germany, 2 , Max-Planck-Institut für Mikrostrukturphysik, Halle Germany
Show Abstract1D nanostructures have the potential to revolutionize broad areas of nanotechnology, such as electronics, sensing, and information technology. As building blocks for future applications, however, one of the biggest challenges in the study of these 1D nanostructures is their controlled synthesis and organization on a substrate. An elegant way to perform this is the membrane-based synthesis, also called template growth. Template growth of nanowires has been extensively studied over the past few years, since it provides compactness and uniformity which are necessary for reproducible device fabrication based on arrays of individual nanoobjects. Especially porous anodic alumina (PAA) film has attracted much interest due to the high aspect ratio, high level of ordering, high pore density, uniformity and low cost. PAA templates are commonly obtained with the pores oriented vertically on a substrate [MAS, LEE]. Unfortunately this method is hardly compatible with the mainstream Si planar processing technology.Here, we present a novel approach to synthesize PAA parallel to the substrate surface [COJ]. Using our sample design and fabrication method horizontally aligned PAAs with few nanopores or single nanopore can be fabricated, enabling the application for single or few nanowire devices. The horizontally aligned, well-defined nanopores are fabricated by anodic oxidation of aluminum stripes and aluminum fingers using two-step anodization. Using different electrolytes and different anodization voltage, pore diameters between 15 nm and 130 nm, and interpore distances between 45 nm and 250 nm have been obtained. The pore diameter is linearly dependent on the anodization voltage, but slightly differently from that of typical vertical anodization. Due to the anisotropy of our material system, the geometry is slightly changed from the typical honeycomb structure. By decreasing the finger widths down to 750 nm, the pore diameter and the interpore distances remains constant, proving that our fabrication approach enables the fabrication of single and few wire devices. Using these templates, metal wires are grown via pulsed electro-deposition. Electrical transport measurements at room temperature are presented. As a result of horizontal alignment and separation of the individual nanowires, our approach is promising for nanoelectronics and sensing.Reference:[LEE] W. Lee, R. Ji, U. Gösele and K. Nielsch, Nature Materials 5, 741-747 (2006)[MAS] H. Masuda and F. Fukuta, Science 268, 1466 (1995)[COJ] C.S. Cojocaru, J.M. Padovani, T. Wade, C. Mandoli, G. Jaskierowicz, J.E. Wegrowe, A. Fontcuberta i Morral and D. Pribat, Nano Letters 5(4), 675-680 (2005)
9:00 PM - JJ3.2
Enhancing the Electrical and Optoelectronic Performance of Nanobelt-Devices by Molecular Surface Functionalization.
Chang Shi Lao 1 , Yi Li 1 , C. Wong 1 , Zhong Wang 1
1 Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractEnhancing the Electrical and Optoelectronic Performance of Nanobelt-Devices by Molecular Surface FunctionalizationChangshi Lao, Yi Li, C.P. Wong, Z.L. WangSchool of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0245Self-assembled thin molecular-layer has demonstrated the effectiveness in modifying surface physics and properties of metal and metal oxide materials. It has been used as a functional group in different nanowire based devices for chemical and biological sensing. In this presented work, we have explored a novel approach of using self-assembled thin monomolecular-layer on nanowire surface for improving the electrical and optoelectronic performances of nanowires (NWs) and nanobelts (NBs). A few kinds of molecules with different terminal groups (stearic acid, lysine, dodecanedioic acid, mercapto-acetic acid and perfluorotetradecanoic acid) were tested as functional layers and their performances were compared. For ZnO NBs with molecular coating, the contact properties and the carrier mobility were greatly enhanced. More importantly, the optical and gas sensing performance of these small organic molecule functionalized ZnO were also greatly enhanced. Details of achievements with coating of the molecular layers are listed as follows. First, due to energy band tuning and surface modification, coating molecule layer has changed a Schottky contact into an Ohmic contact without sophisticated deposition of multilayered metals the conductance. This enhanced magnitude of the transport current (i.e. conductivity) by six orders of magnitude; Secondly, a functionalized NB showed negative differential resistance which is a useful electron transport phenomenon in molecular devices; Thirdly, these functional layers huge improved photoconductivity and gas sensing response; Lastly, the functionalized molecular also greatly reduced the etching rate of the ZnO NBs by buffer solution, largely extended their life time for biomedical applications. This study demonstrates a new approach for improving the physical properties of oxide NBs and nanowires for device applications and also is a simple and cost-effective method for improving the performance of oxide nanowire/nanobelt based devices.[1] Chang Shi Lao, Yi Li, C.P. Wong, Z.L. Wang “Enhancing the Electrical and Optoelectronic Performance of Nanobelt-Devices by Self-Assembled Monolayer Surface Functionalization”, Nano Letters, 7 (2007) 1323-1328.[2] for more details: http://www.nanoscience.gatech.edu/zlwang/
9:00 PM - JJ3.20
Investigation of the Structural Properties of Li+{Mo3Se3}- Nanowires, Nanowire Networks and Ion Exchanged X+{Mo3Se3}- Networks by High Resolution TEM and Solution Characterisation Techniques.
John Sheridan 1 , A. Heidelberg 1 , D. Brougham 2 , P. Nellist 3 , D. Ozkaya 4 , John Boland 1
1 CRANN and School of Chemistry, Trinity College Dublin, Dublin Ireland, 2 School of Chemical Sciences, Dublin City University, Dublin Ireland, 3 Dept of Materials Science, Oxford University, Oxford United Kingdom, 4 , Johnson Matthey, Sonning Common, Reading United Kingdom
Show AbstractWith the limits of current silicon processing techniques drawing nearer, the “bottom up” approach for future technologies has become a focus of major research worldwide. This requires detailed studies of possible replacement materials for interconnects and the active components of nanoscale devices. To this end we present results for the inorganic nanowire system, Li+{Mo3Se3}- and of its ion exchanged network counterparts, X+{Mo3Se3}-, by a variety of techniques, including high resolution TEM and its associated spectroscopies, AFM, rheology and dynamic light scattering of solutions.Li+{Mo3Se3}- forms quasi-1D crystals that can be dissolved in polar solvents such as DMSO. Dispersing these solutions on surfaces via drop casting or spin coating yields single wires (0.6nm), bundles of nanowires and nanowire networks. Rheometry solution data is consistent with highly anisotropic particles or wires and light scattering measurements indicate a polydispersed size distribution. HR-TEM shows that networks of this material are continuous and not comprised of assemblies of individual wires. The mechanism of network formation is discussed based on cryogenic TEM imaging of nanowire solutions.By replacing the Li+ counter ion with a fluorinated organic ligand, dense networks of X+{Mo3Se3}- can be obtained. HR-TEM reveals the inter-wire spacing to be ligand dependent and that individual nanowires within these networks persist over large length scales. Electrical measurements of these networks show that their susceptibility to corrosion in moist air is much less than that of uncoated wire networks, and resistance vs. temperature measurements show a semiconducting like behaviour with a phase transition noted at low temperatures.
9:00 PM - JJ3.21
Bridged ZnO Nanowires Across Trenched Electrodes.
Pu-Xian Gao 1 3 , Jin Liu 3 , J. Lee 2 , Zhong Wang 3
1 Institute of Materials Science & Department of Chemical, Materials and Biomolecular Engineering, University of Connecticut, Storrs, Connecticut, United States, 3 School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States, 2 , Sandia National Laboratories, Livermore, California, United States
Show AbstractUsing a hydrothermal synthesis approach, large scale and laterally bridged nanowires (NWs) have been successfully grown across trenched Au/Si, Au/SiO2/Si, and ZnO/Si electrodes. This technique shows a low temperature (80oC) approach for growing ZnO nanowires on a pre-patterned substrate, showing its potential for integrating with silicon based technology. The I-V characteristics of the nanowires have been measured and their non-linear behavior has been analyzed. The bridged nanowire arrays could be useful for fabricating gas, chemical, or biochemical nanosensor arrays.
9:00 PM - JJ3.22
Nanowire Self-Assembly and Integration.
Zhiyong Gu 2 , David Gracias 1
2 Chemical Engineering, University of Massachusetts , Lowell, Massachusetts, United States, 1 Chemical and Biomolecular Engineering, Johns Hopkins University, Baltimore, Maryland, United States
Show AbstractWe describe the fabrication and assembly of multisegmented nanostructures using electrodeposition in nanoporous templates. We have focused on structures that can be assembled into 3D integrated structures for electronics, sensing and fluidic applications. We have utilized several forces to direct assembly of the nanowires including surface tension, magnetic and dielectrophoretic. We also demonstrate a new strategy to bond nanowires (NWs) using fluidic interfacial diffusion bonding of gold (Au), The strategy was used to form very large scale, electrically interconnected three dimensional, NW networks, composed of both homogeneous and heterogeneous (multisegmented) NWs. The size of the networks ranged from tens micrometers to millimeters. We have measured the electrical characteristics of the networks and explored one application of the networks in 3D spatial chemical sensing.
9:00 PM - JJ3.23
Controlled, Highly Aligned Growth of Vertical GaN Nanowires on Sapphire.
George Wang 1 , Qiming Li 1 , J. Randall Creighton 1
1 , Sandia National Laboratories, Albuquerque, New Mexico, United States
Show AbstractWe report the Ni-catalyzed growth of very high-density (up to 150 per square micron) and highly aligned vertical GaN nanowires on unpatterned r-plane sapphire substrates. The degree of alignment and density was found to be highly sensitive to the growth temperature and Ni catalyst film thickness, particularly as the thickness was decreased below 1 nm, down to submonolayer thicknesses. The growth is highly controllable and uniform over very large areas. Interestingly, an investigation of the initial stage growth of the nanowires indicates a significant number of tilted nanowires in addition to the vertical nanowires, the density of which sharply decreases with growth time. We propose and present a collision-based model to explain the sharp decay in the density of tilted nanowires due to collisions with vertical nanowires during growth. The results show that at high nanowire densities, tilted nanowires can be rapidly selected out via this mechanism.
9:00 PM - JJ3.24
Single Potential Electrodeposition of Cu2Sb: Toward the Fabrication of Nanowire Arrays of a Promising Anode Material.
James Mosby 1 , Amy Prieto 1
1 Department of Chemistry, Colorado State University, Fort Collins, Colorado, United States
Show AbstractSecondary lithium-ion batteries are the current power source of choice for portable electronics and account for approximately 63% of the portable battery sales world wide. Improvements in the energy capacity, rate capabilities, and cycle life of secondary lithium-ion batteries have been pursued by investigating new materials and material morphologies. We are focused on nanowires of anode materials, in particular in developing synthetic methods for materials with strong structural relationships between the lithiated and delithiated compounds. One such example is Cu2Sb, which has been shown to exhibit smaller volume changes upon cycling and hence a longer cycle life. We have developed a single potential electrodeposition of Cu2Sb thin films and nanowires from aqueous citrate solutions at room temperature. This facile synthesis produces polycrystalline Cu2Sb (without annealing) directly on a copper current collector, which is then ready for battery testing. We have electrodeposited Cu2Sb into porous alumina templates, resulting in ordered arrays of nanowires. The increased surface area of the nanowires relative to bulk films is expected to further improve the cycle life and improve the rate capability of this promising anode material. We are in the process of applying this single potential deposition procedure to other intermetallics of interest as anode materials. The mechanism of electrodeposition and subsequent material characterization will be presented.
9:00 PM - JJ3.25
Synthesis of Si Nanowires Using Pt Catalyst and Structural and Compositional Modulation.
Han Nah Jeong 1 , Tae Eon Park 1 , Ungkil Kim 1 , Myoung Ha Kim 1 , Ryong Ha 1 , Han Kyu Seong 1 , Heon Jin Choi 1
1 , Yonsei University , Seoul Korea (the Republic of)
Show AbstractSilicon nanowires have novel properties such as high aspect ratio, single crystallinity and CMOS compatibility. As a result of these properties, Si nanowires are one of the most outstanding materials which may serve as the building blocks for the next generation of electronic devices. In most case, Si nanowires are grown by a vapor-liquid-solid (VLS) mechanism with Au as a catalyst. However, Au has limitations in some aspects of structural and compositional modulation of Si nanowires. We explored synthesis of Si nanowires with the use of Pt as a catalyst. The growth was performed in a CVD furnace. Small pieces of Si wafer coated with Pt with thickness of several nanometers were located in a horizontal furnace. With SiCl4 as precursor gas, Si naowires were grown at 1000 degrees Celsius with various range of holding time. The lengths of nanowires were controlled by holding time. In case of 10-hour holding, up to centimeter-scaled Si nanowires were fabricated. The growth rate of Si nanowires using both Au and Pt catalyst were measured at 1000 degrees Celsius with 5~30 minutes of holding time. According to our experiment, the growth rate of Si nanowires using Pt catalyst was 2~3 times faster than those using Au catalyst. Interestingly, single crystalline Si nanoribbons could be fabricated with assistance of Pt. They had a few μm long and nm scaled width. In addition to structural modulation, compositional modulation could be carried out with Ge alloying in Si nanowires. In our experiments, Si nanowires can be homogeneously alloyed with Ge up to 30 %. This indicates that Pt forms an alloy with both Si and Ge and simultaneously acts as a catalyst for these two components. In summary, we confirmed that Pt works on growth and engineering of Si nanowires as a catalyst.
9:00 PM - JJ3.26
Fabrication and Electrical Properties of the ZnO Single Nanowire Device.
Seung Eon Moon 1 , Eun Kyoung Kim 1 , Hong-Yeol Lee 1 , Jonghyurk Park 1 , So-Jeong Park 1 , Jun-Hyuk Kwak 1 , Sunglyul Maeng 1 , Kang-Ho Park 1 , Sang Woo Kim 2 , Hyun-Jin Ji 3 , Gyu-Tae Kim 3
1 , ETRI, Daejeon Korea (the Republic of), 2 , Kumoh National Institute of Technology, Gumi Korea (the Republic of), 3 , Korea University, Seoul Korea (the Republic of)
Show AbstractA single ZnO nanowire device was fabricated by electron beam lithography and its current-voltage characteristics were recorded with varying the atmospheric pressure to test the possible applications as a chemical gas sensor. Vertically well-aligned ZnO nanowires were grown on GaN epilayer on c-plane sapphire via a vapor-liquid-solid (VLS) process by introducing an Au thin film (3 nm) as a catalyst. Semiconducting nanowire devices were fabricated using photolithography and e-beam lithography, and their electrical properties were studied. To realize the reliable device operation which is a key factor for a chemical sensor, the contact resistance should be optimized. Here, we studied the contact resistance problem using scanning probe microscopic tool to characterize surface potential behaviors. To overcome contact resistance problem, post thermal process was adapted to the nanowire device. And atmospheric pressure and other environmental gas dependent electrical properties of the ZnO nanowire device were studied for chemical sensor application.
9:00 PM - JJ3.27
Portable Environmental Gas Sensor using Metal-Oxide Nanowires.
Eun-Kyoung Kim 1 , Seung Eon Moon 1 , Hong-Yeol Lee 1 , Jonghyurk Park 1 , So-Jeong Park 1 , Jun-Hyuk Kwak 1 , Sunglyul Maeng 1 , Kang-Ho Park 1 , Sang-Woo Kim 2 , Tak-Hee Lee 3
1 , ETRI, Daejeon Korea (the Republic of), 2 , Kumoh National Institute of Technology, Gumi Korea (the Republic of), 3 , Gwangju Institute Science and Technology, Gwangju Korea (the Republic of)
Show Abstract9:00 PM - JJ3.28
Solution Based Synthesis and Optical Characterization of CdS Nanowires.
James Puthussery 1 , Aidong Lan 1 , Thomas Kosel 2 , Masaru Kuno 1
1 Dept of Chemistry and Biochemistry, University of Notre Dame, Notre Dame, Indiana, United States, 2 Electrical Engineering, University of Notre Dame, Notre Dame, Indiana, United States
Show Abstract One dimensional systems such as nanowires and nanotubes have attracted considerable attention due to their unique charge transport properties which make them potential candidates in nanoelectronics. The synthesis of nanowires using solution-liquid-solid (SLS) synthesis offers improved control over nucleation and their subsequent growth. We carried out the synthesis of cadmium sulfide (II-VI) nanowires using SLS, which employs au/Bi core shell nanoparticles as catalyst and temperatures below 300 °C. The resulting nanowires have diameters around 10 nm and length of the wires varied from 1 to 25 μm. X-ray diffraction measurements and high resolution TEM images clearly show that the wires are highly crystalline and both wurtzite and zinc blende phases are present along the wires. It is also observed that although the diameter of the wires is greater than the exciton Bohr radius of CdS (aB=2.9 nm), the absorption measurements show a significant blue shift of 200 meV, compared to the band edge absorption of bulk material. Interestingly, CdS nanowires exhibit band edge emission at room temperature with the peak centered at 487 nm and the quantum yield of emission is measured to be of 1%. The NW emission, as opposed to quantum dot emission is further confirmed by polarization anisotropy measurement and the anisotropy value is calculated to be 0.76(σ=0.06). The high anisotropy value confirms the one dimensional origin of the optical signal consistent with large aspect ration of CdS nanowires. The transient absorption of CdS NWs is recorded using femtoseond transient absorption spectrometer and the bleaching at 482 nm is in good agreement with the spectral position of the first transition in the linear absorption spectrum. The rate of recovery of bleaching can be fit to biexponential curve with lifetimes 34 ps and 100 ps.
9:00 PM - JJ3.29
Pressure Dependent Electrical Properties of Vanadium Pentoxide Nanowires.
Han Young Yu 1 , Byung Hoon Kim 1
1 Nano-bio electronic device team, ETRI, Daejeon Korea (the Republic of)
Show AbstractTime-dependent current characteristics of V2O5 (VO) have been investigated as a function of pressure with the various gases: air, nitrogen, oxygen, helium, and argon. The main mechanism adsorption of gases is physisorption, which is related to the layer structure of VO. The electrical detection of the pressure-dependent structural deformations of the vanadium pentoxide nanowire was done using the conventional field effect transistor configuration composed of the source and drain electrodes of normal metals, the conductance channel of vanandium pentoxide nanowire, and the gate oxide of silicon dioxide with increase of the injected gas pressure to a chamber. For the applied voltage the current paths are generated through the nanowires and the interstitial layer of water, and the conducting channel is modified with the transition from nanowire to water or vice versa by not only the injection of the gases, but the increase of the ambient pressure. The mechanism of the conductance variation is ascribed to the modulation of distance between the layers of vanandium pentoxide crystal, substitutional packing of the interstitial area by injected gases, and the switching of the conducting paths by the gases. The adsorption of gases is related to physisortption and the structural properties of the VO layer. Furthermore, using the intrinsic properties originated from the structural modification by the injection of the gases, the vanadium pentoxide nanowire device can be used as a good pressure gauge for various gases.
9:00 PM - JJ3.3
Polymer Functionalized Piezoelectric-FET as Humidity/Chemical Nanosensors.
Chang Shi Lao 1 , Qin Kuang 1 , Myung-Chul Park 2 , Yulin Deng 2 , Zhong L. Wang 1
1 Materials Science and Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States, 2 School of Chemical and Biomolecular Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractPolymer Functionalized Piezoelectric-FET as Humidity/Chemical NanosensorsChang Shi Lao, Qin Kuang, Myung-Chul Park, Yulin Deng and Zhong L. WangSchool of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0245 USAMost recently, a new research direction termed of nanopiezotronics has been coined based on the piezoelectric-semiconducting coupled properties of ZnO NWs and NBs for fabricating novel and unique electronic components. [1,2] Prototype devices such as piezoelectric nanogenerator, piezoelectric field-effect transistors (PE-FET) and diodes are demonstrated. In this presented work, we report the first demonstration of humidity/chemical sensor based on PE-FET, which also contributes as a new component of nanopiezotronics. The devices were based on a single-side coated ZnO NB functionalized with multi-layers of polymers. The functionalization process was realized with electrostatic self-assembly method. By dipping the substrate into cationically charged PDADMAC solution and anionically charged PNIPAM solution with different cycles, we can coat polymers onto ZnO NB with control of different layers. Upon exposure of high humidity moisture, the as-functionalized polymers swell and produce an asymmetric strain across the ZnO NB, which bends the ZnO NB. In return, the deformation of ZnO NB generates a piezoelectric field across the NB which serves as a gate for controlling the flow of current along the NB. This is the working principle of the polymer functionalized PE-FET. It is a brand-new way in fabrication of nanopiezotronic devices and might bring a broad future of potential applications. Here, in this paper, we also demonstrated the possible application of use this polymer functionalized PE-FET as a chemical sensor to monitor the phase transition of PNIPAM upon temperature increase in aqueous solution. PNIPAM undergoes hydration and dehydration in aqueous solution when temperature is increased. By monitoring the current changed across NB, we can observe the phase transition of the polymer in situ. With the increase precise in polymer functionalization control and device fabrication, this polymer functionalized PE-FET might bring an alternative option in nanodevice fabrications to generate and convert energies between two different formats, which adds an attracting and promising component to the family of nanopiezotronics. [1]Z.L. Wang “The new field of Nanopiezotronics”, Materials Today, 10 (No. 5) (2007) 20-28.[2]Z.L. Wang “Nano-piezotronics”, Adv. Mater., 19 (2007) 889-992.[3] for more details: http://www.nanoscience.gatech.edu/zlwang/
9:00 PM - JJ3.30
Pulsed PECVD Growth of Silicon Nanowires on Various Substrates.
David Parlevliet 2 , John Cornish 2
2 Physics & Energy Studies, Murdoch University, Perth, Western Australia, Australia
Show AbstractSilicon nanowires of high density and high aspect ratio similar to those shown in the literature (Hofmann, Ducati et al. 2003; Niu, Sha et al. 2004) have been grown using a variation of Plasma Enhanced Chemical Deposition (PECVD) known as Pulsed PPECVD (PPECVD). A number of different materials have been trialled as substrates for the growth of silicon nanowires by this technique. This paper details the differences in nanowire morphology and density with the use of different materials as substrates. The nanowires grown in this work were produced via the VLS mechanism using gold as a catalyst.Deposition was carried out in a parallel plate PECVD chamber at temperatures up to 350°C, in an atmosphere of semiconductor grade silane. A square wave was used to modulate the 13.56MHz RF power. A 100nm gold catalyst layer was used for all samples. Substrate materials included polished n-type Si substrates with various orientations, stainless steel, copper, glass and ITO coated glass which was either clean or pre-coated with a thin layer of amorphous silicon. Some crystalline substrates were given an HF etch after the gold deposition (3nm) and immediately before the growth of silicon nanowires to remove the silicon oxide over layer as recommended by Jagannathan, Nishi and co-workers (2006) to aid epitaxial growth (Jagannathan, Nishi et al. 2006). Scanning electron microscopy was used to compare the growth and morphology of silicon nanowires on these substrates.Due to the thickness of the gold catalyst layer used there was little evidence of aligned or epitaxial growth upon the crystalline silicon substrates despite HF etching. Copper and stainless steel substrate were found to be unsuitable substrates for the growth of silicon nanowires at the deposition temperature used, with only a few nanowires being observed. The nanowires observed on these substrates were of an unusual morphology compared to those grown on crystalline silicon or glass.Of the glass samples it was found that nanowires grew with higher density on the ITO coated glass substrates. The reason for this was proposed to be the presence of a conductive layer immediately preceding the gold catalyst layer. Samples where a poorly conducting amorphous silicon layer was interposed between the ITO and Au layers were found to have a lower density of nanowires. Of all the substrates trialled, ITO coated aluminosilicate glass was found to be the most effective substrate to produce high density silicon nanowires.Hofmann, S., C. Ducati, et al. (2003). "Gold catalyzed growth of silicon nanowires by plasma enhanced chemical vapor deposition." Journal of Applied Physics 94(9): 6005-6012.Jagannathan, H., Y. Nishi, et al. (2006). "Effect of oxide overlayer formation on the growth of gold catalyzed epitaxial silicon nanowires." Applied Physics Letters 88(10): 103113-1.Niu, J., J. Sha, et al. (2004). "Tiny silicon nano-wires synthesis on silicon wafers." Physica E 24(3-4): 328-32.
9:00 PM - JJ3.32
Growth of SnO2-In2O3 Hetero Nanostructures.
S. Joon Kwon 1 , Dong-Wan Kim 1 , In-Sung Hwang 1 , Kyoung-Soo Park 1 , Jae-Gwan Park 1
1 Nano Science and Technology Division, Korea Institute of Science and Technology, Seoul Korea (the Republic of)
Show AbstractWe report on the growth of hetero nanostructures composed of SnO2 and In2O3. The single-crystalline hetero nanostructures were formed by thermal evaporation accompanied by vapor-liquid-solid (VLS) process catalyzed by Au. The difference between the transport properties of the precursors of SnO2 and In2O3 led to the formation of the hetero structures. We observed that there exists a distinguished structural evolution of the hetero nanostructures. In the initial stages, nanowires were formed, and the core was SnO2 covered by a thin SnO2-In2O3 alloy layer. In the final stages, periodic array of In2O3 nuclei were formed on the surface of the SnO2 core, and the formation of SnO2-In2O3 core-shell nanowires, subsequently. The structural evolution of the hetero nanostructruers were thoroughly analyzed and electronic properties were also examined.
9:00 PM - JJ3.33
Memory Characteristics of Top-gate ZnO Nanowire Field-effect Transistors with Floating Gate Nodes of Au Nanoparticles.
Donghyuk Yeom 1 , Jeongmin Kang 1 , Changjoon Yoon 1 , Byoungjun Park 1 , Kihyun Keem 1 , Dong-Young Jeong 1 , Mihyun Kim 1 2 , Eui Kwan Koh 2 , Sangsig Kim 1
1 , Department of Electrical Engineering and Institute for Nano Science, Korea University, Seoul Korea (the Republic of), 2 , Nano Bio System Research Team, Seoul Center, Korea Basic Science Institute, Seoul Korea (the Republic of)
Show AbstractNanowire-based field-effect transistors (FETs) with floating gate nodes of nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to both their excellent transportation of charge carriers in the nanowire channels and outstanding capability of charge trapping in the nanoparticles. In this work, top-gate single ZnO nanowire-based FETs were fabricated and characterized, after the formation of Au nanoparticles on Al2O3-coated ZnO nanowire channels using thermal evaporation and rapid thermal annealing processes. I-V curves taken from the top-gate single ZnO nanowire-based FETs with the Au nanoparticles embedded in the Al2O3 gate layers show clockwise hysterisis loops with ΔVth = 1.9 V, resulting from the tunneling of the charge carriers from the nanowire channels into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop. The observation reveals that the influence of oxide trap charges or mobile ions is negligible and that the charge storage effect mainly comes from the nanoparticles present on the surface of the Al2O3–coated nanowire. Our experimental results demonstrate that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are one of promising devices for the application in the nonvolatile memory devices of next generation.
9:00 PM - JJ3.34
Charge Transfer Mechanism in Hybrid Systems Composed of Semiconductor Nanoparticles and Single Nanowires.
Hojun Seong 1 , Changjoon Yoon 1 , Donghyuk Yeom 1 , Kyoungah Cho 1 , Kihyun Keem 1 , Miyoung Park 2 , Dongmok Whang 2 , Sangsig Kim 1
1 Department of Electrical Engineering and Institute for Nano Science, Korea University, Seoul Korea (the Republic of), 2 Department of Advanced Materials Science and Engineering. SKKU Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon Korea (the Republic of)
Show AbstractCharge transfer mechanism from nanoparticles to nanowires in hybrid systems composed of semiconductor nanoparticles and single nanowires were investigated by photocurrent and photocurrent spectra. Two different hybrid systems were prepared in this work; a single ZnO nanowire channel attached with ZnO nanoparticles and a single Si nanowire channel attached with CdTe nanoparticles. The photocurrent measured in these hybrid system excited by the 325 nm wavelength light from a HeCd laser is larger by several hundred times in intensity, compared with single nanowires without nanoparticles. In contrast, any photocurrent was not observed for systems composed of only nanoparticles, indicating that photo-excited charge carriers are not able to transport in these systems. In the photocurrent spectra taken from the two different hybrid systems, excitonic absorption bands originating from the nanoparticles were observed. The observation reveals that charge charriers in the nanoparticles excited by light are transferred efficiently to the nanowire channels. Charge transfer mechanism will be discussed in detail on the basis of band diagrams of the hybrid systems.
9:00 PM - JJ3.35
Heterostructures of Transition Metal Oxide Nanowires.
Takeshi Yanagida 1 , Kazuki Nagashima 1 , Aurelian Marcu 1 , Hidekazu Tanaka 1 , Tomoji Kawai 1
1 ISIR-Sanken, Osaka University, Osaka Japan
Show AbstractOne-dimensional nanowires have gained attention recently because of their potential applications in nanoscale devices and sensors [1]. Transition metal oxides exhibit the rich variation of the physical properties, such as superconductivity, ferromagnetism and ferroelectricity. Such rich functionalities might expand the application range of nanowire devices. Principally, there is a limitation to create diverse transition metal oxide nanowires. “Oxide-Heterostructures in Nanowires” would be one of ways to overcome such difficulties since many oxide heterostructures in thin film forms have been realized and proved to be useful and powerful [2-8]. Here we report heterostructures of transition metal oxide nanowires via controlling precisely “core” magnesium oxide nanowire morphologies as “nanoscale substrate” [9-11] and depositing “shell” iron-, and/or titanium- oxides onto the core nanowires. The oxide heterostructures in nanowires were fabricated by in-situ pulsed laser deposition (PLD) technique. Magnesium oxide “core” nanowires were synthesized on MgO (001) single crystal by Au catalyst-assisted PLD. Controlling appropriately the growth atmosphere, including temperature, pressure, catalysts, and others, was found to be crucial to determine the morphologies of “core” nanowires [9-11]. Especially, the diffusion of catalyst on the tip must be controlled by varying the ambient pressure and temperature. This essentially allows the fabrication of long-untapered core oxide nanowires. When the formation of “shell” oxides onto the core nanowire formation, macroscopically controlling the ablated particle flux is important to achieve the homogeneity of shell layer. When the ablated particle flux was too high, selective shell layer formation near the tip was observed. Microscopically, controlling the ambient temperature was a key factor. In addition, the diffusion of core nanowire into the shell layer was also observed, which was confirmed by HRTEM, transport and magnetic measurements. Thus well-defined “Oxide-Heterostructures in Nanowires” can be realized by precise control using in-situ PLD technique.[1] F.Patolsky et al., Scinece, 313, 1100 (2006)[2] T.Yanagida et al., Phys. Rev. B, 70, 184437 (2004)[3] T.Kanki, T.Yanagida et al., Phys. Rev. B, 71, 012403 (2005)[4] T.Yanagida et al., Phys. Rev. B, 73, 132503 (2006)[5] K.Nagashima, T.Yanagida et al., J. Appl. Phys., 100, 063714 (2006) [6] K.Nagashima, T.Yanagida et al., Phys. Rev. B, 74, 172106 (2006) [7] K.Nagashima, T.Yanagida et al., J. Appl. Phys., 101, 026103 (2007)[8] A.Marcu, T.Yanagida et al., J. Appl. Phys., 102, (2007) in press [9] K.Nagashima, T.Yanagida et al., Appl. Phys. Lett., 90, 233103 (2007)[10] K.Nagashima, T.Yanagida et al., J. Appl. Phys., 101, (2007) in press[11] A.Marcu, T.Yanagida et al., J. Appl. Phys., 102, (2007) in press
9:00 PM - JJ3.4
Tailoring of Structural Morphology of Silver Nanowires in Electrochemical Growth.
Amrita Singh 1 , Arindam Ghosh 1
1 Physics Department, Indian Institute of Science, Bangalore, karnataka, India
Show AbstractNoble metal such as Ag normally exists in an fcc crystal structure. However as the size of the material is decreased to nanometer lengthscales, a structural transformation from that of its bulk state can be expected with new atomic arrangements due to competition between internal packing and minimization of surface energy. In many previous studies, it has been shown that silver nanowires (AGNWs) grown inside anodic alumina (AAO) templates by ac or dc electrochemical deposition from silver salts or complexes, adopt fcc structure and below some critical diameter ~ 20 nm they may acquire hcp structure at low temperature. This is, however, critically dependant on the nature of confinement, as AgNWs grown inside nanotube confinement with subnanometer diameter have been reported to have fcc structure. Hence the question of the crystal structure of metal nanowires under combined influence of confinement, temperature and deposition condition remains open.In this abstract we show that the alternative crystal structures of AGNWs at room temperature can be achieved with electrochemical growth processes under specific conditions determined by the deposition parameters and nature of confinement. We fabricated AgNWs of 4H hexagonal structure with diameters 30 – 80 nm inside polycarbonate (PC) templates with a modified dc electrodeposition technique, where the nanowires were grown at deposition potentials as low as 10 mV in 2 M silver nitrate solution. We call this low-potential electrodeposition (LPED) since the electrodeposition process occurs at potential much less than the standard Nernst potential (770 mV) of silver.Two types of electrodes were used – stainless steel and sputtered thin Pt film, neither of which had any influence on the crystal structure of the nanowires. EDS elemental analysis showed the nanowires to consist only of silver. Although the precise atomic dynamics during the LPED process is unclear at present, we investigated this with HRTEM (high-resolution transmission electron microscopy) characterization of nanowires grown over various deposition times, as well as electrical conductivity measurements. These experiments indicate that nanowire growth does not occur through a three-dimensional diffusion controlled process, as proposed for conventional over-potential deposition, but follow a novel instantaneous linear growth mechanism. Further experiments showed that, (a) conventional electrochemical growth at a small over-potential in a 2 mM AgNO3 solution yields nanowires with expected fcc structure inside the same PC templates, and (2) no nanowire was observed under the LPED conditions inside hard AAO templates, indicating that LPED-growth process, and hcp structure of the corresponding nanowires depend on deposition parameters, as well as nature of confinement.
9:00 PM - JJ3.5
Vertical Germanium Nanowires Arrays Studied for Bio-molecule Sensing.
Makoto Koto 1 , Paul Leu 1 , Paul McIntyre 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States
Show AbstractSemiconductor nanowires (NWs) are attractive components for electronic and photonic devices which can be integrated with Si circuitry to achieve novel functions. We propose a reproducible and CMOS compatible fabrication process and report sensor function for vertical free-standing germanium nanowire devices.As FET-channel structure, germanium nanowires were grown vertically on low resistivity Si(111) substrates by a VLS (vapor-liquid-solid) growth method within a 1 um high microfluidic channel formed by patterning silicon nitride. Vertically grown nanowires were covered comformally by high-k dielectric material deposited by ALD (atomic-layer-deposition). After sacrificial layer deposition and CMP (chemical-mechanical-polishing), nanowire cross-sections were exposed. This was followed by metal deposition to make top electrode contacts. By removing the trench-filling sacrificial layer, vertically free-standing nanowire device arrays were obtained inside the microfluid channel.We have demonstrated pH sensing with these nanowire devices, and we will discuss approaches for other chemical and biomolecular sensing applications using such arrays.
9:00 PM - JJ3.6
Novel Planer Microwave Circuit Applications and Characterization of Ni Nanowires.
Ryan Marson 1 , Bijoy Kunar 2 , Sanjay Mishra 1 , Robert Camley 2 , Zbigniew Celinski 2
1 Department of Physics, The University of Memphis, Memphis, Tennessee, United States, 2 Department of Physics, University of Colorado, Colorado Springs, Colorado, United States
Show Abstract9:00 PM - JJ3.7
The Role of Surface in the Transport Properties of Si Nanowires Prepared by Chemical Etching.
Jiansheng Jie 1 2 , Wenjun Zhang 1 , Kuiqing Peng 1 , Zhenhua Chen 1 , Chun-Sing Lee 1 , Shuit-Tong Lee 1
1 Physics and Materials Science, City University of Hong Kong, Hong Kong China, 2 School of Science, Hefei University of Technology, Hefei, Anhui, China
Show AbstractLarger-area oriented p-type Silicon nanowire (SiNW) arrays were synthesized by chemical etching and their transport properties were investigated by fabricating the field-effect transistors (FETs) from individual nanowires (NWs). In ambient air, four-probe measurements demonstrate that the etched SiNWs have much lower resistivity (~2.2 Ωcm for a NW with a diameter of 255 nm) than that of the initial Si wafer (8-13Ωcm); and thinner NWs show higher conductivity. The SiNW FETs made via photolithography show hole mobilities up to 44±22 cm2/Vs, carrier concentrations higher than 1×1017 cm-3, and on-off current ratios up to 104 in air. In vacuum, the conductivity of the SiNWs at zero gate bias has dramatically decreased, but the hole mobility increases on the contrary. The distinct results in air and in vacuum demonstrate the performance characteristics of the SiNW FETs are intimately tied to the presence and nature of adsorbed surface species, and the surface states can dominate the transport properties of the SiNWs. Further improvements on the device performances were achieved by embedding the SiNW FETs with 250 nm SiO2, which can isolate the devices from atmosphere as well as passivate the surface defects of the NWs. A model that involves surface band bending and surface carrier scattering caused by the adsorption of oxygen gas and humidity in atmosphere is proposed to interpret the experimental results. Moreover, it is found the conductivity of Si NWs is proportional to the reciprocal of their diameter. As a result, the density of surface charges can be estimated to be about 8.5×1011 cm-2.
9:00 PM - JJ3.8
Highly Organized Single-Walled Carbon Nanotube-PDMS Hybrid System for Electromechanical Flexible Devices.
Laila Jaber Ansari 1 , Xugang Xiong 1 , Myung Hahm 1 , Sivasubramanian Somu 1 , Ahmed Busnaina 1 , Sinan Muftu 1 , Yung Jung 1
1 Mechanical and Industrial, Northeastern university, Boston, Massachusetts, United States
Show AbstractThe interest in hybrid nanocomposite structures is growing rapidly due to their unique electronic, optical and mechanical properties that have many potential applications towards flexible functional devices. In this presentation, we will discuss composite structures consisting of highly organized single-walled carbon nanotube (SWNT) micro and nanoscale networks on the flexible insulating polydimethylsiloxane (PDMS) matrix and their characterization using several techniques such as Raman spectroscopy, AFM, and 4 points I-V measurement. The synthesis method combines lithographically patterned template guided fluidic self-assembly of SWNTs on the silicon substrate through SWNT solution evaporation with controlled dip coating. Then, with a high pressure PDMS based transfer-printing technique, conductive carbon nanotube architectures in a large scale can be transferred on the PDMS film. In our experiment, the PDMS matrix undergoes excellent conformal filling within the dense nanotube network, giving rise to extremely flexible conducting structures with unique electromechanical properties. This level of mechanical robustness, good electrical performance and optical transparency make transferred SWNT networks an attractive type of electronic material for applications in electro-mechanics, sensors, and other systems such as thin-film transistors (TFTs) in future flexible electronic devices.
9:00 PM - JJ3.9
Novel Synthesis of Metal Nano-whiskers: High-temperature Glancing Angle Deposition.
Motofumi Suzuki 1 , Kenji Hamachi 1 , Koji Nagai 1 , Kaoru Nakajima 1 , Kenji Kimura 1
1 Department of Micro Engineering, Kyoto University, Kyoto, Kyoto, Japan
Show AbstractIt is well known that the so-called Ehrlich-Schwoebel (ES) barrier plays an important role to form islands or mounds at early stages of the thin film growth. An adatom diffusing on an upper atomic layer will likely encounter an additional potential energy barrier, called the ES barrier, when descending to a lower layer at the edge of its residing terrace. The nanostructures taller than the conventional islands or quantum dots may grow if the adatoms are supplied preferentially on the upper layers with strong ES barrier. This situation can be achieved in the glancing angle deposition on a high temperature substrate (HT-GLAD), during which the incident atoms are deposited preferentially on the higher part of the surface due to the self-shadowing effect. In this study, Al, Ag, Au, and Fe were deposited at the deposition angle of 58° - 85° on the substrate of glass or surface oxidized Si held at a temperature of 180°C – 560 °C. For all the metals, nano-whiskers with a thickness of 30-500 nm and a length up to about 10 μm grew on the samples deposited at the very glancing deposition angle larger than 80° and at a high substrate temperature, which is higher than approximately a half of the melting point of the deposited metal. In the case of Al, for example, the critical temperature of formation of the Al whisker at a deposition angle of 85° was found to be between 180 °C and 290 °C. The similar results were obtained for Ag, Au and Fe, though the critical temperatures depended on the metals. These results provide the two crucial concepts to control the growth of nano-whiskers. The first is that the growth cites and direction of nano-whiskers can be controlled by the geometrical conditions, e.g., the nano-whiskers can be grown on the sidewall of the trench pattern fabricated on the Si wafers. This is quite useful to integrate the nano-whiskers with the electrical and/or optical device elements. The second is that the robustness in the selection of materials not only gets nano-whiskers to possess useful properties such as plasmonic, magnetic,