Various methods of fabricating epitaxial silicon nanowires and silicon/germanium heterostructure nanowires will be described and compared including VLS and VSS growth and various kinds of plasma and chemical etching. The use of various templates such as nanoporous alumina to grow nanowires in <100> direction will be discussed as well as the use of a solid catalyst such as aluminum to grow silicon nanowires. Varous promising approaches to grow epitaxial heterostructure Si/Ge nanowires with sharp interfaces will be presented.

Semiconductor nanowires have promising properties to possibly augment or replace top-down, lithographically defined Si MOSFET (metal oxide semiconductor field effect transistor) channels because of their small, bottom-up-defined diameters. [1,2] One major difficulty in using nano-scale structures is controlling their location. It is possible to demonstrate ten, or even 100, devices by individually manipulating and connecting them, a technique which has demonstrated the promising device properties of nano structures. [3,4,5] However, to utilize nano structures to their full capability, thousands or millions of individual nano structures must be used in each system. To this end, we present a technique that shows promising results for controlling the location of nanowires by controlling the location of Au catalyst nanoparticles, which are necessary for nanowire formation using the vapor-liquid-solid (VLS) method.In this work, we use the negative charge on citrate stabilized Au nanoparticles to aid in placing them along a specific line. The line is defined close to the metallurgical junction between a lightly-doped, p-type Si substrate and a heavily doped, n-type region. Near the metallurgical pn junction, an electric field is formed by the positive and negative charge of the depletion region. Since the Au nanoparticles have a negative charge, they are attracted to the positively charged depletion region of the n-type material and repelled by the depletion region of the negatively charged, p-type material. We study the effects of different structures and applied voltages in positioning Au nanoparticles along this junction and then use these nanoparticles as catalysts for Si nanowire growth. Vertical {111} surfaces were formed by etching a (110) Si substrate covered with an epitaxial layer of the opposite conductivity type and catalyst nanoparticles were positioned as described above. We find that highly-doped, n-type material forming a junction with lightly-doped, p-type material is the best structure to use to focus the Au particles. Also, applying a reverse bias across the junction increases the positive charge in the n-type material’s depletion region, thereby enhancing the electric field and better focusing the nanoparticles along the line on the vertical surface.Si nanowires were then grown horizontally from the vertical {111} surfaces using these catalyst nanoparticles and the VLS method. Substantial alignment of the nanowires was achieved.[1] V. Schmidt, H. Riel, S. Senz, S. Karg, W. Riess, and U. Gosele, Small 2, (2006).[2] J. Goldberger, A. I. Hochbaum, R. Fan, and P. Yang, Nano Letters 6, (2006).[3] X. Duan, Y. Huang, Y. Cui, J. Wang, and C. M. Lieber, Nature 409, 681 (2001).[4] Y. Huang, X. Duan, Q. Wei, and C. M. Lieber, Science 291, 550 (2001).[5] Y. Cui, L. J. Lauhon, M. S. Gudiksen, J. Wang, and C. M. Lieber, Appl. Phys. Lett. 78, 1 (2001).

Semiconductor nanowires are being investigated intensively, motivated by a desire to discover and manipulate physics at nanometer dimensions. The result of these investigations may be electronics and optoelectronics with characteristics superior to what is currently available. These fundamental and applied interests drive the materials research and development of nanowires for all types of materials. An issue that remains under investigation is the formation of dense arrays of nanowires with uniform dimensions. We are investigating the formation of ordered GaAs nanowire arrays. Our approach utilizes the controversial vapor liquid solid/vapor solid solid (VLS/VSS) technique using Au to “catalyze” nanowire growth. The first technique forms a template by having Au films, 0.5 to 3.0 nm in thickness, deposited on GaAs(111)B and Si(111) substrates. The template was then annealed under AsH3 at 650°C to disperse the Au prior to cooling to 450°C. A metal-organic chemical vapor deposition system was used to control the growth. Our work has been able to compare trimethylgallium to triethylgallium as group III sources. Growth was performed for times ranging from 10 to 50 minutes. This technique forms a large distribution of diameters, but generates large (5 cm) arrays that are preferentially oriented normal to the growth surface. We have discovered that a small thickness of Au (1 nm and under) leads to a higher fraction of oriented nanowires. As the nanowires get longer than 2 µm, a larger fraction of them kink and deviate from the (111) orientation. Oriented nanowires are only part of the picture. Techniques to control the diameter and placement of these structures are needed. To address this need, we are investigating nano-imprint lithography to form arrays of nanowires. Nano-imprint lithography allows features that are tens of nanometers to be generated in a fixed pattern. Au seeds with a 200 nm diameter on a 600 nm pitch were deposited by metal lift-off. Square arrays approximately 2.5 cm on a side were fabricated. Using the conditions established from planar Au film experiments, we have shown it is possible to form localized nanowires with high fidelity. This result indicates that patterned-substrates represent a route to controlled density and placement of nanowires. Nano-imprint lithography is especially well suited to fabrication of large nanowire arrays with the desired geometrical control. Sandia is a multiprogram laboratory operated by Sandia Corporation , a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under Contract DE-AC04-94AL85000.

Ion beam doping of materials offers advantages in comparison to doping during growth or by diffusion. First, the impurity concentrations as well as the lateral and depth distribution of the dopants are precisely controllable, and secondly, almost all elements can be implanted with sufficient high purity even beyond any solubility limit. However, doping by ion implantation is hampered by the created radiation damage, but this can be removed by thermal treatment.Here, we will report on studies in order to fabricate GaAs nanowires pn-junctions. Nominal undoped GaAs nanowires were grown according to the VLS mechanism using Au nanoparticles on top of Si(100) substrates. Zinc as an acceptor was implanted with different ion energies in such samples in order to create a box-like implantation profile matching the diameter of the GaAs nanowires. Subsequently, the samples were re-insert into the MOCVD system and the growth of the nanowires was continued, but with the addition of Si donors. This growth at high temperatures not only resulted into n-type material, but also also in annealing of the implantation defects of the first section of the nanowires. Finally, the pn nanowires were cut of the growth substrate, and processed with contacts on top of new insulating substrates. First results on the electrical characterization will be presented and discussed in this presentation.

Semiconducting and metallic nanowires (NW) are widely investigated as potential building blocks for future electronic devices. Silicon and nickel silicide NWs are particularly interesting, because these materials are currently used as bulk materials in the volume production of highly integrated circuits. In this work, intrinsic Si and NiSi2 NWs as well as NiSi2/Si/NiSi2 axial NW heterostructures are fabricated and investigated electrically. Si NWs are grown by Au-catalyzed chemical vapor deposition. Axial segments of the Si-NWs are transformed into metallic ones by a longitudinal silicidation process. To this end, Si-NWs are contacted with a Ni reservoir at one of their ends. Annealing leads to longitudinal Ni diffusion inside the NWs for lengths of up to several micrometers. Along the diffusion path, single crystalline NiSi2 NW segments are formed in a solid-state reaction [1]. The interface between the NiSi2 and the pristine Si segment has a sharpness on the nanometer scale. This axial silicidation reaction is different from previous NW silicidation findings, since those ones only observed radial Ni diffusion [2]. Fully Ni-silicided NWs have an ohmic behavior and a resistivity of at most 98 μΩ-cm as determined by two point IV measurements. Moreover, NiSi2 NWs conduct current densities of up to 205 MA/cm2 before breakdown. This high value is within the same order of magnitude as that of metallic carbon nanotubes and higher than that of Cu nano-interconnects. Schottky barrier (SB) field effect transistors (FET) are fabricated by a controlled NiSi2 formation from both NW-ends, leaving a pristine Si segment in the middle which constitutes the active region. Gate control is performed by a common back gate stack. The NiSi2 NW-segments extend the source and drain contacts, reducing the length of the active region, e.g. from 1 µm to 20 nm. Hence, this method gives simple access to fabricate nanoscale Si regions by only employing a single and coarse optical lithography step to structure the Ni reservoirs. Although undoped, the FETs exhibit unipolar p-type behaviour if the NW diameter is below 30 nm. For thicker NWs, the behavior is increasingly ambipolar. Such a NW heterostructure SB-FET has the advantage over a common SB-FET contacted by a large pad; that for geometrical reasons the gate field is enhanced at the needle-like Schottky contacts. Therefore, gate control over SB-width and carrier transmission is optimized as shown by electrostatic calculations. Consequently, modulation of over 10^7 and subthreshold slopes as low as 110 mV/dec are achieved. Moreover, these SB-FETs exhibit the highest current densities in the on-state reported up to date for intrinsic Si-NW FETs, amounting to 0.8 MA/cm2 at 1 V bias. These results reflect the performance improvement of one dimensional metal to semiconductor heterostructures in comparison to bulk devices. [1] W. M. Weber et al. Nano Lett. 6, 2660 (2006)[2] Y. Wu, et al. Nature 430, 61 (2004)

A comprehensive understanding of vapor-liquid-solid (VLS) nanowiregrowth mechanisms and kinetics is of considerable importance for structuraloptimization of nanoscale wires with desired properties. Despite over 40years of research, little has been reported on nanowire nucleation. Here, wereport, for the first time, real time transmission electron microscopy (TEM)measurements of the nucleation kinetics of Au-catalyzed Si nanowires. Ourdirect observations of Au mediated Si nanowire nucleation span from initialobservations of the pure solid Au catalyst to final nanowire nucleation. Ourmeasurements show that the nucleation time is linearly proportional to thediameter of the AuSi alloy drop – contrary to behavior expected from theGibbs-Thomson effect – and that the nucleation rate linearly increases withdisilane pressure. These two observations indicate that the rate limiting stepthroughout the processs is the thermally activated dissociative adsorptionof disilane on the catalyst surface. Furthermore, we classify the subsequentnucleus growth process of Si nanowires into three regimes: an initial rapidgrowth of the nucleus, a subsequent slow growth of the nucleus, followedby axial growth of the nanowires away from the AuSi drop. We show thatfor the initial growth, the growth rate (dr/dt) is simply proportional to thecritical supersaturation required to nucleate the nanowire. Additionally,during the slow growth regime and final nanowire growth, the growth rate isproportional to the ratio between the surface area of the AuSi alloy and the Sinucleus. These observations are in an excellent agreement with a theoreticalmodel we have proposed for nanowire nucleation kinetics. Finally, using thismodel we are working to extract the critical supersaturation of Si at which nanowire nucleation occurs, leading to the determination of an effective, kinetically controlled liquidus line in the binary phase diagram. These quantiative measurements yield critical data needed for controlling nanowire nucleation during the fabrication of high performance nano-electronic devices based on these structures.

Depositing a Si or SiGe film around a Ge nanowire (NW) creates a structure which may have additional advantageous properties beyond that of a single-element Si or Ge NW. A heteroepitaxially grown shell may allow for engineering of strain in both the shell and the inner core. Moreover, the valence band offset may allow confinement of holes to the core, reducing the influence of surface defects on carrier scattering in p-type NWs. The Ge-core/Si or SiGe-shell arrangement is desirable for the higher carrier mobilities of Ge and the superior properties of SiO2 passivation.In this work, vertically aligned arrays of Ge/Si and Ge/SiGe core-shell NWs have been synthesized by CVD. First, <111> Ge NWs were heteroepitaxially grown on Si (111) substrates; the NW diameter was controlled through the use of monodisperse Au nanoparticles as the catalysts. Silane, with or without germane, was then used to deposit the shell. The Au remaining on the Ge NW tips is problematic since (i) the Au can catalyze unwanted Si NW growth and (ii) the Au particles at the NW tips diffuse into the structure at the temperatures required to obtain single crystalline shells. We have found that Ge NWs dissolve in commercially available wet chemical Au etchants. We will present a KI/I2-based wet etching procedure for Au removal from Ge NWs that does not significantly etch the Ge so that a heteroepitaxial Si or SiGe shell can subsequently be deposited. The resulting core-shell NWs were characterized with transmission electron microscopy to determine their defect and stress states.

Semiconductor nanowires and their associated heterostructures have many potential applications in nanoelectronic and nano-optoelectronic devices owing to their unique physical properties, which have drawn extensive research attention in the past decade. The vapor-liquid-solid (VLS) mechanism has been a widely used mechanism for the growth of semiconductor nanowires and their heterostructures. In typical VLS growth, metal nanoparticles are deposited on a substrate surface and heated to the growth temperature under the vapor species of growing material. Nano-sized metal liquid droplets form and then catalyze nanowires growth, so that the nanowires have metal particles at their growth fronts. Au nanoparticles have been widely used to catalyze the nanowires and nanowire heterostructures growth. Axial nanowire heterostructures can be grown by altering the chemical composition of vapor species during the nanowires growth and subsequent achievement of respective compositional alteration along the nanowire growth axis.Successful axial growth of GaAs on InAs nanowires using Au nanoparticles have been reported in the literature. In this work, InAs nanowire sections were grown on GaAs nanowire sections through VLS mechanism using Au nanoparticles. Axial growth failure of InAs on GaAs nanowires was observed through transmission electron microscopy (TEM) characterizations with a sequence of : (i) the initial InAs clustering at an edge of the Au/GaAs interface displaces the Au droplet with respect to its underlying GaAs nanowire; (ii) the Au droplets move sidewards and then downwards with further growth of InAs by preserving an interface with the GaAs sidewalls. The fundamental reason for this failure of InAs axial growth on GaAs nanowires and feasibility of GaAs axial growth on InAs nanowires has been determined by quantifying the interfacial energies between Au-InAs, Au-GaAs and InAs-GaAs at equilibrium. This quantification is done by adopting the model proposed for description of heterogeneous nucleation of a solid from liquid metal along a solid wall of a mold. We use this model because, in our case, the Au particles are in the liquid form during the nanowire growth and GaAs and InAs can act as the wall of the mold and nucleated solid, respectively. Through this quantification, we found that the axial growth failure of InAs on GaAs nanowires is due to higher interfacial energy between Au-InAs than that between Au-GaAs.Thermodynamically, following conclusion can be drawn from this work. When a nanowire axial heterostructure is to be grown with two materials combination “A” and “B” using catalyst particle “C”, and if the interfacial energy between A and C-droplet is higher than that between B and C-droplet, the axial growth of A on B fails, whereas axial growth of B on A is feasible.

Radial core/shell nanowire heterostructures represent important one-dimensional building blocks with substantial potential for tuning materials electronic and photonic properties. Specifically, it is possible to create structures with novel properties through the rational choice of core/shell materials coupled with highly-controlled synthesis. Here, we report the rational design, synthesis and properties of InAs/InP core/shell nanowires as a new one-dimensional electron gas (1DEG) system. Transmission electron microscopy studies revealed uniform, crystalline InP shell growth and clean, epitaxial interfaces between InAs core and InP shell. In addition, energy-dispersive X-ray spectroscopy analysis further confirmed the composition of the designed core/shell nanowire heterostructure. Room-temperature electrical measurements on InAs/InP nanowire field-effect transistors (FETs) showed significant improvement of the on-current and transconductance compared with InAs nanowire FETs fabricated in parallel. Notably, analysis of these transport data yield an electron mobility of 11,500 cm2/V-s that exceeds substantially values previously reported for n-channel nanowire and nanotube devices. In addition, high-performance FET devices were fabricated by incorporating a high-κ dielectric and top-gate geometry. Studies of these top-gated InAs/InP nanowire FET structures yielded a scaled on-current value of 3.2 mA/μm at a bias of 0.5 V, which is larger than any other n-channel electronic devices up to date. The designed 1DEG in InAs/InP core/shell nanowires opens up opportunities for exploring our fundamental knowledge of nanoscale building blocks, and also the development of quantum coherent transport devices and high-speed, low-power nanoelectronic circuits.