Symposium Organizers
Michael Mastro U.S. Naval Research Laboratory
Jeffrey LaRoche Raytheon RF Components
Fan Ren University of Florida
Jen-Inn Chyi National Central University
Jihyun Kim Korea University
A1: GaN Devices
Session Chairs
Monday PM, December 01, 2008
Room 202 (Hynes)
9:00 AM - A1.1
Considerations for Integrating Functional Oxides with Gallium Nitride.
Mark Losego 1 , H. Spalding Craft 1 , Elizabeth Paisley 1 , Ramon Collazo 1 , Anthony Rice 1 , Seiji Mita 1 , Zlatko Sitar 1 , Jon-Paul Maria 1
1 Materials Science, North Carolina State University, Raleigh, North Carolina, United States
Show Abstract9:15 AM - A1.2
Schottky and Ohmic Contacts on Non-Polar Cubic Gan Epilayers.
Donat As 1 , Elena Tschumak 1 , Irina Laubenstein 1 , Ricarda Kemper 1 , Klaus Lischka 1
1 Department of Physics, University of Paderborn, Paderborn Germany
Show AbstractSchottky and ohmic contacts are key elements for the realization of any GaN based electronic devices such as high-power high electronic mobility transistors (HEMTs), high-power metal semiconductor field effect transistors (MESFETs) or UV-photodetectors. Group III-nitrides crystallize in the stable wurtzite structure or in the metastable zincblende structure. An important difference between these material modifications is the presence of strong internal electric fields in hexagonal (wurtzite) III-nitrides grown along the polar c-axis, while these “build-in” fields are absent in cubic (zincblende) III-nitrides. In addition, cubic GaN, although more difficult to grow, allows a 50% gain in FET performance in comparison to wurtzite GaN as proposed by 2D Monte Carlo device simulations of nitride field effect transistors. In this work we focus on the fabrication of ohmic contacts and of Schottky barrier devices (SBD) on non-polar cubic GaN epilayers grown by molecular beam epitaxy (MBE). A Ti/Al/Ni/Au metallization was used for ohmic contacts and the contact resistance was measure by transmission line measurements (TLM). Ni, Pd, Ag and NiSi Schottky barrier devices (SBD) 300 µm in diameter were fabricated by thermal evaporation using contact lithography on cubic GaN epilayers. The current-voltage (I-V) and the capacity-voltage (C-V) characteristics were studied at room temperature in detail. A clear rectifying behavior was measured in all SBDs. In the Ni and Ag SBDs an abnormal large leakage current under reverse bias was observed. Isochronal thermal annealing of these Ni and Ag based SBDs at 200°C in air improved the reverse characteristics by up to three orders of magnitude. This is in contrast to the Pd contacts, where the as grown contact showed already good performance and thermal annealing had nearly no influence on the I-V characteristics. For all SBDs the magnitude of the reverse current is generally larger than that expected due to thermionic emission and an exponential increase of the reverse current is observed with increasing reverse voltage. In-depth analysis of the I-V characteristic showed that a thin surface barrier is formed at the metal semiconductor interface and that crystal defects like dislocations may be the reasons for the discrepancy between experimental data and thermionic emission theory.
9:30 AM - **A1.3
Overview of GaN HEMT Technology and its Future Outlook Beyond Power Performance.
Eduardo Chumbes 1
1 , RF Components, Ratheon Integrated Defense Systems, Andover, Massachusetts, United States
Show Abstract10:00 AM - **A1.4
High Temperature Stable Contacts for GaN HEMTs and LEDs.
S. Pearton 1 , L. Voss 1 , R. Khanna 1 , F. Ren 2 , A. Dabiran 3 , A. Osinsky 3
1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States, 2 Chemical Engineering, University of Florida, Gainesville, Florida, United States, 3 , SVT Associates, Eden Prairie, Minnesota, United States
Show Abstract10:30 AM - A1.5
Geiger-mode and Linear-mode Operation of Deep-ultraviolet Avalanche Photodiodes Based on Homoepitaxial GaN PIN Diodes.
Suk Choi 1 , Hee Jin Kim 1 , Jae-Hyun Ryou 1 , Yun Zhang 1 , Shyh-Chiang Shen 1 , Xiaogang Bai 2 , Joe Campbell 2 , Russell Dupuis 1
1 School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States, 2 Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, Virginia, United States
Show AbstractGaN p-i-n avalanche photodiodes (APDs) structures were grown on GaN free-standing substrate by using metalorganic chemical vapor deposition (MOCVD). The thickness of i-drift layer and p-layer was set to 300 nm and 100 nm, respectively, to control the leakage current originate from deep-level defects in the depletion region of p-layer. APDs were fabricated with 2-mesa structure to suppress the sidewall leakage with the PN-junction surface depletion technique. In DC photocurrent test, the APD showed leakage current density less than 10-7 A/cm2 for the reverse bias electric field of 2 MV/cm, and avalanche gain of 2000 was achieved near breakdown voltage. Peak quantum efficiency was appeared as 53% at 360 nm, and 25% at 280 nm. Geiger mode measurement was performed on the APD using passive quenching circuit with 360 nm D2 lamp. During the measurement, 2.5x106 counts/s dark count and 3.7x106 counts/s count under light event was observed at a constant reverse bias, and dark current was much reduced to about 10-folds near breakdown voltage, indicating that the APD did perform as a photon counter. In pulsed Geiger mode measurement, the APD showed single photon detection efficiency (SPDE) of 1% and dark count probability (DCP) of 3x10-2 at DC reverse voltage of 91 and pulsed voltage of 12 V, and no afterpulsing effect was observed up to 100kHz.
10:45 AM - A1.6
Surface-state Induced Transients in Gallium Nitride Nanowires.
Blake Simpkins 1 , M. Mastro 1 , C. Eddy 1 , P. Pehrsson 1
1 , Naval Research Lab, Washington, District of Columbia, United States
Show AbstractIt is well-established that surface-mediated phenomena in semiconducting nanowires (NWs) dramatically alter their optical, electrical, and mechanical properties, making them excellent candidates for chemical and biological sensors. However, surface-induced effects such as carrier trapping or scattering at surface-states can also degrade optical or electronic performance. The relative impact of these effects increases with decreasing NW radius and can limit the nanowire’s optical or electronic functionality. With these implications in mind, we have evaluated gate-induced conductivity transients and methods for their remediation in GaN NW-based FETs. These current transients occur over 10-100’s of seconds and appear to reflect surface-state charge trapping. We obtained the temporal responses of NW-based FETs with (1) a native oxide, (2) a surface with the native oxide removed, and (3) a passivation PECVD SiO2. The data were fit to a stretched exponential, which models a characteristic decay time and a time varying barrier. The magnitude and characteristic decay time of these conductivity transients varied substantially as a function of surface condition and indicated reduced surface trap density after deposition of the PECVD oxide. This observation is consistent with previous work on planar nitrides. Additionally, the transient response measured in the dark and under illumination reveals characteristics of the charge transfer mechanism. Measurements carried out in ambient light indicated a standard (non-stretched) exponential behavior. However, experiments carried out in the dark showed a time-dependent barrier for charge trapping/detrapping.
11:00 AM - A1: GaN Devices
BREAK
A2: GaN Device Reliability
Session Chairs
Eduardo Chumbes
Steve Pearton
Monday PM, December 01, 2008
Room 202 (Hynes)
11:15 AM - **A2.1
GaN HEMT Reliability: An Industrial Perspective.
Kurt Smith 1
1 , Raytheon RF Components, Andover, Massachusetts, United States
Show Abstract11:45 AM - **A2.2
Temperature, Stress and Reliability of Power Transistors: Sub-Micron and Nanosecond Raman Thermography.
Martin Kuball 1 , Andrei Sarua 1 , James Pomeroy 1 , Gernot Riedel 1 , Richard J. Simms 1 , Athikom Manoi 1 , Hangfeng Ji 1 , Timothy Batten 1 , Michael Uren 2 , Trevor Martin 2
1 H.H. Wills Physics Laboratory, University of Bristol, Bristol United Kingdom, 2 , QinetiQ Ltd., Malvern United Kingdom
Show AbstractIncreased performance requirements for high-power and high-frequency electronics have promoted the development of GaN and SiC electronic devices, additionally resulted in further advances in III-V devices. Significant challenges, however, remain in their device reliability. Key parameters affecting device reliability are device temperature and stress/strain, both of which are very local effects, and therefore challenging to assess. This is as traditional assessment of devices during operation does not provide the required micron/sub-micron spatial resolution needed for today’s technologies. For example, in a HEMT heat is typically generated in a sub-micron size region near the gate contact. IR thermography, traditionally used to measure the resulting device temperature rise, therefore often underestimates peak channel temperature by more than a factor of two due to its limited spatial resolution of only 3-10 micron. We review here our development of Raman thermography. This technique enables accurate device temperature measurement with sub-micron spatial and 10 ns time resolution, furthermore the possibility not only to assess device properties laterally, but also vertically through a device structure, for full three-dimensional thermal device analysis. Corresponding information can be obtained on the local stress/strains in devices using this technique, which for example for GaN with its high piezoelectricity provides additional aspects for device reliability via the converse piezoelectric field effect. We illustrate the advantages and the potential Raman thermography offers for device thermal and stress assessment, on the example of AlGaN/GaN HEMTs and GaAs pHEMTs. This will include detailed measurements of the temperature profile across active device regions, thermal diffusion processes during pulsed device operation, thermal cross-talk in multi-finger devices, and converse piezoelectric field induced stress/strain. We will furthermore discuss the role interfaces play for heat extraction from an active device area, on the example of the GaN/SiC interface in AlGaN/GaN HEMTs grown on SiC substrates, which in this case is responsible for almost a third of the actual device temperature rise. Responsible is the high thermal resistance the nucleation layer typically present at this interface poses.
12:15 PM - A2.3
Measurement of AlGaN/GaN High-Electron-Mobility-Transistor Device Temperature Under DC Bias by μ-Photoluminescence Mapping.
Bruce Claflin 1 2 , E. Heller 1 2 , J. Gillespie 3 , G. Jessen 3
1 Semiconductor Research Center, Wright State University, Dayton, Ohio, United States, 2 Materials and Manufacturing Directorate, AFRL/RXPS, WPAFB, Ohio, United States, 3 Sensors Directorate, AFRL/RYDD, WPAFB, Ohio, United States
Show AbstractThe performance and reliability of AlGaN/GaN-based high-electron-mobility-transistor (HEMT) devices are significantly impacted by localized self-heating effects under high-power, high-frequency operation. Heat generation is concentrated within a small volume at the drain-side edge of the gate contact, so reliable measurement of the temperature requires high spatial resolution. Several experimental probes have been employed to measure the temperature of biased HEMT devices, such as IR thermal imaging1, as well as μ-Raman1 and μ-photoluminescence2 (μ-PL) spectroscopies. In this work, room temperature μ-PL mapping, with 1 μm spatial resolution, is used to produce a 2D temperature profile for HEMT devices under DC bias conditions. A 2 x 150 μm wide, AlGaN/GaN HEMT, grown on SiC, with 0.25 μm T-gate and 4 μm source-drain spacing, and mounted on a thermal stage held at a constant temperature of 70 ○C, was operated at several values of DC bias while maintaining a constant 3.4 W/mm dissipated power. The active region of the device exhibits a fairly uniform (spatial) temperature distribution, increasing from 125 ○C to 135 ○C, with increasing drain bias. A point in the exposed area surrounding the device, about 50 μm away from the channel, shows a temperature of 100 ○C as a result of heat conduction through the SiC substrate. These values are higher than calculated values from a full electro-thermal simulation. Similarly, IR imaging measurements made under similar operating conditions show a lower temperature in the active region of the device by more than 20 ○C. A comparison of the different temperature measurement techniques as well as the effectiveness of different substrates on thermal spreading will be discussed.1 A. Sarua, H. Ji, M. Kuball, M. J. Uren, T. Martin, K. P. Hilton, and R. S. Balmer, IEEE Trans. Electron Devices 53, 2438 (2006).2 N. Shigekawa, K. Onodera, and K. Shiojima, Jpn. J. Appl. Phys. 42, 2245 (2003).
12:30 PM - **A2.4
Correlation Among Material Quality, Performance and Reliability of High Power and High Frequency AlGaN/GaN HFET.
Yasushi Nanishi 1
1 Photonics, Ritsumeikan University, Kusatsu Japan
Show AbstractA3: GaN Transistors
Session Chairs
Eduardo Chumbes
Russell Dupuis
Monday PM, December 01, 2008
Room 202 (Hynes)
2:30 PM - **A3.1
Recent Progress on GaN HEMTs.
Shigeru Nakajima 1 , Yasunori Tateno 1 , Seigo Sano 1
1 , Eudyna Devices Inc., Yokohama Japan
Show AbstractThis paper is reported recent progress on GaN HEMTs. High power, high efficiency, and broadband performance will be reported. A 100W device shows 70 % drain efficiency with 20 dB linear gain at 2.1 GHz. In addition, the devices show high reliability and high reproducibility for mass production phase. These results suggest that GaN HEMTs are quite promising for microwave and millimeter wave applications.
3:00 PM - A3.2
Integration of High Dielectric Constant Epitaxial Oxide for GaN-based MOS Devices.
Jesse Jur 1 , Virginia Wheeler 1 , Michael Morgensen 2 , Matthew Veety 2 , Daniel Lichtenwalner 1 , Doug Barlage 2 , Mark Johnson 1
1 Materials Science and Engineering, North Carolina State University, Raleigh, North Carolina, United States, 2 Electrical and Computer Engineering, North Carolina State University, Raleigh, North Carolina, United States
Show AbstractThe improvement in epitaxial growth of high dielectric constant rare earth oxides on GaN is examined for use in metal oxide semiconductor field effect transistor (MOSFET) devices. Integration of such oxides has been limited by the presence of a large lattice mismatch at the semiconductor-oxide interface resulting in high defect state densities. For the study, Sc2O3 and La2O3 are grown by molecular beam epitaxy (MBE) up to thicknesses of 25 nm. Characterization shows epitaxial growth in a (111) fcc preferred orientation for each oxide, as well as a lattice mismatch of 7.2% (Sc2O3) and 21% (La2O3). Electrical analysis of MOS devices provides a dielectric constant as high as 21.1 for Sc2O3 and 35.6 for La2O3, values higher than what has been reported for amorphous phases of the oxides grown on Si. A surface charge density of the 5E13 cm-2 is achieved for 10 nm of the La2O3 on GaN. Band alignment measurements by x-ray photoelectron spectroscopy provide a band gap energy of 6.3 eV (2.18 eV conduction band offset, CBO) for Sc2O3 and 6.2 eV (1.4 eV CBO) for La2O3. In addition, the implementation of a native oxide “buffer” layer by chemical solution on the GaN is examined as a method to minimize the lattice mismatch induced defects at the GaN/oxide interface. Significant improvement in device gate leakage, as compared to a Si3N4 gate dielectric, is observed. The incorporation of a thin native oxide and the improvement of the epitaxial quality of the rare earth oxide films are believed to be potential routes toward the improvement of GaN based MOSFET devices.
3:15 PM - A3.3
Electrical and Structural Properties of Proton Irradiated AlGaN/GaN HEMTs.
Hong-Yeol Kim 1 , Jihyun Kim 1 , Travis Anderson 2 , Fan Ren 2 , Stephen Peaton 3
1 Chemical and Biological engineering, Korea University, Seoul Korea (the Republic of), 2 Chemical engineering, Florida University, Gainesville, Florida, United States, 3 Material science and engineering, Florida University, Gainesville, Florida, United States
Show Abstract GaN-based device has their applications in space orbit due to exceptional radiation hardness. It has been known that the atomic displacement threshold energy depends on reverse of the lattice constant. Since GaN lattice constant(a=3.19, c=5.19) is smaller than other semiconductor substrates such as Si(5.43) and GaAs(5.65), displacement threshold energy is relatively lager than that of others. There is a need to investigate the hardness of this kind of device at various fluency and various proton energy. Therefor, 13th, 15th, and 16th order of 17MeV protons were irradiated to AlGaN/GaN high electron mobility transistors (HEMTs) and we compared electrical and structural properties of irradiated HEMT with that of unirradiated HEMT. I-V measurements were carried out at elevated temperatures(20~250°C). In order to characterize the damage from high energy protons, cathodoluminescence(CL) spectroscopy was employed. There are no significant degradation in electrical properties such as drain-source current (IDS) and transconductnace (gm) up to 13th order of proton irradiation. When HEMT was irradiated with 16th order of 17MeV protons, drain-source current was decreased by 43% of original value and transconductance was reduced by 29%. It was believed that high energy protons collide with GaN lattice and make the atoms displaced. These displaced atoms disturb current of electrons and reduce carrier concentration because the defect centers capture free electrons. The result of CL spectroscopy is similar to that of I-V measurement but the decrease in CL intensity was severe than that in I-V data. This results show that HEMT’s crystal structure is degraded by proton irradiation but device performance is maintained. It means AlGaN/GaN HEMTs have enough tolerance for radiation and appropriate for space applications. Schottky barrier height and ideality factor of proton irradiated AlGaN/GaN HEMT was also investigated. I-V characteristics and CL data at various fluency and various proton energies will be presented. And I-V characteristics at elevated temperatures will be discussed.
3:30 PM - A3.4
Normally Off AlGaN/GaN HEMTs with AlGaN Back Barrier.
Vibhu Jindal 1 , Neeraj Tripathi 1 , Fatemeh Shahedipour-Sandvik 1 , Siddharth Rajan 2 , Alexei Vert 2
1 College of Nanoscale Science and Engineering, University at Albany, State University of New York, Albany, New York, United States, 2 , General Electric Global Research Center, Niskayuna, New York, United States
Show AbstractAlGaN/GaN high electron mobility transistors (HEMTs) have attracted a great interest owing to high polarization induced 2DEG density, higher breakdown voltage and high electron mobility. Two modes of operations have been demonstrated for AlGaN/GaN HEMTs: 1) Enhancement mode (normally-off), 2) Depletion mode (normally-on). Conventional AlGaN/GaN single heterostructure HEMTs operate in depletion mode, providing finite drain current even at 0V of gate bias. Enhancement mode devices are of particular interest due to reduced circuit complexity and power consumption. A number of groups have demonstrated enhancement mode operation using recess gate, fluoride ion and thin AlN sandwich layer. Here, we demonstrate normally-off operation for a double heterostructure AlGaN/GaN/AlGaN HEMT using an AlGaN based back barrier structure. In this design, lower AlGaN layer acts as a barrier and depletes the polarization induced 2DEG at the upper AlGaN/GaN interface for 0V gate voltage. Simulations were performed to optimize thicknesses and Al composition for the different epilayers of the heterostructure. Simulations suggest that Al0.15GaN/GaN/Al0.10GaN double heterostructure with 30nm/5nm/1μm of respective thicknesses would result in operation of HEMT structure in enhancement mode. Device structures were grown on sapphire by MOCVD. Surface roughness of the bottom AlGaN layer and quality of GaN layer were optimized and were observed to play an important role for normally off operation. Initial on-wafer measurements were performed using mercury probe CV and current voltage measurements to confirm the normally off operation. Device growth and characterization results will be presented along with the simulation results demonstrating enhancement mode operation of AlGaN/GaN/AlGaN based HEMT.
3:45 PM - A3.5
Optical Characterization of Orientation-Patterned GaN Templates by μ-Photoluminescence and μ-Raman Mapping.
Bruce Claflin 1 2 , R. Collazo 3 , A. Rice 3 , Z. Sitar 3
1 Semiconductor Research Center, Wright State University, Dayton, Ohio, United States, 2 Materials and Manufacturing Directorate, AFRL/RXPS, WPAFB, Ohio, United States, 3 Department of Materials Science and Engineering, North Carolina State University, Raleigh, North Carolina, United States
Show AbstractThick, orientation-patterned, III-V semiconductor compounds, such as GaAs, AlGaAs, and GaP, have attracted interest for non-linear optical frequency conversion applications1, making use of the polar nature of their zincblende crystal structures. The recent demonstration of simultaneous epitaxial growth of patterned Ga- and N-polar GaN domains2 provides an opportunity to explore similar effects in III-V wurtzite structures, as well as other applications, such as electroluminescence3 from lateral p-n junctions. In this work, thin, orientation-patterned, GaN films are characterized using room temperature μ-photoluminescence (μ-PL) and μ-Raman mapping. The inversion domain boundaries (IDBs) are relatively sharp and exhibit higher PL intensities than the bulk Ga- (2x higher) and N-polar (10x higher) regions. Raman maps show a more modest increase in the intensity of the E2(high) mode at the IDBs compared to the bulk material. In addition, PL and Raman maps show defects such as inversion domains and a small number of cubic-phase GaN inclusions in the film. These defects are typically less than 10 μm in diameter. Finally, shifts in the positions of the PL near-band-edge (NBE) peak and the Raman E2(high) and A1(LO) modes provide estimates of local stress and carrier concentrations in the different polar domains.1 A. Szilagyi, A. Hordvik, and H. Schlossberg, J. Appl. Phys. 47, 2025 (1976).2 R. Collazo, S. Mita, A. Aleksov, R. Schlesser, and Z. Sitar, J. Cryst. Growth 287, 586 (2006).3 R. Collazo, S. Mita, A. Rice, R. F. Dalmau, and Z. Sitar, Appl. Phys. Lett. 91, 212103 (2007).
4:00 PM - A3: GaN FETs
BREAK
A4: GaN Material Development
Session Chairs
Monday PM, December 01, 2008
Room 202 (Hynes)
4:15 PM - **A4.1
Recent Achievement in the GaN Epitaxy on Silicon and Engineering Substrates.
Bove Philippe 1 , Hacene Lahreche 1 , Arnaud Wilk 1 , Robert Langer 1 , Melania Lijadi 1
1 Research & Developement, picogiga International SAS, Courtaboeuf France
Show Abstract4:45 PM - A4.2
Strain Evolution Study by Nondestructive Methods in Large Area Dislocation Reduced GaN on Engineered AlN/Si Substrate.
Mihir Tungare 1 , Neeraj Tripathi 1 , Vibhu Jindal 1 , Gayathri Rao 1 , Vimal Kamineni 1 , Alain Diebold 1 , Robert Geer 1 , Fatemeh Shahedipour-Sandvik 1
1 College of Nanoscale Science and Engineering, University at Albany, SUNY, Albany, New York, United States
Show Abstract5:00 PM - A4.3
Assessment of the Surface Electron Accumulation Properties of Polar and Non-Polar InN Surfaces.
Tino Hofmann 1 , V. Darakchieva 2 , B. Monemar 2 , H. Lu 3 , W. Schaff 3 , L. Chen 4 , Y. Nanishi 5 , M. Schubert 1
1 , University of Nebraska-Lincoln, Lincoln, Nebraska, United States, 2 , Linköping University, Linkoping Sweden, 3 , Cornell University, Uijungbu Korea (the Republic of), 4 , National Taiwan University, Taipei Taiwan, 5 , Ritsumeikan University, Shiga Japan
Show AbstractThe incorporation of contemporary semiconductor materials into novel electronic devices requires a precise understanding and controlling of doping mechanisms. The determination of the carrier generating mechanisms in InN is especially challenging because true bulk free-charge carrier properties are difficult to assess experimentally due to the presence of a charge carrier accumulation layer. Here we report on the determination of the free charge carrier properties of various non-polar and polar InN surfaces using a nondestructive, contactless optical Hall effect technique. Although previous experiments suggested universal properties of the electron accumulation layer in InN regardless of surface orientation, polarity, and structure our data clearly shows that the sheet density depends on polarity, structure, surface orientation, and bulk doping concentration and type. We find that the surface electron density decreases with decreasing bulk electron density. A comparison between experimental and calculated surface sheet densities indicates a variation of the surface Fermi level position with changing the bulk electron density. Although the exact mechanism behind this effect is still to be found, our results show that the surface charge density can in fact be manipulated. This finding has significant implications for novel InN-based device designs.
5:15 PM - A4.4
Facet Stabilization Study in MOCVD grown III-Nitride Nanostructures.
Vibhu Jindal 1 , Nirag Kadakia 1 , Fatemeh Shahedipour-Sandvik 1
1 College of Nanoscale Science and Engineering, University at Albany, State University of New York, Albany, New York, United States
Show Abstract5:30 PM - A4.5
Growth and Characterization of AlGaN Grown by Digitally-Alloyed Modulated Precursor Flow Epitaxy: A New Growth Scheme for AlGaN with High Al Content.
Hee Jin Kim 1 , Suk Choi 1 , Jae-Hyun Ryou 1 , Russell Dupuis 1
1 School of ECE, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractIn this paper, we propose a new growth scheme of digitally-alloyed modulated precursor flow epitaxial growth (DA-MPEG) using metalorganic and hydride precursors at relatively low temperatures and demonstrate high-quality AlGaN layers with high Al content (> 50%) grown on AlN/sapphire template/substrates by DA-MPEG. A period of DA-MPEG consists of an AlN sub-layer by modulated precursor flow epitaxy growth and an AlyGa1-yN sub-layer. The overall composition of the ternary AlxGa1-xN material by DA-MPEG can be controlled by adjusting the group III mole fraction of the atomic AlyGa1-yN sub-layer and AlGaN layers with Al composition of 0.81 and 0.66 were achieved. X-ray diffraction rocking curves and optical transmittance results show that the AlGaN materials have good crystalline quality. The surface morphology of DA-MPEG AlGaN with Al composition of 0.81 measured by atomic force microscopy (AFM) shows well-developed step flow in all scan areas, which is comparable to high-temperature-grown AlGaN and free from nano-pits. RMS roughness was measured to 0.152 nm and 1.713 nm for 1×1 and 5×5 μm2 scan areas, respectively. AFM images of AlGaN with Al composition of 0.66 tend to be slightly rougher than AlGaN with Al composition of 0.81, especially in larger scan areas. This tendency might be originated from larger lattice mismatch between AlN and Al0.45Ga0.55N sub-layer. However, the surface of AlGaN with Al composition of 0.66 also shows pit-free smooth surface and maintains RMS roughness around 2 nm, suggesting managed layer strain by DA-MPEG. Detailed experimental results will be presented.
5:45 PM - A4.6
Optimization of GaN Barriers During the Growth of InGaN/GaN Quantum Wells at Low Temperature.
Kalyan R Kasarla 1 , W. Chiang 1 , D. Korakakis 1
1 Lane Department of Computer Science and Electrical Engineering, West Virginia University, Morgantown, West Virginia, United States
Show AbstractGroup III- nitrides have emerged as a promising material system for optoelectronic applications ranging from infrared to ultraviolet regions as well as for high power/high temperature and high frequency electronics. In particular, quantum wells (QWs) based on InGaN active layers have been playing a key role in the achievement of high brightness blue and green light emitting diodes (LEDs) and laser diodes (LDs) [1,2]. Inspite of the progress made during last several years in the growth technologies; there are still a lot of unresolved issues related to InGaN multi quantum well (MQW) growth. Large lattice mismatch and low miscibility between InN and GaN lead to misfit dislocations and stacking faults, also In incorporation decreases with increase in growth temperature. The lower temperature growth of barriers in these MQW’s is characterized by increase in V-defects which affect the reliability and the lifetime of the devices. Literature suggests the growth of these barriers at an increased temperature when compared to the growth of the InGaN well to reduce the density of these defects [3]. In this work, growth mechanisms for the reduction of density of defects with out affecting the surface morphology at low temperatures are discussed. InGaN/GaN MQWs are grown on c-plane sapphire substrates using a low pressure metal organic vapor phase epitaxy (MOVPE) system. Trimethylgallium (TMGa), Triethylgallium (TEGa), Trimethylindium (TMIn) and ammonia were used as precursors for Ga, In and N, respectively and the growths were carried out at low temperature. Structural properties of grown MQWs are characterized using atomic force microscopy (AFM), and scanning electron microscope (SEM) and x-ray diffraction technique (XRD) is used to calculate the Indium incorporation in these MQWs. Surface morphologies over large areas of InGaN/GaN MQWs are observed using the tapping mode AFM; results indicate the surface roughness depends on the barrier thickness. Our results indicate roughness values of about 1nm rms for a 5nm barrier width and about 1.5nm rms for a 10nm barrier width. Density of V- defects, effect of growth time of barriers and wells on the surface morphology and also on V-defect density will be presented and discussed. Transmission spectroscopy results on these different samples will also be presented.Reference:[1]. Nakamura S, Mukai T and Senoh M, 1994 Appl. Phys. Lett. 64 1687[2]. Nakamura S, 1999 Semicond. Sci .Technol. 14 R27[3]. Senthil Kumar M, Park J Y, Lee Y S, Chung S J, Hong C-H and Suh E-K, 2007 J.Phys. D: Appl. Phys. 40 5050
Symposium Organizers
Michael Mastro U.S. Naval Research Laboratory
Jeffrey LaRoche Raytheon RF Components
Fan Ren University of Florida
Jen-Inn Chyi National Central University
Jihyun Kim Korea University
A5: Nano Devices
Session Chairs
Charles Eddy
Blake Simpkins
Tuesday AM, December 02, 2008
Room 202 (Hynes)
9:30 AM - A5.1
Quantum Dot Nanodevice with Electron-lattice Coupling.
Karel Kral 1
1 , Institute of Physics, ASCR, v.v.i., Prague 8 Czechia
Show AbstractThe multiple scattering of electrons on LO phonons in quantum dots, included in the electronic quantum kinetic equation in the self-consistent Born approximation to the electronic self-energy, leads not only to the fast electronic energy relaxation [1,2] in these nanostructures, but also to the effect of the upconversion of electronic level occupation in quantum dots [1]. From the experimental point of view the upconversion theoretical mechanism can give an alternative explanation of the lasing of the quantum dot lasers from the higher excited electronic states. Recently the self-consistent Born approximation has also been shown to provide an explanation of the shape of the luminescence spectral line of individual quantum dots, namely the form of a very narrow peak with a shoulder at the low-energy side.The mechanism of the up-conversion is likely to play an important role in the open nanostructures like those of a quantum dot connected to two electrodes, or in similar structures. We present some theoretical results on the electronic transport in such a zero-dimensional nanostructure, or a nanotransistor, in which we demonstrate the influence of the multiple-phonon scattering of electrons. Upon using the simple well-known Toy Model of Supprio Datta, or alternatively upon using the Meir and Wingreen formulation of the electronic transport in nanodevices, we are going to show that in an asymmetric nanodevice we can meet an effect of a spontaneous electric potential step generation between the two electric contacts of such a device. This will be documented numerically on a model of the active region of the nanotransistor having two electronic bound states. The presently discussed approximation uses the Toy Model for the electronic transport between the electric wires and the quantum dot, while the electron-LO-phonon interaction effect is included as a mechanism added to the mechanism based on the Toy Model. The electron-phonon coupling is included in the self-consistent Born approximation to the electronic self-energy. The relation of the presented theoretical results to some measurements of current-voltage characteristics of nanodevices will be discussed.The work was supported by the grant ME 866 OS of MSMT and by the project AVOZ10100520.References[1] K. Král, P. Zdeněk, Z. Khás, Surface Science, 566-568, p. 1, pp. 321-326 (2004).[2] K. Král, Czech. J. Phys. 56, 33-40 (2006).
9:45 AM - A5.2
High Performance Field-effect-transistors and Logic Circuits Constructed on CdS Nanowires/belts.
Lun Dai 1
1 School of Physics, Peking University, Beijing China
Show AbstractMetal-semiconductor field-effect-transistors (MESFETs) based on single CdS nanobelts (NBs) and nanowires (NWs) have been fabricated and studied. The single CdS NB MESFETs exhibit n-channel depletion (normally-on) mode, low threshold voltage (~–1.56 V), high transconductance (~3.5 μS), low subthreshold swing (~45 mV/dec), and high on/off current ratio (~2 108). The single CdS NW MESFETs exhibit n-channel enhancement (normally-off) mode, low threshold voltage (~ 0.18 V), and an on/off current ratio of about 5 103. We also find out that the operating voltage, and the transconductance for the metal-insulator-semiconductor field-effect-transistors made on a single CdS NB can be reduced from ~12.5 to ~0.4 V and increased from ~0.2 to ~3.2 μS, respectively, by fabricating an extra Au Schottky contact on the CdS NB, the mechanism of which is discussed. Based on the high performance single CdS NW MESFETs, logic NOT gates (inverters), logic NOR and NAND gates have been constructed. The inverter has a voltage gain as high as 83, which is, so far, the highest reported value for the inverters made on one-dimensional nanomaterials. KEYWORDS: A. CdS; B. nanobelts; C.nanowires D. Schottky junction; E. FET* Author to whom correspondence should be addressed; electronic mail: lundai@pku.edu.cn
10:00 AM - A5.3
Superior Neutron-irradiation Hardness for Solution-grown ZnO Nanocrystals.
Elena Flitsiyan 1 , Casey Schwartz 1 , Robert Peale 1 , Oleg Lupan 1 2 , Leonid Chernyak 1 , Lee Chow 1 , William Vernetson 3
1 Physics, University of Central Florida, Orlando, Florida, United States, 2 Microelectronics/ Semiconductor devices, Tech Univ Moldova, Chisinau Moldova (the Republic of), 3 Nuclear Radiological Eng, Univ of Florida, Gainsville, Florida, United States
Show AbstractPrevious studies with light particle irradiation (electrons or protons) or ion implantation indicate that ZnO is more radiation hard than other common semiconductors such as Si, GaAs, CdS and GaN, suggesting that ZnO devices are promising for electro-optical space applications. We report here, as has been found for GaN, that nanostructuring further enhances the radiation hardness of ZnO. ZnO nano-rods were grown from solution and compared with bulk hydrothermally grown samples as a function of thermal neutron irradiation, which introduces the transmutation products Cu, Ga, and F as well as lattice damage. Hall effect measurements for bulk samples reveal that a flux of 3.6 x 1017 n/cm2 leads to n-type material with a 50 x increase in electrically-active shallow donor concentration after annealing in comparison with unirradiated material. The near-band-edge cathodoluminescence peak strengthens after irradiation due likely to an increase in donor-acceptor pair recombination. A broad visible band strengthens and blue shifts with irradiation. Comparison of these cathodoluminescence effects for bulk and nanorods indicate that the changes are one order of magnitude smaller for the nano-rods. We suggest that this enhanced radiation hardness is due to the larger surface-to-volume ratio for the nano-rods, which facilitates defect migration to the ZnO surface during irradiation.
10:15 AM - A5.4
Modeling and Fabrication of Cladded Ge Quantum Dot Gate Silicon MOSFETs Exhibiting 3-State Behavior.
Faquir Jain 1 , Mukesh Gogna 1 , Fuad Alamoody 1 , Suprya Karnakar 1 , Ernesto Suarez 1 , John Chandy 1 , Evan Heller 2
1 Electrical and Computer Engineering, University of Connecticut, Storrs, Connecticut, United States, 2 Design Group, RSoft Inc, Ossinings, New York, United States
Show AbstractRecently, we reported the observation of 3-state behavior in SiOx-cladded Si quantum dot gate Si FETs. The drain current-gate voltage Id-Vg characteristics exhibited an intermediate state “i” that was explained, using a model that self-consistently solves Schrödinger and Poisson equations with built-in transfer of carriers from the inversion channel to two layers of cladded SiOx-Si quantum dots (QDs) forming the gate.This paper presents preliminary transfer and output characteristics of a GeOx-cladded-Ge quantum dot gate Si MOSFETs. Similar to QD-gate Si FETs, Ge quantum dot gate FETs show an intermediate 'i' state in Id- Vg characteristic. This state is manifested when an increase in gate voltage Vg is compensated over a range by an increase in effective threshold voltage via charge neutralization in the QD gate, resulting in an intermediate state ‘i’. This paper also describes the methodlolgy to site-specifically self-assemble cladded Ge dots (~2nm) on channel region to form the QD gate. In addition, capacitance-voltage behavior recently observed in GeOx-cladded-Ge quantum dot gate Si MOS capacitors that distinctly show two threshold regimes (that is, a step in the capacitance plot) corresponding to presence of an intermediate state. This results in a novel plateau in the C-V behavior. Quantum dot (QD) gate memories have been fabricated in a number of ways since the first reporting by Tiwari et al. [1]. During the fabrication of self-assembled quantum dot gate nonvolatile memories, it was observed that certain QD gate FET structures exhibit a novel intermediate state in the transfer (drain current Id-gate voltage Vg) characteristic not observed in conventional FETs [2]. That is, the transfer characteristics show three stable states ("0", "1" and "i"), where the low-current saturation state "i" is manifested over a range of gate voltages. In QD-gate FETs, the threshold voltage depends on the charge in the gate region (e.g. discrete charge on quantum dots located in two layers and insulator-semiconductor interfaces, etc). The net charge depends on the tunneling rate of electrons from channel to the QDs. This in turn neutralizes the positive charge at the GeOx-Ge boundaries and elsewhere in the gate, increasing the effective threshold voltage. An increase in effective VTH (beyond the first threshold) produces an intermediate state region in which drain current does not increase as much with Vg. This also explains reduction of dQ/dV for the gate capacitance in this region. The 3-state FETs can be used for analog and digital circuits including multiple-valued logic [MVL]. [1] S. Tiwari, F. Rana, K. Chan, H, Hanafi, W. Chan and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage,” IEDM, pp. 521-525, Dec. 1995.[2] F. C. Jain, E. Heller, S. Karmakar, and J. Chandy, Device and Circuit Modeling using Novel 3-State Quantum Dot Gate FET, ISDRS Proc. December 11-14, 2007 (College Park, Md).
10:30 AM - A5.5
Barrier Heights at Nanoscale Metal-Semiconductor Contacts.
Ramsey Kraya 1 , Dawn Bonnell 1
1 Materials Science and Engineering, University of Pennsylvania, Philadelphia, Pennsylvania, United States
Show AbstractThe issue of charge transport across nanoscale metal-semiconductor interfaces is of primary importance in the downscaling of components for future electronic devices. The present paper provides new information on the conduction mechanisms involved across such barriers, namely between SrTiO3 and gold nanocontacts, as a function of contact size. SrTiO3 (STO) is a common perovskite oxide with an atomically smooth surface, and is used as a substrate for superconductors, in thin film electronics, and potentially in future VLSI systems. To determine the barrier heights and transport characteristics as a function of contact size, current-voltage and capacitance-voltage measurements were performed on gold/ STO interfaces at temperatures ranging from 15-125oC.
10:45 AM - A5: Nano
BREAK
A6: Optoelectronics
Session Chairs
Charles Eddy
Michael Shur
Tuesday PM, December 02, 2008
Room 202 (Hynes)
11:30 AM - A6.2
Mass Production of Optoelectronic Devices for Solid-State-Lighting (SSL).
K. Christiansen 1 , B. Schoettker 1 , A. Boyd 1 , B. Schineller 1 , Brian Dlugosch 1 , C. Sommerhalter 1 , R. Schreiner 1 , M. Heuken 1
1 , AIXTRON AG, Aachen Germany
Show AbstractWe addressed the issue of cost reduction for the mass production of SSL devices by developing two new reactor configurations for the AIX2800G4 HT Planetary Reactor® (11x4 inch) and CRIUS® Close-Coupled-Showerhead (CCS) (12x3 inch) platforms, respectively. To assess the performance of the new reactor configurations, layers and test structures were grown using standard precursors and growth conditions and characterized using a Nanometrics VERTEX photoluminescence setup and a Panalytical X-Pert MRD-Pro X-ray diffraction (XRD) system.For a 4 µm thick GaN:Si layer grown in the AIX2800G4 HT in the 11x4 inch configuration, an XRD full-width-at-half-maximum (FWHM) of 293 arcsec was measured for the (102)-reflex. The electron concentration was at 4.7x1018 cm-3 without any measurable deviation from center to edge of the wafer. The electron mobility was determined to be 240 cm2/Vs for these layers. The absolute max-min wafer to wafer (w2w) thickness deviation was Δdw2w=±0.03 µm at a mean thickness of 4 µm for all 11 wafers. For p-type GaN:Mg layers the same growth rate performance was achieved. Hall-effect measurements showed a mean hole concentration of 4.7x1018 cm-3 with a total max-min spread of 7% from center to edge of the wafer. The hole mobility was established to be 9 cm2/Vs.AlGaN-ternary alloy layers were grown at 100 mbar for the two device relevant Al-concentrations of 10% and 30%. Al-composition measurements yielded a spread of xAl,30%=0.9% and xAl,10%=0.1% for the 30% and 10% case, respectively. The thickness uniformity standard deviation of both layers was determined to be on the order of σd=1.7% for both layers.To assess the performance for the growth of the active layers of the LED, 5 period InGaN/GaN-multi-quantum-well (MQW) structures were grown on 4 µm thick GaN:Si buffers. PL mappings yielded absolute max-min deviations of the wavelength of Δλw2w=±1.1 nm for a mean wavelength of 460 nm for all 11 wafers.For the 12x3 inch CRIUS® tool room-temperature PL mappings over 12 wafers of the same run showed a max-min total spread of the wavelength of Δλw2w=±1.45 nm for a mean wavelength of λ = 470.8 nm (blue spectral range). The standard deviation of the wavelength on wafer was about σλ,1w=1.53 nm for the same run. White-Light-Interference (WLI) thickness measurements yielded a mean thickness of the layer stacks of d = 6.03 µm with a total max-min spread of Δdw2w=±0.02 µm. The standard deviation of the thickness on wafer was on the order of σd,1w=2.9%. All measurements were evaluated without any edge exclusion.In the green spectral range a max-min spread of the wavelength of Δλw2w=±2.4 nm was found for a mean wavelength of λ=537 nm. The mean on-wafer standard deviation of the wavelength was measured to be σλ,1w=2.94 nm. WLI thickness measurements yielded a mean thickness of d = 6.07 µm with a max-min spread of Δdw2w= ±0.15 µm for the same set of 13 wafers. The on-wafer thickness distribution was σd,1w=3%.
11:45 AM - A6.3
Growth and Performance of InP/InAlGaAs Light Emitting Transistors and Transistor Lasers.
Russell Dupuis 1 , Yong Huang 1 , Jae-Hyun Ryou 1 , Forest Dixon 2 , Milton Feng 2 , Nick Holonyak 2
1 School of ECE, Georgia Institute of Technology, Atlanta, Georgia, United States, 2 Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, Illinois, United States
Show AbstractLight emitting transistors (LETs) and transistor lasers (TLs) operating at around 1.55 μm were investigated using InP/InAlGaAs heterostructures grown by metalorganic chemical vapor deposition (MOCVD). LET structures were realized by incorporating InGaAs quantum wells (QWs) in the base region of the N-InP/p-InAlGaAs/N-InAlAs double heterojunction bipolar transistors (HBTs), and a current gain of 45 and light emission at 1650 nm were demonstrated. The light output was found to be linearly proportional to the base current. By increasing the thickness of the emitter to enhance the optical confinement, laser operation of the transistor was achieved at -180 oC with a threshold current of 12 mA. Secondary ion mass spectroscopy shows that the p-type dopant in the base doping, zinc (Zn), which is commonly used in the growth of InAlGaAs, diffuses into the emitter and the base active QW region, leading to compromised electrical performance and light output intensity. Consequently, an alternative low-diffusivity dopant, carbon (C), was studied and a LET with a C-doped base was grown and fabricated. The highest light output was recorded for the C-doped LETs owing to the improved quality of the active layer.
12:00 PM - A6.4
Cathodoluminescence Study of the Defects Created by the Degradation of High Power AlGaAs/GaAs Multiemitter Laser Bars.
Alonso Martin 1 , Pilar Iniguez 1 , Manuel Avella 1 , Juan Jimenez 1 , Myriam Oudart 2 , Julien Nagle 3
1 Física Materia Condensada, Universidad de Valladolid, Valladolid Spain, 2 , Alcatel Thales 3-5 Lab, Palaiseau France, 3 , Thales Research and Technology (TRT), Palaiseau France
Show Abstract12:15 PM - A6.5
Comparative Characteristics of GaAs Detectors and Silicon Pixel Detectors with Internal Amplification.
Gennady Koltsov 1 , V. Murashev 1 , A. Chubenko 2 , R. Mukhamedshin 3 , G. Britvich 4 , S. Chernykh 1 , A. Chernykh 1
1 , Moscow State Institute of Steel and Alloys, Moscow, -, Russian Federation, 2 , Lebedev Physical Institute of RAS, Moscow Russian Federation, 3 , Institute for Nuclear Research of RAS, Moscow Russian Federation, 4 , Institute for High Energy Physics, Protvino Russian Federation
Show Abstract12:30 PM - A6.6
Single Longitudinal Mode InGaAsSb/AlGaAsSb Lasers for Gas Sensing.
Pedro Barrios 1 , James Gupta 1 , Jean Lapointe 1 , Geoffrey Aers 1 , Craig Storey 1
1 Institute for Microstructural Sciences, National Research Council of Canada, Ottawa, Ontario, Canada
Show AbstractResearch for gas sensors is of global significance and is rapidly expanding, fueled by new applications based on ever-growing public concerns over such issues as pollution, health and safety at work. Fortunately, many gaseous byproducts of industrial processes have strong absorption features in the mid-infrared, which can be conveniently monitored using tunable diode laser absorption spectroscopy (TDLAS). In this work, single-mode lasers were developed for TDLAS monitoring near 2.4μm. The laser structures were grown on GaSb substrates by MBE in a V90 system. The laser structure consists of 2um-thick Te- and Be-doped Al0.6Ga0.4As0.0516Sb0.9484 cladding layers lattice-matched to the GaSb substrate. The active region contains three 94.2Å In0.4Ga0.6As0.14Sb0.86 quantum wells separated by 300Å Al0.24Ga0.76As0.021Sb0.979 barriers, embedded in an Al0.24Ga0.76As0.021Sb0.979. Uniform doping of 2x1018 cm-3 was used throughout the n-cladding, while the p-cladding doping was carefully graded close to the waveguide to reduce optical losses. This structure was designed using the approach of Ref. [1], which uses a broader optical waveguide mode in order to reduce the fast-axis beam divergence. Distributed feedback lasers (DFBs) were fabricated following a similar method to that of Ref. [2], which involves the deposition of lateral metal gratings on either side of a narrow ridge waveguide to provide evanescent coupling to the optical mode. The ridges were fabricated using inductively-coupled plasma reactive ion etching (ICP-RIE). E-beam lithography was used to write the lateral gratings using ZEP resist. First-order Cr gratings with a 50% duty cycle and a thickness of 40nm were deposited by e-beam evaporation and lift-off process. A 150nm SiO2 layer was deposited on the grating for insulation before TiPtAu was deposited on top of the ridges. Samples were thinned and coated on their backside with NiGeAu.The Ith for a 400um-long DFB device was 45mA, with a total output power of nearly 11mW in CW operation at 20°C. The emission spectra were single-mode throughout the entire range of operation, attesting to the strong grating coupling, even for the rather short cavity length. The current tuning was well-described by a 2nd-order polynomial, and at the target wavelength of 2395.8nm the tuning is 0.062nm/mA. Adjustment of the heatsink temperature results in a tuning coefficient of 0.2nm/K. The DFB wavelength can also be readily adjusted by varying the grating pitch, Λ, e.g. the wavelength was shifted from 2396nm to 2376nm by varying Λ from 339.6nm to 336.65nm. This provides a means of monitoring many gases using lasers from a single epiwafer by adjusting the grating pitch, operating temperature and current.[1] M. Rattunde, J. Schmitz, G. Kaufel, M. Kelemen, J. Weber and J. Wagner, Appl. Phys. Lett. 88, 081115 (2006)[2] M. Kamp, J. Hofmann, F. Schäfer, M. Reinhard, M. Fischer, T. Bleuel, J.P. Reithmaier and A. Forchel, Opt. Mater. 17, 19 (2001).
12:45 PM - A6.7
Metamorphic GaAsP ~1.7 eV Solar Cell Materials and Structures Grown on Si Substrates Using Anion-Graded GaAsyP1-y Buffers.
Tyler Grassman 1 , Mark Brenner 1 , Andrew Carlin 1 , Steve Ringel 1
1 Electrical and Computer Engineering, The Ohio State University, Columbus, Ohio, United States
Show AbstractA7: SiC Devices
Session Chairs
Kurt Gaskill
John Williams
Tuesday PM, December 02, 2008
Room 202 (Hynes)
2:30 PM - **A7.1
4H-SiC Power DMOSFETs – Performance and Reliability.
Sei-Hyung Ryu 1 , Sarah Haney 1 , Sarit Dhar 1 , Brett Hull 1 , James Richmond 1 , Craig Capell 1 , Anant Agarwal 1
1 , Cree, Inc., Durham, North Carolina, United States
Show AbstractProgresses in 4H-SiC Power MOSFET technology and materials quality in recent years resulted in demonstrations of 4H-SiC DMOSFETs with performances not available in Silicon devices. Current ratings have also been increasing steadily, making power MOSFETs in 4H-SiC suitable for practical applications. However, for a successful commercialization of power MOSFETs in 4H-SiC, several issues, such as device stability, robustness, and reliability, must be addressed in addition to further performance improvements.The most important issue for a 4H-SiC power MOSFET is achieving a sufficiently positive and stable threshold voltage (Vth). The NO Post Oxidation Anneal (POA) currently used in the fabrication of 4H-SiC power MOSFET provides adequate MOS channel mobility. However, the Vth is too close to zero, resulting in a very small noise margin. At operating junction temperatures, around 150C, trapping at the MOS interface reduces, and the MOS channel mobility improves. In addition, bulk electron mobility decreases with temperature, which results in greater drift resistance. As a result, the MOS channel resistance accounts for a smaller fraction of the device on-resistance. This suggests that a small sacrifice in MOS channel mobility is acceptable in exchange for a more positive Vth, which results in a more stable operation.One of the approaches for a more positive Vth is to increase the p-well concentration. Test MOSFETs, with p-well concentrations ranging from 1E15 cm-3 to 5E18 cm-3 have been fabricated. It was shown that the Vth shifts more positive with increasing p-well concentration, but the MOS mobility decreases. A 2V positive shift in Vth was observed when p-well concentration was increased from 5E15 cm-3 to 1E17cm-3, but approximately a factor of 2 decrease in MOS channel mobility (μch) was also observed. The other approach is to vary the NO POA temperatures. Two different NO POA temperatures, 1100C and 1175C, were used in this experiment. The 1100C NO annealed device showed approximately 1.25 V more positive Vth compared to that of the 1175C sample. The Vth was further shifted positive by 1 V after a subsequent forming gas anneal. However, a factor of 2 decrease in μch was also observed. Further analysis of these samples and additional experimentation with other oxidation techniques are in progress. The 4H-SiC DMOSFETs are also being tested for stability, robustness and reliability. The 1.2 kV 4H-SiC DMOSFETs have been characterized for avalanche robustness. The High-Temperature-Reverse-Bias (HTRB) tests are being performed on power DMOSFETs and the Time-Dependent-Dielectric-Breakdown (TDDB) tests are being done on gate dielectrics. In addition, characterization for on-state stability on the built-in body diodes and Vth on the 4H-SiC power DMOSFETs are being performed. Detailed results of the experiments on 4H-SiC power DMOSFETs and test structures will be presented at the conference.
3:00 PM - **A7.2
Growth of High Quality SiC for Power Device Applications.
Charles Eddy 1 , Brenda VanMil 1 , Kok-Keong Lew 1 , Rachael Myers-Ward 1 , Kurt Gaskill 1 , Robert Stahlbush 1 , Yoosuf Picard 1 , Mark Twigg 1 , Paul Klein 1 , Evan Glaser 1 , Ronald Holm 1 , Joshua Caldwell 1
1 , U.S. Naval Research Laboratory, Washington, District of Columbia, United States
Show AbstractFor some time, the wide bandgap semiconductor silicon carbide (SiC) has been identified as the material of choice for future high-voltage, high-power electronic device technologies. However, the full realization of this potential has been slow to develop. A significant factor in this delay has been the slow, but steady, maturation of large-area, high-quality substrates. An equally important contributor has been the rate of development of growth methods for the high quality epitaxial layers required in the power device structure. These layers, which must block large voltages in reverse bias, need to possess very low defectivity, both in terms of point defects and extended defects. This presentation will highlight important recent advances that are vastly improving the properties of SiC epilayers grown by hot-wall chemical vapor deposition. Research on substrate surface preparation, high purity growth processes, and growth interrupts to realize epilayers with smooth surface morphologies, long injected carrier lifetimes and significantly reduced extended defectivity will be presented. A careful examination of surface evolution while being ramped to the growth conditions used in SiC epitaxy (hydrogen at 1600°C) is conducted to ensure that in situ etch processes result in optimal substrate surface morphology, that being bilayer atomic steps, producing smoother epitaxial surfaces and interfaces. Long injected carrier lifetimes are essential to the performance of any bipolar high-voltage power switch and we shall show that low background doping (or equivalently high purity) of epilayers and substrate properties (even subtle imperfections) can significantly impact the lifetime of injected carriers in unintentionally or intentionally low-doped epilayers (< 1x1014 cm-3). Lifetimes exceeding 5 microseconds, as measured by microwave photoconductive decay, have been realized in epilayers that were grown under conditions to address these issues. Finally, it has been well reported that extended defects, namely basal plane dislocations and associated stacking faults, can significantly degrade the performance of SiC bipolar devices. We shall present results showing that in situ growth interruptions can significantly reduce the basal plane dislocation density in epilayers – down to the level required for high-voltage power device technologies. The combination of these advances has led to realization of epilayers with properties that are rapidly approaching those that are required for the desired device technologies.
3:30 PM - **A7.3
Low Defect Density Silicon Carbide Epitaxial Layers for Large-Area, High-Power Devices.
Al Burk 1 , Michael O'Loughlin 1 , Jonathan Young 1 , Lara Garrett 1 , Joe Sumakeris 1
1 , Cree, Durham, North Carolina, United States
Show Abstract4:00 PM - A7.4
Electrical Characterization of Epitaxial MgO on SiC.
Agham Posadas 1 , Fred Walker 1 , Charles Ahn 1 , Trevor Goodrich 2 , Zhuhua Cai 2 , Katherine Ziemer 2
1 Applied Physics, Yale University, New Haven, Connecticut, United States, 2 Chemical Engineering, Northeastern University, Boston, Massachusetts, United States
Show AbstractOne limitation on the performance of field effect transistors based on the wide bandgap semiconductor SiC is the breakdown of the gate dielectric before reaching the high fields needed for optimum transistor operation. Alternative gate dielectrics that are more electrically matched to the SiC while simultaneously providing a high quality interface with the semiconductor are needed to work around this limitation. Here, we report on the growth and electrical properties of epitaxial MgO (111) crystalline layers grown on 6H-SiC (0001) substrates.We measured the capacitance vs. voltage characteristics of epitaxial MgO grown by MBE on SiC, which shows modulation of the SiC between accumulation and depletion. Capacitance measurements for samples with different MgO thicknesses reveal a dielectric constant of 10 for the epitaxial MgO. Current vs. voltage characteristics of the epitaxial MgO on SiC were also measured and show typical breakdown fields approaching that of bulk single-crystal MgO. These measurements show that epitaxial MgO is a potential alternative gate dielectric for SiC field effect transistors.
4:15 PM - A7: SiC Devices
BREAK
A8: THz and Graphene Devices
Session Chairs
Tuesday PM, December 02, 2008
Room 202 (Hynes)
4:30 PM - **A8.1
Graphene Films Synthesized under High Vacuum Conditions in a CVD Reactor.
D. Kurt Gaskill 1 , B. VanMil 1 , P. Campbell 1 , J. Culbertson 1 , G. Jernigan 1 , R. Myers-Ward 1 , J. McCrate 1 , S. Kitt 1 , C. Eddy Jr. 1
1 , Naval Research Laboratory, Washington, District of Columbia, United States
Show AbstractThe scientific community is keenly interested in exploiting the unique properties of graphene. In particular, fabricating devices based upon this planar form of carbon is of great interest. Thus, it is necessary to form large area, i.e., wafer-size, sheets of graphene with sufficient uniformity to meet lithographic and device requirements. Synthesizing graphene on SiC substrates appears to be an attractive path for meeting such a goal [1]. This presentation will discuss the latest results to form graphene on SiC substrates using an Epigress/Aixtron VP508 SiC epitaxial reactor. This reactor is also being used to grow high quality epitaxial 4H-SiC structures having low unintentional doping (≤1014 cm-3) and high injected carrier lifetime (>2us).Graphene layers were formed on both C- and Si-faces of 4H- and 6H-SiC on-axis semi-insulating substrates; all 4 samples types were grown simultaneously. The SiC substrates were prepared by in-situ hydrogen etching at ca. 1600 °C to remove polishing damages. The graphene layers were subsequently synthesized at temperatures from 1400 to 1500°C under high vacuum conditions (< 10-4 mbar). The film properties were significantly influenced by the surface orientation of the substrate. Graphene on Si-face substrates were conformal to the underlying substrate and were generally thin (<10nm). However, graphene on C-face substrates developed a complex morphology, with atomically flat areas (10-30nm thick) intersected by micron-length ridges (0-50nm high). Surprisingly, the underlying C-face SiC substrate morphology had significantly changed during the graphene formation. The substrate was no longer atomically smooth, as is observed after hydrogen etching, but instead appeared to have irregular steps which were reflected in the overlying graphene film.In an attempt to limit the impact of graphene film non-uniformities on measured properties, the graphene was lithographically patterned and Van der Pauw Hall geometries (2um x 2um) were defined. It was found that film morphology affects the electrical properties of the graphene; examples of smoother regions having higher mobilities for C-face substrates will be presented. Several samples with approximately atomically smooth morphologies and having a smaller number of ridges tended to have the highest 300K mobilities – up to 11,500 cm2 V-1 s-1. Raman spectra were acquired for Hall geometries that exhibited a wide range of mobilities; 1 or 2 distinct peaks centered near 2705 and 2730 cm-1 were observed. Samples with lower mobility tended to show the higher energy peak or portions of both peaks; higher mobility samples tended to show just the lower energy phonon peak. Note that a single sample can contain Hall squares displaying a broad range of mobility variations or Raman peak behaviors, suggesting that controlling the underlying substrate morphology during graphene synthesis may be essential.[1] C. Berger et al., J. Phys. Chem. B 108, 19912 (2004).
5:00 PM - **A8.2
Terahertz Transistors.
Michael Shur 1
1 , Rensselaer, Troy, New York, United States
Show AbstractThe quest to reach higher and higher speeds and operation frequencies has driven transistor feature size down to the ballistic or quasi-ballistic limit. [1] In this regime, conventional rules do not apply, and the effective field effect mobility becomes proportional to the gate length. [2] The channel impedance becomes an oscillatory function of frequency. [3] This happens because the electron inertia starts playing a dominant role at small feature sizes and/or at high frequencies leading, among other effects, to instability of the waves of electron density – plasma waves. [4] These waves enable the transistor operation at sub-terahertz and terahertz frequencies, and, in the ballistic limit, the channel acts a resonant cavity for the plasma waves. These waves become unstable when driven by the electron current. Tunable terahertz emission attributed to this instability has been observed in InGaAs and GaN-based transistors, including recent reports of room temperature emission. [5] The emitted intensity was low (on the order of nanowatts from a single device). However, the theory predicts much orders of magnitude higher intensity for devices arrays with optimized coupling. Excitation and rectification of plasma waves can be used for detection of terahertz radiation impinging on a FET and exciting electron density waves in the gated and ungated sections of the device channel. [6] (The waves in the ungated sections have a much higher frequency and couple more efficiently to the THz radiation but can they still be tuned by the gate bias.) Plasma wave THz electronics based on these ideas holds promise of developing tunable efficient sources and tunable sensitive detectors of sub-THz and THz radiation using arrays of nanoscale field effect transistors.[1] M. S. Shur and L. F. Eastman, IEEE Transactions Electron Devices, Vol. ED-26, No. 11, pp. 1677-1683, November (1979)[2] A. A. Kastalsky and M. S. Shur, Solid State Comm. Vol. 39, No. 6, p. 715-718 (1981)[3] A. P. Dmitriev and M. S. Shur, Appl. Phys. Lett., 89, 142102, (2006)[4] M. Dyakonov and M. Shur, Phys. Rev. Lett., vol. 71, 2465, (1993)[5] N. Dyakonova et al. Applied Physics Letters, vol. 88, 141906, (2006)[6] W.J. Stillman and M.S. Shur, Vol. 2, Number 3, pp. 209-221, December 2007
5:30 PM - A8.3
Emission of Terahertz Radiation from SiC.
Jared Strait 1 , Paul George 1 , Shriram Shivaraman 1 , Mvs Chandrashekhar 1 , Farhan Rana 1 , Michael Spencer 1
1 Electrical and Computer Engineering, Cornell University, Ithaca, New York, United States
Show AbstractWe report for the first time the emission of strong terahertz (THz) radiation from hexagonal Silicon-Carbide (SiC) via nonlinear difference-frequency-generation. The large bandgap and large thermal conductivity of SiC make it a promising candidate for high-field and high-power electronics [1]. More recently, SiC-based electrically pumped THz emitters have been demonstrated [2]. The nonlinear optical properties of various polytypes of SiC have also been studied [3]. In this paper, we present results on the emission of terahertz radiation from 6H-SiC using femtosecond optical pulses. Broadband terahertz generation and detection with optical pulses is a powerful and well-studied method with applications in spectroscopy, imaging and sensing [4]. Optical pulses with width ~90 fs, center wavelength ~780 nm, and energies varying from 1-15 nJ were used for excitation of semi-insulating c-cut 6H-SiC wafers, thickness ~500 microns. The emitted THz pulses were detected using a balanced electro-optic detection setup [4]. Strong THz pulses with signal-to-noise ratios better than ~1 million and detection-limited bandwidths wider than ~3 THz were observed.Most III-V semiconductors, such as GaAs and InAs, emit broadband THz pulses upon excitation with optical pulses due to free-carrier generation and their subsequent dynamics [4]. The large bandgap of SiC (> 3 eV) suggests that free-carrier generation via interband absorption plays a minor role in THz emission. However, free-carrier generation via defect or two-photon absorption cannot be ruled out. The mechanism responsible for THz emission from SiC was explored by varying the power, the angle of incidence, and the polarization of the optical excitation. The emitted THz radiation was found to be strongly dependent on the angle of incidence and polarization of the optical excitation. Both dependencies were found to be in perfect agreement with the optical rectification model. The average value of the ratio of the two independent components of the second-order electric susceptibility tensor, χ2zzz and χ2zxx, was found to be approximately -2, also in approximate agreement with the theory [5]. In addition, the peak THz field was found to be proportional to the square of the optical pulse field. These observations suggest difference-frequency-generation via optical rectification as the mechanism responsible for THz emission. In this paper we discuss in detail THz generation from SiC and compare the properties of SiC to other nonlinear crystals for generating THz radiation. [1] R. Yakimova, Physica Scripta, T126, 121 (2006)[2] P. C. Lv, X. Zhang, J. Kolodzey, A. Powell, Appl. Phys. Lett., 87, 241114 (2005). [3] P. M. Lundquist, W. P. Lin, G. K. Wong, M. Razeghi, J. B. Ketterson, Appl. Phys. Lett., 16, 1883 (1995). [4] K. Sakai (Ed.), Terahertz Optoelectronics, Springer, NY (2005). [5] S. Niedermeier, H. Schillinger, R. Sauerbrey, B. Adolph, F. Bechstedt, Appl. Phy. Lett., 75, 618 (1999).
5:45 PM - A8.4
Terahertz Ellipsometry Using Electron-Beam Based Sources.
Tino Hofmann 1 , C. Herzinger 2 , U. Schade 3 , M. Mross 4 , J. Woollam 2 , M. Schubert 1
1 , University of Nebraska-Lincoln, Lincoln, Nebraska, United States, 2 , J.A. Woollam Co., Lincoln, Nebraska, United States, 3 , BESSY mbH, Berlin Germany, 4 , Vermont Photonics Technologies Co., Bellows Falls, Vermont, United States
Show AbstractThe precise determination of materials' optical constants in the THz frequency domain is an important new challenge in basic research and is crucial for novel technological applications. Spectroscopic ellipsometry is known as a vital tool for the determination of the materials’ dielectric function including its anisotropy. However, ellipsometric measurements at very long wavelengths are difficult due to the lack of reliable sources of sufficient intensity and brilliance. Here we report on our recent advances to use ellipsometry in combination with different electron beam based sources in order to in investigate condensed matter samples in the frequency range from 0.1 to 8 THz. We successfully employ terahertz radiation emitted from a broad band terahertz synchrotron radiation source (BESSY II, Berlin) and two different tunable table top sources (Smith-Purcell-effect source and a backward wave oscillator) in a polarizer-sample-analyzer ellipsometer scheme. We discuss and present THz range physical material properties due to bound and unbound charge resonances in low-dimensional semi- and superconducting materials. This research will provide important understanding of optical properties for novel materials, inspire new designs, and accelerate development of optical Terahertz devices.
A9: Poster Session: Semiconductor Devices
Session Chairs
Wednesday AM, December 03, 2008
Exhibition Hall D (Hynes)
9:00 PM - A9.1
DLTS Study of Inductively Coupled Plasma Induced Defects in the Near-surface Region of N-type GaN.
Yutaka Tokuda 1 , Kazuki Akiyama 1 , Takeshi Seo 1 , Hiroyuki Ueda 2 , Osamu Ishiguro 2 , Narumasa Soejima 2 , Tetsu Kachi 2
1 Department of Electrical and Electronics Engineering, Aichi Institute of Technology, Toyota Japan, 2 , Toyota Central R&D Labs. Inc., Aichi Japan
Show AbstractWe have characterized inductively coupled plasma (ICP) induced defects in n-type GaN grown by MOCVD on sapphire substrate using DLTS for fabricated Schottky diodes. The ICP etching was performed under a Cl2 plasma at the source power of 300 W and with the rf power of 30 W for 1 min followed by the rf power of 10 W for 2 min. Another ICP etching was done by the addition of 17% BCl3 to a Cl2 plasma. DLTS measurements were carried out in the temperature range from 80 to 400 K for Schottky diodes fabricated after ICP etching, and comparison was made between Cl2 and BCl3/Cl2 plasmas.DLTS with the quiescent bias voltage of -10 V and the filling pulse voltage of 0 V reveals two dominant electron traps labeled E2 (0.25 eV) and E5 (0.59 eV) for the control sample. In addition, there are broad DLTS signals increasing with temperature above 300 K. It is found that a slight variation in DLTS peak intensities is caused by the present ICP etching as compared with the result for the control sample. In order to inspect the plasma-induced damage in more detail, we extended the DLTS measurement depth range to the near-surface region by using the forward-going filling pulse. Then, one peak labeled E1 (0.19 eV), related to the N vacancies, appears for the control sample, which indicates that the N vacancies exist in the near-surface region. Moreover, a substantial increase in DLTS signals is observed for the ICP etched sample, especially by the BCl3/Cl2 plasma. From these results, it is found that the plasma-induced damage is confined in the surface region up to around 60 nm with the higher defect densities in the sample etched by the BCl3/Cl2 plasmas.
9:00 PM - A9.10
In Situ Passivation and Modification of GaAs Surface using TBP by MOVPE.
Hong-Liang Lu 1 , Yuki Terada 1 , Momoko Deura 1 , Yukihiro Shimogaki 2 , Yoshiaki Nakano 3 , Masakazu Sugiyama 1
1 Department of Electronic Engineering, The University of Tokyo, Tokyo Japan, 2 Department of Materials Engineering, The University of Tokyo, Tokyo Japan, 3 Research Center for Advanced Science and Technology, The University of Tokyo, Tokyo Japan
Show Abstract9:00 PM - A9.11
Fabrication and Electrical Properties of Metal/Double-Insulator/Metal Diode.
Kwang Nam Choi 1 , Jun-woo Park 2 , Hosun Lee 2 , Kwan Soo Chung 1
1 Electronic Engineering, KyungHee University, Yongin-si, Gyenggi-do, Korea (the Republic of), 2 Physics and applied phyhsics, Kyunghee University, Yongin-si, Gyenggi-do, Korea (the Republic of)
Show AbstractSilicon based transistor have been the most popularly used switch element. However, silicon based transistor do not conform to high density, nonvolatile memories with three dimensional(3D) stack structures due to their high processing temperatures and the difficulty of growing high quality epitaxial silicon over metals. MIM (Metal Insulator Metal) diodes may provide a suitable rectifying element. MIM diodes are rectifying electron devices made out of metals and insulators. The advantage of the MIM diode over semiconductor rectifiers is its extremely fast response time and wide bandwidth. These attributes make possible the promise of higher speed detection and mixing of optical radiation. Despite this conceptual simplicity fabricating functional and reliable MIM diodes is challenging. However, MIM diodes show less asymmetry and nonlinearity than desired. We would like a diode with increased asymmetry for linear rectification and increased nonlinearity. Most MIM diodes follow Fowler-Nordheim and direct tunneling mechanisms. Moreover, a third possibility is resonant tunneling. Increased asymmetry may be achieved by making the electrons traverse the oxide by resonant tunneling under one polarity of bias and standard tunneling under the other polarity. This situation can be realized by using a multilayer structure between the electrodes instead of the single oxide layer. Therefore, we have fabricated several metal/double insulator/metal diodes using atomic layer deposition. Here, we show metal/double insulator/metal diode applied as a switch element. The diode exhibits good rectifying characteristics at room temperature. We used the electrode material with Pt and insulators were HfO2/ZnO, HfO2/ZrO2 and NiO/ZnO each. The devices were fabricated using the lithographic system and top electrode size were 10~100 μm2. The double insulator diode produces an enhanced nonlinearity by incorporating two adjacent oxides instead of the single oxide layer of the MIM diode. In the double insulator diode the mode of tunneling under positive applied biases can be made different from that under negative applied biases resulting in improved asymmetry.
9:00 PM - A9.12
Device Performance and Reliability Characterization of Interface and Bulk Effect in Amorphous Indium Gallium Zinc Oxide (a-IGZO) Thin Film Transistor.
Kwang-Il Choi 1 , Dong-Ho Nam 1 , Sung-Soo Park 1 , Jae-Kyeong Jeong 2 , Ga-Won Lee 1
1 Electronic Engineering, ChungNam National University, DaeJeon, Yuseong-Gu, Korea (the Republic of), 2 Corporate R&D Center, Samsung SDI Co., Kiheung-Gu, Yongin-Si, Gyeonggi-Do, Korea (the Republic of)
Show Abstracta-IGZO TFT is a promising candidate device for an alternative to poly-Si TFTs or a-Si TFTs, because they provide better uniformity in terms of their important device parameters, including the threshold voltage and mobility due to their amorphous phase, and a high mobility (>10 cm2/Vs) is attainable with these devices even in the amorphous phase. Recently, a-IGZO TFTs have been extensively studied by various groups. However, there is little report on interface and bulk effect on device performances and reliability as separately. For investigating the interface and bulk effect, we fabricated two a-IGZO thin film transistors with different channel deposition conditions, RF and DC magnetron sputtering. Specific conditions of RF and DC sputtering are described as follows; magnetron power density of 1.4 W/cm2/2.0 W/cm2 in Ar/O2 gas ratio of (65/35)/(72/28), and the entire gas pressure was 5.0 mTorr and 3.4 mTorr, respectively.In order to characterize the channel quality, C-V curve was measured with various frequencies of (10KHz~1MHz). RF sputtered channel has higher frequency dependency compared to DC sputtered channel. It means that RF sputtered channel has higher bulk traps in channel compared to DC sputtered channel.Device performance was characterized through the ID-VG measurement. Electrical parameters of RF and DC sputtered devices are VT=3.5/2.7V, on-off ratio=105/108, SS=2/0.4 V/decade, and uFE= 5/11 cm2/V-s, respectively. It is thus clear that the device performance of DC sputtered device is more superior to RF sputtered device. Therefore, it can be said that the poor device performance of RF device is ascribed to insufficient channel quality, as mentioned in C-V curve.For reliability study, we measured PBTI and ID-VG hysteresis with normalized gate stress bias and high temperature hot chuck system. Through the unchanged field effect mobility during the stress and relaxation time, and nearly recovered VT and subthreshold slope (SS) after long relaxation time, we were able to know that pre-existed trap was main factor of reliability degradation. Moreover, SS degradation during stress time is more severe in RF device than DC device. It is also proving that RF channel characteristic is worse than DC channel. In high temperature, leakage current increments of RF device were more severe than DC device. This also indicates that bulk traps of RF device in channel region are larger than that of DC device. VT shift of DC sputtered device for PBT stress and hysteresis was higher than that of RF sputtered device. As well known, PBTI is closely related to insulator bulk traps, which shows that channel deposition conditions affect insulator trap characteristics. In summary, device performance of a-IGZO deposited by DC sputtering is better than RF sputtering, which is because DC sputtering improves channel quality of a-IGZO. However, VT shift of DC sputtered device are worse than RF sputtering, which may be related with high magnetron power density.
9:00 PM - A9.13
Source/Drain Overlap Length Dependence of VT in Thin Film Transistor on a-IGZO Channel Deposited by RF and DC Sputtering.
Dong Ho Nam 1 , Kwang-Il Choi 1 , Sung-Soo Park 1 , Jae-Kyeong Jeong 2 , Ga-Won Lee 1
1 Electronic Engineering, Chungnam National University, Daejeon, Yuseong-Gu, Korea (the Republic of), 2 Corporate R&D Center, Samsung SDI Co., Yongin-Si, Gyeonggi-Do/Kiheung-Gu, Korea (the Republic of)
Show AbstractThe ZnO TFTs have attracted much attention as key component for flexible displays because they can be fabricated on plastic substrates at low temperature and exhib/it good electrical performance(e.g.high field effect mobility). However,the ZnO films are polycrystalline with grain boundaries even if formed at room temperature,which deteriorate the uniformity of TFT characteristics. Recently,a few research groups have reported high performance amorphous indium-gallium-zinc oxide TFTs to solve the native problem of nonuniformity of ZnO TFTs. However,there are few researches on the process parameter effects on the variation of a-IGZO TFT characteristics.In this study, we focus on the effect of the S/D overlap length on threshold voltage(VT) of a-IZO TFTs with differentiating channel deposition method. The experimental structures for this work are bottom-gated TFTs with a-IGZO channel that were deposited by RF and DC magnetron sputtering on glass. RF and DC sputtering were carried out by magnetron power density of (1.4W/cm2)/(2.0W/cm2) in Ar/O2 gas ratio of (65/35)/(72/28), and the entire gas pressure were 5.0 mTorr and 3.4 mTorr. The width/length(um/um) of device was split to 10/7,10/10,10/30,10/50. Each of the patterns has seven source/drain overlap length:-3um,-2um,-1um,0um,1um,2um,3um. We extracted VT of RF and DC through VG-ID curve. There are significant VT difference in both RF and DC according to the overlap length: VT of DC(RF) is 1.31(0.74)V at W/L=10/50 and 10.21(5.74)V at W/L=10/30. VT increases definitely where less than 1um overlap length and short channel TFT is more influenced by overlap length, which is more severe in RF group. We calculated total channel resistance(RT) from VD-ID curve. RT of devices with the positive overlap can be expressed by RT, Postive=Rch+Rc. Here, Rch is net channel resistance which becomes smaller when channel length decreases and Rc is contact resistance. RT with negative overlap, is RT, Negative=Rch+Rc+Roffset. Roffset is offset resistance formed by negative overlap and can be extracted by subtracting RT, Postive from total RT, Negative. The Roffset of DC(RF) at offset channel length of -1um,-2um,and-3um is 4.41×105(2.68×106)Ωcm, 1.14×106(3.46×106)Ωcm, and 1.44×106(4.72×106)Ωcm, respectively(W/L=10/10um).RF group which shows inferior electrical characteristics such as lower mobility and larger subthreshold slope to DC, have larger Roffset than DC. This implies that the devices require a bit of positive source/drain overlap length for uniform VT especially when the channel resistance is high. But Overlap region causes difficulties in the device area to be miniaturized.In summary, as the S/D overlap length decreases to negative value, the threshold voltage of a-IGZO TFTs increases sharply and these tendency strongly depends on a-IZO film quality, which means the overlap length is very important control parameter of a-IZO TFTs for the uniform threshold voltage especially when the channel resistance is high
9:00 PM - A9.14
Admittance and Impedance Spectroscopy of Mn-, Co-, Ni-, and Cr-doped ZnO.
Youn-Woo Hong 1 , Hyo-Soon Shin 1 , Dong-Hun Yeo 1 , Jong-Hee Kim 1
1 IT Module Team, Division of Fusion & Convergence Tech., Korea Institute of Ceramic Engineering & Technoloy, Seoul Korea (the Republic of)
Show AbstractPolycrystalline ZnO has numerous applications in such diverse areas as UV light-emitters, piezoelectric transducers, varistors, gas sensors, phosphors, and transparent conducting films. It is important to evaluate the defect levels and grain boundary characteristics in ZnO for the numerous applications.In this study, we investigated the effects of Mn, Co, Ni, and Cr dopants on the bulk trap and interface state levels of ZnO using admittance and impedance-modulus spectroscopy (AS, IS and MS). For the identification of the bulk trap levels, it is useful to examine the zero-biased admittance spectroscopy as a function of frequency and temperature. Impedance and electric modulus spectroscopy is a powerful technique to characterize grain boundaries of ceramic materials as well. We prepared ZnO doped with 0.1~3.0 at% MOx (M=Mn, Co, Ni, and Cr) sintered at 1000~1400°C and measured its electrical characteristics. The origin of varistor behavior has been discussed in relation to interfacial and bulk traps.As a results, three kinds of bulk defect trap levels were found below the conduction band edge of ZnO in 0.1 and 0.5 at% Mn-doped ZnO (ZM): 0.14, 0.25, 0.25~0.32 eV. The conductance peaks corresponding to and were inclined to overlap at higher doping levels of Mn in AS. The distribution parameter α of 0.13 was not disturbed by the doping level of Mn or sintering temperature. Thus the interface of Mn-doped ZnO is believed more stable and homogeneous than that of pure ZnO. Doping of Co (≥0.5 at%) to ZnO seemed to form Vo (0.33 eV) as dominant bulk defect. According to IS, the distribution parameter α was decreased continuously with increasing temperature. Thus it was conclude that the interface of Co-doped ZnO (ZCo) reacts rapidly with ambient oxygen and becomes homogeneous. ZnO-NiO (ZN) system did not form definite double Schottky barrier due to the p-type nature of NiO. Low-level doping of Ni (≤1.0 at%) decreased the conductance, which was increased with high-level doping over 1.0 at%. Three kinds of bulk trap level were 0.10~0.14 eV, 0.21~0.29 eV, and 0.31~0.35 eV, and one interface state level 1.03 eV. In Cr-doped ZnO (ZCr), also three kinds of bulk defect levels were found as 0.10~0.14 eV, 0.21~0.29 eV, and 0.31~0.35 eV. The overlapped defect levels (Zni and Vo) were successfully separated by the combination of IS and MS.
9:00 PM - A9.15
Effect of Underlayer in the Growth of Ta2O5 Films Prepared using MOCVD Method for Metal-Insulator-Metal Capacitors in RF-BiCMOS Technology.
Namwoong Paik 1 , Kaman Lau 1 , Ajita Rajan 1 , Margaret McDonald 1 , William America 1 , Daniel Codi 1
1 , NXP Semiconductor, Hopewell Junction, New York, United States
Show AbstractThe properties of Ta2O5 thin films with respect to different underlayer stack have been investigated. At first, a set of samples were produced at various conditions as an underlayer of Ta2O5 film. Then, Ta2O5 films were grown using a MOCVD method with Ta(OC2H5)5 pre-curser at 440 °C. The Process parameters for Ta2O5 films were remained same all through the preparation of the sample set. The results were analyzed using various methods including laser incorporated spectrometer, SEM, stress measurement, X-ray diffraction (XRD), and electrical tests. Different crystalline structures and growth rates were observed with respect to the different underlayer preparation condition, mainly as a function of underlayer deposition temperature. Interestingly, the crystalline form of Ta2O5 films was obtained at some conditions even under the phase transition temperature previously reported (>600°C). Crystalline Ta2O5 (orthorhombic β-Ta2O5 phase) films were obtained on large-grain-size underlayer films. Electrical characteristics such as leakage current, capacitance of Ta2O5 films were compared. Amorphous and crystalline Ta2O5 films exhibit different conduction mechanisms depending on the electric field. Bulk permittivity was found to be (23~27) for amorphous and (32~37) for crystalline Ta2O5 layers, respectively. The results suggest that there is strong dependence in the growth rate as well as in grain structure of Ta2O5 with respect to different underlayer structures.
9:00 PM - A9.16
Multiprobe Atomic Force Nanoelectrical and Chemical Probing of Semiconductor Structures.
Aaron Lewis 1 , Hesaham Taha 2 , Andrey Ignatov 2 , Oleg Zhinoviev 2 , Anatoly Komissar 2 , Sasha Krol 2 , David Lewis 2
1 , The Hebrew University, Jerusalem Israel, 2 , Nanonics Imaging Ltd., Jerusalem Israel
Show AbstractA platform will be described that permits multiprobe atomic force microscopy based nanoelectrical characterization with chemical characterization of semiconductor structures including strained silicon. To achieve such multiple parameter nanocharacterization involves a number of innovations both in instrument and probe design. This presentation will focus on how these advances were achieved and the results obtained with such instrumentation on nanoelectrical and nanochemical characterization of such semiconductor structures. The advances include: 1. Specialized scanners; 2. An ultrasensitive feedback mechanism based on tuning forks with no optical feedback interference that can induce carriers in semiconductor devices; and 3. Unique probes compatible with multiprobe geometries in which the probe tips can be brought into physical contact with one another. Experiments will be described with such systems that will include multiprobe electrical measurements with metal and glass coated coaxial nanowires of platinum. The tip enhanced Raman spectral imaging was accomplished with a single gold nanoparticle at the tip of multiprobe compatible probe. The probe itself is produced without any Raman background. When such a probe is brought into contact with a silicon surface on which a thin film of strained silicon is produced there is an increased in the strained silicon (sSi) peak. This combination of scanning electron microscope integrated multiprobe instrumentation and a broad spectrum of multiprobe compatible nanotool set portends important applications that are significant in the current and future dimensionalities that are and will be achieved in semiconductor processing technology.
9:00 PM - A9.17
Impact of an AlN Interlayer on the Transport Properties of AlGaN/GaN Heterostructure on Silicon at Both Low and High Temperatures.
Mo Ahoujja 1 , Said Elhamri 1 , William Mitchel 2 , Rex Berney 1 , J. Roberts 3 , P. Rajagopal 3 , J. Cook 3 , E. Piner 3 , K. Linthicum 3
1 Physics, University of Dayton, Dayton, Ohio, United States, 2 , AFRL, Materials and Manufacturing Directorate, Wright-Patterson AFB, Ohio, United States, 3 , Nitronex Corporation, Durham, North Carolina, United States
Show AbstractAlGaN/GaN- based high-electron mobility transistors have attracted worldwide research interest due to their potential applications in the microwave power device area. Improving the electron mobility, a key transport parameter, has been one of the main objectives for these structures. It has been shown that a very thin layer of AlN inserted between the GaN and AlGaN layers resulted in a dramatic improvement in the electron mobility at low temperatures. However, since GaN-based devices are developed to operate at high temperatures, we conducted a study to investigate the impact of the AlN interlayer at both high and low temperatures. In this study we report on the transport parameters of AlGaN/GaN structures grown on silicon substrates using Hall effect measurements at temperatures ranging from 10 K to 675 K. The heterostructures studied were all passivated with SiN, some included a 1nm AlN interlayer (AlGaN/AlN/GaN) (Sample A) and others did not (Sample B). Room temperature Hall mobilities and carrier densities were 1900 cm2/Vs and 9.51 x1012cm-2, and 1500 cm2/Vs and 8.2x1012cm-2 for samples A and B, respectively. At temperatures below 300 K, the carrier density for both samples was basically insensitive to the temperature, but the mobility increased for both samples, as expected. The impact of the AlN interlayer became more significant at low temperatures as the mobilities increased to roughly 11000 cm2/Vs for Sample A and only 6000 cm2/Vs for Sample B. However, Hall data taken at temperatures above 300 K clearly indicated that the impact of the AlN interlayer is greatly diminished. The mobility for both samples decreased, as expected, to roughly 407 cm2/Vs and 387 cm2/Vs for samples A and B, respectively. However, the carrier density for both samples remained relatively unchanged as the temperature was increased from 300 to 675 K.
9:00 PM - A9.18
Effect of In as Surfactant on the Growth of AlN/GaN Distributed Bragg Reflectors by Metal Organic Vapor Phase Epitaxy.
Lee Rodak 1 , Dimitris Korakakis 1 2
1 Lane Department of Computer Science and Electrical Engineering, West Virginia University, Morgantown, West Virginia, United States, 2 , National Energy Technology Laboratory, Morgantown, West Virginia, United States
Show Abstract9:00 PM - A9.2
High Performance InAlAs/InAs/InGaAs Pseudomorphic High Electron Mobility Transistors.
Nobuhito Wakimura 1 , Yugo Nakagawa 1 , Hirohisa Taguchi 1 , Tsutom Iida 1 , Yoshifumi Takanadhi 1
1 , Tokyo University of Science, Chiba Japan
Show AbstractInP-based high-electron mobility transistors (HEMTs) have attracted much attention and demonstrated an excellent high-frequency performance because of their superior electronic transport properties. Especially, HEMTs with a pseudomorphically strained InAs channel (InAs-PHEMTs) have higher electron mobility than conventional lattice-matched InGaAs HEMTs. In addition, it is possible to enhance the density of two-dimensional electron gas due to a large conduction band discontinuity.In this paper, we report the intrinsic transit-time when electrons transit the InAs channel under the gate in InAs-PHEMTs. Moreover, we have calculated InAs-PHEMT’s energy state and potential profile by self-consistently solving the Schrödinger and Poisson equations. In solving the Schrödinger equation, the energy-dependent effective mass was employed to take account of the strong non-parabolicity of InAs conduction-band based on the kp perturbation theory by E. O. Kane. A comparison between theory and experimental results was made in detail. Epitaxial structures of InAs-PHEMTs were grown on Fe-doped semi-insulating InP substrate using MOCVD method. They consist of an undoped InAlAs buffer layer (20 nm), an undoped InGaAs/InAs channel layer and an InAlAs barrier layer, where the thickness of InAs layer was 3 nm. The electrode metals for the gate, the source, and the drain were non-alloyed Ti/Pt/Au. The gate length (LG) was 0.7μm. The intrinsic cut-off frequency (fT, int.) can be obtained as follows. First, we measure the following parameters: 1) the Y parameters of the device under test (Ydut), 2) the Ys under the condition that device is open (Yopen), and 3) the Ys under the condition that device is short (Yshort). Next, the intrinsic transit-time (τint) is estimated by transforming Y parameters into Z parameters according to the relation of Z[Ydut –Yopen] – Z[Yshort – Yopen]. Finally, fT, int. is given by 1/2πτint. A network analyzer (HP8510B) was used for measuring the frequency dependence of the S-parameters. For the source-to-drain voltage of 1.4 V and the gate-to- source voltage of 0.3 V, InAs-PHEMT’s showed an excellent intrinsic cut-off frequency (fT, int.) as high as 90 GHz regardless of their longer LG, where fT, int. was obtained by extrapolating the current gain, H212, with a -20 dB/decade slope. To the first approximation, fT, int. is known to be inversely proportion to LG. Therefore, fT, int. of InAs-PHEMT’s may reach 630 GHz if their LG is reduced to 0.1μm. Most of electrons are confined to the InAs channel layer with a higher mobility due to the non-parabolicity of InAs conduction band. This is the reason why InAs-PHEMTs have excellent frequency performance. On the contrary, electrons were found to spread over the InGaAs channel layer when the non-parabolicity is not taken into account as usually done.
9:00 PM - A9.21
Theoretical Investigation of Adatom Kinetics on III-Nitride Surfaces.
Vibhu Jindal 1 , Fatemeh Shahedipour-Sandvik 1
1 College of Nanoscale Science and Engineering, University at Albany, State University of New York, Albany, New York, United States
Show Abstract9:00 PM - A9.22
Resistive Switching Properties of N-implanted TiO2 Thin Films for Nonvolatile Memory Application.
Young Ho Do 1 , June Sik Kwak 1 , Jin Pyo Hong 1
1 physics, Hanyang University, seoul Korea (the Republic of)
Show Abstract9:00 PM - A9.23
Nanoporous Arrays on Blue InGaN/GaN Light Emitting Diodes using Anodic Aluminum Oxide Masks.
Ha Doan 1 , Duy Nguyen 1 , Sangin Kim 1 , Hanjo Lim 1 , Fabian Rotermund 1 , Sunil Mo 1 , Jaejin Lee 1
1 , Ajou University, Suwon Korea (the Republic of)
Show Abstract9:00 PM - A9.24
Detailed Investigation of GaN Metal-insulator-Semiconductor Structures by Capacitance-voltage and Deep Level Transient Spectroscopy Methods.
Junjiroh Kikawa 1 , Yuki Horiuchi 1 , Eiji Shibata 1 , Masamitsu Kaneko 1 , Hirotaka Otake 2 , Tatsuya Fujishima 2 , Kentaro Chikamatsu 2 , Atsushi Yamaguchi 2 , Yasushi Nanishi 1
1 , Ritsumeikan Univ., Kusatsu, Shiga, Japan, 2 , ROHM CO.,LTD, Kyoto, Kyoto, Japan
Show AbstractInterface states produced at the interface between an insulator and GaN semiconductor determine the performance of GaN metal-insulator-semiconductor (MIS) field effect transistors. Therefore, it is important to know details of interface states characteristics to improve device performances. For above purpose, we have fabricated GaN MIS capacitors, then carried out capacitance-voltage (CV) and deep level transient spectroscopy (DLTS) measurements, and analyzed the obtained results in detail. Wafers used in this study were n-type GaN grown on sapphire substrates by metal organic chemical vapor deposition. A film of SiN was deposited as an insulating layer using electron-cyclotron-resonance plasma-assisted deposition at room temperature, then samples were annealed at 400, 600 or 800°C in N2 atmosphere for 10 min. CV measurements were performed for all the samples at various frequencies and bias sweep rates in the dark condition. CV curves of all the samples exhibited ledges in the curves. Here, ledge indicates a region of which capacitance is independent of applied bias. Although each sample was annealed at each different temperature, it was observed at the same surface potential for all the samples. This result indicates that the Fermi level of the GaN/SiN interface is pinned by a particular trap. In addition, the shape of the CV curve depended on both frequency and bias sweep rate, and it was not observed in the results obtained by a quasi-static capacitance voltage measurement. This can be explained that the shape of ledge is determined by the quasi-equilibrium between a filling rate of traps and a bias sweep rate or test frequency. In the positive bias region of the ledge, a hysteresis window of the CV curve had some dependence on frequency but little dependence on bias sweep rate. On the other hand, in the negative bias region of the ledge, it had little dependence on frequency but obvious dependence on bias sweep rate. These dependences indicate two different traps and related to the ledge formation. The trap energy level related to the sweep rate dependence is estimated to be 0.34 eV by the temperature dependence of the width of hysteresis window. Deep level transient spectroscopy measurements were carried out to characterize the trap levels observed in the CV curves. Trap levels with activation energies of 0.32 and 0.78 eV were observed [1]. The former is almost equal to 0.34 eV obtained from the temperature dependence of the width of hysteresis window. The latter is similar to the interface trap reported by Nakano et al., which is considered to be originated from the complexes of Si and surface defect [2].[1] E. Shibata et al., Ext. Abstracts 2008 IMFEDK, Osaka, pp.69-70. (2008).[2] Y. Nakano and T. Jimbo, Appl. Phys. Lett. 80, 4756 (2002).
9:00 PM - A9.25
Cleaning of GaN(0001): Surface Chemistry and Morphology.
Thomas Schmidt 1 , Christian Schulz 1 , David Krueger 1 , Jan Flege 1 , Nina Berner 1 , Christian Tessarek 1 , Detlef Hommel 1 , Jens Falta 1
1 Institute of Solid State Physics, University of Bremen, Bremen Germany
Show Abstract9:00 PM - A9.26
Characterization of Electronic Defects in Hafnium Oxide Thin Films via Atomic Force Microscopy.
Matthew Brukman 1 , Maxim Nikiforov 2 , Dawn Bonnell 1
1 Materials Science, University of Pennsylvania, Philadelphia, Pennsylvania, United States, 2 , Oak Ridge National Lab, Oak Ridge, Tennessee, United States
Show AbstractNanometer-sized defects in thin hafnium oxide films are detected by AFM-facilitated leakage current measurements. Differences in the electrical properties of individual defects are distinguished by both spatially-averaged and point spectroscopy. The effects of two pressure-induced mechanisms that localize the tip-sample interaction and increase spatial resolution -- narrowing of the substrate bandgap and/or substrate phase change -- are discussed. A behavior diagram is presented that relates the experimental conditions under which these mechanisms can operate.
9:00 PM - A9.27
Transparent Indium Oxide Thin-Film Transistor Fabricated by RF Magnetron Sputtering at Room Temperature.
Joo Hyon Noh 1 , Hong Koo Baik 2 , Dong-Joo Kim 1
1 Material Engineering, Auburn University, Auburn, Alabama, United States, 2 Material Science and Engineering, Yonsei University, Seoul Korea (the Republic of)
Show AbstractTransparent thin-film transistors (TTFTs) have recently attracted a great deal of attention because their role as key devices in realizing the development of transparent circuits, which are expected to serve as the basis for new optoelectronic devices. . In2O3 has a bixbyte structure in which a linear chain of edge-sharing octahedra is running isotropically, that is preferred for high mobility. We have fabricated In2O3 transparent thin-film transistor (TTFT) by rf magnetron sputtering at room temperature. The fabricated In2O3 TTFT operates in an enhanced-mode with a field-effect mobility of 4.3 cm2 V-1 s-1, a threshold voltage of 0.3 V, an on-off current ratio of 4.0 × 107, and a subthreshold gate voltage swing of 0.26 V decade−1. Optical characterization of these devices indicates > 73 % transparency in the visible portion of the electromagnetic spectrum as viewed through the device. This result suggests that the In2O3 combined with sputtering will be a prominent candidate for commercial production of the TTFT toward future transparent electronics.
9:00 PM - A9.28
Characterizations of Boron Carbon Nitride and Boron Carbide Films Synthesized by PECVD.
Qingguo Wu 1 , Mandyam Sriram 1 , Jim Sims 1 , Haiying Fu 1 , Sesha Varadarajan 1 , Tim Archer 1 , Nathan Trujillo 2 , Karen Gleason 2
1 PECVD Unit, Novellus Systems, Inc., Tualatin, Oregon, United States, 2 Department of Chemical Engineering, Massachusetts Institute of Technology, Boston, Massachusetts, United States
Show AbstractTo improve drive current in complementary metal oxide semiconductor (CMOS) devices, highly stressed films are needed. Many efforts have been made in recent years to develop high compressive and high tensile stressed films, including the investigation of precursors and deposition methods such as plasma enhanced chemical vapor deposition (PECVD) using SiR4 (R= H or CH3) [1-2] and high density plasma (HDP) using SiR4 (R=H and/or CH3 and/or Cl) etc.[3-4] Among these methods, however, none of them have achieved the desired stress of < -3.5 GPa at the relatively low temperature of ≤ 400 °C. Recently there has been great interest in depositing boron carbon nitride (BCN) and boron carbide (BC) films because they exhibit many attractive properties for thin film applications. They are expected to have excellent mechanical properties similar to diamond, cubic boron-nitride (c-BN), and carbon-nitride (β-C3N4) [1], and they have high compressive stress under certain conditions.[5-6] Lousa et al presented high stressed boron carbide thin films deposited by tuned-substrate RF magnetron sputtering and using pure solid B4C as precursor. However, repeatable film thickness and uniformity may be difficult to obtain with this method due to the use of a solid precursor and the fact that the active solid surface area changes during deposition. Herein we reported boron carbon nitride (BCN) and boron carbide (BC) film stability and the formation of BCN and BC films synthesized by plasma enhanced chemical vapor deposition (PECVD) using boron containing compound and hydrocarbon as precursor materials. Fourier transform infrared spectroscopy (FTIR), Raman spectroscopy, Nano-Indentor, Flexus stress instrument and x-ray photoelectron spectroscopy were used to study the deposited films. The BC films are much more stable than BCN films under high humidity (100%) environment. Both BCN and BC films are very stable under atmosphere. High compressive stress of -4.2 GPa film with excellent non-uniformity and repeatability was achieved by conventional PECVD at substrate temperature < 400°C, which show promising applications in high performance ultra large-scale integrated circuit (ULSI) devices. REFERENCES1. A. J. Silvestre, M. J. Santos and O. Conde, Key Eng. Mater. 56, 230-232 (2002).2. P. Jamroz and W. Zyrnicki, Diamond Relat. Mater. 14, 1498-1507 (2005).3. I. V. Afanasyev-Charkin and M. Nastasi, J. Appl. Phys. 96, 7681-7685 (2004).4. R. C. Sharma and M. Koshi, Spectrachimica Acta Part A 65, 787-791 (2006).5. E. Pascual, E. Martínez, J. Esteve and A. Lousa, Diamond Relat. Mater. 8, 402-405 (1999).6. A. Lousa, J. Esteve, S. Muhl and E. Martínez, Diamond Relat. Mater. 9, 502-505 (2000).
9:00 PM - A9.29
Determination of the InGaN Composition from Strain Measurements.
Francisco Morales 1 , J. Lozano 1 , R. Garcia 1 , V. Lebedev 2 3 , S. Hauguth-Frank 2 , V. Cimalla 2 3 , O. Ambacher 2 3 , D. Gonzalez 1
1 Materials Science and Engineering, University of Cádiz, Puerto Real, Cádiz, Spain, 2 Institute of Micro- and Nanotechnologies, Technical University Ilmenau, Ilmenau Germany, 3 Fraunhofer Institute for Applied Solid State Physics, Fraunhofer Institute Freiburg, Freiburg Germany
Show Abstract9:00 PM - A9.3
Optimizing MIM Device Electrical Properties: Impact of Bottom Electrodes and High K Materials.
Marceline Bonvalot 1 , Christophe Vallee 1 , Patrice Gonon 1 , Hichem Abed 1 , Corentin Jorel 1 , Olivier Joubert 1
1 LTM, CNRS, Grenoble France
Show Abstract9:00 PM - A9.30
Low Resistance Ohmic Contact Formation and Mechanism of Current Transport Through p-GaN and p-AlGaN.
Indra Chary 1 , Boris Borisov 1 , Anilkumar Chandolu 1 , Vladimir Kuryatkov 1 , Sergey Nikishin 1 , Mark Holtz 1
1 Nano Tech Center, Texas Tech University, Lubbock, Texas, United States
Show AbstractLow resistance ohmic contacts to GaN are essential to substantially improve the efficiency and reliability of devices based on GaN. Various contact metallization schemes have been successfully demonstrated for n-GaN with contact resistance. Similar success has eluded good contacts to p-GaN. This is mainly due to high acceptor activation energy of Mg, large work function of p-GaN and surface contaminations which increase the metal-semiconductor barrier height. We report the influence of surface treatment and annealing conditions of the metal bilayer stack on the formation of low resistance Au/Ni ohmic contacts to p-GaN. We also report the influence of surface treatment on the mechanism of current transport through the Au/Ni/p-GaN interface. We will also report Au/Ni ohmic contacts to AlGaN:Mg with Mg incorporation varying from 1.2 x 1019 cm-3 to 1.2 x 1020 cm-3. The role of self compensation on the specific contact resistivity will also be discussed.The Mg doped p-GaN layers used in this work were grown by gas source molecular beam epitaxy with ammonia on sapphire substrates. Room temperature Hall measurements showed the average film resistivity ranging from 2.5 to 1.2 Ωcm and hole concentrations from 1x1016 cm-3 to 1x1018 cm-3, respectively. A thin layer of native oxide formed on the GaN surface contributes to the increase in barrier height and contact resistance. Surface cleaning is critical as it helps in the removal this oxide and other surface contaminants such as carbon and oxygen. The samples were treated with four different treatments based on KOH, HCl, HF, and HF+HNO3 with different dilutions of each. The lowest specific contact resistance was consistently obtained for samples treated with HCl:H2O = 3:1 solution and annealed at 500oC. XRD studies performed on as deposited, and annealed samples (400oC–600oC), showed inter-diffusion between Au/Ni bilayers, formation of NiO and nickel gallide (Ni3Ga4) at the metal-semiconductor interface. These factors were found to be strongly dependent on annealing temperature. Based on these studies we propose a model explaining the mechanism of low resistance ohmic contacts to p-GaN. Current-Voltage-Temperature (I-V-T) measurements were carried out to determine the current transport mechanism. Dilute HCl treated samples showed a dominant thermionic emission while field emission was dominant for samples treated with concentrated HCl. The sample with p=1x1018 cm-3 yielded the lowest specific contact resistivity of 3.9 x 10-5 Ωcm2 and 2.2 x 10-7 Ωcm2 at room temperature and at 150oC respectively.This work is supported by NSF (ECS–0304224 and ECS-0609416), THECB-ARP-003644-0014-2006, and the J. F Maddox Foundation.
9:00 PM - A9.31
Microstructural Analysis of Conducting Path in TiO2 Film.
Deok-Hwang Kwon 1 , Kyung Min Kim 1 , Miyoung Kim 1
1 School of Material Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Show Abstract9:00 PM - A9.32
Nucleation and Stochiometry Dependence of Rutile-TiO2 Thin Films Grown by Plasma-assisted Molecular Beam Epitaxy.
Costel Constantin 1 , Kai Sun 2 , Randall Fenstra 3
1 Physics, Seton Hall University, South Orange, New Jersey, United States, 2 Electron Microbeam Analysis Laboratory(North Campus), University of Michigan, Ann Arbor, Michigan, United States, 3 Physics, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States
Show Abstract9:00 PM - A9.33
Performance Characteristics of Inorganic Materials under Plasma Process Environments and Analysis of Etching Mechanisms.
Brock Alexander 1 , John Foggiato 1 , Ramas Raman 2 , Rick Cooke 2 , Nilesh Gunda 2 , Timothy Edwards 1
1 , Greene, Tweed & Co., Kulpsville, Pennsylvania, United States, 2 Entegris Specialty Coatings, Entegris, Inc, Burlington, Massachusetts, United States
Show Abstract9:00 PM - A9.34
The Effect of BCl3 Pretreatment on Cl2/Ar Plasma Etching of Epitaxial AlN.
Xiaoyan Xu 1
1 Electrical Engineering, Texas Tech University, Lubbock, Texas, United States
Show Abstract9:00 PM - A9.35
High Quality ZnO Thin Films for High Frequency Surface Acoustic Wave Generation on III-V Semiconductors.
Qijie Wang 1 , Christian Pflugl 1 , William F. Andress 1 , Donhee Ham 1 , Federico Capasso 1 , Masamichi Yamanishi 2
1 , Harvard University, Cambridge, Massachusetts, United States, 2 , Hamamatsu Photonics K.K., Shizuoka Japan
Show Abstract9:00 PM - A9.4
Change in Tunneling Spectrum of a Co/AlOx/Co Junction under Constant Voltage Stress.
Kouhei Horikiri 1 , Kazuo Shiiki 1
1 Department of Applied Physics and Physico-Informatics, Keio university, Yokohama Japan
Show Abstract To investigate the aging effect for a tunneling junction due to constant voltage stress, tunneling resistance and inelastic electron tunneling spectra were measured. Tunneling junctions of Co (10 nm)/AlOx/Co (10 nm) were fabricated on a glass substrate by ion-beam sputtering. After a 2.5-nm-thick Al layer was deposited on the bottom Co electrode, an insulator layer of AlOx was formed by thermal oxidation in pure O2 at 200 °C. The tunneling resistance was measured by the four-probe method with constant voltage stress. Voltage polarity was considered positive for tunneling current flowing from the top electrode to the bottom one. At a low voltage of about 0.5 V, the tunneling resistance of junctions increased gradually over time. On the other hand, at a high voltage of about 0.9 V, the tunneling resistance of junctions decreased gradually. This change in tunneling resistance was observed independent of voltage polarity. The tunneling spectra of as-made junctions showed a peak at about ±0.03 V. This peak is thought to be an Al phonon peak, as reported in previous reports [1-2]. No other peaks were observed up to 0.3 V. The peak at +0.03 V was larger than that at −0.03 V. This asymmetric peak means that a larger amount of metallic Al exists at AlOx/bottom electrode interface than at top electrode/AlOx interface. When ±0.5 V was applied for 12 h, the tunneling resistance increased by a few ohms. When the applied voltage was positive, the tunneling spectrum did not change, whereas when it was negative, the tunneling spectrum changed. The asymmetric peak became symmetric, implying that the AlOx barrier had become homogeneous. After the peak became symmetric, it did not become asymmetric again after application of a constant voltage of +0.5 V. By XPS analysis, the junction exhibiting an asymmetric peak contained metallic Al at the AlOx/bottom electrode interface, and the junction exhibiting a symmetric peak contained a homogeneous barrier layer. Increase in the tunneling resistance indicates that the amount of metallic Al in the AlOx barrier layer decreased. Transformation from an asymmetric peak to a symmetric peak indicates that the metallic Al in the AlOx/bottom electrode interface was oxidized, which lead to the AlOx layer becoming homogeneous. If voltage stress had not been applied, this change would not have occurred for 12 h. Oxidation of metallic Al in the AlOx layer is accelerated by voltage stress.[1] W. M. Bowser and W. H. Weinberg, Surface Sci. 64, 377, 1977.[2] M. Higo and S. Kamata, J. Phys. Chem. 94, 8709, 1990.
9:00 PM - A9.5
Characteristics of Inter Poly Dielectric (IPD) Prepared by Plasma Oxidation Treatment of LP-CVD SiO2 Film.
Jung-hwan Kim 1 , Yong-Seok Kim 1 , Byong-Hyun Jang 1 , Hyun Namkoong 1 , Seung-Ju Park 1 , Woo-Sung Lee 1 , Hun-Hyoung Lim 1 , Han-Jin Lim 1 , Seok-Woo Nam 1 , Chang-Jin Kang 1 , Tae-Hyuk Ahn 1
1 Semiconductor Business, Samsung Electronics Co., Hwasung, Gyeonggi, Korea (the Republic of)
Show AbstractUntil recently, the oxide/nitride/oxide (ONO) structure has been conventionally used as IPD material of NAND flash memory. However, as the design rule of the device shrinks below 50nm, the reduction of the operation voltage is required due to the interference phenomenon. So, it is necessary that the equivalent oxide thickness (EOT) of ONO scale down without the degradation of charge retention capability. In general, the dielectric reliability of LP-CVD SiO2 for ONO IPD is inferior to that of thermal oxide due to the generation of the unstable bonding and impurities in film during deposition. To improve the quality of LP-CVD SiO2, various post-treatments have been evaluated. e.g., N2, NO, N2O annealing. In this paper, plasma oxidation was introduced as post-treatment. The electrical (I-V, BV) and physical (Density, Roughness, Wet etch rate, Impurity) properties of LP-CVD SiO2 were respectively examined according to with and without plasma oxidation treatment. The thickness change of LP-CVD SiO2 was observed in order to find out the appropriate treatment time to be able to modify SiO2 film without the EOT addition. The LP-CVD SiO2 prepared by plasma oxidation was used for the ONO IPD of 50nm NAND flash device and also compared with the conventional LP-CVD SiO2 in the aspect of the device reliability. From the evaluation results, the possibility of ONO IPD scaling down will be discussed.
9:00 PM - A9.6
Optical Characteristics of Transition Metal Doped ZnO BulkSingle Crystals.
Yongmin Kim 1 , Yong Ho Shin 1 , Young Hwan Park 1 , Hee Soo Kim 1 , Seung Jung Noh 1 , Ki Seok Ahn 2
1 Applied physics, Dankook University, Yongin Korea (the Republic of), 2 Thin Film Materials Laboratory, Korea Research Institute of Chemical Technology, Daejeon Korea (the Republic of)
Show AbstractTransition metal doped wide-gap semiconductors such as GaN or ZnO are of prominent candidate for future spintronics applications. In this study, we report optical properties of ZnO:Mn, ZnO:Fe bulk crystals by photoluminescence (PL) measurements and Raman scattering spectra. For PL emission properties at high temperature above 60 K, free-carrier like transition dominates while at low temperature below 60K impurity related bound state transitions emerge for both Mn and Fe doped samples. Unlike an epilayer thin film ZnO, these bulk crystals show exceptionally small activation energies (10 ~ 15 meV) of bound excitons. For Raman measurements, conventionally well known A1 and E2 related transitions appear. However, peak intensities are quite different between Mn and Fe doped samples. These are due possibly to the reason that the sizes of ionic radii between two dopants substitute Zn atoms in a different way. We will discuss detailed temperature-dependence of photoluminescence transitions and room temperature Raman spectra of different transition metal doped samples along with thin film epilayer fabricated by CVD method.
9:00 PM - A9.7
Influence of Titanium Nitride Cap Layer Thickness on the Oxygen Sensitivity of Cobalt Films During Silicide Processing.
Nathan Hoffman 1 , Roger Ketcheson 1 , Daniel Stambaugh 1 , Laura Safran 1 , Thomas Fryxell 1 , Richard Campos 1 , Jerry Mase 1 , Daniel Codi 1
1 , NXP Semiconductors, Hopewell Junction, New York, United States
Show AbstractTitanium and cobalt silicides have long been used as gate electrode materials for very large-scale integrations (VLSI) circuits. As scaling has pushed the industry to quarter micron technologies and below, cobalt has become the material of choice for forming silicides, since it can maintain its low resistivity on much narrower line widths. Oxidation of the cobalt film is a concern during silicide processing, as the cobalt oxide will not be removed during the cobalt etch step. To protect against the oxidation of the cobalt layer during the silicidation process, the reaction is conducted underneath a titanium nitride capping layer. Variations in the TiN capping layer thickness were investigated to determine the affect on oxygen sensitivity of the cobalt silicide process. A strong correlation was found to the thickness of the TiN capping layer, to the oxygen concentration required to oxidize cobalt during the silicidation process.
9:00 PM - A9.8
Investigation of Amorphous InGaZnO Based TFT Interface Properties with Synchrotron Radiation Analysis.
Minho Joo 1 , Jongkwon Choi 1 , Kyuho Park 1 , Kyuwook Ihm 2 , Ki-Jeong Kim 2 , Tai-Hee Kang 2
1 Devices & Materials Laboratory, LG Electronics Advanced Research Institute, Seoul Korea (the Republic of), 2 Pohang Accelerator Laboratory, POSTECH, Pohang Korea (the Republic of)
Show AbstractFlexible displays are of great interest for future applications, such as wearable displays, cell phone displays, and electronic papers. Recently ZnO based TFTs (Thin Film Transistor) have attracted much attention from researchers and engineers because of their novel potential for the realization of flexible displays. Hosono et. al. reported the high performance TFTs with amorphous In-Ga-Zn oxide (a-IGZO) channel layers deposited by physical vapor deposition [1-2]. These TFTs showed high mobility (>10 cm2/V s) for a-IGZO TFTs, which is comparable to those of the polycrystalline ZnO TFTs, even in the amorphous phase. Nevertheless, most previous works have focused on the improvement of the TFT characteristics [1-4]. Low temperature TFT processes were easily degraded by process damages or current-driven damages. Therefore, it is important to understand how process damages affect the overall device characteristics of a-IGZO TFTs in order to fabricate TFT arrays showing high performance and high reliability. The top gate TFT samples for photoemission characteristics between gate dielectric layer and active channel layer were prepared with IGZO (30 nm_ sputter deposition) / SiNx (5 nm_ plasma enhanced chemical vapor deposition) on Si substrate. In the case of the bottom gate TFTs, layer structure was SiNx (30 nm) / IGZO (5 nm) on Si substrate. Interface analysis for the samples was performed using synchrotron radiation source. Near edge x-ray absorption fine structure (NEXAFS) shows the characteristic vibrational structures indicating the presence of N2 molecules between gate dielectric layer and active channel layer. The intensity of π* resonance peak of N K-edge was more increasing in the bottom gate structures. In the case of oxygen hybridization between gate dielectric layer and active channel layer, the π* resonance peaks of O K-edge were also more increasing in the bottom gate structures. It is noted that sputtering process after SiNx deposition enhanced the interfacial damage showing the increase of impurity species. After anneal process at 300 oC for 10 min, interface damage layer was reconstructed showing decreasing of π* resonance peaks of N K-edge in the bottom gate structures. The impurity species of the physical damage enhanced by sputtering process were the molecular N2 between gate dielectric layer and active channel layer.We investigated the a-IGZO based TFT interface properties using synchrotron radiation analysis. TFT device structures (bottom and top gate) were specially designed to study chemical species by interface reaction because it is impossible to investigate the interface non-destructively with thick layer by photo emission spectroscopy. It was found that the physical process damage between gate dielectric and active channel was the origin of the device degradation evolving molecular state impurities.
9:00 PM - A9.9
On the use of Shubnikov-de Haas Effect for the Determination of the Effective Mass in GaN.
S. Elhamri 1 , E. Timko 1 , R. Berney 1 , M. Ahoujja 1 , W. Mitchel 2
1 Physics, University of Dayton, Dayton, Ohio, United States, 2 Materials and Manufacturing Directorate, AFRL, Wright-Patterson AFB, Ohio, United States
Show AbstractThe Shubnikov-de Haas (SdH) effect, a quantum mechanical oscillation in the longitudinal resistance as a function of the magnetic field, is routinely used to characterize two-dimensional electron systems. The carrier density and the corresponding effective mass are some of the key transport parameters that can be determined from these oscillations. We report here the results of a study of the magnetic field dependence of the electron effective mass in AlGaN/GaN heterostructures using two different methods of analyzing the SdH oscillations. In the first approach, the sinh(χ) term in the standard equation for the amplitude of the oscillations is approximated by exp(χ)/2. In the second approach, the data are fit to the full equation, including the sinh(χ) term. A field dependence in the effective mass is observed in several samples when the first approach is used to analyze the date. However, when the sinh(χ) term is included without approximation no field dependence was observed in the effective mass. These results can explain a recently reported observation of a magnetic field dependent effective mass in AlGaN/GaN heterostructures. In addition, these results might also explain the scatter in the reported GaN effective mass values extracted from the SdH oscillations.
Symposium Organizers
Michael Mastro U.S. Naval Research Laboratory
Jeffrey LaRoche Raytheon RF Components
Fan Ren University of Florida
Jen-Inn Chyi National Central University
Jihyun Kim Korea University
A10: Dielectrics
Session Chairs
Francisco Morales
Francois Pagette
Wednesday AM, December 03, 2008
Room 202 (Hynes)
9:15 AM - A10.1
Performance of Catalyst-based Solid-state Sensors for Wide Temperature Range Hydrogen Leak Detection.
Claudiu Muntele 1 , Sandra Sadate 1 , Malek Abunaemeh 1 , Cydale Smith 1 , Daniel McElhaney 1 , Jonathan Gardner 2 , Abdalla Elsamadicy 2 , Daryush Ila 1
1 , Alabama A&M University, Normal, Alabama, United States, 2 , University of Alabama in Huntsville, Huntsville, Alabama, United States
Show AbstractSilicon carbide based non-linear electronics devices (MOSFET, metal-semiconductor, or p-n junctions) are promising candidates for hydrogen detection schemes if used in conjunction with a platinum group catalyst. For the past decade, the emphasis was mostly on high temperature applications in the automotive (for hydrogen-fueled engines) and in the aerospace industry (for jet engines), but now the focus is broadening to include auxiliary systems such as storage tanks, fuel lines, fuel production systems, all operating in a wide range of temperatures, all the way down to cryogenic levels. Hydrazine is a particular chemical of interests, as is widely used as a fuel in rocket propulsion systems, as well as fuel cells, pesticides, dyes etc. It is also a neurotoxin, causing damage to most organs in the human body. Therefore sensors able to detect hydrazine leaks at sub-ppm level at RT (anhydrous hydrazine melts at 2 °C and evaporates at 113.5 °C) and in a wide humidity range (hydrazine is fully miscible in water) are highly desirable. Sensitive analytical methods have been developed for the determination of hydrazine in air, water, food, drugs, and cigarette smoke. However, all these methods involve complicated analytical instrumentation generally available only in a specialized laboratory environment.In this paper we are evaluating, on a comparative basis, solutions to challenges associated with using catalysts as active agents in capacitive, non-linear (p-n structures), and linear (resistors) hydrazine and hydrogen detection schemes in a temperature range from 77 K (liquid nitrogen) to 400 K. We used e-beam deposition and low energy ion implantation for preparing our samples, and current vs. voltage electrical measurements to monitor the devices’ response to hydrazine and hydrogen. Raman spectroscopy was used for investigating the surface chemistry of the devices exposed to hydrazine at various temperatures.
9:30 AM - **A10.2
Plasma Nitridation of the SiO2/4H-SiC Interface and (000-1) MOSFET Characteristics.
John Williams 1 , X. Zhu 1 , Z. Chen 1 , A. Ahyi 1 , T. Isaacs-Smith 1 , J. Rozen 2 , S. Dhar 3 , L. Feldman 4
1 , Auburn University, Auburn University, Alabama, United States, 2 , Vanderbilt University, Nashville, Tennessee, United States, 3 , Cree, Inc., Durham, North Carolina, United States, 4 , Rutgers University, Piscataway, New Jersey, United States
Show Abstract MOSFETs for 4H-SiC are commonly fabricated on the Si-face using dry or wet thermal oxidation and a post-oxidation anneal (POA) in NO, hydrogen or both (using sequential anneals). NO effectively reduces the trap density near the 4H conduction band edge, while hydrogen seems more effective from 0.6eV below the band edge to mid-gap. Dit increases dramatically near the 4H conduction band edge, and an improvement in mobility of ~ x10 has been observed for the Si-face using NO. Herein we report the results of studies to determine whether alternatives to standard Si-face MOSFET fabrication procedures result in lower trap density and higher effective mobility. The alternatives are passivation using a nitrogen plasma and MOSFET fabrication on (000-1) 4H-SiC. During a nitric oxide POA, oxide growth continues while nitrogen is simultaneously introduced at the SiO2/SiC interface. Additional oxide growth generates interface traps, and possibly less than optimal passivation of Dit by nitrogen. Following plasma nitridation of a dry oxide on the Si-face, Dit near the band edge is around 2.5e12/cm2/eV compared to 1e12/cm2/eV for NO. Near mid-gap however, plasma nitridation is somewhat better. The plasma nitridation mobility of 45cm2/V-s is slightly higher than the value of 35-40cm2/V-s normally observed using NO, and similar to the mobility measured using NO followed by a 500C anneal in atomic hydrogen. However the threshold voltage for the plasma process is approximately 8V compared to 2-3V for an NO oxide of similar thickness (~ 40nm). Oxide breakdown following plasma nitridation is not as good – only 6-7MV/cm even after improvement obtained using a post-plasma, 30min, 1160C anneal in N2 followed by a cool down in N2. The lower breakdown field and higher threshold voltage may result from damage and negative charge buildup in the oxide. We have not optimized the post-plasma anneal/cool down process with respect to time and temperature, and we do not know whether the breakdown field will remain significantly lower compared to NO. Trap densities, effective mobility and I-V characteristics have also been measured for the 4H-(000-1) face. NO and NO + H2 do not reduce Dit to (0001) + NO levels. However, mobilities are similar for both faces (~ 40cm2/V-s). A threshold voltage of 6V was measured for a 75nm oxide compared to 2-3V for a 40nm oxide on the Si-face. I-V measurements indicate that oxides on the carbon face have a breakdown field of around 6MV/cm, or approximately 2MV/cm lower compared to (0001) NO oxides. These results for plasma nitridation and for (000-1) MOSFETs indicate that higher effective mobility is not always directly correlated with lower interface trap density and that other scattering mechanisms such as surface roughness may also be important.
10:00 AM - A10.3
Optimization of Samarium Oxide Deposition on Gallium Arsenide.
Anthony Stewart 1 , Brent Gila 1 , Andy Gerger 1 , Cammy Abernathy 1 , Stephen Pearton 1
1 Materials Science & Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractSamarium oxide (Sm2O3) has been proposed as a candidate dielectric for development of gallium arsenide (GaAs) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology. Growth of thin (20nm-50nm) samarium oxide layers on GaAs substrates via plasma-assisted molecular beam epitaxy (MBE) has been performed using a range of growth temperatures and samarium cell temperatures. X-ray photoelectron spectroscopy (XPS) of the deposited films showed evidence of residual Sm metal in the films which decreased with decreasing Sm cell temperature, but was relatively independent of substrate temperature. Stoichiometry of the oxide was found to be independent of substrate temperature, but increased in oxygen to metal ratio as the Sm cell temperature was decreased. Decreasing the Sm cell temperature also suppressed the formation of the monoclinic phase and promoted the growth of the cubic phase. Films grown at higher (500C) temperature showed the presence of a crystalline interface, but relatively high surface roughness and the presence of multiple crystalline phases. Current-voltage analysis of one hundred micron diameter MOS diodes showed breakdown fields at 1 mA/cm2 of up to 3.6 MV/cm. Breakdown field was found to decrease with increasing Sm free metal content in the films. Post-growth annealing under an oxygen plasma in the MBE chamber of films grown at higher temperatures resulted in an increase in the oxygen to metal ratio but effected no change in the crystalline phase distribution. Effect of stoichiometry, phase distribution and microstructure on the interface state density and capacitance-voltage behavior of MOS diodes will also be presented.
10:15 AM - A10.4
High Dielectric Constant Epitaxial Oxide Integration for GaN-based MOS Devices.
Jesse Jur 1 , V. Wheeler 1 , D. Lichtenwalner 1 , M. Veety 2 , D. Barlage 2 , Mark Johnson 1
1 Materials Science and Eng., NC State University, Raleigh, North Carolina, United States, 2 Electrical and Computer Eng,, NC State University, Raleigh, North Carolina, United States
Show Abstract10:30 AM - A10.5
Interface Study in a "High-k / Metal" Gate Stack : Titanium Nitride on Hafnium Oxide.
Clement Gaumer 1 , Eugenie Martinez 2 , Sandrine Lhostis 1 , Dominique Lafond 2 , Frederic Fillot 2 , Virginie Loup 2 , Francois Pierre 2 , Jean-Paul Barnes 2 , Mickael Gros-Jean 1 , Pierre Perreau 2
1 , STMicroelectronics, Crolles France, 2 , CEA-LETI, MINATEC, Grenoble France
Show AbstractHistorical “poly-silicon/silicon oxide” gate stack technology reaches its physical limits as 1nm of Equivalent Oxide Thickness (EOT) is targeted. Thus, new materials have to be implemented into the gate stack in order to achieve the down scaling of MOSFETs below the 65nm technological node. High permittivity materials (high-k) such as hafnium-based oxides lead to a reduction of the gate leakage current as low EOT (about 1nm) can be obtained with a physically thicker dielectric layer. The poly-silicon used as the gate has to be replaced by an intrinsic metallic material, since depletion does not occur in metals. Nitrided metals are good candidates to address this topic [1]. Electrical performances of MOSFETs are impacted by both interface, considering the smaller and smaller targeted thicknesses, and volume effects. As an example, carrier mobility in SOI FinFET devices has been shown to be metal gate thickness dependant [2]. This is why physical and chemical properties of the layers and their interfaces in the gate stack have to be identified and understood.In this work we focuse on the impact of the gate stack crystalline structure on its chemical properties and more particularly the interdiffusion phenomenon. We studied gate stacks made up by a TiN layer deposited using Atomic Layer Deposition (ALD) on a HfO2 layer deposited using Atomic Vapour Deposition (AVD). Since the crystalline properties are thickness and thermal budget dependant, 1.5 and 5nm-thick HfO2 layers were processed. 1.5nm-thick layers are amorphous as deposited whereas 5nm-thick layers are crystalline. Expecting a similar behaviour for TiN, we deposited thicknesses between 2 and 10nm. For each TiN/HfO2 gate stack, some of the wafers were capped with 100nm of poly-silicon. Some of the capped wafers were then annealed for 5 seconds at 1050°C in He (spike anneal for dopant activation). These “full-sheet” samples were processed using integration-like conditions, making them relevant for technological applications. Gate stack morphology has been studied by XRR, deep-UV ellipsometry and HRTEM. The layers crystalline structure has been analyzed by ATR-FTIR and XRD. Chemical properties have been investigated using complementary analytical techniques. For some of them, probing the high-k/metal gate stack requires the removal of the thick poly-Si layer. Medium Energy Ion Scattering (MEIS) technique appears to be the most suitable for the investigation of the TiN/HfO2 interface due to its high sensitivity to heavy elements. We show that no inter-diffusion of Hf and Ti atoms occurs, even for annealed samples. On the other hand, light elements behaviour has been analyzed using XPS, ToF-SIMS and EELS. Both oxygen contamination of the TiN layer and nitrogen diffusion from TiN into HfO2 have been shown. The effect of the thermal budget will be discussed.[1] E. P. Gusev et al., IBM Journal of Research. and Development 50, 387-410 (2006)[2] C. Y. Kang et al., SOI Conference, 135-136 (2006)
10:30 AM - A10: Dielectrics
A10.5 Abstract Withdrawn
Show Abstract10:45 AM - A10.6
Post-Stress/BD Leakage Mechanism in Ultrathin High-κ (HfO2)x(SiO2)1-x/SiO2 Gate Stacks: Nano-Atomic Force Microscopy C-AFM.
Hasan Uppal 1 , Vladimir Markevich 1 , Athanasios Dimoulas 2 , Stelios Volkos 2 , Bruce Hamilton 1 , Anthony Peaker 1
1 Electrical and Electronics Engineering, Microelectronics and Nanostructures (M&N) Research Group, University of Manchester, Manchester, Greater Manchester, United Kingdom, 2 MBE Laboratory, Institute of Materials Science, NCSR DEMOKRITOS, Athens Greece
Show AbstractA conductive atomic force microscopy (C–AFM) in ultra high vacuum (UHV) has been used to characterize charge trapping in ultrathin as–deposited oxide films of 2 – 4nm (HfO2)x(SiO2)1-x/SiO2 gate stacks. Pre– and post–stress/BD dielectric degradation phases are ascertained on a nanoscale. A systematic comparison has been made to probe stress induced trap generation which leads eventually to physical stack breakdown (BD). The degradation mechanism is considered in terms of the pronounced localized leakage contribution of the high–κ and interfacial SiOx layers. Simultaneous interpretation of nanoscale current–voltage I–V characteristics and C–AFM imaging demonstrates charge trapping into the native or stress induced traps with intrinsic lateral charge propagation from the vicinity of the stressed areas. Constant voltage imaging in post–stress/BD phase shows the dependence of stress bias polarity on the BD induced topography artifacts and trap assisted nano–current variations. The physical attribute of deformed artifacts relates strongly with the direction of electron injection (gate and substrate injection) so discriminating the role of high–κ and interfacial SiOx in multilayer gate stacks. The technique has been shown to reveal the effect of post-stress/BD imaging for mapping non–homogeneous dynamic stack leakage.
11:00 AM - A10: Dielectrics
BREAK
A11: Advanced Devices
Session Chairs
Reinhart Job
John Williams
Wednesday PM, December 03, 2008
Room 202 (Hynes)
11:15 AM - A11.1
Charge Trapping Characteristics of SONOS Capacitors with Control Gates of Different Work Functions during Program/Erase Operations.
Donghua Li 1 , Seongjae Cho 1 , Il Han Park 1 , Jang-Gn Yun 1 , Jung Hoon Lee 1 , Doo-Hyun Kim 1 , Gil Sung Lee 1 , Yoon Kim 1 , Se-Hwan Park 1 , Won Bo Sim 1 , Jong Duk Lee 1 , Byung-Gook Park 1
1 Electrical Engineering and Computer Science, Seoul National University, Seoul Korea (the Republic of)
Show Abstract11:30 AM - A11.2
Contact Resistivity of NiPtSi on n-doped Silicon Activated by Laser Annealing.
Francois Pagette 1 , Paul Solomon 1 , Paul Kozlowski 1 , Anna Topol 1 , Wilfried Haensch 1
1 T. J. Watson Research Center, IBM, Yorktown Heigths, New York, United States
Show AbstractReducing specific contact resistivity of the silicide to silicon interface is advantageous to achieve high planar density and high drive current FET devices. Measuring the differential resistivities at different low voltage bias conditions of four terminal Kelvin test structures with a range of contact sizes has proven particularly effective in characterizing the linearity behavior and specific contact resistivity. This study shows that adding laser activation annealing for a n+ doped silicon contacted by a standard NiPt silicide is found to significantly improve the contact electrical properties. Initial results with only rapid thermal anneal activation show a size dependence of the contact resistivity with non-linear behavior exhibiting maximum resistance at zero bias, and contact resistivities ranging from 4E-8 Ω-cm2 to 4E-7 Ω-cm2. Adding laser activation anneal after the rapid thermal anneal gives ohmic behavior, for contact down to 50nm in size, with a specific contact resistivity of 1E-8 Ω-cm2. The metal-to-silicide contact resistance was measured separately using a novel test structure and it was confirmed to be negligible. We will describe our device structure, our experimental methodology, and the implications of our results for future devices.
11:45 AM - A11.3
Improved Trade-off Between Capacitance Density and Voltage Response in MIM Capacitor using SrTiO3-Medium K Bilayers.
Corentin Jorel 1 , Christophe Vallee 1 , Maurice Kahn 1 , Patrice Gonon 1 , Marceline Bonvalot 1 , Bernard Pelissier 1
1 , LTM (CNRS), Grenoble cedex 9 France
Show Abstract12:00 PM - A11.4
3-D Finite Element Simulation of a Phase-change Random Access Memory Cell with a Novel Self-insulated Structure.
Ke Sun 1 , Wen Feng 1 , Ya-Hong Xie 1
1 Materials Science & Engineering, University of California, Los Angeles, Los Angeles, California, United States
Show AbstractIn this paper, we proposed a phase-change random access memory (PCRAM) cell with a novel self-insulated structure (SIS), which is expected to have better thermal efficiency than the conventional structures. 3-D finite element simulation is used to study the most power consuming RESET process for both SIS and conventional normal bottom contact (NBC) cells driven by a MOSFET. Instead of programming current, power consumption is investigated to give a more fundamental comparison between the two structures. Thermal proximity effect for both kinds of cells is directly analyzed by simulating a 3×3 device array. The potential slow-quenching issue of SIS is also discussed.
12:30 PM - A11.6
Electronic Structure Study about the Role of Different Capping Metals (Hf, Ti, Zr) in Electrical Property of HfO2 Dielectric.
Jae Hyuck Jang 1 , Tae Joo Park 1 2 , Jeong Hwan Kim 1 2 , Kwang Duk Na 1 2 , Cheol Seong Hwang 1 2 , Miyoung Kim 1
1 Department of Material Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 Inter-university Semiconductor Research Center, Seoul National University, Seoul Korea (the Republic of)
Show Abstract12:45 PM - A11.7
Cathodoluminescence Study of Orientation Patterned (OP)–GaAs Crystals for Non-Linear Optical Conversion by Quasi- Phase Matching (QPM).
Hector Angulo 1 , Manuel Avella 1 , Oscar Martinez 1 , Juan Jimenez 1 , Candace Lynch 2 , Bavid Bliss 2
1 Fisica Materia Condensada, Universidad de Valladolid, Valladolid Spain, 2 Sensors Directorate, Air Force Research Laboratory, Hanscom, Massachusetts, United States
Show AbstractA12: Advanced Materials
Session Chairs
Jesse Jur
Francois Pagette
Wednesday PM, December 03, 2008
Room 202 (Hynes)
2:30 PM - A12.1
Strained P-channel for InGaAs CMOS.
Padmaja Nagaiah 1 , V. Tokranov 1 , M. Yakimov 1 , S. Oktyabrsky 1
1 College of Nanoscale Science and Engineering, University at Albany, SUNY, Albany, New York, United States
Show AbstractGroup III-V semiconductors are being investigated as potential replacements for conventional CMOS technology due to their higher mobility and saturation velocity. High performance n-FETs have been demonstrated previously. On the contrary, hole mobilities in the bulk III-V's are quite low due to large effective mass of holes. To overcome this fundamental problem, structures incorporating biaxial strain in quantum wells (QW) are used. However, high channel current requires low in-plane mass along with high carrier concentration, the latter calls for maximizing the strain in QW. In this work, we present systematic studies of transport properties of p-type QWs with varied strain, thickness (4-20 nm) and hole concentration (1-6x1012 cm^2). QW structures were designed and grown by MBE to maximize biaxial strain while preventing formation of misfit dislocations. Epitaxial pseudomorphic p-InxGa1-xAs/GaAs (x=0.15-0.30) and p-InxGa1-xAs/InP (x=0.53-0.83) strained QWs have been studied at various temperatures (T = 77-400K). The highest room temperature hole mobility of ~390 cm^2/V-s and the lowest sheet resistance of 8500 kΩ/sq was demonstrated for x=0.83 and QW thickness of 6 nm. In most cases, mobility varied as T^(-1.8) indicating a similar scattering mechanism in all of the structures. The highest mobility structure was used along with high-k hafnium oxide gate stack to fabricate p-channel MOSFETs.
2:45 PM - A12.2
Frequency Dependent Kelvin Probe Force Microscopy on Dopant Structures.
Anne-D. Mueller 1 , Heidemarie Schmidt 2 , Falk Mueller 1
1 , Anfatec Instruments AG, Oelsnitz Germany, 2 , FZ Rossendorf, Dresden Germany
Show Abstract3:00 PM - A12.3
Formation of Doping Profiles in Float Zone Silicon by Helium Implantation and Plasma Hydrogenation.
Reinhart Job 1 , Franz-Josef Niedernostheide 2 , Hans-Joachim Schulze 2 , Holger Schulze 3
1 Mathematics and Computer Science, University of Hagen, Hagen Germany, 2 , Infineon Technologies AG, Munich Germany, 3 , Infineon Technologies Austria AG, Villach Austria
Show AbstractApplying light ion irradiation – protons or alpha particles – the properties of semiconductors, i. e. usually silicon wafer substrates, can be easily modified under well controllable conditions [1]. Hence, nowadays the implantation with light ions is a powerful tool in semiconductor device technology, and it is widely used for device optimization. Implantations with hydrogen or helium can penetrate a wide spatial range within the silicon target wafer spanning 4 orders of magnitude between a depth of about 100 nm and 1 mm. Therefore, such substrate modifications can follow rather complex profiles if desired. In the actual presentation the formation of hydrogen-related donor and acceptor states were studied in helium implanted and subsequently hydrogen plasma treated n-type float zone (FZ) silicon wafers. He+-implantations were carried out at energies of 3.75 or 11 MeV, and fluences between 2x10E13 1/cm2 and 1x10E14 1/cm2. 13.56-MHz RF-plasma hydrogenations were done at a power of 150 W for 15 min or 1 hour applying substrate tem¬peratures of 400 °C or 450 °C. The samples were analyzed by depth resolved two-point-probe spreading resistance measurements. H-plasma exposure for 15 min at 400 °C causes an enhanced donor concentration in the subsurface region down to the projected range of the implanted He ions. Close to the surface acceptor-like states can be observed, too. The donor states in the subsurface region of the treated wafers as well as the acceptor states near the surface can be related to vacancy-hydrogen complexes. Long-term plasma hydrogenation leads to a strong injection of hydrogen into the FZ Si wafer; and a transformation of the vacancy- and hydrogen-related donor states into electrically in-active defect complexes, such as V-H4 defects, occurs. The formation and annihilation of the vacancy- and hydrogen-related donor and acceptor-like states will be discussed. If handled under appropriate conditions the studied processes might be useful for the optimization of power devices in the future. [1]A. A. Kozlov, V. V. Kozlovski, Semiconductors, 35, 735 (2001).
3:15 PM - A12.4
Observation of Microstructure of Grain Boundaries of ZnO Varistors using Backscattered-electron.
Masayuki Takada 1 , Yuuki Sato 1 , Shinzo Yoshikado 1
1 , Doshisha university, Kyotanabe Japan
Show AbstractIt is well-known that the degradation of voltage-current (V-I) characteristics progresses with the application of a voltage. One of the causes of this degradation was explained to be that the disappearance of the nonlinearity of the V-I) characteristics is caused by the redistribution of electrons or holes near grain boundaries between ZnO grains due to the movement of oxide ions or Zn2+ ions across the grain boundaries under the electric field. It is considered that the grain boundary structure is formed the spinel-type particles, Bi2O3 phase, and crystal orientation of the ZnO grains affect the movement of oxide ions or Zn2+ ions across the grain boundaries. The degree of the electrical degradation is related to the grain boundary structure formed by added the impurities [1]. It is necessary to observe clearly the change in grain boundary structure. Recently, composition of the samples such as elemental-mapping, is widely investigated using energy dispersion X-ray spectroscopy (EDX) to determine the distribution of the elements in the sample. However, the detection of small amount of additives, which segregated at grain boundaries or triple points, using EDX was difficult, because the elemental-mapping image is not clear. It is well known that the backscattered-electron (BSE) detector can not determine composition quantitatively, but can observe a sharp composition image with high contrast due to the strong atomic number Z dependence of the backscattering coefficient. This coefficient monotonically increases with Z. In this study, we clarify the distribution of small amount of additives at grain boundaries or triple points, such as Bi phase or spinel particles which affect the electrical degradation of ZnO varistors using BSE detector. ZnO varistors were fabricated using ZnO, Bi2O3, MnO2, Co3O4, SbCl3. The samples were sintered at 1150°C for 3 h in air. The composition image of Bi phase and spinel particles at grain boundaries and triple points using BSE were much sharper than that using EDX. In the BSE image, the thickness of Bi layer at grain boundaries were from approximately 25 nm to several μm. Moreover, the grain boundaries, where Bi layer existed uniformly and exist interrupted in the one grain boundary, were observed. It is found that there are two types of interface which spotted by Bi layer and faced Bi layer. The formation of grain boundary, where interrupted Bi layer is due to the ZnO grain interface attached spot-type Bi layer. Therefore, it is speculated that the various shapes of the Bi layer at the interface lead to the difference of the mobility of oxide ions or Zn2+ ions and the difference of the pathway through which ions move to the Bi layer at grain boundaries. Furthermore, it is speculated that the ZnO grain boundary with spotted Bi layer affect the electrical degradation progress due to the strong electric field.[1] M. Takada, and S. Yosikado: Proc. 10th. Eu. Ceram. Soc., (2007) 507
3:30 PM - A12.5
Characterization of High Quality InP on GaAs Grown by Hydrogen-assisted Molecular Beam Epitaxy by TEM and PL.
Francisco Morales 1 , A. Aouni 2 1 , R. Garcia 1 , P. Postigo 3 , C. Fonstad 4 , S. Molina 1
1 Materials Science and Engineering, University of Cádiz, Puerto Real, Cádiz, Spain, 2 Faculté de’Sciences et Techniques, Université Abdelmalek Essadi, Tanger Morocco, 3 Instituto de Microelectrónica de Madrid, Centro Nacional de Microelectrónica, CSIC, Madrid Spain, 4 Department of Electrical Engineering and Computer Science, and Microsystems Technology Laboratory, MIT, Cambridge, Massachusetts, United States
Show Abstract3:45 PM - A12.6
Spectroscopic Investigations of Oxide/GaN Interfaces for Integration in Multifunctional Structures.
Spalding Craft 1 , Jon Ihlefeld 2 , Darrell Schlom 2 , Jon-Paul Maria 1
1 Materials Science and Engineering, North Carolina State University, Raleigh, North Carolina, United States, 2 Materials Science and Engineering, Pennsylvania State University, State College, Pennsylvania, United States
Show AbstractA13: Thin Film Transistors
Session Chairs
Reinhart Job
Francisco Morales
Wednesday PM, December 03, 2008
Room 202 (Hynes)
4:15 PM - A13.1
The Electrical Stability of Room Temperature Deposited Amorphous Indium-gallium-zinc-oxide Thin Film Transistors.
Wantae Lim 1 , Yu-lin Wang 1 , Jewon Lee 1 , David Norton 1 , Stephen Pearton 1 , Fan Ren 2
1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States, 2 Chemical Engineering, University of Florida, Gainesville, Florida, United States
Show AbstractWe studied on Enhancement-mode amorphous indium gallium zinc oxide (α-IGZO) channel thin film transistors (TFTs) with a 10µm gate length and a 100µm gate width fabricated on glass substrates by RF magnetron sputtering near room temperature. The resistivities of the α-IGZO films were controlled from 10-1 to 103 Ω-cm by varying the deposition power, 75W to 300W. The n-type carrier concentration in the channel was 6.5x1017 cm-3. The gate oxide was 90 nm-thick-SiNx or 100nm-thick-HfO2, deposited by plasma enhanced chemical vapor deposition (PECVD) at 70°C and RF sputtering at room temperature, respectively. The bottom-gate TFTs had saturation mobility of ~17 cm2.V-1.s-1 and the drain current on-to-off ratio of ~ >105, a subthreshold gate-voltage swing of ~ 0.5 V.decade-1, and a threshold voltage of 2.1V. In the TFT with SiNx and HfO2 gate dielectrics, the relative change of saturation mobility and threshold voltage was less than ±1.5% after 500 hours aging time at room temperature. This demonstrates that α-IGZO films are promising semiconductor materials for long-term-stable transparent TFT applications
4:30 PM - A13.2
Low Temperature a-Si:H TFT on Soda Lime Glass.
Sangwoo Whangbo 1 , Bong-Kyu Shin 1 , Kapsoo Yoon 1 , Min Kang 1 , Jinho Ju 1 , Shiyul Kim 1 , JunHyung Souk 1
1 LCD Technical Center, AMLCD Division, Samsung Electronics. Co., Yongin-City, Kyungki-Do Korea (the Republic of)
Show AbstractAmorphous silicon thin film transistors were fabricated on soda lime glass substrate. To prevent the out-diffusion of alkali metal ions in the soda lime glass, the plasma-enhanced chemical vapor deposition (PECVD) SiNx barrier was used. In addition, to minimize the glass bending and compaction during heat-related processes, low temperature less than 220 degree C was applied through the whole fabrication processes. In this article, the amorphous silicon deposited at 220 degree C was investigated by IR absorption and transmittance measurement and the relationships with the property changes of thin film transistors (TFTs) were explained. The increased dihydride bonding configuration in a low-temperature amorphous silicon network indicates increased number of dangling bond and it caused higher optical band gap of the films. The transfer characteristics of low temperature a-Si:H TFT (LT-TFT) were basically compatible with those of high temperature ones. The behavior of leakage current level with/without light illumination was explained in terms of defect density in the film. The origin of TFT instability was proved that it follows the defect generation model and it caused the reducing of activation energy of LT-TFT.
4:45 PM - A13.3
Influence of In-Situ Arsenic Doped Emitter Poly Process Conditions on RF-BiCMOS Device Parametrics.
Richard Egloff 1 , Namwoong Paik 1 , Susan Beckett 1 , Jerry Mase 1 , Dan Codi 1
1 , NXP Semiconductors, Hopewell Junction, New York, United States
Show AbstractThis paper discusses the influence of polysilicon film structure and deposition conditions on in-situ As doped amorphous silicon emitter films used in NPN RF bipolar transistors. In-situ As doped amorphous and/ or polysilicon layers improve electrical performance in BiCMOS devices by reducing the number of process steps and eliminating issues associated with implanted polysilicon on high aspect ratio topographies (plug effect). This study was made using a vertical furnace configuration capable of 150 wafer loads. Because adsorbed AsH3 decomposition species block the adsorption sites and inhibit the deposition rate the process recipe is complex. Predictable bipolar parametrics require control of the As diffusion profile near the base region after activation, so a thorough understanding emitter film growth and dopant incorporation is necessary. We describe the relationship between of process conditions and recipe variants on transistor gain (Hfe), base current (Ib), and emitter resistance (Re). SIMS and in-line sheet resistivity measurements were used to monitor dopant incorporation into the emitter. This data was found to be predictive not only of the Hfe for a population, but also as an indicator of potential “renegade” Hfe behavior.
5:00 PM - A13.4
A Comprehensive Study of Stability in Bottom Gate a-IGZO Thin Film Transistor Grown by RF and DC Sputtering.
Sung Soo Park 1 , Kwang-Il Choi 1 , Dong-Ho Nam 1 , Won-Ho Choi 1 , Jaekyeong Jeong 2 , Gawon Lee 1
1 Dept. of Electronic Engineering, Chungnam National University, Daejeon Korea (the Republic of), 2 Corporate R and D Center, Samsung SDI, Yongin-Si, Gyeonggi-Do, Korea (the Republic of)
Show AbstractThough amorphous indium gallium zinc oxide (a-IGZO) TFTs have been extensively studied by various groups, very few experimental work has been reported on the stability characteristics though the stability of TFTs under gate bias stress is of crucial importance for their exploitation. In this paper, we focus on the gate bias stress effect on a-IGZO TFTs whose channels are formed by different sputtering conditions. Subsequently, the a-IGZO film of 50nm was grown by sputtering, using a polycrystalline InGaZnO target at room temperature. During sputtering, the Ar/O2 gas mixing ratio, input power density, and chamber pressure for RF (and DC) were 65/35 (and 72/28), 1.4 W/cm2 (and 2.0 W/cm2), and 5.0mTorr (and 3.4mTorr), respectively. To understand the cause of stress behavior, interface traps are extracted by subthreshold slop and low-high frequency C-V measurement and compared before and after gate bias stress. In both methods, the trap density is much lower in DC sputtered ones, which well explains the superior electrical properties like as threshold voltage, On/Off current ratio, and mobility. Under the gate bias stress, however, threshold voltage shift was larger in DC sputtered TFTs. In the case of interface traps, subthreshold slop and low-high frequency C-V are measured before and after gate bias stress which implies the trap density is not increased after gate bias stress in both DC and RF. The dependence of the threshold voltage shift on the duration of the gate bias indicates charge trapping phenomenon. To compare the charge trapping properties, DC and RF devices were subjected to four back to back hysteresis loop sweep at room temperature. We observed that in DC, flat band voltage shift is larger and successively to more positive voltage for each hysteresis loop during the reverse sweep. The result shows that RF recovers faster than DC, so it can be concluded that RF has more shallow traps which affect on temporary interface charge trapping than DC. This was further verified by measuring the time dependence of the total resistance (RT) after stress using the transfer line method (TLM). As measurement result, RT shift of RF between 0min and 60min after stress shows larger than DC which confirms the difference of recovery characteristic again in both RF, DC. That is, these results show larger detrapping characteristic of RF compared with DC. Therefore, it means that the more the charge density in active layer increase, the larger the RT is. From these, the extracted trap densities can explain the process-dependent device properties like as threshold voltage, mobility and On/Off current ratio, but are not dependent on bias stress in both DC and RF. And also we can conclude that the threshold voltage instability by gate bias stress arises due to the process of temporary charge trapping and that trapping and detrapping behavior is strongly dependent on the channel layer deposition condition by measurement of RT shift.
5:15 PM - A13.5
Charge Trapping in Low Power Back-Side ONO Non-Volatile Memory Devices.
Kung Ming Fan 1 2 , Helena Silva 2 , Chao Sung Lai 1 , Sandip Tiwari 3
1 Electronic Engineering, Chang Gung University, Tao-yuan Taiwan, 2 Electrical & Computer Engineering, University of Connecticut, Storrs, Connecticut, United States, 3 School of Applied and Engineering Physics, Cornell University, Ithaca, New York, United States
Show Abstract