The high operative voltages and the low mobility of semiconductors are probably the most relevant problems that have affected so far organic electronics devices and have significantly limited their employment in practical applications.
Many attempts of solving these problems have been done, aiming at a better performance of organic semiconductors. We believe that an as important route for achieving the final goal consists in improving the device architecture, aiming, at the same time, at a fabrication procedure able to be easily scaled up for industrial production.
By combining an ultra-thin dielectric layer with a self-aligned architecture, Organic Thin-Film Transistors (OTFTs) with ultra-low operational voltages (<2 V) and a very high (100 kHz) cut frequency have been obtained, with a traditional, low mobility organic semiconductor as Pentacene. The devices are fabricated using a one-mask, photolithographic self-alignment technique that can be realized with standard photoresists and without further chemical treatments. This technique allows a dramatic reduction of the parasitic capacitances thus leading to a remarkable increase of the cut-off frequency, even with organic semiconductors with a relatively low mobility. In this contribution, the main electrical parameters of ultra-low voltage, self-aligned devices are reported, and a complete frequency characterization of the devices is given. These characteristics make the reported approach suitable for the development of basic circuitries for high frequency applications.
In addition, optimized structures may be successfully employed for the realization of OTFT-based sensor devices, that also greatly benefit of the reduction of operating voltages and optimization of the frequency performances.

Getting away from oxide dielectrics in organic field-effect transistors (OFETs) is not only cost-effective but has tremendous advantages for improving carrier mobility and stability of devices. The charge carrier mobility in organic field-effect transistors OFETs can be enhanced by a few orders of magnitude by an appropriate choice of the dielectric-polymeric interface. Moreover, the polarity of solvents used for dissolving the dielectric material also plays a large role in enhancing charge carrier mobility and improving the transport characteristics. We demonstrate low-operating voltage, high mobility, and stable OFETs using both non-polar and polar polymeric dielectrics such as poly(4-vinyl phenol) (PVP), poly methyl metacrylate (PMMA), and polyvinylidene fluoride-trifluoroethylene (PVDF-TrFe), dissolved in solvents of high dipole moment. High dipole moment solvents such as propylene carbonate and dimethyl sulfoxide used for dissolving the polymer dielectric enhance the charge carrier mobilities by three orders of magnitude in pentacene OFETs compared to low dipole moment solvents. Fast switching circuits with patterned gate PVP-based pentacene OFETs demonstrated a switching frequency of 75 kHz at low input voltages. The frequency response of the OFETs is attributed to a high degree of dipolar-order in dielectric films obtained from high-polarity solvents and the resulting energetically ordered landscape for transport. Remarkably, these pentacene-based OFETs exhibited high stability under bias stress and in air with negligible shifts in the threshold voltage. Our results pave the way for high performance easily fabricated OFETs on flexible substrates, thus opening up a range of applications in real time fast organic logic circuits for radio frequency identity tags and e-paper applications.

In recently years, there has been great interest in the use of high-speed printing for manufacturing flexible electronic systems such as RFID tags, sensors and displays. In this work, we demonstrate a gravure printing-based fabrication process to realize high performance printed thin film transistors (TFTs) and discuss the challenges associated therewith. To improve device performance, the channel length and line width need to be scaled significantly. Recently, we demonstrated that direct gravure can print very fine features on flexible substrates. However, the alignment requirement for such features is very challenging, particularly at high printing speeds. Therefore, we introduce a fully overlapped source/drain structure with high-resolution source/drain lines, since this structure reduces parasitic capacitance while simultaneously relaxing layer-to-layer registration requirements. To enable this, the formation of printed lines using gravure printing is explained based on surface energy minimization and the impact of cell spacing is discussed. Because the printed volume is an important factor for line formation, we demonstrate that the printing speed can control the printed volume precisely. As a results of this understanding, linewidths below 10mu;m can be achieved consistently. Next, the printed lines are characterized in term of line edge roughness (LER) and line width roughness (LWR). The results reveal that the LER and LWR are independent of cell sizes and gaps and possible sources of LER and LWR are suggested. Finally, by optimizing deposition and annealing conditions for each layer, we realize optimized devices with saturation mobility of ~0.6cm2/Vsec and Imax/Imin of ~ 2E3. These represent some of the highest performance fully printed organic TFTs reported to date.

Organic thin-film transistors (OTFTs) are the most promising candidates for flexible electronics due to their flexible structures, simple ability to process large area displays, and excellent compatibility with flexible substrates [1]. To date, many studies have been reported that have aimed at developing a wide range of plastic electronics such as flexible displays, sensors, etc. In this talk, we will discuss the recent work, focusing on OTFT arrays and its application to flexible display. Active-matrix (AM) backplane using low-temperature cross-linkable olefin-type polymer as the gate insulator (GI) and air-stable DNTT as the organic semiconductor was successfully fabricated on a plastic substrate. The short channel TFT array exhibited a high hole mobility over 0.5 cm2/Vs, a low subthreshold slope of 0.31, and excellent environmental and operational stability. 5-inch flexible OLED display showed a high luminescence over 300 cd/m2 by driving of the DNTT-based OTFTs [1]. Solution-processed OTFTs are also attracting considerable attention due to both their simple and facile manufacturing processes and excellent transistor performances. We present a simple patterning process of solution-processed OSC for developing a high mobility short channel TFT array [2]. The OSC film was directly patterned on the confined active channel region by a simple lamination coating technique and the corresponding TFTs showed high mobility of up to 1.3 cm2/Vs. In the final section, we will demonstrate eco-friendly paper-based organic TFT array. Transparent cellulose nanofibers paper [3] was firstly applied to the flexible substrate for the TFT backplane. Solution-processed TFT exhibited high mobility exceeding 1 cm2/Vs, good air-stability, and an excellent mechanical stability.
[1] Y. Fujisaki et al., IEEE Trans. Electron Devices 59 (2012) 3442. [2] Y. Fujisaki et al., Appl. Phys. Lett. 102 (2013) 153305. [3] M. Nogi et al., Adv. Mater. 21 (2009) 1595.

Colloidal semiconducting nanoparticles and nanowires are interesting building blocks for large area and printable electronics. Solution-processability, potentially high mobilities and environmental stability compared to organic semiconductors are some of the possible advantages. However, the final device performances, for example, in field-effect transistors (FETs), often fall short of these high expectations. This may be due to intrinsic and extrinsic effects, such as large disorder, surface traps, injection barriers and inefficient planar gating. Few of these problems can be solved by using electrolyte-gating with ionic liquids or ionogels for nanowire FETs. The high capacitance (1-10 mu;F/cm²) of the electric double layer (EDL) that is formed evenly at the semiconductor- electrolyte interface under applied gate bias allows for the efficient injection of high charge carrier densities at very low voltages (<2 V). This is particularly useful for non-flat or porous semiconducting layers such as arrays and thin films of nanowires, because the EDL creates a uniform gating effect.
We present several examples, in which electrolyte-gating is used to obtain high mobility field-effect transistors with semiconducting nanowires, which are not possible with traditional gating techniques These include ambipolar PbSe nanowire FETs, that are not limited by any Schottky barriers and therefore show intrinsic one-dimensional charge transport behavior, and FETs based on highly aligned ZnO nanorod films with orientation-dependent electron mobilities of up to 9 cm²V^-1s^-1. Finally, we developed a new ionogel based on microcellulose and tailored ionic liquids that enables fabrication of low-voltage, flexible ZnO nanorod FETs and simple circuits on paper.

Vertical field effect transistor is a new architecture for Organic transistor in which the channel length is determined by the semiconductor film thickness. Since creating thin layers is a trivial process in a vertical architecture, it is possible to build high performance devices in spite of the organic semiconductors&’ relative low mobility. Owing to the patterned source electrode architecture, the gate is able to induce an efficient potential barrier lowering between the source electrode and the semiconductor and, as will be presented, enables fast switching (sub 2us) and high current densities (3A/cm^2).
Most of our results to date were based on the fabrication of the patterned electrode using di-block copolymer (polystyrene-block-polymethyl methacrylate) lithography that relies on its ability to self-assemble over cm scale areas. To extend the applicability of the structure to various material systems as well as to standard FAB lines we have developed a stepper photo-lithography process that can be applied to meter scale substrates as done in the display industry. We will show how judicious design of the electrode allows to optimize the device performance in terms of ON/OFF ratio and current levels. Using the ambipolar ActivInk N2200 [P(NDI2OD-T2)] by Polyera we demonstrate robust operation in a range of designs.
The experimental data will be accompanied by results from 2D numerical simulations of the device highlighting the physics that underlines the structure property relation between the nano-patterned electrode and the device performance Moreover, simulations results predict a possible switching time of a few tens of nanosecond once parasitic capacitances are minimized.

In the early 80&’s ferroelectric PVDF was proposed as an ideal candidate for data storage applications as it exhibits a bistable, remnant, polarization that can repeatedly be switched by an electric field. However, fabrication of smooth ferroelectric PVDF thin films, as required for microelectronic applications, was a longstanding problem. Recently smooth neat PVDF films can be made at elevated substrate temperatures. Upon applying a short electrical pulse the ferroelectric polar δ-phase is formed. [1]
Due to its relatively high coercive field, polymer films should be fabricated as thin as possible to operate the devices at low voltage. Thin films should have a large crystallinity and effective crystal orientation to obtain high remanent polarization. Here we show that by carefully optimizing the processing procedure, ultra-thin ferroelectric δ-PVDF capacitors can be achieved with a programming voltage below 5 V. The possibility to produce ferroelectric, smooth δ-PVDF, and with the drastic reduction in film thickness, paves the way to fabricate FeFETs that have low programming voltage and an excellent data retention and programming cycle endurance.

References
[1] M. Li et al, Nat. Mater., 2013, 12, 433.
Corresponding email:
Mengyuan Li: mengyuan.li@rug.nl

In this study we report the fabrication of fully transparent p-type SnO thin film transistors (TFT) at temperatures as low as 180 oC with record device performance. Specifically, by carefully controlling the process conditions, we have developed SnO thin films with a Hall mobility of 18.71 cm2V-1s-1 and fabricated TFT devices with a linear field-effect mobility of 6.75 cm2V-1s-1 and 5.87 cm2V-1s-1 on transparent rigid and translucent flexible substrates, respectively. These values of mobility are the highest reported to date for any p-type oxide processed at this low temperature. We further demonstrate that this high mobility is realized by careful phase engineering. Specifically, we show that phase-pure SnO is not necessarily the highest mobility phase; instead, well-controlled amounts of residual metallic tin are shown to substantially increase the hole mobility. A detailed phase stability map for physical vapor deposition of nanoscale SnO is constructed for the first time for this p-type oxide. In addition, nanowire devices based on SnO will be discussed.

Transfer printing and electrohydrodynamic jet printing represent versatile techniques for patterning two and three dimensional structures of diverse materials, with feature sizes from the cm to the nm range. Some of the most compelling application opportunities are in electronic and optoelectronic devices that combine high performance inorganic semiconductor materials in the form of nanomembranes/ribbons/wires with unusual substrates, such as sheets of plastic or slabs of rubber. This talk presents some recent advances in these technologies, with examples of their use in transient and epidermal electronic systems.

Large area coating with conjugated polymers is typically achieved by casting from chlorinated organic solvents. The marginal solubility of the polymers results in highly variable film quality and limited ink solution shelf life. These technical challenges can be met through creation of stable aqueous suspensions that also reduce hazards to health and environment in the casting procedure. In this work, poly(3-hexylthiophene) (P3HT) colloids were prepared by dispersion in aqueous solution using a mini-emulsion technique. A blade coating procedure was used to produce high quality films from these colloidal suspensions, and the morphology of the films was compared with that of active layers coated from solutions in organic solvents. We show that both size and crystallinity of these colloids and their films can be tuned by controlling the initial solution concentration, surfactant type and processing parameters.
The colloidal size was measured by dynamic light scattering (DLS), which showed that the particles were stable against aggregation for several weeks. The presence of different surfactants affected the crystal structure of P3HT colloids, which in turn could affect the photoelectric properties of active layers. The morphology of both colloids and active layers were characterized using imaging and spectroscopy. In addition, the optical and electronic properties of active layers blade coated from colloids were investigated and correlated to the specific crystallinity and morphology of the films. Results from this work could have important implications for solution printing technologies in organic electronics.

Based on the recent works of our group on ultra-thin, ultra-conformable circuits made of free-standing PEDOT:PSS nanosheets [1-3], we further extended the processing and application capabilities of this technology by developing a new technique that uses temporary tatto paper as a novel unconventional substrate for fabrication. Single layer PEDOT : PSS, as well as multilayer nanosheets with poly(styrene) (PS), poly(lactic acid) (PLA) or poly(dimethylsiloxane) (PDMS) with total thickness 50 < t < 600 nm were fabricated over large areas by spin-coating deposition on commercially available tattoo paper. Conductive nanosheets were patterned by an ink-jet technique with an overoxidizing solution (NaClO, 5 wt.% in water) in order to draw circuits with various design. Alternatively, by making use of commercial tattoo kits, conductive patterns were created on polymer nanosheets or on common temporary tattoos by ink-jet deposition of properly modified PEDOT :PSS dispersion in water. Conductive tattoo nanosheets were finally released from the temporary substrate by simple wetting of the paper. Thus, circuits can be transferred onto the desired surfaces with an extremely easy, cheap and fast procedure as in normal tattoo for kids. The released free-standing nanosheets are characterized by ultra-conformability on a variety of different substrates, such as tissues or soft and rigid materials with complex topography and non-planar shapes; "tattoo" nanosheets maintain their conductive functionality when transferred onto skin, suggesting their use in the field of skin-contact electronics as sensors or electrodes [4,5]. Here we report the details about the fabrication processes and the characterization of tattoo nanosheets as concerns their morphology, structure and conductivity. In particular, various configurations of multilayers nanosheets are reported with the conductive layer put in contact or isolated with respect to the surface onto which the tattoo is attached.
Very large area nanosheets can be realized thanks to the fact that their lateral dimensions are solely determined by the size of the paper substrate. The overall technique has been designed and optimized in order to permit its easy implementation in roll to roll processing with the use of materials and equipment characterized by reduced costs with respect to more demanding and costly clean-room related technologies. Possible applications of conductive tattoo nanosheets are foreseen in the field of sensing and actuation [6], as well as in the biomedical field.
References
1. F. Greco, et al., Soft Matter 7 (22), 10642-10650 (2011).
2. F. Greco, et al., MRS Online Proceedings Library 1403 (2012).
3. A. Zucca, et al., MRS Online Proceedings Library 1530 (2013).
4. J. R. Windmiller, et al., Analyst 137, 1570-1575 (2012).
5. J. R. Windmiller, et al., Chemical Communications 48, 6794-6796 (2012).
6. S. Taccola, et al., ACS Applied Materials & Interfaces, Accepted, In Press (2013).

The structure resolution of mass printing processes such as flexographic printing, gravure printing, screen printing or offset printing is typically found in the range of 100µm. There are patterning techniques compatible with roll-to-roll manufacturing such as laser ablation and ink jet printing that have been shown to be capable of producing features with dimensions down to 10µm. However, since there is always a trade-off between throughput and minimum feature size these serial patterning techniques are not compatible with industrial and low cost production. Contrary, roller-based imprinting processes such as R2R-UV-nanoimprint lithography (R2R-UV-NIL) and hot embossing are capable of patterning on the nanoscale with production-fit throughput thus paving the way for high-resolution patterning on large flexible areas.
This paper will introduce NIL as a very powerful patterning technique in fabricating high-performing small-channel organic thin film transistors used as backplanes for LCD displays. By utilizing a self-aligned process sequence it was possible to fabricate low-voltage flexible ring oscillators with a stage delay of only 4mu;s at 5V. The second part builds a bridge from batch-UV-NIL to R2R-UV-NIL. It will be shown that substantial effort is necessary to optimize the imprint resist, the material and fabrication of the stamps as well as the surface treatment of the imprint tools. Applications ranging from biomimetic surfaces, over metallic nano-patterns to microfluidics - all realized on m2-areas- will be presented.

Oxide semiconductor thin film transistor (TFT) use in display applications is increasing rapidly. Thus far, interest has centered on indium gallium zinc oxide (IGZO) deposited by sputtering, which can provide TFTs with mobility about ten times larger than amorphous silicon. IGZO TFTs easily meet the requirements of liquid crystal displays and can provide increased resolution and reduced power consumption. Recently, IGZO TFTs have also begun to find commercial application in active matrix organic light emitting displays (AMOLEDs), but TFT uniformity and stability can be problematic for this application. More general large area electronic applications will be even more demanding and will require high performance analog circuits and fabrication on flexible substrates. For such applications, plasma enhanced atomic layer deposition (PEALD) ZnO TFTs and modified device structures can provide important advantages. Atomic layer deposition (ALD) deposition can provide high yield even on flexible substrates with significant roughness and defect density. PEALD ZnO TFTs have typical field-effect mobility of 20-30 cm²/Vs and high yield on flexible substrates. It is also likely that TFTs used for large area applications will need to interface with conventional low voltage silicon ICs. By using a double-gate PEALD ZnO TFT structure, TFT threshold voltage can be tuned which allows high gain (>100) enhancement/depletion mode amplifiers and digital circuits tuned for low voltage operation or interfacing [2]. Large area applications will also require robust device passivation that does not degrade TFT performance. Tri-layer PEALD ZnO TFTs with a dielectric-semiconductor-dielectric stack deposited in a single pump down provide protection for the TFT channel during and after processing, and improved bias stress stability compared to end-of-process passivated TFTs [3]. PEALD ZnO together with double-gate and tri-layer TFT structures provide important building blocks for general large area electronic applications.
1. D. A. Zhao, D. A. Mourey, and T. N. Jackson, “Fast Flexible Plastic Substrate ZnO Circuits,” IEEE Electron Device Letters, 31, pp. 323-5 (April 2010).
2. Y. V. Li, J. I. Ramirez, K. G. Sun, and T. N. Jackson, “Low-Voltage Double-Gate ZnO Thin-Film Transistor Circuits,” IEEE Electron Device Letters, 34, pp. 91-3 (July 2013).
3. Y. V. Li, K. G. Sun, J. I. Ramirez, and T. N. Jackson, “Tri-layer PEALD ZnO Thin Film Transistors and Circuits,” 2013 Device Research Conference Digest, pp. 167-8 (June 2013).

Gas diffusion barriers (GDB) are inevitable to protect sensitive materials or devices against oxygen and moisture. Atomic layer deposition (ALD) has been shown to allow the preparation of outstanding thin-film gas permeation barriers on large-area substrates even at relatively low processing temperatures (< 150°C). Typically, these barriers are insulators, e.g. Al2O3 or multilayers of Al2O3/ZrO2, etc.[1]
A wide range of applications requires GDB which are at the same time transparent and electrically conductive. For flexible electronics on polymer substrates they could serve as electrode and moisture barrier simultaneously, thereby simplifying production. In a similar sense, transparent conductive barriers pave the way to robust transparent conductive electrodes based on thin films of oxidation sensitive metals. While conductive barriers can protect these metal electrodes, they concomitantly allow to electrically connect to these metals in device applications. For example, Cu either as a sub-10 nm thin-film or as a percolating Cu nanowire mesh[2] is considered as a promising material to prepare highly conductive, transparent and cost effective electrodes for opto-electronic devices (e.g. OLEDs or solar cells) without the use of scarce and costly Indium or Silver. Unprotected thin Cu layers with a thickness of 7 nm are completely oxidized within 20 minutes under damp heat conditions.
We show that transparent conductive GDBs based on ZnO layers prepared by ALD are not the optimum choice.[3] In spite of its poly-crystalline morphology 100 nm thick layers of pristine or Al doped ZnO show low gas permeation rates on the order of 10-5 g/m2 day. However, their electrical conductivity degrades by 3 orders of magnitude within less than a day under damp heat conditions (85°C / 85% rH). We show that moisture induced degradation becomes the more severe for lower deposition temperatures, limiting the applicability in cases where low temperature processing is mandatory. Opposed to that, we introduce SnO2 and nano-laminates of SnO2/TiO2 as highly robust transparent conductive GDBs, prepared by low-temperature ALD. Thin Cu layers protected by a 100 nm thick conductive SnO2-based GDB retain their low sheet resistance of (< 20 Ohm/sq) without change after several days @ (85°C / 85%rH). They even remain unaffected by immersion in boiling water for several hours. We will show that these novel highly robust composite Cu/SnO2 transparent conductive barrier electrodes can be favorably applied as a cost effective alternative to ITO electrodes in organic solar cells and OLEDs.
[1] J. Meyer, P. Gorrn, F. Bertram, S. Hamwi, T. Winkler, H. H. Johannes, T. Weimann, P. Hinze, T. Riedl, W. Kowalsky, Adv Mater 2009, 21, 1845; M. Fakhri, N. Babin, A. Behrendt, T. Jakob, P. Görrn, T. Riedl, Adv Mater 2013, 25, 2821.
[2] L. Hu, H. Wu, Y. Cui, Mrs Bull 2011, 36, 760.
[3] C.-T. Chou, P.-W. Yu, M.-H. Tseng, C.-C. Hsu, J.-J. Shyue, C.-C. Wang, F.-Y. Tsai, Adv Mater 2013, 25, 1750.

Solution deposition of organic semiconductors (OSC) is a leading contender for producing large-area, inexpensive, and flexible organic electronics. We recently developed a solution deposition method called solution shearing, which resulted in better organic field effect transistor (OFET) performance for small molecules, due to changing the molecular packing of the OSC. Certain conditions on the small molecule TIPS-pentacene have yielded remarkable FET performance, with average charge carrier mobility around 2 cm2 V-1s-1 with some transistors showing mobilities as high as 4 cm2 V-1s-1. However, it is unclear whether solution shearing can also change the molecular packing of polymeric OSCs. We discuss the applicability of solution shearing to a range of polymeric OSCs as well. We show effective tuning of molecular packing of polymers that can tune charge carrier performance through solution processing. The ability to influence polymer molecular packing without resorting to chemical synthesis will allow for more methods to improve the FET properties of polymers in organic electronics.
Industrial applications of lattice strained OFETs requires that the OFETS are patterned, and it is unclear whether the patterned OFETs will still maintain a lattice strained crystal packing. We have developed a surface functionalization procedure that utilizes hydrophobic/hydrophilic interactions on the interface to isolate lattice strained OSCs. We show the existence of strain though X-ray diffraction techniques, and study the charge transport properties of the patterned, lattice strained OFETs. We show that charge carrier mobilities up to 2 cm2/Vs are possible in the patterned OFETs of TIPS-pentacene, and that strained OFETs can exist at patterning sizes of 100 microns and lower. We show that the pattern size can have an effect on the lattice strain possible in the OSCs, and investigate methods that enable sub 10 micron scale patterning using solution shearing.

Direct, additive printing of solution-based conductors, semiconductors and dielectrics enables digital fabrication of electronics over large areas at low-cost. Using drop-on-demand ink-jet printing we have developed n- and p-type field-effect transistors (FETs) based on organic materials. Complementary logic circuits such as shift registers and threshold detectors were designed and fabricated based on extracted design rules and models for these FETs. Such circuits, when combined with other printed components such as power sources, sensors and memory, can provide the signal processing capabilities for print production of large-area sensing systems. While these systems can address many application areas (such as health monitoring and item tracking), their functionality is limited by the typical feature sizes (10s of microns) provided by traditional graphics printing systems.
In order to bridge the length-scale gap between typical printing systems and high performance electronic devices we have developed a system of mesoscale assembly for arbitrary patterning of microelectronic components. Taking inspiration from xerography (where large numbers of micron-sized toner particles are assembled electostatically), a method of programmable assembly of pre-fabricated microchips using electric fields will be described. Here, small silicon pieces (100s of microns in size) are fabricated and formulated into a solution-based ink. The chips are pre-treated to bear a pattern of electric charge, so that they respond to dynamic electric fields which are used to freely orient and transport them into position with micron-level accuracy. Once correctly assembled, the chips are then transferred and fixed to a final substrate, and interconnections are made. Such a system should enable a digital, print-like method of assembling and integrating high-performance electronics over large areas.