A combination of favorable materials properties such as a high breakdown field, high polarization-doped two-dimensional electron gas density, high electron mobility, and high peak electron saturation velocity make the (Al,Ga)N material system of great interest for power switching devices. In order to take advantage of the intrinsic benefits offered by this material system, key challenges associated with surface passivation, epitaxial growth, leakage, gate dielectrics, and electric field management must be addressed in power switching transistors. In this talk, recent materials and device innovations addressing these challenges and enabling high-efficiency high-frequency power switch operation will be overviewed. The potential impact of high-speed high-voltage (Al,Ga)N transistors on power switching and RF applications will be discussed.

GaN-based materials are high attractive for power electron devices because of their combination of high breakdown field and high conductivity - particularly in two dimensional electron gases that form at the AlGaN/GaN interface. We present recent results on improved conductivity in AlGaN/AlN/GaN and InAlN/AlN/GaN heterostructures based on precise layer and composition control in both plasma-assisted molecular beam epitaxy (PAMBE) and ammonia molecular beam epitaxy (NH₃ MBE). In a series of systematic experiments, we elucidate the role of threading dislocations in gate leakage, channel conductivity, and three-terminal breakdown voltage. We also will present new data on high flux PAMBE growth and record bulk electron mobility in NH₃ MBE GaN - we place these later two results in the context of vertical GaN-based structures for high voltage operation.

AlGaN/GaN High Electron Mobility Transistors (HEMTs) are well suited for high power applications in the frequency range from 2 to 100 GHz due to a high breakdown voltage and large charge densities in the channel even without doping the AlGaN barrier. It is assumed that the two-dimensional electron gas (2DEG) in the channel originate from surface donors [1]. Moreover, due to the small distance between channel and surface, it can be expected that the 2DEG may be changed by altering the surface of the HEMT structure.
Plasma based techniques like deposition and dry etching are widely used in the fabrication scheme of modern semiconductor devices. In particular, plasma treatment on the surface of the active transistor area should be avoided because it may affect the electronic properties of the transistors strongly. In the case of AlGaN/GaN HEMTs it has been shown that fluorine plasma treatment depletes the 2DEG channel from electrons and thus changes the transistor characteristics from normally on to normally off. The observed depletion has been attributed to an enhanced surface potential. We have shown recently that incorporation into the AlGaN barrier also enhances impurity scattering of the channel electrons [2].
In this work, we have systematically studied the influence of fluorine and nitrogen based plasma processes on the electronic properties of AlGaN/GaN HEMT structures having different barrier thicknesses, and aluminum content. Also, the influence of a GaN-cap layer with different thicknesses has been investigated. The electrical properties of the 2DEG were characterized by Hall measurements, while photo electron spectroscopy and x-ray reflectivity were used to analyze material properties. The results which will be presented in more detail at the conference can be summarized as follows:
(i) Plasma treatment affects the 2DEG properties primarily by changes of the surface potential.
(ii) Hard plasma treatments reduce the mobility in the 2DEG strongly, which may be explained by enhanced scattering due to the incorporation of negatively charged fluorine ions.
(iii) Annealing in nitrogen at 425°C leads to complete recovery of the electronic properties except for samples which were subjected to hard plasma treatment.
The results of these investigations have been applied for the fabrication of HEMT devices with improved characteristics.
[1] J.P. Ibbetson et al. Appl. Phys. Lett. 77 (2000) 250.
[2] St. Linkohr, et al., Phys. Status Solidi C 9 (2012) 938.

III-nitride (III-N) materials system and related bipolar devices, e.g. PIN diodes and transistors offer greatly increased power-switching performance and a dramatic theoretical advantage in the standard Figures of Merit. Although extensive efforts were spent on the development of III-N unipolar devices such as heterojunction field effect transistors, recent developments of III-N heterojunction bipolar transistors (HBTs), in particular GaN/InGaN HBTs, have shown that III-N bipolar transistors could able be suitable for next-generation high-power switching and amplification. We have previously reported npn GaN/In_0.03Ga_0.97N HBTs with high current gain (h_fe > 100) and high current density (J_C > 20 kA/cm²) for devices grown on sapphire substrates [[1],[2],[3]]. The microwave performance of InGaN/GaN HBTs with f_T = 8GHz were also reported [[4]]. However, these devices were prone to degradation under a high current stressing condition and the achievable J_C and the d.c. power density (P_d.c.) were limited for GaN/InGaN HBTs grown on sapphire. In this paper, we report on a drastic InGaN HBT performance improvement using a palladium-based metallization for the base layer contact. When compared to a typical nickel-based metallization, the Pd-based contact demonstrated a much improved contact stability and is less susceptible to the high-current-stressing related device degradation. The fabricated GaN/InGaN HBTs using the newly developed metal scheme also shows a record J_C > 94 kA/cm² and P_d.c.> 1.3 MW/cm² for a device with an emitter area (A_E) of 11.7 mm². To the best of our knowledge, the results represent the highest current and power handling performance achievable for III-N HBTs grown on sapphire substrates to date. We also report on State-of-the-Art GaN PIN diodes with a reverse blocking voltage of 800V and a specific on-resistance of (R_ONA) of 0.28 mOmega;-cm² at a current density (J) of 2.5 kA/cm². The Baliga Figure of Merit of these devices is 2.5 GW/cm². The on-state resistance represents the lowest value a semiconductor power rectifier could achieve in the 800-V range.
References:
[[1]] S.-C. Shen, et al., “GaN/InGaN Heterojunction Bipolar Transistors with fT > 5 GHz,” IEEE Electron Device Letters, vol. 32, no. 8, pp. 1065-1067, August 2011.
[[2]] Y.-C. Lee, et al., "GaN/InGaN heterojunction bipolar transistors with ultra-high d.c. power density (>3MW/cm²)," Phys. Status Solidi A, vol.209, no. 3, pp.497, 2012
[[3]] Yun Zhang, et al., “High- performance GaN/ InGaN double heterojunction bipolar transistors with power density >240 kW/cm², ” Phys. Status Solidi C, vol. 8, no. 7-8, pp. 2451-2453, 2011
[[4]] R. D. Dupuis, et.,al., “III-N High-Power Bipolar Transistors,” in ECS Transactions, vol. 58, no. 4, pp. 261-267, 2013

There is a great interest in developing rectifying and switching power devices based on wide bandgap materials such as SiC and GaN, while silicon power devices are approaching material physical limits. To date, a majority of GaN power device development effort has been directed toward lateral devices, such as high-electron mobility transistors, fabricated in thin layers of GaN that are grown on foreign substrates. By fabricating power semiconductor devices on bulk GaN substrates with low defect density, it is possible to realize the fundamental material limit potential of GaN including true avalanche breakdown capability.
Here we describe materials-related issues associated with bulk-GaN-based power electronic devices, including challenges of MOCVD growth, estimates of fundamental properties such as electron mobility and breakdown field; and their temperature-dependence and their impact on performance. Vertical GaN pn junction diodes with breakdown voltages up to 3.7kV have been fabricated on bulk GaN substrates. Large-are diodes with 400A pulsed-current capability and 700V reverse breakdown are also demonstrated. However, due to design and process complexities it has been difficult to demonstrate high performance vertical GaN transistors. These devices lag behind the lateral GaN transistors and their SiC-based counterparts. Here we report vertical GaN transistors with breakdown voltages of 1.5kV fabricated on bulk GaN substrates. These transistors operate in a normally-off condition, with a specific on-resistance of 2.2mOmega;-cm².

GaN is a promising material for the development of power electronic devices due to its superior material properties. A problem for device design is that the break-down voltages for lateral and vertical GaN is still limited by field crowding, both at the sample edges and at defects. While field termination techniques such as incorporating field plates or damage implants have been implemented, device breakdown voltages are still well below theoretical GaN limits. In this paper, we propose a novel wrap around field plate termination technique for a vertical device fabricated on a free standing GaN substrate.In the wrap around structure, the field plate is designed so that it controls the entire device area, unlike conventional field plates which simply shift field crowding away from the sample edge. 2D finite element simulations using ATLAS show that this produces a uniform field distribution, similar that of an infinite plate capacitor, with no field crowding at the edges. The wrap around structure outperforms conventional field plate structure, and shows breakdown voltages beyond 1400 V for a 5um thick epilayer vertical Schottky barrier diode.

Continuous scaling of Si transistors has enabled us to sustain Moore&’s law for over 30 years. However, the physical gate length has already reached 30nm in the current 65nm technology node and is expected to reach 10nm within the next few years. This is widely believed to be the physical limit, beyond which we have to look at alternatives to scaling in order to continue enjoying the benefits of Moore&’s law. III-nitrides offer unique advantages over other materials for high frequency and high power applications. Although, in terms of mean electron velocity, these predictions are much less than those possible with GaAs, GaN has a larger peak electron velocity, larger saturation velocity, higher breakdown voltage and thermal stability, making it ideal for use as a channel material in microwave and high frequency integrated circuits. Successful realisation of these devices requires Schottky contacts with large Schottky barriers and good thermal stability. The wide and direct bandgap (3.4eV) of GaN results in a lower leakage current and consequently, an ability to operate at higher temperatures. These properties make GaN an important material for high frequency and high power applications. Schottky diodes have advantages like high operating frequency, fast switching speed and low forward voltage drop. As a result, Schottky diodes are widely used in a variety of RF and microwave applications like varactors, detectors, mixers, multipliers and low-voltage reference circuits. In the study of semiconductor surfaces, the metal-insulator-semiconductor Schottky diode is an important device. The performance of semiconductor devices is closely related to their surface conditions and an understanding of surface physics with the help of MIS diodes is of great importance to device operation.
GaN (n-type) films were grown using plasma assisted molecular beam epitaxy (PA-MBE). Pt/HfO₂/n-GaN metal-insulator-semiconductor Schottky diodes were fabricated using standard lithography techniques. 10nm thick HfO₂ was deposited using RF sputtering as the insulator layer. Conventional Pt/n-GaN metal-semiconductor Schottky diodes were also fabricated. The performance of the Pt/n-GaN (MS) structure was compared with the Pt/HfO2/n-GaN (MIS) structure . IV and CV measurements were carried out to confirm the Schottky nature of contacts.
It was found that introduction of the HfO₂ layer resulted in a decrease in leakage current, slight increase of barrier height and a reduction in the ideality factor. Mechanism of current transport in MS and MIS structures were studied. Diode parameters like barrier height and ideality factor were extracted and were found to be temperature dependant. This indicates that there are inhomogenities in the barrier height at the interface. The experimental observations were modelled by assuming a Gaussian distribution of barrier heights at the interface. Results were validated using industry standard device simulator Silvaco Atlas.

GaN electronic devices despite already achieving outstanding device performance have still limitations in reliability resulting in a restricted safe-operating area (SOA) which could be dramatically increased once trapping and thermal challenges have been addressed. This may even involve the beneficial use of dislocations which have been shown to be able to reduce dynamic Ron effects. Degradation mechanisms have also not been fully understood yet. Our latest results in this field will be presented, using a combination of electrical, optical experimental device assessment and device simulation.

The development of GaN on Si substrates is a critical technology for potential low cost power electronics. These devices can accommodate faster switching speeds, hotter temperatures, and high voltages needed for power electronics applications. However, the lattice mismatch and difference in crystal structure between 111 Si and c-axis hexagonal GaN requires the use of buffer layers in order to grow device quality epitaxial layers. For lateral high electron mobility transistors, these interfacial layers act as a potential source of increased thermal boundary resistance which impedes heat flow out of the GaN on Si devices. In addition, these interfacial layers impact the growth and residual stress in the GaN epitaxial layer which can play a role in device reliability. In this work, we explore the impact of the use of AlN and super lattice (SL) interfacial layers on the thermal boundary resistance and residual stress AlGaN/GaN heterostructures grown on 111 Si. Transient domain thermoreflectance measurements were used to measure the thermal boundary resistance on device stack with increasing complexity beginning with samples of AlN or SL on Si followed by GaN/Al/Si or Gan/SL/Si. In addition the thickness of the GaN layer was increased clearly showing the impact of the GaN layer thickness on the intrinsic thermal conductivity of the GaN layer. The residual strain in the GaN layer was measured using Raman spectroscopy and photoluminescence. Data show that large thermal boundary resistances can be introduced through the use of SL interfacial layers, depending on the number of periods used. In addition, a strong thickness dependence in thermal conductivity exists for the GaN layers. These results suggest that while SL layers may help with the residual stress in the GaN layer, care must be taken in their design in order to minimize the impact on interfacial thermal boundary resistance for GaN on Si devices.

AlGaN/GaN high electron mobility transistors (HEMTs) are promising for high frequency high power device applications in space-based communication systems, due to their unique combination of strong transport properties and radiation hardness. Nevertheless, these devices do degrade after being exposed to large doses of high energy particles. One of the commonly observed degradation features is the shift of threshold voltage (V_th). In particular, proton irradiation has been reported to cause a positive V_th shift in both HEMTs and AlGaN/GaN structures.^[1] Although this effect is generally attributed to the radiation-induced deep levels, the detailed degradation mechanism is not well established yet. Our previous work has revealed that proton irradiation introduces compensating centers in n-type GaN,^[2] therefore, it is of particular interest to investigate the possible correlation between the radiation-induced traps in the GaN buffer and V_th shifts in proton-irradiated AlGaN/GaN structures. Here, we explored the V_th shift as a function of proton fluence for two AlGaN/GaN structures with different GaN buffers. The V_th evolutions for these two samples were significantly different, clearly revealing the impact from the GaN layer. By comparing experimental and simulated results, the V_th shift behavior can be explained by radiation-induced buffer traps.
The two AlGaN/GaN heterostructures studied here consist of identical 26 nm-thick Al_0.2Ga_0.8N/800 nm-thick GaN structures, but with different doping densities in the GaN layers; one was unintentionally doped (UID) while the other one was doped with 4×10¹⁶ cm^-3 Si. The samples were processed into Schottky diodes and exposed to 1.8 MeV proton radiation of different fluences varying from 5×10¹² cm^-2 to 1×10¹⁴ cm^-2. Although both samples exhibit positive V_th shifts after radiation, their evolutions are substantially different. For the sample with UID-GaN, V_th increases rapidly at low fluence. In contrast, for the sample with Si-doped GaN, there is a clear threshold behavior for V_th shift: the V_th is almost constant at low fluences, and starts to increase drastically only after a fluence of 3×10¹³ cm^-2. The simulated band structure shows that large density of irradiation-induced acceptors in GaN can significantly lower the Fermi level in buffer, thus positively shifts V_th in AlGaN/GaN. As this effect on the Fermi level position depends on the ratio between the densities of traps and background doping, a higher trap density, therefore, a higher fluence, is needed for such a behavior to be revealed in the sample with doped GaN. Using the trap energies and densities obtained from our study in n-type GaN, the simulated V_th evolutions match the experimental data, revealing that the proton radiation-induced traps in GaN causes the V_th shift in these AlGaN/GaN structures.
[1] X. Hu, et. al., IEEE Trans. Nucl. Sci.50, 1791 (2003)
[2] Z. Zhang, et al., Appl. Phys. Lett. 103, 42102 (2013)

GaN-based High Electron Mobility Transistors (HEMTs) are contenders for replacing existing Si and GaAs devices in high-power radio-frequency applications. AlGaN/GaN HEMTs take advantage of sheet of highly mobile electrons, confined in a two-dimensional electron gas (2DEG), that forms at the heterointerface and are easily modulated by an applied bias. Unfortunately, high-power operating conditions often result in unpredictable and catastrophic device degradation. In previous work, we correlated the formation of clusters of defects under the drain edge of the gate as a function of device lifetime and performance. Evolution of strain in the AlGaN layer was utilized to estimate the sheet polarization charge density over time. However, the formation mechanisms of these defects as well as contribution of existing threading dislocations have not been fully investigated. As such, quantitative analysis on the evolution of defects is needed to further understand device failure mechanisms.
In this work we employed in-situ Transmission Electron Microscopy (TEM) to investigate degradation of a pristine transistor under electrical bias. Specifically, we compared device degradation during both off- and on-state stresses. Off-state stressing causes the device to enter a pinch off state, wherein the 2DEG is depleted of mobile carriers and the device is only subject to electric field effects. On-state stressing causes the device to experience both electric field and thermal effects caused by accelerated electrons. These experiments resulted in the formation and increase in density of defects as well as shortening of the threading dislocations under bias.
Coupling in-situ experiments with geometric phase analysis and NanoMEGAS orientation mapping, we quantified the evolution of strain and dislocations within the devices. After biasing, High-angle annular dark-field imaging and electron energy loss spectroscopy were performed on the bias-induced defects in order to further analyze their nature and electronic state, and also to investigate possible diffusion of gate metals in the AlGaN layer. This research serves to improve the current understanding of physical degradation of GaN HEMTs during operation and can lead to improved prediction models and better device reliability.

In this study, we have investigated GaN channel layer to suppress drain lag, which is an important parameter for switching performance. During the drain-lag test, the device with our proposed GaN channel layer showed a reduction in trap effect.
GaN HEMTs is a promising device for high-voltage switching and high power amplifier (PA) in RF power applications due to its high breakdown voltage and high electron mobility. A lot of research has been carried out to reveal the mechanism of the trap effect [1-2]. However, in terms of GaN channel layer, the relationship between channel layer quality and drain lag has not yet been fully investigated. In this report, we applied a trap-reduced GaN channel to improve drain-lag performance.
We fabricated GaN HEMTs on a SiC substrate with a normal GaN channel layer (epi-A) and a quality controlled layer (epi-B). After we fabricated an Al-based metal as an ohmic electrode, we annealed it to form an ohmic contact. Both samples showed that specific on-resistance were about 5×10^-6 Omega;cm². SiN passivation film was deposited on the surface and the opening was formed for the Schottky contact area by dry etching. The Schottky electrode was Ni/Au. These devices were used to investigate drain-lag performance.
First, we evaluated the crystal quality by using X-ray diffraction (XRD). The value of the GaN channel tilt angle of epi-A and epi-B were 209 arcsec and 243 arcsec, respectively. The twist angle was also assessed by using XRD. However, from the results, there was no difference of the twist angle between epi-A and epi-B. Additionally, electron mobility and sheet resistance were almost the same value at RT.
Second, we measured devices whose gate periphery and width were 1.8 mm and 0.5 µm, respectively. To investigate the trap effect, drain-lag performance was evaluated and trapping time constant (tau;), which is the maximum value of δ(I_d)/δ(time) calculated from drain lag performance, was also measured. In the measurement, the time period was 10 msec, V_ds = 50 V and V_g were set for I_d to be 20 mA/mm. In the pinch-of state, V_gs = -3 V, V_ds = 100 V and time width was 100 mu;sec. We also surveyed the device with epi-A for comparison.
As a result, tau; were 6.4×10^-5 sec and 1.6×10^-5 sec for the devices with epi-A and epi-B, respectively. This result suggested that the GaN channel tilt angle influenced the drain-lag performance.
[1] A. R. Arehert, A. Sasikumar, G. D. Via, B. Winningham, B. Poling, E. Heller, and S. A. Ringel, IEDM10-465 20.1.1-20.1.4
[2] I. Rosetto, M. Meneghini, G. Meneghesso, E. Zanoni, Microelectronics Reliability 53 (2013) 1456-1460.

Silicon has the lowest cost among all suitable substrates for III-nitride crystal growth and the thermal conductivity of Si is large enough to make it competitive with other substrates for both high voltage and RF applications. Silicon substrates are available in diameters of beyond 300 mm although the substrate size available for nitride growth is limited by suitable deposition equipment and the requirement of (111) substrate orientation. Nitride-based structures grown on Si can be processed in well-established low-cost device fabrication lines and significant effort is underway worldwide to adopt Si-based processes to enable complete integration of GaN-on-Si wafers into these high volume foundries.
Despite the tremendous promise and progress in GaN-on-Si technology, challenges associated with epitaxial growth of large diameter wafers remain. In this work, we will summarize current status of GaN HEMT growth on (111) on-axis silicon substrates varying from 4 to 8 inch in diameter. All substrates used for this study were per SEMI standard thickness. The total thickness of the HEMT epilayers was in the range of 2 - 5 µm.
Detailed in-situ wafer curvature and temperature monitoring was performed to analyze evolution of the MOCVD growth process. The maximum wafer curvature during growth of identical HEMT structures decreased with increasing wafer diameter. For 8 inch substrates, the in-situ wafer curvature peaked at about 100 km^-1 of convex bow. The temperature of the wafer surface was measured in-situ using optical thermometry. Temperature deviated more significantly across 8 inch wafers as compared to 4 and 6 inch. Moreover, the temperature profile across 8 inch wafers changed from nearly flat at the beginning of the growth to convex (hotter at center and colder at edge) in the middle of the process, further to concave (colder at center and hotter at edge) at the end. The change of the temperature profile from convex to concave occurred when the wafer shape was slightly convex, illustrating the complexities associated with maintaining uniform layer thicknesses, doping concentrations, and other film properties in the presence of significant wafer bow.
Typically, as-grown wafers were slightly concave with the warp of less than 30 µm for thinner (~2mu;m) structures and less than 50 µm for thicker (~5mu;m) ones. Good crystal quality and electron transport properties were routinely obtained. Contactless Eddy-current mapping of 8 inch HEMT wafers produced sheet resistance in the range of 400 - 450 Ohm/sq with standard deviation of about 2%. Spreading resistance analysis of the nitride-silicon interface revealed modest to low parasitic conductivity with reasonable uniformity across the 8 inch diameter. Additionally, DC device characteristics from 8 inch HEMT wafers will be presented and discussed.

Gallium Nitride (GaN) is arguably the best suited semiconductor for the next generation of power transistors and diodes. Not only the combination of high critical electric field and excellent transport properties enables much better performance than Si-based power electronics, but also the momentum gained by this semiconductor family thanks to GaN-based solid state lighting and the early prototypes of GaN power devices will be difficult to match by any other material in the future.
This talk will summarize some of the work done by my group at MIT to improve the performance of GaN power transistors and diodes, as well as to benchmark the performance of GaN devices in power electronic circuits. Material growth, device technology and design, reliability, thermal dissipation and packaging, and final system-level application are all important issues that need to be carefully analyzed in order to get the maximum performance out of this amazing semiconductor.
We will also describe the recent progress to seamlessly integrate GaN power transistors and state-of-the-art Si control electronics on the same chip. This heterogeneous integration, which is being developed for 8" wafers, also allows for the integration of magnetic components in order to demonstrate fully integrated power circuits. In these circuits, the high switching frequency of GaN devices is key to minimize the real estate use by the power electronics and lower the cost of the entire integrated system. The proposed integration has important applications in future power management, advanced RF power electronics, and high temperature electronics.
Acknowledgements.- This work has been partially funded by the DARPA DAHI program, the DOE GIGA program, the ARPA-E ADEPT and SWITCHES programs, and the ONR PECASE program.

AlGaN based high-electron-mobility-transistors (HEMTs) grown on silicon are the focus of considerable research efforts, due to the availability of low-cost, large-diameter wafers and the potential for integration with Si-based technologies. However, epitaxy of GaNonSi is challenging compared to growth on sapphire or SiC because of eutectic Ga-Si reactions, and the larger mismatch in lattice constant and thermal expansion coefficient. The