Wide-bandgap materials are poised to revolutionize power electronics, offering higher efficiency, reliability, and output power in a broad range of energy conversion and RF power amplifier (PA) devices. Gallium nitride (GaN) is emerging as the wide bandgap material of choice for both industrial and defense applications but thermal impediments present a significant bottleneck to realization of the full potential enabled by the GaN material properties. Traditional “remote cooling” solutions, which rely on thermal conduction and spreading through low thermal conductivity substrates and across multiple interfaces, are incapable of limiting device junction temperature rise. Recent “embedded cooling” efforts, largely funded by Defense Advanced Research Projects Agency Microsystems Technology Office (DARPA-MTO), have focused on reduction of the near-junction thermal resistance through the use of diamond substrates and efficient removal of the dissipated power with convective and evaporative microfluidics.
This paper will first motivate the need for advanced thermal management in GaN PAs. Attention will then turn to the accomplishments of the DARPA Near-Junction Thermal Transport (NJTT) program, including the thermal and electrical characteristics of GaN epitaxial layers bonded to bulk diamond, GaN with directly grown polycrystalline diamond as a replacement for the native substrate, and GaN on a native substrate with diamond-filled vias. The paper will then turn to on-going research in the DARPA ICECool program, which further enhances the performance of GaN PAs through intra-chip microfluidic cooling and the thermal and electrical co-design necessary to design high power GaN PAs.

The III-Nitride material system has the potential to create a new generation of highly efficient compact power electronics. In this work we will describe our work towards understanding the device physics of metal-insulator-semiconductor III-Nitride transistors with enhancement mode operation. Fundamental properties of III-Nitride materials, such as polarization and doping, make it challenging to achieve enhancement mode devices with good performance. We will first present our work on AlGaN/GaN metal-insulator high electron mobility field effect transistors, focusing on our theoretical and experimental work to understand the effect of interface states on electrostatics[1], transport[2], and threshold voltage stability in such devices. We will discuss our demonstration of interface charge density engineering [3] leading to the demonstration of normally off transistors [4] with high current density. We will then show that high threshold voltage and efficient device performance can be simultaneously achieved using ultra wide band gap AlGaN as the channel material [5]. A calculation of theoretical figures of merit for such devices taking into account the effects of electron scattering in the channel and breakdown field [5] will be presented to compare resistance and switching losses in ultra wide band gap AlGaN devices with those in GaN. Finally, we will discuss our work on experimentally realizing device structures based on ultra wide band gap materials, and our approach to improving electron transport and contacts in such devices.
[1] Esposto M, et al, Appl. Phys. Lett. , 99, 133503 (2011).
[2] Hung, TH, et al, Appl. Phys. Lett. 102, 072105 (2013)
[3] Hung TH, et al, Appl. Phys. Lett. , 162104 (2011).
[4] Hung, TH, et al, IEEE Elec. Dev. Lett., 35 (3), 99. 312-314 (2014)
[5] Bajaj, S, et al, Appl. Phys. Lett. 105.26, 263503, (2014)

Application of AlGaN/GaN high electron mobility transistor (HEMT) to power controlling devices is highly expected. AlGaN/GaN HEMT has excellent features for managing large electrical power: high breakdown voltage, high electron mobility, low on-state resistance, low switching losses and high thermal conductivity. It is now generally recognized that two dimensional electron gas (2DEG) is one of the key factor which determine the electrical property of AlGaN/GaN HEMT. The polarization in AlGaN/GaN heterostructure plays important roles in forming 2DEG. Thus, 2DEG and polarization are crucial factors of evaluation.
Techniques for device evaluation are important for effective development of high performance device at low cost. Scanning nonlinear dielectric microscopy (SNDM)[1] is one of candidates of evaluation techniques for analyzing carrier distribution and polarization. SNDM measures the variation of capacitance between sample and conductive tip responding to the applied ac voltage and can detect carrier polarity, density, and polarity of polarization. SNDM has such high capacitance variation sensitivity of 10^minus;22 F that the detailed profile of carrier and polarization distribution can be measured.
2DEG is observed by measuring the variation of depletion layer thickness of Schottky contact formed between tip and sample. Moreover, polarization can be observed by measuring the variation of capacitance due to nonlinear dielectric response related to the nonlinear dielectric constant whose sign is determined from polarization polarity[1].
AlGaN, GaN, and buffer layer thicknesses of the sample were 30nm, 1.6mu;m, and 2.4mu;m, respectively. The Al composition ratio in AlGaN was 30%. These layers were epitaxially grown on Si substrate. AlGaN layer and GaN layer have their own spontaneous polarization Psp. In addition, the lattice mismatch between GaN layer and AlGaN layer causes piezo-induced polarization in AlGaN layer [2]. The acquired SNDM data showed the direction of AlGaN polarization and that of the GaN polarization were same and the magnitude of polarization of AlGaN was larger than that of GaN. At the GaN layer, the signal value near the AlGaN/GaN interface went down from minus;50 Hz/V to minus;300 Hz/V. The difference of these signal values 250 Hz/V was caused by 2DEG. The half width of the 2DEG profile was about 10 nm, which means that the range of signal influenced by 2DEG was 10 nm. When the tip is near 2DEG, an electric field arrive at 2DEG from the tip because there are no carriers that block electric field in undoped AlGaN layer and undoped GaN layer. It is reasonable to assume that the half width is slightly thicker than real 2DEG thickness. Thus, we concluded that SNDM has a useful tool for evaluating the 2DEG and polarization distribution in AlGaN/GaN heterostructure.
[1] Y. Cho, A. Kirihara, and T. Saeki: Rev. Sci. Instrum., vol. 67, p. 2297, 1996.
[2] O. Ambacher et al.: J. Appl. Phys., vol. 85, p. 3222, 1999.

The emergence of wide band gap semiconductor devices has pushed the boundaries of power converter operation. The devices enable the user to increase the switching frequency of power converters while maintaining high efficiency. Potential operation at higher temperatures allows the user to further reduce the size and weight of such conversion systems. The talk will attempt to present the state of the art in wide band gap devices, the challenges associated with designing with such devices and its adoption in power conversion equipment.

AlGaN/GaN HEMTs attract lots of attention for high frequency and power applications owing to high mobility of two-dimensional electron gas (2DEG). However, one important issue concerning these devices is the formation of ohmic contacts with low contact resistance. Since contact metal layers are usually deposited on an insulating AlGaN layer, beneath which a 2DEG is induced, current pathways need to be formed through the AlGaN layer. On the other hand, thinning the AlGaN layer leads to a decrease in 2DEG concentration induced by the large polarization in the AlGaN layer. These properties result in an inherent tradeoff involving the AlGaN layer thickness. Recently, we proposed a new technique to reduce contact resistance overcoming the inherent tradeoff, in which uneven AlGaN layer structures were intentionally introduced [1]. In this technique, fringing effects at the edges of lateral patterns of the uneven structure are expected to play an important role. In this study, effects of scaling down of various lateral patterns on reduction of contact resistances are discussed.
An AlGaN/GaN heterostructure grown on a Si(111) wafer for HEMT applications was used as a substrate. The thickness and composition of the AlGaN layer was 30 nm and Al_0.25Ga_0.75N. Contact resistances were evaluated by the TLM method. The uneven structures were formed by laterally partial etching of the AlGaN layer, in which thin AlGaN regions (5 nm in thickness) and thick AlGaN regions (30 nm in thickness) coexist with particular periodic lateral patterns. The thin AlGaN regions were formed by Cl₂/BCl₃/Ar RIE. The uneven structures were formed under contact metal layers composed of Mo/Al/Ti (35/60/15nm). The lateral patterns, such as parallel line/space stripe configurations or dot matrix configurations, whose feature size was from a few hundreds nm to 5 µm were formed by electron beam lithography or photo lithography. Finally, annealing was carried out in N₂ ambient.
In the case of flat AlGaN structures (not uneven structures), the lowest contact resistance was obtained at an AlGaN thickness of around 10 nm. For the uneven structures with stripe configuration parallel to current flow, contact resistances were much smaller than the reference value for the 10 nm thick flat AlGaN structure. In particular pattern size regions, the resistance was fond to be inversely proportional to pattern density per unit area, indicating fringing effects. In the case of the stripe with 700 nm width, the contact resistance was reduced to 30% of the reference. The mechanism of contact resistance reduction is discussed along with the effects of pattern configuration and pattern size.
[1] Y. Takei et al., Physica Status Solidi A, DOI 10.1002/pssa.201431645, (2015).

Graphene has received lot of attention in the last few years due to its extraordinary electrical, optical, mechanical and thermal properties, opening the gate for potential applications in electronic and optoelectronic devices. Hence it is important to investigate the properties of graphene/semiconductor interfaces in order to understand their nature and functionality.
In the present work, electrical properties of graphene/AlGaN/GaN systems have been investigated in the temperature range 80-300 K. AlGaN/GaN heterostructures grown on Si by metal organic chemical vapor deposition (MOCVD) are used for the present study. 2DEG is formed at the interface of 24 nm Al_0.25.GaN_0.75 barrier layer and 500 nm GaN layer. Low surface roughness (RMS=0.5 nm) revealed good surface quality of the heterostructures. Sheet resistance and 2DEG sheet carrier concentration are found to be 384 ohm/sq and 1.1 × 10¹³ cm^-2, respectively. Four layer Ti/Al/Ti/Au contacts pads deposited onto this structure using e-beam evaporation served as Ohmic contacts. Another pad of SiO₂/Cr/Au (50/5/50 nm) is sputtered for graphene transfer, as the contact from graphene is taken via Au. Single layer grapheme (SLG) is transferred in such a way that one side of graphene is in contact with AlGaN/GaN surface while other side is in contact with Au pad. Self-adaptive contacts are established between graphene-AlGaN/GaN and graphene-Au. Raman measurements are performed on selected graphene layers prior to its transfer. The intensity ratio of G and 2D peaks revealed the presence of single layer graphene (SLG). Rectifying nature of I-V characteristics at each temperature indicates that graphene act as Schottky contact on AlGaN/GaN. Due to difference in work function of graphene (4.6 eV) and electron affinity of Al_XGaN_1-X/GaN (2.7 eV for x=0.25), a Schottky contact with barrier height equal to 1.9 eV should be formed theoretically as predicted by the Schottky-Mott model. However, experimental values of SBHs are always lower than the predicted values due to existence of interface states, barrier inhomogeneities, and surface modifications during device processing. In the present case, ideality factor (#414;) and Schottky barrier height (SBH) are calculated at 300 K using thermionic emission theory and found to be equal to 1.7 and 0.70 eV, respectively. On lowering the temperature to 80 K, ideality factor increases to 4.5 while SBH decreases to 0.2 eV. The increase in ideality factor and decrease in SBH on lowering the temperatures are attributed to the existence of barrier inhomogeneities as well as presence of other current transport mechanisms apart from the thermionic emission process. This kind of study can potentially be useful for electronic and optoelectronic devices for energy efficiency applications.

Introduction: Since 1990s, increasing the energy bandgaps of semiconductor materials from ~1eV in Si and GaAs to ~3.4 eV in GaN and SiC has created new revolutionary applications arenas in high-speed and high-power RF electronics and in solid-state lighting and lasers. Much of the current device technologies exploit the large energy bandgaps of GaN and SiC. We present a few preliminary structures that exploit electronic polarization to exceed the conventional power electronics figures of merit and initial experimental demonstrations of the new physics in action.
Prior and current work: The strong spontaneous and piezoelectric polarization fields in III-nitride semiconductor heterostructures is central to the realization of Al(Ga)N/GaN high-electron mobility transistors (HEMTs) on Silicon, which is currently being intensively investigated for ~600 Volt power electronics. Looking beyond, a pertinent question is - can one exceed the breakdown voltage - on resistance limits of GaN by combining heterostructures with polarization? To that end, we have investigated several vertical heterostructures on bulk GaN substrates with very low dislocation densities to exploit polarization effects^1,2 to exceed conventional figures of merit of breakdown and on-resistance. The results achieved are highly revealing not just about the effects of polarization, but of bulk GaN itself. For example, p-n junctions with ideality factors close to unity are realized for the first time in GaN, and leakage currents at ~ nA/cm² levels are measured due to the exponential dependence of leakage currents on the energy bandgap. P-i-n diodes with breakdown voltages in the 1-2 kV range are realized, and non-destructive avalanche breakdown is observed. When the traditional impurity-doped p-n junction is replaced by polarization-induced doping using graded AlGaN, enhanced performance with fundamental changes in transport mechanism is observed. The impurity and polarization doped high-voltage devices have distinct spectral emission, which helps probe the high-field transport mechanisms in these power devices, something that is difficult in Silicon and SiC due to their indirect bandgaps.

Recently, power conversion systems in vehicles are of increasing importance with the development of hybrid or electric vehicles (HV/EVs). Higher efficiency in these systems will contribute to energy-saving society in future. Wide-bandgap semiconductors such as GaN are expected as material of new-generation power devices for HV/EVs. There are mainly two major classes of power conversion system in vehicles, such as high-power modules and medium-power modules. A boost converter which is connected to a high voltage battery and a 3-phase inverter for motor driving are classified as high-power modules. GaN vertical power devices are strong candidates for these modules. There are following requirements of performance of the devices in this module: the breakdown voltage of 1.2 kV, the current capability of more than 200 A per device and the specific on resistance of less than 2 m#8486;middot;cm² beyond the performance of Si-IGBTs. To satisfy these demands, large diameter of high-quality GaN wafer and low carrier concentration control by epitaxial growth are desired. Recently, quality of GaN substrate is improving and pn-diodes over 3kV breakdown voltage and MOSFETs over 1.5kV breakdown voltage have been reported. Lower carrier concentration than 1×10¹⁶ cm^-3 is also required for 1kV breakdown voltage. For this requirement, reduction of residual carbons in the epitaxial layer which compensate Si donors and deteriorate electron mobility is a large issue of MOCVD growth. Other issues to be solved still remain in the fabrication process of the GaN vertical device. On the other hand, down converters for a low voltage source and a charging system are classified as medium-power modules. High-frequency operation over several hundred kHz and high current density are required as performance of devices though desired breakdown voltage is lower than 600V. GaN lateral power devices are suitable for this category. AlGaN/GaN HFETs on Si substrates are the main stream of the GaN lateral devices. Normally-off operation and current collapse free operation are achieved and they are applied to inverters or converters in industrial systems. For automotive applications, reliability of the device is strongly required, which is under investigation now. At the meeting, the GaN vertical device for high-power modules and issues in the fabrication process will be presented mainly.

GaN-based N-channel (N-ch) devices, especially heterojunction field effect transistors (HFETs) utilizing 2D electron gas (2DEG), was demonstrated to have a merit of significant footprint reduction compere to that of Si-based lateral devices [1]. This property is useful for integrated circuit applications. In addition, P-channel (P-ch) HFETs using 2D hole gas (2DHG) are also needed to realize gate drive circuits, hence, to integrate power converter system on one GaN chip [2]. In previous work [3], N-ch and P-ch HFETs with normally-on operation were developed on one GaN chip. A problem was that normally-off operation of P-ch HFETs, desirable for the gate drive applications, was not realized so far. The normally-off operation was reported only for MESFETs [4], however, MOSFETs are desirable due to their low gate leakage. In this abstract, we report GaN-based P-ch MOSFETs for the first time.
The polarization-junction wafers with p-GaN/i-GaN/AlGaN/i-GaN structure grown on sapphire substrates were used for the fabrication. To realize them, we have developed polarization-junction wafers with a GaN/AlGaN/GaN double-hetero structure [5] grown on sapphire substrate. The upper GaN (000-1)/AlGaN (0001) and the bottom AlGaN (000-1)/GaN (0001) interface have negative and positive polarization charges, which automatically induce high-density 2DHG and 2DEG (~10¹³ cm^-2). The MOS gates were fabricated between source and drain electrodes by recess etching of the top p-GaN layer by RIE and the following deposition of SiO₂ by PECVD and gate electrodes of TiN/Ti by sputtering. Source and drain electrodes made of Au/Ni were formed to contact to the 2DHG. The devices with 30-nm-thick SiO₂ gate insulator, channel recess length of 10 µm and channel width of 100 mu;m were fabricated.
The fabricated MOSFETs exhibited negative threshold voltage (V_th) of -0.8 V, in which transconductance (g_m) of -0.2 mS/mm was obtained. The normally-off operations were observed on the P-ch MOSFETs probably due to positive fixed charge in SiO₂ and smaller work function of Ti than that of GaN. Furthermore, gate leakage current was reduced to less than 3.2×10^-4 mA/mm at ±5 V of gate voltage. These results indicate a potential of applications to power ICs made of GaN-based CMOS.
[1] N.-Q. Zhang et al., IEEE Electron Device Lett., vol.20, no. 9, pp. 421-423, 2000.
[2] T. Zimmermann et al., IEEE Electron Device Lett., vol. 25, no. 7, pp. 450-452, 2004.
[3] A. Nakajima et al., in Proc. ISPSD, pp.241-244, 2014.
[4] H. Hahn et al., IEEE Trans. Electron Dev., vol.60, no.10, pp.3005-3011, 2013.
[5] A. Nakajima et al., Appl. Phys. Express, vol. 3, no. 12, p. 121004, 2010.

In the last 2 decades, AlGaN/GaN based high electron mobility transistors (HEMTs) have emerged as one of the most promising technology platform for high power/high frequency applications due their superior material properties such as large bandgap energy, high breakdown electric field, high saturation drift velocity, excellent electron mobility and large sheet carrier concentrations. In addition to this, AlGaN/GaN heterostructures have excellent interface properties due to the presence of large polarization fields and conduction band offset which enable great performance of these devices. Despite these advantages, there exist several performance challenges which make these devices non-ideal power switches. In the ON-state, a commonly seen issue is the degradation of the saturation drain current and in the OFF-state, a major source of power loss is the subthreshold leakage current. To counter these issues, and to utilize the full potential of this technology, we have investigated the implementation of a device design technique which can dynamically mitigate the performance challenges during both ON and OFF states of the device operation. In this technique, the body terminal is connected to the GaN channel layer of the AlGaN/GaN HEMT structure to control the body potential of the device. A similar technique has been successfully implemented in silicon technology and is popularly known as “dynamic body bias technique". In CMOS technology, the device performance challenges which emerged with technology scaling, active/stand-by power losses, speed and reliability concerns were successfully addressed with the implementation of this technique.
In our work, we report the implementation of dynamic body bias technique in AlGaN/GaN HEMTs for the first time. The role of the body potential in controlling the performance characteristics of HEMTs is been experimentally and theoretically studied in both ON and OFF states of the device. The HEMT structure used for fabrication is epitaxially grown in our lab using metal organic chemical vapor deposition technique. To incorporate the body terminal, additional mask layers are added to the conventional HEMT design. The current - voltage characteristics of the fabricated HEMTs show modulation of the drain current with the change in the magnitude and polarity of the applied body bias. In the ON-state, application of negative body bias is shown to improve the saturation drain current and in the OFF-state, application of positive body bias is shown to improve the subthreshold drain-leakage current. The modulation in the drain current is attributed to the resultant conduction band and electric field profile across the GaN channel region with the applied body bias. We will further discuss a comprehensive study of the experimental results, mechanism involved and a physics-based modelling of the HEMT device with body bias using Synopsys Sentaurus TCAD.

A high-resistance (HR) buffer layer is critical for GaN-based HEMTs to suppress the drain current leakage. A typical method to obtain the HR buffer layers is the acceptor impurity doping that is able to compensate the background electrons in the buffer layers. However, the intentional acceptor impurity doping may result in current collapse in GaN-based HEMTs. To address this issue, we used the polarization doping method to achieve high resistance without introducing any acceptor impurity in the GaN-based buffer layer. The polarization doping is realized in aluminum-composition-graded AlGaN layer structures that can create holes by the polarization field. This polarization doping method paves a way for achieving HR buffer layer without impurities for high performance GaN-based HEMTs.
In this work, three samples of 3-mu;m-thick unintentionally doped (UD) GaN layers are deposited on c-plane sapphire substrates by MOCVD. One is left as a GaN buffer layer, named Sample A. On the other two GaN layers, 200-nm-thick UD AlGaN layers with Al composition grading from 0.04 to 0 and 0.08 to 0, respectively, are regrown, named Sample B and Sample C. The Al composition grading is realized through reducing the TMAl molar flow linearly, while the TMGa molar flow was increased linearly.
The mechanism of the polarization doping is explained as follows. For the Ga-face Al_x2Ga_1-x2N layer grown on Al_x1Ga_1-x1N layer (x₁>x₂), there is 2DHG at the interface due to different polarization charge in the two layers. Consequently, when the interface of the abrupt hetero-junction is instead of a layer with Al composition grading from x₁to x₂, 2DHG will spread to the whole graded layer, and form 3DHG. According to the non-linear formulas from Fiorentini, the concentration of the polarization-induced 3DHG is
ρ=4.169E13*Δx /d cm^-3 (1)
Where Δx =x₁-x₂, d is the thickness of the graded AlGaN layer. The Δx_Al of the Sample B is 4%, so the polarization-induced 3DHG density is 0.82E17/cm³. When Δx_Al is increased to 8%, for the Sample C, the concentration of the polarization-induced 3DHG is increased to 1.65E17/cm³. These 3DHG are expected to compensate the background electrons in the buffer layers.
The square resistance (Rsh) of the Sample A is 3.94×10³ Omega;/#9633;. While for the Sample B, the Rsh is remarkably enhanced to 1.23×10⁴ Omega;/#9633;, three times higher than the Rsh of the Sample A. We ascribe this improvement to the 3DHG induced by the polarization field in the graded AlGaN layer. Part of background electrons are compensated by the polarization-induced 3DHG, hence the resistance is increased. When the Al composition degree is further increased to 8% (Sample C), Rsh is further increased to 2.89×10⁴ Omega;/#9633;. The likely reason is that the concentration of the polarization-induced 3DHG is increased with the Al composition degree increasing, more background electrons are compensated.

Due to the wide bandgap and high electron mobility of gallium nitride (GaN), GaN-based high electron mobility transistors (HEMTs) are one of the most exciting technologies for radio-frequency (RF) and power electronics applications. However, the high power densities and high operating voltages of GaN HEMTs often lead to reliability concerns due to elevated channel temperatures and mechanical degradation. As suggested by modeling and experimental studies, the inverse piezoelectric (IPE) effect may induce stresses and strains in the device barrier and buffer that result in cracking and pit formation. Despite the importance of the inverse piezoelectric effect in the reliability of GaN HEMTs, there are only a few experimental studies in literature that report stress and strain measurements on devices under bias. In these previous studies, the application of an off-state bias positively shifted the E₂ high and negatively shifted the A₁ (LO) Raman peaks of GaN in the gate-drain region. However, varying assumptions about how the Raman peaks shifts are correlated to the stress and strain components resulted in inconsistent conclusions about the stress/strain state.
In this study, we determined the nature of the IPE stress/strain state in GaN HEMTs under bias with high precision micro-Raman spectroscopy, simple physical arguments, and electro-mechanical modeling. Micro-Raman spectroscopy measurements were conducted on GaN HEMTs with a confocal micro-Raman system (LabRAM HR800, Horiba Jobin-Yavon) capable of a spatial and spectral resolution as low as 1 µm and 0.02 cm^-1, respectively. Using the phonon deformation potentials to relate the change in Raman peak positions and strain results in overestimation of the normal strains (~10^-3) and corresponding electric field component along the z-axis (~1 MV/cm). Based on group theoretical arguments and first principles calculations in the literature for other III-V semiconductors, we believe that the high electric field in the GaN buffer could be negatively shifting the A₁ (LO) Raman peak apart from the inverse piezoelectric effect. Assuming a simple linear relationship between the change in A₁ (LO) peak position and the electric field due to this effect allows one to recover normal strains of ~10^-4 and an electric field of 0.3 MV/cm as expected for this device at a particular bias. This explanation yields strain values consistent with measurements of the E₂ high and E₂ low Raman peaks, which are not affected by the electric field apart from the inverse piezoelectric effect. We believe these results provide important physical insights into the inverse piezoelectric stress/strain state in GaN HEMTs under bias and provide a consistent explanation for some of the discrepancies in the literature. This will help to enrich our understanding of the use of the pinched-off state as a reference in micro-Raman thermography and to validate complex electro-mechanical models for reliability prediction.

AlGaN/GaN HEMTs are promising candidates for switching power transistors because of their high off-state breakdown strength combined with excellent channel conductivity at on-state. These features relate to the particular physical properties of GaN in combination with its heterostructure material AlGaN. GaN power switching transistors are known to outperform competing Si devices in terms of the static on-state resistance (R_on) at a given breakdown voltage by about two orders of magnitude. If the device are turned on the remaining on-state resistance R_on determines device losses to a large extend. Devices having low R_on values should therefor show better switching efficiencies. However, a low static on-state resistance is of practical interest only if this value is maintained also upon dynamic switching. Any increase of R_on significantly compromises power switching performance. In GaN devices the on-state resistance can deviate from its static (DC) value upon operating the devices in a dynamic mode. This effect is referred to as a “dynamic on-state resistance increase”. It is caused either by dynamic switching of the devices or by single event switching from one bias level to another, for example from an off-state bias condition to on-state. Physically, this effect can be interpreted as temporary charging of regions close to the device channel (trapping) during device operation at a certain bias level. If the bias level changes rapidly, these temporary charges cannot respond that fast and, due to the request for overall charge neutrality in the device, lead to a temporary change of the channel electron density. In consequence, electron transport in the channel region immediately after switching from one condition to another condition is impeded as long as the trap population is adjusting.
The dynamic on-state resistance (R_{on_dyn}) usually increases with operation voltage and can exceed its static value by more than two orders of magnitude. Recent investigations showed that the dynamic performance of GaN power switching devices has a quite complex dependency on device biasing and timing of switching events. These dependencies have now been analyzed in more detail and will be presented in this invited paper.
It has been found that operating the devices at off-state for longer time intervals may gradually increase internal charge trapping which in-turn increases dynamic on-state resistance immediately after the switching event. In contrast, device operation at on-state usually leads to de-trapping and to a reduction of adverse dynamic effects. Thus, during continuous switching an effective dynamic on-state resistance appears which relates to the superposition of off-state trapping and on-state de-trapping mechanisms.

For last two decade, different kind of device structures like AlGaN/GaN, AlGaN/GaN/AlGaN or AlGaN/InGaN/GaN are studied extensively to find out superior performance. Various reliability issues like current collapse, self-heating effect and converge electric field, are main obstacle in successful commercialization of these devices. AlGaN/InGaN/GaN HEMT has shown superior electron confinement and current collapse characteristics. But, no further study has been made so far to see the trapping effect in this structure. Here in this brief, we have shown that the AlGaN/InGaN/GaN is more immune to trapping effect owing to Fermi level elevation than conventional AlGaN/GaN structure. We found that the InGaN based structure is free from interface trapping effect, whereas the conventional single heterostructure suffers from two kinds of trap states with density ~ 10¹² .
AlGaN/GaN and AlGaN/InGaN/GaN structures are grown by Plasma assisted molecular beam epitaxy (PA-MBE). The conventional four probe Hall measurement has yielded 2DEG of 2.09x10¹³ cm^-2 for AlGaN/InGaN/GaN structure and that for single heterostructure is 5.62x10¹² cm^-2. The HRXRD scan of (002) plane shows the In content in InGaN layer is 2%.
The trap energy state at the interface and at the surface of structure can be analysed by conductance measurement in depletion region and accumulation region voltage biases respectively. The extracted values from measured conductance curve of AlGaN/InGaN/GaN does not show any interface trapping effect as the time constant is very large (>100 s). But, the AlGaN/GaN structure suffers from two kinds of trap energy levels in -3.2 V to -4.8 V in depletion region. The interface trapping effect elimination for AlGaN/InGaN/GaN is mainly found due to the Fermi level shift from the conduction band minimum which can be seen in conduction band diagram. The higher 2DEG in the interface elevates the Fermi position and hence the trap energy states become dipper. The same effect is also expected to reduce the surface trapping effect in AlGaN/InGaN/GaN compare to AlGaN/GaN. The extracted values of surface trap states from the accumulation conductance behaviour of AlGaN/InGaN/GaN are found to be (5.87-4.39) in -0.8 V - 0 V which is at least two order less than that of AlGaN/GaN structure.

Traps in AlGaN/GaN HEMT is one of the most researched area due to its severe effect on performance degradations of high power electronic devices like distortions, noise generations, current collapse etc. The trapping of electrons occurred in three regions of the devices mainly: surface, barrier (AlGaN) and bulk (GaN). Most of the literatures have tried to focus on the effect of interface traps on the device performance considering both AlGaN and GaN together. However, the AlGaN and GaN traps have contributed individually on two-dimensional electron gas (2DEG) confined in triangular potential well at the heterointerface. Linearity of a device is defined through modulation efficiency of 2DEG by gate bias at certain drain voltage. Suppression of third order Intermodulation Modulation Distortion (IMD-3) is necessary as it signifies the nonlinearity of the devices at microwave frequency. In this work, effect of both AlGaN and GaN traps has been studied in view of spectrum of IMD-3 for AlGaN/GaN HEMT on both Sapphire and Si (111) substrate for the first time. The results indicate effect of traps in GaN epilayer profoundly for HEMT on Si as compared HEMT on Sapphire substrates.
Al_0.3Ga_0.7N (20 nm)/GaN HEMT has been grown on Sapphire and Si(111) substrate by PAMBE. Drain current can be represented by power series expansion of gate bias by different gain factors (g_o,g1, g2.. ) for low frequencies. A two-tone source signal consisting of frequencies f₁ and f₂ produces third-order products at frequencies 2f₂-f₁ and 2f₁-f₂ which occurs adjacent to fundamental frequency f1 and f2. Amplification term describes the generated harmonics from IMD-3. The normalized indicates the generated IMD-3 for the device signifying its inherent non-linearity.
The CV characteristic provides information of the AlGaN and GaN barrier of the potential well by its accumulation and depletion regions respectively.Biasing range of the IMD3 spectrum has been determined considering the CV profile for both heterostructures. The normalized spectrum of IMD-3 delineates more distorted terms at depletion region with negative gate bias in case of HEMT on Si as compared to HEMT on Sapphire. Due to both high lattice and thermal expansion coefficient mismatch growth of GaN on Si, there is more effect of threading dislocations as compared to GaN on Sapphire. These dislocations cause for more traps and related distortion for HEMT on Si(111). Additionally, the 2DEG at the heterojunction is function of electron wave function in QW as per Schrodinger&’s equations. The wave functions generally penetrates more into comparatively low energy GaN epilayers than AlGaN. Therefore, effects of trapped electrons on confined 2DEG are more for GaN side of the triangular QW than AlGaN barrier. Spectrum of IMD-3 and CV profile confirmed more effects of trapped electron from GaN bulk side in case of GaN on Si than GaN on Sapphire.

The characteristic wide bandgap (3.4 to 6.1 eV), high saturation velocity and moderate mobility along with low sheet resistivity of polarization induced charge confinement in heterostructures ensure that even in non-vertical architecture, AlGaN/GaN HEMTs are prime contenders for energy conversion as well as amplification in power electronics sector. Hence, with the efforts in improving epitaxial quality of the device layers, considerable cause-and-effect studies are also being conducted to scrutiny the degradation mechanisms of these transistors.
On account of the non availability of native substrates, III-nitride heterostructures are grown on either SiC, or sapphire, or silicon. Now, though reliability studies of GaN HEMTs on SiC are relatively well documented, degradation modes of these same HEMTs fabricated on sapphire or silicon remains much less investigated and understood. Yet, considering the superior cost feasibility of devices fabricated on the latter, these voids need to be addressed for achieving mass commercial adaptation AlGaN/GaN HEMTs on non-native substrates.
In this study, we investigate the electrical degradation of GaN HEMTs on Si/sapphire, biased in the off-state (V_DS=0). Scribed groups of HEMTs are subjected to on-wafer step-stress where the gate voltage (V_GS) is continually decreased in -5V steps upto -100V or catastrophic device failure, with 300s holding time in each step. During the steps stresses, the temporal responses of gate, source, and drain current are continuously monitored whereas maximum drain current (I_DMAX at V_GS=1V, V_DS=8V), off-state gate current (V_G at V_GS=-6V, V_DS= 6V), and current collapse are measured after each step as a measure of degradation. To isolate the effects of apparent device degradation in the form of trapping from permanent degradation, stress recovery tests are also carried out with either UV assisted detrapping or evaluation of the said parameters at intervals of 6 or 24 hours. From the completely differing degradation patterns of off-state gate current and on-state drain current, the plausibility of assigning a ‘critical voltage of device degradation&’ is considered in detail. Finally, the influence of inverse piezoelectric effect induced strain relaxation on the observed degradation behaviour is analyzed from the epitaxial perspective.

Influence of the sub-bandgap defects were investigated using the spectroscopic photo current-voltage (IV), the depth-resolved ultra-violet (UV) spectroscopic photo current voltage (IV) (DR-UV-SPIV), and time-resolved photocurrent (TRPC) spectroscopy measurements. Investigating the defects in large area AlGaN/GaN HEMTs wafers is of great importance since they limit device performance due to undesirable effects including current collapses. For device fabrication, the AlGaN/GaN HEMT layers grown on the Si wafer via metal-organic chemical vapor deposition (MOCVD) were diced into individual pieces and two pieces were chosen from different locations of the AlGaN/HEMTs wafer. Semi-transparent Ni Schottky contacts were illuminated with a light from a Xenon lamp and photo IV measurements were performed. Spectroscopic photo IV measurements revealed the existence of sub-badgap defects as well as their nonhomogeneous distribution across the wafer. After confirming the presence of the defects, we discovered variations in the depth dependent distribution of electrically active defects across the wafer via DR-UV-SPIV measurement. It was found that while one sample had predominant defects close to the interface of the AlGaN/GaN HEMTs structure the other one had more defects deeper into the bulk. Finally, TRPC spectroscopy with variable-wavelength sub-bandgap light excitations was performed to understand the different origins of the defects. Even though two samples exhibited the same characteristics for wavelength-dependency on photocurrent generation, dissimilar TRPC spectra were observed for the samples. We have shown that TRPC spectroscopy can be utilized to differentiate the traps that originate for different reasons but display similar de-trapping energy. In conclusion, it was demonstrated that a combination of these three spectroscopic measurements can be a very useful diagnostic tool for the quick evaluation of the nature and distributions of surface defects in AlGaN/GaN HEMTs wafer.

Commercial GaN-based RF power amplifiers already offer greatly increased output power densities with respect to GaAs technology, reducing die size and circuit complexity. Further increasing the power density of GaN transistors will ultimately require new thermal management approaches in order to efficiently spread 10&’s of Watts of waste heat and ensure that transistor channel temperatures are kept within safe operating limits.
Since GaN devices are fabricated on foreign substrates, the close proximity of the substrate to the transistor channel (< 1 µm) offers the potential for a high thermal conductivity substrate to efficiently cool the channel. Given the importance of cooling through the substrate, SiC is currently the most commonly used substrate material for high power GaN devices, because SiC has a relatively high thermal conductivity (κ_SiC) of ~420 W/mK. SiC compares favorably with alternative substrate materials used in low cost applications, e.g. silicon which has a thermal conductivity (κ_Si) of 130 W/mK. However, at higher power dissipations (P_diss) the SiC substrate becomes a thermal bottleneck. Replacing the foreign substrate with diamond, the highest thermal conductivity material available (bulk CVD diamond has thermal conductivity (κ_dia) up to 2000 W/mK), is a highly attractive option for reducing the thermal resistance of GaN transistors - potentially increasing their power handling capability manifold.
This paper will review and summarize recent approaches to enhanced cooling solutions of GaN devices using diamond grown by microwave plasma enhanced CVD processes. The GaN to diamond integration methods discussed range from heat spreaders with a novel metal scheme that reduces semiconductor to diamond thermal resistance to our integrated GaN-on-Diamond platform. In all cases emphasis will be placed on measuring the thermal resistance and finding ways to minimize it. The paper will also discuss recent progress in the use of micro-channels to dissipate 10 kw/cm^2 heat flux.

Diamond has a relatively wide bandgap but it can be made into a semiconductor, or even a metal, by doping it with impurity atoms. Semiconducting diamond layers, grown epitaxially on diamond substrates, have outstanding electrical and thermal properties in view of high power applications. Diamond high power devices are now being intensively investigated. In particular, Schottky diodes based on a metal/diamond junction appear very promising.
Zr metal deposited on oxygen terminated p-type boron doped diamond has been demonstrated to be a Schottky contact. This interface allows us to fabricate pseudo-vertical Schottky diode having large current density in forward regime (1000 A/cm² at 6V) and high breakdown voltage in reverse regime (larger than 1000 V). We have also investigated the reverse current induced by low barrier height and doping level due to thermionic emission (TE) and thermionic-field emission (TFE), taken into account the barrier lowering (BL). These two mechanisms can induce a high leakage current in the reverse regime which are also voltage-dependent. Consequently, for practical application, a fine trade off on the barrier height, doping level, contact size values must be found in order to obtain a low specific resistance in ON state and a low reverse current in OFF state, while keeping high breakdown voltage. Thermal effects are also very important for power devices and joint measurement of temperature,voltage current in order to observe thermal runaway and its effect on devices performance have been also investigated. Based on the analysis of the experimental data measured on annealed Schottky contacts, optimal structure (doping, thickness and diode geometry) will be proposed in order to fabrication high performance Schottky diodes based on Zr/p-doped diamond interface with taking into account thermal limitation.

Gallium nitride (GaN) high electron mobility transistors (HEMTs) have gained significant interest over the last few years for their excellent electrical properties, high efficiencies, and high power densities for both power electronics and radio-frequency applications. However, these high power densities result in high channel temperatures and temperature gradients that induce thermo-elastic stresses and the formation of defect sites and may accelerate many other degradation mechanisms. The highly localized temperature profile in a GaN HEMT peaks over a narrow region (~0.5 to 1 µm) in which the heat flux is very high (~10¹⁰ W/m²) near the edge of the gate contact towards the drain. Thus, it is extremely challenging to measure the peak channel temperature in GaN HEMTs due to the small length scales involved and the close proximity of semiconducting layers and metal contacts. Many thermal metrology techniques, such as infrared thermography and even micro-Raman spectroscopy, are limited in their ability to measure the peak channel temperature because of a diffraction-limited lateral spatial resolution or depth-averaging throughout the GaN buffer.
In this study, we have developed a robust technique for measuring the channel temperature of GaN HEMTs with sub-500 nm lateral spatial resolution under various input powers that can significantly affect the performance of GaN-based devices. To obtain a comprehensive understanding of thermal management in GaN devices, we have utilized thermoreflectance thermography, a well-established technique that is fully optical and noncontact and has several advantages over the currently available high resolution techniques: it provides a thermal map of the device, and it also provides surface measurements, which is crucial due to the unique geometries of transistors. We have focused on the temperature measurement at the interface of AlGaN/GaN interface adjacent to the gate where power densities are significantly high. By choosing the appropriate illumination wavelength, we have been able to measure the junction temperature with a spatial resolution of 300 nm for gated and ungated GaN HEMTs on different substrates. These devices were biased at voltages ranging from 0 to 25 V. To validate the temperature measurements obtained from thermoreflectance thermography, we have utilized micro-Raman thermography with a spatial and temperature resolutions of ~3 µm and 5 °C, respectively. A good agreement was achieved between temperature profiles from both techniques on transmission line method (TLM) pads on GaN-on-GaN devices. In addition, the effect of drain and gate voltage on the electroluminescence (EL) intensity in gated GaN HEMTs were investigated. This work helps to better understand the structural and thermal changes in GaN HEMTs, the formation of defect cites, and their relation to temperature through high-resolution thermal imaging.

The surface transfer doping process allows for diamond to be used as an active semiconductor for the production of diamond based electronic devices and components. The lack of stability of this doping mechanism due to its typical reliance on environmental operating conditions however has limited its practical application in diamond device technology. A particular focus for this technology is the development of high power, high frequency transistors [1] which are required to operate in "hostile" or "extreme" environments. Development of a temperature stable and operating-atmosphere independent doping mechanism for diamond is therefore of significant interest.
Recent work has identified MoO₃ as a potential surface acceptor material that when used to encapsulate the hydrogen-terminated diamond surface dramatically improves both the doping efficiency and stability [2]. Optimisation of the processes used to integrate this material into diamond electronics technology however must be developed to maximise potential benefits to performance.
In this work we discuss the latest developments utilising MoO₃ for the doping of H-diamond, including time and temperature dependent stability trials and the potential to integrate these new doping processes into diamond electronic devices such as field effect transistors.
[1] Stephen A. O. Russell et al,IEEE Electron Device Letters, Vol. 33, No. 10, October. 2012 p. 1471 - 1473
[2] Stephen A. O. Russell et al, Applied Physics Letters, Volume 103, Issue 22, 202112, November 2013

Power devices made of diamond have remarkable potentials based on the highest breakdown field and thermal conductivity. We have reported high-blocking voltage planar diamond MOSFETs [1-3]. The surface of channels in our devices are covered with C-H bonds. A thermally stable Al₂O₃ passivation film was used as gate insulator inducing the additional conduction layer beneath the diamond surface. The planar FETs have well controlled the source-drain current. To obtain the higher current density, however, it is inevitable to form vertical-shaped devices to avoid large planar drift area. In this study, we fabricated the test structure for the vertical diamond power FET by forming the trenches in the source-drain channels to estimate the conduction of C-H diamond sidewall.
In this study, the MOSFETs were built on C-H diamond surface by using atomic layer deposition (ALD), as a passivation layer and a gate insulator sheet, which produce and control two-dimensional hole gas (2DHG), GaN-HEMT is known as FET applying two-dimensional electron gas (2DEG) on its interface. In case of vertical structure, however, 2DEG is not formed on the sidewall of GaN because the 2DEG appears on a special surface having spontaneous and piezo polarization. In this point, the 2DHG on C-H diamond covered by Al₂O₃ can be formed on the sidewall easily regardless of crystal orientation. That is why diamond trench-channel vertical MOSFET with 2DHG is superior to AlGaN/GaN devices.
In this paper, we have fabricated a vertical-shaped diamond MOSFET. The process is almost same to that of planer FETs which we have reported. At first, the un-doped layer is grown about 2 um on P+ diamond substrate (single crystalline diamond doped with boron concentration of 1x10¹⁹cm^-3). This substrate has high p-type conductivity so that the hole current is able to run through the substrate. Second, the homo epitaxial layer was etched to the bottom to form a trench by using inductively coupled plasma ion etching (ICP-RIE), and regrown the un-doped layer by CVD to form 2DHG on the sidewall of trench. The un-doped layer must be re-grown after trench structure is fabricated by plasma etching to get damage free side wall conduction. We covered inside the trench. Ti/Au were put as a source electrode on the surface and as a drain at the bottom, Al as a gate and Al₂O₃ used ALD as a gate insulator sheet. The hole current run from the source electrode and is controlled by the trench gate on the sidewall and inside the P+ substrate. They suggest that 2DHG at side wall is available as a FET channel with trench gate. We have confirmed that side wall FET can modulated hole current as well as planar FET.
This study was supported by Grant in Aid for Fundamental Research S of JSPS.
References
[1] A. Daicho, H. Kawarada, et al., J. Appl. Phys. 115, 223711 (2014)
[2] H. Kawarada, et al., Appl. Phys. Lett. 105, 013510 (2014)
[3] H. Kawarada et al. IEDM 2014 11.02 (2014)

Diamond has strong potential as a semiconductor material for high power electronics due to its material properties including high thermal conductivity, high electric field breakdown strength, and high carrier mobilities. In this paper we will report on our work to produce vertical diamond diodes with characteristics that include a reverse bias breakdown voltage exceeding 1000 V and a forward current exceeding 10 A. Two diode architectures are being studied including a Schottky vertical diode and a merged Schottky/pn-junction vertical diode. The Schottky diode consists of an ohmic contact, thick heavily-doped p-type layer, lightly-doped drift p-type layer and a metal Schottky contact. The merged Schottky/pn-junction diode has localized heavily-doped n-type regions in the drift layer in contact with the Schottky metal contact. The lightly-doped p-type layer and heavily-doped p-type layer are deposited in microwave plasma-assisted CVD reactors using boron as the dopant. The n-type diamond is deposited using phosphorus as the dopant.
Diodes have been fabricated with both small Schottky contact areas of 150 micrometer diameter and larger Schottky contact areas of 1 mm X 2 mm. Diodes with the smaller contacts have been fabricated with breakdown voltages of 1000V and forward current flow densities of 500 A/cm². Diodes with the larger contacts have been fabricated with current flow up to 18 A and current density of 900 A/cm². Arrays of the smaller contact area diodes have been fabricated across single crystal diamond substrates to study the spatial variation in the diode characteristics and correlate these variations to defects in the diamond. Diode characteristics are measured from 300-600 K and comparisons are made to device simulations using the MEDICI semiconductor device simulator. This paper will also discuss diamond power electronics in comparison to other wide bandgap semiconductor materials.
This work is supported by US Department of Energy: ARPA-E SWITCHES program.

With its wide bandgap (5.45eV) and high breakdown field (5.6MV/cm) diamond presents itself as an ideal candidate for power electronics. As p-type material is readily achieved through boron doping recent advances in phosphorus doping established a suitable process for the preparation of n-type diamond. Furthermore, economical availability of single crystal (100) diamond substrates provides a cornerstone for diamond power devices. We report on the preparation and characterization of a high current density p-i-n diode synthesized by plasma enhanced chemical vapor deposition on a (100) type IIa CVD diamond substrate. A wet-chemical cleaning process was utilized to prepare the p-type boron doped diamond layer for successive intrinsic diamond deposition where a pure hydrogen plasma exposure initiated the intrinsic diamond deposition. Phosphorus doped diamond was deposited on the i-layer using a 200ppm trimethylphosphine/hydrogen gas mixture (10sccm) under the addition of methane (2sccm) and hydrogen (388sccm). With a microwave power of 2500W and a chamber pressure of 80Torr a pyrometer recorded a temperature of about 900°C. In a final deposition step growth parameter adjustments established a temperature >1000°C to realize a highly doped contact layer. The experimental growth configuration exploited plasma focusing effects to enhance dopant incorporation. Employing a SiO₂ hardmask reactive ion etching was used to expose the p-layer. Electrical contacts comprised of Ti/Pt/Au/Ni and Ti/Pt/Au to the n and p-layer, respectively, were patterned using standard bi-layer photolithography. Electrical characterization at room temperature demonstrated a repeatable forward current density >500A/cm². This was attributed to the low contact resistance of 1.6 Omega;.mm at the n-type diamond layer. Due to a reduced i-layer thickness and moderate impurity incorporation a breakdown field of 1.25MV/cm was observed. Device performance will be discussed in terms of material preparation and corresponding material properties.
This research was funded by the Advanced Research Projects Agency - Energy (arpa-e).

Due to the exceptional thermal conductivity of diamond, GaN devices fabricated on diamond substrates are gaining more interest due to diamond&’s ability to extract heat very efficiently, compared to those fabricated on Si, sapphire or SiC substrates. Great progress has been made on the development of the conventional GaN-on-Diamond HEMT since the first demonstration in 2005 [1]. In this technology, GaN-on-Diamond wafers are prepared from epitaxial GaN-on-Si wafers. During the preparation, the host Si substrate and the growth-defect-containing transition layers are removed and a polycrystalline diamond layer is grown at high temperature on the GaN layer [2]. With this diamond growth approach, Tyhach, et al. reported an RF output power density of 5.9W/mm with 50% power added efficiency (PAE) at 10GHz operating CW at a V_DS of 28V [3]. Dumka, et al. also demonstrated a GaN-on-Diamond HEMT with an output power density of 7.9W/mm and PAE of 46% when operated at 10GHz, 40V V_DS [4].
In this paper, we describe a new GaN-on-Diamond device approach involving the lifting off an industry-standard GaN-on-SiC HEMT from the host SiC substrate and transfer onto a polycrystalline CVD diamond substrate through a low-temperature bonding technology. This innovative approach allows the placement of very high thermal conductivity diamond within 1µm of the hot spot in a high-performance high-power GaN HEMT. The thermal resistance of the GaN-on-Diamond device is significantly reduced when compared to that of a GaN-on-SiC HEMT, allowing a smaller gate pitch in the device channel to provide higher power capability (i.e., RF output power per active area of the device) without impacting device junction temperature and reliability. Device drain current reached a record 1.2A/mm with transconductance of 390mS/mm. Measured maximum microwave power density was 11.0W/mm CW at 10GHz with a PAE of 51%, representing the highest microwave power density from a GaN-on-diamond transistor reported to date. Thermal measurements and analysis were also performed on the GaN-on-diamond HEMTs. Based on IR imaging and drain current transient results, the GaN-on-diamond HEMT is demonstrated to possess 3.6 times higher power capability than the industry-standard GaN-on-SiC device. The measured results - consistent with the device electrical and thermal analysis - clearly demonstrate GaN-on-diamond HEMTs fabricated by low-temperature device-transfer technology exhibit superior electrical and thermal performance than the standard GaN-on-SiC HEMTs.
This work was supported by DARPA NJTT program under the guidance of Drs. A. Bar-Cohen, J. Maurer, A. Kane and J. Felbinger.
1. G. Jessen, IEEE Compound Semicond. Integr. Circuit Symp., San Antonio, TX, 2006, p. 271.
2. F. Ejeckam, Lester Eastman Conf., Cornell University, Ithaca, NY, 2014, p. 1.
3. M. Tyhach, Lester Eastman Conf., Cornell University, Ithaca, NY, 2014, p. 6.
4. D. Dumka, Lester Eastman Conf., Cornell University, Ithaca, NY, 2014.

Wide band gap semiconductor, SiC, GaN and Diamond, are expected to next generation power device applications. Especially, diamond has wide band gap energy (5.5 eV), high thermal conductivity (20 W/cm#12539;K) and high breakdown field (10 MV/cm). It&’s important for power MOSFETs to rise breakdown voltage. We fabricated MOSFETs using the hole accumulation layer (2DHG) induced by coating the hydrogen-terminated (C-H) diamond surface with Al₂O₃ insulator by high temperature ALD method. We have reported 1 kV breakdown voltage characteristics [1] and 10 K~673 K operations [2].
In this paper, we fabricated hydrogen-terminated (C-H) diamond MOSFETs using Al₂O₃ insulator by high temperature ALD method. C-H MOSFETs showed over breakdown voltage of 1.6 kV at room temperature and 1.5 kV at 200#8451;. In addition, the highest breakdown voltage of 1.7 kV and high current density (over 190 mA/mm) has been obtained with thicker Al₂O₃ (400nm) on channel and drift region.
C-H diamond MOSFETs was prepared in the following method. First, undoped layer was deposited on 1b (001) diamond substrate by chemical vapor deposition (CVD) and Ti/Au (30 nm/100 nm) were deposited as source and drain electrode. Second, the diamond surface was hydrogen-terminated by remote plasma and isolation by O-terminated. Third, Al₂O₃ film as insulator and passivation were deposited by high-temperature ALD method (Oxidation; H₂O, Temperature; 450#8451;). Fourth, Al₂O₃ on the channel region etched by NMD-3 to make thicker oxide structure and the second Al₂O₃ film was deposited. Finally, Al was deposited as gate electrode.
Nearly 1 kV breakdown voltage V_B was achieved at L_GD of 9 µm and the average electric field strength (V_B/ L_GD) were 1 MV/cm. The highest breakdown voltage of 1646 V was obtained at L_GD of 22 µm. Moreover the average electric field strength reached 3.7 MV/cm at L_GD of 1 µm. It&’s over SiC and GaN properties limit.
Higher temperature (@200#8451;) off stage showed similar high breakdown voltage as that of room temperature. It exceeded the maximum breakdown voltage of diamond FETs at high temperature. The maximum current drain density was 82.0 mA/mm is also as high. Low off current (10^-11 ~ 10^-6 A) was maintained even at 200#8451; until breakdown.
Thicker oxide structure with 400nm Al₂O₃ layer has been introduced in the present C-H diamond MOSFET. This device showed the highest breakdown voltage 1708 V. The length of device were L_GD = 16 µm. 1708 V was the highest breakdown voltage of diamond FETs ever reported. The V_B/ L_GD tendency could keep 1 MV/cm up to 1700V. The maximum current drain density was 97.2 mA/mm comparable to lateral SiC or AlGaN/GaN device.
[1] H. Kawarada et al. IEEE IEDM 2014 11.02 (San Francisco, 2014).
[2] H. Kawarada, et al., Appl. Phys. Lett. 105 (2014) 013510.

β-Ga₂O₃ is an attractive material for deep ultraviolet sensors and next-generation power device applications due to its large band gap energy of 4.5-4.8 eV [1]. It is advantageous in comparison with SiC and III-nitrides that single crystal substrates with large-diameter and high quality can be fabricated by melt growth. Recently, our group has thermodynamically analyzed the HVPE growth of Ga₂O₃ and determined that the use of gallium chloride (GaCl) and oxygen (O₂) precursors together with an inert carrier gas is suitable for Ga₂O₃ growth by HVPE [2]. Actually, high-speed growth of high-purity β-Ga₂O₃ layers with low effective donor concentration (N_d - N_a < 10¹³ cm^-3) has been achieved by HVPE, which was fabricated on the basis of thermodynamic analysis [3]. These results indicated the possibility to control the carrier concentration of β-Ga₂O₃ above 10¹³ cm^-3 by the use of various doping techniques. In this study, we report homoepitaxial n-type β-Ga₂O₃ thick layer growth by HVPE using tetrachlorosilane (SiCl₄) as a dopant material.
Si-doped β-Ga₂O₃ thick layers were grown on semi-insulating (001) β-Ga₂O₃ substrates by HVPE using GaCl and O₂ precursors, and SiCl₄ dopant gas with N₂ carrier gas. GaCl was generated in the upstream region of the reactor by the reaction between high-purity Ga metal and chlorine (Cl₂) gas at 8500C. A GaCl partial pressure of 5.0x10^-4 or 1.0x10^-3 atm was used with a fixed input VI/III ratio (2O₂/GaCl) of 10. The SiCl₄ supply during the growth was varied by using the input partial pressure ratio (R_Si) of SiCl₄ to GaCl (R_Si=P^o_SiCl4/(P^o_SiCl4+P^o_GaCl)) as an index. The growth rates of the Ga₂O₃ epitaxial layers were 5 - 10 mu;m/h depending on P^o_GaCl.
It was revealed that the electron concentration of β-Ga₂O₃ homoepitaxial layer was almost the same as the Si concentration measured by SIMS, and linearly increased from the orders of 10¹⁵ to 10¹⁸ cm^-3 by increasing the R_Si, while the Hall mobility at room temperature decreased from 150 to 90 cm²/Vs. Thus, a precise control of n-type conductivity of the β-Ga₂O₃ layer is possible by the change of R_Si. The Ga₂O₃ vertical Schottky barrier diodes (SBDs) using the epitaxial wafers with Si-doped n^minus;-Ga₂O₃ drift layers grown on n⁺-Ga₂O₃ (001) substrates by HVPE [4] will be also shown.
Acknowledgment
Part of this work was supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: NEDO).
[1] M. Higashiwaki et al., Appl. Phys. Lett. 100 (2012) 013504.
[2] K. Nomura et al., J. Cryst. Growth 405 (2014) 19.
[3] H. Murakami et al., Appl. Phys. Express 8 (2015) 015503.
[4] K. Sasaki et al., 2015 Int. Conf. Solid State Devices and Materials.

In this study, we present the results on the room-temperature (RT) epitaxial solid-phase crystallization of a β-Ga₂O₃ thin film, which was obtained by pulsed laser annealing of an amorphous Ga₂O₃ thin film on NiO-buffered α-Al₂O₃ (0001) substrates. The β-type Ga₂O₃ is a wide band gap, and deep-UV transparent semiconductor with an E_g of 4.9 eV; β-type Ga₂O₃ crystalline thin film is a promising material for a wide variety of UV optoelectronic applications and future high-power devices. Until now, crystalline β-Ga₂O₃ thin films have been prepared by pulsed laser deposition (PLD), metal-organic vapor phase epitaxy, molecular beam epitaxy, sputtering, and other relatively high-temperature (>4000C) processes. On the other hand, further smooth surfaces and interfaces as well as the good crystallinity and high-orientation would advance the device applications of these functional thin films. In this view point, lower temperature material processing would suppress the mutual interdiffusion of the elements and thermal surface roughening. However, there are few reports on RT fabrication techniques for Ga₂O₃ crystalline thin films. We have previously reported about RT oriented carystallization of Ga₂O₃ thin films by the combination of pulsed laser deposition (PLD) and KrF excimer laser annealing (ELA) [1]. In this study, epitaxial crystallization of β-Ga₂O₃ thin films was obtained by RT ELA of amorphous Ga₂O₃ thin films grown on epitaxial NiO buffer layer also prepared at RT. An epitaxial NiO (111) buffer layer with a thickness of ~2 nm was grown on α-Al₂O₃ (0001) substrates at RT by the PLD using a focused KrF excimer laser (~1.5 J/cm²) and a sintered NiO target. An amorphous Ga₂O₃ thin film was subsequently grown on the NiO buffered substrate at the same deposition condition using a sintered target of β-Ga₂O₃. After deposition of the layer and film, the KrF excimer laser (250 mJ/cm²) was irradiated on the amorphous thin film in air at RT. The results of x-ray diffraction measurements indicated that epitaxial β-Ga₂O₃ (-201) thin films were obtained after ELA at RT owing to the epitaxial NiO buffer. The optical bandgaps of the crystalline thin films was determined as 4.9 eV from the UV/Vis transmittance. The film after laser annealing revealed the ultra-flat surface that the root mean square roughness was 1.9 Å. Furthermore, the influence of the laser intensity, annealing time and the film thickness on crystallinity, surface morphology and optical property of Ga₂O₃ thin films were investigated to discuss the mechanisms of the present excimer laser crystallization at RT.
[1] D. Shiojiri et al., Journal of Crystal Growth 424, 38 (2015).

Gallium oxide has the potential for application in wide band gap power electronics potentially transforming the optoelectonic and power electronic markets. This requires a more complete knowledge about the nature and importance of defects, dopants and processing before gallium oxide based technologies can reach the market. This work investigates the impacts of tin doping on the electrical properties of pulsed laser deposited Ga2O3 thin films. The films were deposited from a 2% Sn doped Ga2O3 target onto (0001) sapphire substrates from 350-550 °C. The conductivity and transparency were found to be dependent on the processing temperature, with films processed below 450 °C exhibiting decreased transparency and increased conductivity. There was a corresponding change in the oxidation state of