In most advanced integrated circuits, more than ten levels of interconnect lines are used to connect transistors through copper lines insulated by low dielectric constant materials (porous SiCOH). The integration of copper/porous SiCOH in interconnects is one of the key points for devices performance, process manufacturability and future scalability. Building interconnects requires the patterning of damascene structures into the porous SiCOH. The most important difficulties in porous SiCOH patterning by plasma are the profile control and the plasma-induced damages. We will first address the profile control of sub-100 nm trenches (CD control and profile distortion) by comparing the two main industrial masking strategies (metallic versus organic masks). We will mainly address the porous SiCOH damages induced by the plasma processes in terms of material modification, post-etch residues and surface roughness. The plasma damages is characterized on the bottom and sidewalls of the porous SiCOH patterns thanks to conventional characterization techniques (spectroscopic ellipsometry, infrared spectroscopy, X-ray photoelectron spectroscopy,..) and also advanced characterization techniques (ellipsometric porosimetry, scatterometric porosimetry,..). The plasma damages will be discussed in terms of plasma-surface interaction and damages mechanisms. The plasma process optimization and potential technological solutions to minimize plasma damages will be also presented.

Interpretation of a helium ion microscope (HIM) secondary electron (SE) mode imaging has not been well understood, while the HIM has spread as our cutting-edge measurement tool (1),(2). During the imaging, even at the very low helium ion dose or current, surfaces of the samples were atomically etched off, which phenomenon has been applied to a single layer graphene film patterning (3) for example, and blistering and physical etching occurred with the increase of the helium ion dose. This makes the interpretation of the HIM SE imaging difficult. An Al-Si-Cu film surface was imaged by the HIM SE at 30 kV with an ion beam dwell time of 200, 100, and 50 u sec, respectively. In the case of 200 u sec. dwell time, the Al alloy film received 4 times larger dose of helium ions of 50 u sec. dwell time. With the longer dwell time, several regions of darker contrasts were seen in the Al alloy surface. The different contrasts were probably caused by local generation of very thin modified regions underneath the surface by the helium ion irradiation which decreased the SE generations from the regions. This phenomenon was applicable to image damaged low-k areas in Cu/low-k structures. The HIM SE cross sectional imaging of a 140 nm pitch Cu/low-k structure was performed. At an optimized helium ion beam condition, areas of 10 nm thick at the side walls of the low-k regions adjacent to Cu interconnects were clearly seen with darker contrast than center of the low-k regions between the Cu interconnects. On the other hand, using a secondary electron microscope (SEM), no different contrast in the low-k regions was seen. Damage distribution in the low-k regions was characterized by a TEM/valence EELS method (4), and the darker contrast areas imaged by the HIM SE was quite similar to the damaged areas. It indicated that SE generation is affected by sample surface conditions with or w/o damages, and HIM SE can image the damages in the low-k regions with strong contrast which is a ratio of the SE generation from the nm-order areas with or w/o damages. (References) (1) J. Morgan, J. Notte, R. Hill, B. Ward: An Introduction to the Helium Ion Microscope, Microscopy Today 16 No.4, p.24 (2006), (2) S. Ogawa, W. Thompson, L. Stern, L. Scipioi, J. Notte, L. Farkas, and L. Barriss, Jpn. J. Appl. Phys., 49 04DB12 (2010), (3) M.C. Lemme, D.C. Bell, J. R. Williams, L. A. Stern, B.W. H. Baugher, P. Jarillo-Herrero, and C.M. Marcus, Proc. ACS Nano, 3 (9), p 2674 (2009), (4) Y. Otsuka, Y. Shimizu, N. Kawasaki, S. Ogawa, and I. Tanaka, Jpn. J. Appl. Phys., 49 11501 (2010)

Enabling porous SiCOH (pSiCOH) low-k materials in BEOL requires the ability to mitigate processing effects that degrade the integrity of the films. While post-deposition film properties may initially look promising, showing low permittivity and high modulus, the damaging effects of film patterning have been reported to result in critical dimensions (CD) loss, increase of the dielectric constant, reduced breakdown voltage and dielectric flopover. These issues are believed to result from structural changes in the films due to carbon lost during etching and ashing processes. Subsequent moisture uptake further increases the dielectric constant by adding polarizable Si-OH bonds to the film. This paper will discuss repair chemistries designed to enhance reactivity with damaged pSiCOH films. To effectively gauge the extent of repair, we look specifically at the repaired films resistance to wet-etching in dilute hydrofluoric acid (HF) solution. Using a stepwise HF exposure method, we uncover the ability of a chemistry to diffuse and react in the sub-surface film region, and provide effective protection from HF attack. This method provides a more sensitive indication of film repair that may not be easily indicated by other methods such as element profiles. Additional metrics were used as well such as dielectric constant restoration, hydrophobicity and element profiles. Different classes of chemicals were studied and ligand choice refinements used to optimize the repair properties. By considering the ability of tested molecules to restore both surface and bulk film properties, we found a new class of reactive chemistries that can be considered as successful candidates for post-patterning film repair. The physical properties of the best performing molecules were also studied as a means to confirm their suitability for elevated temperatures wafer processing.

For the 45 nm technology node and beyond, the introduction of new classes of materials for ultralow-κ interlayer dielectrics (ILD) and high-κ/metal gate (HKMG) stacks necessitates that semiconductor-processing steps such as photoresist strip must be compatible with these materials. Another major challenge for the advanced-device fabrication is to achieve high photoresist ash rates while minimizing the loss of materials such as silicon substrate and its nitride. In this work, we showed that downstream hydrogen-based plasma processing is compatible with ultralow-κ ILD and HKMG stacks, and found that it has potential in achieving high photoresist ash rates and low material etch rates. To demonstrate the latter, films of photoresist, Si, and Si3N4 were exposed to downstream pure-hydrogen plasma, and their etch rates were characterized by ellipsometry as a function of the following parameters: substrate temperature, reactor pressure, hydrogen flow rate, and source power. We also discussed the fundamental reaction mechanisms for photoresist strip and Si-etch under hydrogen plasma and addressed how they relate to the etch data obtained. The fact that we are able to reconcile the reaction mechanisms with the process trends not only suggests that our data are valid and accurate, but it also deepens our understanding of the hydrogen-plasma process. We found that hydrogen-based photoresist strip and Si3N4 etch are both thermally-activated reactions with activation energies of ~ 5.2 and 2.7 kCal/mol, respectively. Si substrate exhibits a rather unique thermal behavior where the etch rate increases initially to a maximum, which occurs at ~ 40°C, and then decreases upon further increase in temperature. The decrease in Si etch rate at higher temperatures is attributed to the activation of competing side reactions that consume the chemisorbed H atoms on the Si surface, which then suppresses the Si-etch step. For each of the three films, the etch rate increases initially with increasing source power and plateaus starting at between 2500 and 3000W. The photoresist and Si3N4 removal rates increase initially with increasing pressure, reaching maxima at ~ 800 and 2000 mtorr, respectively, beyond which the removal rates drop with increasing pressure. The initial increase in removal rate at the low-pressure regime is attributed to the increased atomic-hydrogen density, while the decrease in ash rate at the high-pressure regime could be attributed to the recombination of H atoms that could occur by various mechanisms. At temperatures where the reaction rates are relatively fast, the photoresist and Si removal rates both increase continuously with the hydrogen flow rate, indicating that both reactions are in the reactant-limited regime. Based on the process trends obtained, we have identified a process window that attains relatively high ash rates and low Si and Si3N4 etch rates, which would be useful for applications in the 45 nm technology node and beyond.

In this work, we demonstrate the etch patterning capability of narrow pitch dual damascene structures by using extreme ultraviolet lithography combined with a spin-on trilayer resist system. The latter consists of three layers. The photoresist on top is used to pattern a thin spin-on glass layer (SOG) which is then used to pattern a thick spin-on carbon layer (SOC). The SOC has two functions. It is used for its good gap-filling capability to avoid patterning over nonplanar surfaces but it also acts as a hardmask to pattern the dielectric stack (150-nm of oxide on top of 15-nm of SiCO and 5-nm of SiCN). Regarding the patterning scheme, the via-first approach has been chosen as it is less sensitive to misalignment. In this scheme, two lithography and etch steps are needed, first to form the via then to pattern the trench and etch the barrier layer. In both cases, the spin-on trilayer resist system has been used. As a masking material, the SOC layer displays two main drawbacks: its low etch resistance compared to the PECVD carbon layer and its poor mechanical stability during the oxide opening for 50-nm line and beyond. To address the first issue, we introduced C4F8 and CO to substitute C4F6 and O2 in the original chemistry. This modification significantly improves the etch selectivity and clearly increases the process window. Regarding the second issue, we kept it under control by changing three different process parameters: the bottom electrode temperature, the baking conditions after coating and the film thickness. Each of them has an impact but we got the best result by combining the three together. To further understand the mechanism driving the instability, we study and compare two SOC films baked at different temperatures (250degC/1min and 250degC/1min + 350degC/2min). Both films have a different density, a different glass transition temperature and are chemically different. However, they show a similar behavior after a short exposure to the oxide etch chemistry (F-based). Indeed, a thin F-rich layer is formed at the film surface which leads to a drastic change of its mechanical properties. After only few seconds exposure, the stress in the film is going from tensile to compressive causing the apparition of line wiggling. The same study realized with a F-free chemistry shows a different behavior proving that the thin F-rich modified layer is mostly driving this instability. The modified layer also has a different glass transition temperature compared to the bulk. This explains why the degree of the instability is dependent of the wafer temperature. The SOG film and the impact of the VUV light have been also considered in this study. To conclude, it was shown that narrow pitch dual damascene structures can be obtained by using EUVL in association with a spin-on trilayer resist system. The SOC line instability during the oxide opening has been studied and a solution has been proposed.

We present a new class of ULK dielectrics, cross-linked polycarbosilane (CLPCS) thin films consisting of C-Si-C and C-C bonds, which exhibit not only superior mechanical properties [1-2] but also insensitivity to moisture-assisted cracking. CLPCS thin films were synthesized by a solution process in which spin-coated disilacyclobutane rings opened to form 3-D networks by 300 oC thermal cure [3]. CLPCS thin films exhibited an excellent thermal stability up to 400oC together with dielectric constants as low as 2.3 without additional porosity. CLPCS thin films showed excellent Youngâ?Ts modulus and cohesive fracture resistance, which are much greater than those of MSSQ, and higher than those of CDO organosilicate ULK dielectrics [4]. Perhaps more importantly as ULK dielectrics, CLPCS thin films exhibited insensitivity to moisture-assisted cracking in moist environments, which cannot be achieved by organosilicate ULK dielectrics containing Si-O-Si bonds susceptible to moisture attacks [5]. Moreover, the absence of supermicropores and mesopores in CLPCS thin films mitigates problems associated with moisture diffusion currently encountered in conventional organosilicate dielectrics. These attractive properties make CLPCS thin film a novel and promising candidate for advanced interconnects. [1] Rathore JS, Interrante LV, Dubois G. Adv Funct Mater 2008;18:4022. [2] Oliver MS, Dubois G, Sherwood M, Gage DM, Dauskardt RH. Adv Funct Mater 2010;20:2884. [3] Interrante LV, Rathore JS. Dalton T 2010;39:9193. [4] Dubois G, Volksen W, Miller RD. Chem Rev 2010;110:56. [5] Dauskardt R, Lane M, Ma Q, Krishna N. Eng Fract Mech 1998;61:141.

Continual decrease of feature size of transistors in accordance with Mooreâ?Ts law leads to the fact that ultra low-k materials (k2.0) should be used for technology nodes beyond 22 nm to maintain IC performance. Such materials are normally organosilicate glasses (OSG) and have high porosity exceeding 40% and have pore size larger than 3 nm. Moreover, the pores size is significantly increasing with the reduction of dielectric constant. The high porosity deteriorates all critical properties of ultra low-k materials including mechanical properties (stiffness and adhesion) and chemical/plasma resistance. Normally, the chemical and plasma resistance can be improved by increasing of the terminal CH3 groups concentration in the film matrix, but the terminal groups decrease the degree of interconnectivity of the network atoms and deteriorate the mechanical properties of low-k films. Recently, a new â?ospin-onâ? deposited model system in which silicate is initially present as mixtures of tetraethyl orthosilicate (TEOS), terminally alkylated silicate ester, and alkylbridged silicate has been developed by SBA Materials, Inc. [1]. It was postulated that such modification provides deposition of ultra low-k materials with exceptionally good mechanical properties and chemical resistance. In this work, the low-k materials designed by SBA were systematically evaluated. Two sorts of this material with different target k-values of 2.0 and 1.8 were investigated in terms of its composition, mechanical properties, pore structure, UV properties and chemical stability. According to results of the evaluation both materials SBA-1.8 and SBA-2.0 demonstrate mechanical robustness with Youngâ?Ts modulus of about 3 GPa and 5 GPa respectively and demonstrate exceptionally good chemical stability. It is shown that this advantageous behavior of new low-k material can be related to amount of Si-O cage-like structures constituting the film skeleton, what was confirmed by comparison of FTIR spectra between two versions of SBA-2.0. 1. Mark L. F. Phillips, Travis J. Savage. This Symposium.

Ultralow-κ (uLK) spin-on dielectric sols are often made by hydrolyzing mixtures of silicate esters in organic solvents, usually in the presence of a detergent that acts as a template during drying and as a porogen when the film is annealed. Many of the physical properties of the annealed film such as Young's modulus, hardness, adhesion, resistance to etch, hydrophobicity, etc are controlled by how the silicate backbone is functionalized. We investigated a model system in which silicate is initially present as mixtures of tetraethyl orthosilicate (TEOS), terminally alkylated silicate ester, and alkyl-bridged silicate. This is mixed with fixed quantities of water, catalyst, detergent and solvents to make a series of uLK sols with varying amounts of bridging and terminal alkyl groups. These sols were designed to produce films with specific dielectric constants that are in the range of 1.8 to 2.4. The sols were spun onto Si chips and the uLK films were thermally cured in an inert atmosphere. We altered the relative amounts of terminal and bridging carbon fragments as well as the overall framework carbon/silicon (C/Si) value and noted the effects of these ratios on etch resistance, Young's modulus (E), hardness (H), adhesion to the SiCN etch stop layer, and shelf life of the sol. As expected, there are tradeoffs: increasing the ratio of bridging/terminal alkyls improves adhesion, E and H but decreases shelf life. Likewise, increasing C/Si improves etch resistance but decreases E, H, and adhesion. We found that rather than producing a single ideal sol, exploring the TEOS: terminally alkylated silicate: alkyl-bridged silicate phase space yields a locus of compositions that are useful for making a family of uLK sols which may be further tuned to yield a sol with performance that is designed to optimize a particular semiconductor manufacturing process.

Organic low-k (OLK) materials do offer certain advantages over organo-silicon (hybrid) materials, amongst which their ability to reach similar k values with much less porosity. They are also less sensitive to plasma etch damage because of their mono-component (non-hybrid) nature. During plasma patterning and subsequent air exposure, insignificant degradation of dielectric constant happens, but it has a more complicated nature than in the case of hybrid materials. In order to understand this phenomenon, this work investigates the mechanism of damage occurring in a k=2.3 spin-on, porogen-free organic low-k material exposed to Ar plasma, i.e. without chemically active radicals into the plasma. The effects of processing temperature, processing time, bias voltage have been studied in details. By means of MgF2, Quartz and Si windows, the effects of VUV light, ion radiation and Ar metastable atoms have been separated and evaluated. The exposure to VUV light only (wavelength > 120nm) does not lead to any surface or bulk material modification. However, simultaneous effects of VUV light, ions and metastable atoms lead to significant modification of the low-k surface. For this reason, at zero bias voltage, although the etch rate is negligible, the surface is turned hydrophilic even for very short exposure times. A slight surface densification occurs, which translate into a partial surface sealing but no measurable k-value degradation. At high bias voltage, the etch rate is severely enhanced and the surface is also turned hydrophilic, but to a less extent than at zero bias; the surface is sealed and densified, leading to the formation of an amorphous-C-like layer, resulting in a significantly increased k-value.

The ability to realize the full potential of highly porous dielectric materials (k2.4) has been severly limited due to plasma damage during traditional damascene-based integration processes [1]. The resulting detrimental effect on electrical reliability along with significantly lower mechanical properties of such highly porous systems has caused the conservative microelectronics industry to shy away from these materials. Although recent advances in the design of new low-k dielectric materials has addressed mechanical deficiencies [2], little progress has been made on process related damage issues. In this respect, we have developed an innovative integration strategy, which addresses the latter [3,4]. Here, a fully cured, i.e. dimensionally stable, porous matrix is filled with a suitable polymer. The resulting â?onon-porousâ? material is exposed to the various integration processes followed by the complete removal of the pore filler via thermal means, fully restoring the initial properties. This presentation will describe the steps necessary to achieve virtually complete filling of the porous matrix, characterization of the filled films consistent with a uniform/homogeneous fill and demonstrate the protection efficiency offered by this simple, yet effective approach as observed on blanket films and single-damascene test structures.

Novel materials are required to reduce interconnect RC delay in technology nodes beyond 22-nm. These materials include porous low-k inter-layer dielectrics (e.g., porous SiOC:H) and ultra-thin Cu diffusion barriers (e.g., TaN, Ru) deposited using atomic layer deposition (ALD). Integrating porous dielectrics with ALD metals presents a unique interfacial engineering challenge: since the ALD precursor molecules are smaller than the pores of low-k dielectric film, they tend to penetrate the dielectric which damages the interconnect properties. This phenomenon can have serious reliability consequences such as elevated leakage, early dielectric breakdown, and low TDDB. This talk will outline two strategies for pore sealing of porous low-k dielectrics. These strategies rely on modifying the dielectric surface functionality and its porosity to minimize precursor penetration into the ILD pores. Pore sealing performance of both strategies was analyzed using analytical tools (SIMS, top-down SEM and TEM) as well as integrated electrical tests to characterize leakage, via-R and k-damage. With continued scaling of dielectric constant below k=2.0 and the introduction of novel metallization schemes for future technology nodes, a greater emphasis on interface engineering is required. In this context, areas of research including novel functional molecules for pore sealing and novel ALD deposition precursors and methods will be highlighted.

Materials with low dielectric constant (low-k) and low resistivity metal wires are needed to provide high speed, low dynamic power dissipation and low cross-talk noise in interconnects of ULSI devices. The reduction of dielectric constant is achieved by introduction of porosity into organisilicate (OSG) glasses. However, the pores must be sealed to prevent diffusion of metal ions from the wires and chemical species formed during the technological processing. Advanced nanoelectronics research is presently developing materials and processes for 22 nm technology nodes and beyond. In this case the dielectric constant of interlayer (ILD) dielectrics is required to be smaller than 2.0. Such ultralow-k materials (ULK) have porosity exceeding 50 % and a pore size of 3 nm or more, and all existing sealing technologies are not efficient anymore. The lack of a closed porosity in these interlayer dielectrics is one of the most important limiting factors in the further miniaturization and development of integrated circuits. In this work we demonstrate a new strategy to seal highly porous low-k materials with an actual pore size of 3 nm. This is achieved by a simple deposition of a self-assembled carbon-bridged organosilica layer on top of a mesoporous silica film with a porosity of 38 %. Diffusion in the porous material is prohibited by allowing that these cyclic carbon-bridged organosilane precursors form intermediate fragments with molecular sizes exceeding pore sizes of 3 nm before deposition. Moreover, a completely sealed, hydrophobic and still highly porous material is obtained by grafting the remaining hydroxyl groups of the organosilica top layer with trimethylsilyl groups through hexamethyl disilazane (HMDS) treatment. We also demonstrate that partial sealing, realized after deposition of the organosilica layer without extra HMDS treatment, is already sufficient for the deposition of copper barrier layers in actual device applications. Therefore, approximately 7 nm TaN was sputtered on partial sealed and non-sealed mesoporous silica films. The partial sealed film shows a sharp interface, in HRTEM analysis, between the TaN layer and the cyclic carbon-bridged layer, proving its perfect sealing property.

LSI technology for 22 nm node and beyond needs ultra-low-k films having k-value below 2.1. In order to reduce the dielectric constant, porous low-k film is indispensable and widely studied. However, porous low-k film is sensitive to process-induced stimuli caused by plasma and metallization process, because such plasma or metals may diffuse via open pores of film. In addition, new metal deposition technologies are developed such as metal CVD or ALD in order to form conformal metal layers on the wall in trenches or vias whose aspect ratio is large. Therefore, pore seal layer which suppresses the diffusion of those metal precursors into porous low-k film is indispensable. So far, we succeeded in fabricating ultra-thin (3 nm-thick ) layer on top of the surface of porous low-k which suppresses the diffusion of metal into porous low-k film and in discovering that the ultra-thin layer is stable after thermal cycle stress and bias stress. In this paper, we developed various types of pore sealants and porous low-k and studied the relationship between the molecular structure of pore sealant and the porous structure of porous low-k using toluene based Ellipsometric Porosimetry (EP) measurements. The typical porous low-k we used here has dielectric constant of 2.1, porosity of 49 % and pore radius of 2.55 nm. When the molecular size of pore sealant is too small, porosity decreased to 34 % and pore radius decreased to 2.01 nm, refractive index of whole layer increased from 1.242 to 1.325, showing that pore sealant enter into whole layer through pores. On the other hand, when the molecular size of pore sealant is optimized, refractive index of only the vicinity of the surface increased to 1.515 and toluene did not diffuse into pores. It shows that a thin layer forms on the surface of porous low-k and toluene diffusion is blocked. We found for the first time that molecular structure of pore sealant determines the pore seal performance. We believe that such ultra-thin layer, which we propose here, would prevent the diffusion of CVD or ALD metal precursor and opens the door to apply porous low-k.

Advanced interconnect technology is presently selecting materials for technology nodes smaller than 22 nm. The low-k materials for these technology nodes (with the presently used integration scheme) should have dielectric constant smaller than 2.0. If the low-kâ?Ts are based on organosilicate glasses (SiOCH), their porosity exceeds 40% and pore size is larger than 3 nm. These properties request development of new sealing approaches because the traditional sealing methods are becoming hardly applicable. On the other hand, the presently used dielectric barrier layers used for interlayer planarization like SiN and SiCN have too large k-value (k > 4.0) which make difficult to realize advantages of ultra low-k materials. In this work, thin films of rigid-chain polyimide (PI) with the k-value of about 3.2-3.3 have been deposited and investigated. Deposited by molecular self-assembling based on Langmuir-Blodgett (LB) technique these films can be made as thin as several monolayers whereas partial polymerization of precursor monolayer before transfer on porous substrate allows to avoid contamination of pores with the precursor molecules. The partial polymerization was achieved by choosing of appropriate precursors and optimization of surface pressure during the deposition that allows Pi-stacking of adjacent polymers and seal pores with even larger diameter. It was found that LB films of about 4 nm comprised of 8 PI monolayers are able to seal the surface of porous material with average pore size of 2 nm without significant deterioration of its pristine properties. Such a small thickness of sealant was achieved thanking to transfer of partially polymerized monolayers of PI precursor on the porous substrate. The efficiency of sealing was examined by ellipsometric porosimetry.

Integration of ultra low-k materials (k2.4) presents a difficult challenge for the semiconductor industry [1]. Excessive plasma damage during BEOL integration due to the increased porosity required to reduce k continues to be one of the main issues in the reliable manufacturing of high performance microprocessors. To mitigate this problem we developed and previously reported the P4 (Post Porosity Plasma Protection) integration scheme that protects the ULK during BEOL integration [2,3]. This strategy consists of protecting the fully cured porous ULK material by filling the pores with a sacrificial agent then integrating an apparently non-porous dielectric. We demonstrated the P4 efficacy using a polymer to protect a mesoporous (pore diameter > 2 nm) material with k = 2.0. Unfortunately polymer penetration in microporous (pore diameter2 nm) materials is less efficient, therefore making the strategy not adaptable to the integration of materials in near-term technology (2.4k2.2). Hence, an alternative P4 scheme is required, which will work in the microporous regime and realize similar protective efficacy. In this presentation we will describe a new approach for mitigating the damage associated with the BEOL integration of ULK materials with dielectric constants raging from 2.2 to 2.4. We will demonstrate the successful filling of microporosity using low molecular weight monomers followed by in-situ polymerization. Key parameters, such as monomer physical properties, free radical polymerization characteristics, polymer thermal stability and pore filling will be discussed. In addition, we will demonstrate the protection of microporous ULK materials form plasma induced damage by successful integration at relaxed ground rules. We believe that this approach will address the more near-term needs of the microelectronics industry. [1] W. Volksen et al., Chem Rev, 2010, 110, 56. [2] T. Frot, et al., Adv. Mater. 23, pp. 2828-2832, 2011. [3] T. Frot, et al., Future Fab Intl 2011, 39, 67.

In the fast paced microelectronics industry there is a continuous need to increase circuit density in multilevel Copper (Cu) back-end-of line (BEOL) interconnects (IC) to improve the operating speed and reduce power consumption. With downscaling of IC dimensions, one approach to meet the BEOL capacitance-resistance (RC) target is by introducing organo silicate glass (SiCOH) materials with low dielectric constants as interlevel dielectrics (ILD). At the 45 nm node, porosity was first introduced into the BEOL IC structures in the form of porous organo silicate glass films (p-SiCOH) with ultra low-κ (� 2.55) to further minimize the RC delay. Porous ULK materials incorporate a large number of methyl groups and pores into Si-O based network structures, although the initial precursors and final properties may vary. OSG materials are commonly deposited by plasma-enhanced chemical vapor deposition (PECVD). The effects of porosity significantly complicate the integration of ULK materials into conventional copper damascene schemes. For example, due to inherent porosity ULK films are mechanically weak and tend to crack as a result of elastic mismatch with the substrate. Meanwhile, pore collapse and carbon depletion can occur when ULK is exposed to RF-plasma during etching or ashing, and wet chemical strip. Subsequent moisture adsorption leads to the increase of effective κ-value, which negates the advantage of ULK films and degrades RC performance. Therefore, the integration challenges are significant, such as plasma damage, chip packaging interaction, and dielectric/metal barrier compatibility. Precise optimization of the ULK properties is crucial for successful integration for sub-22 nm BEOL nodes. This study reports on simple characterization techniques used to screen and optimize the processing conditions of ULK films with κ � 2.55 to successfully meet specific integration requirements. ULK films deposited using four different chemistries were characterized to compare electrical, mechanical, chemical, physical, and thermal stability properties. The effect of UV Cure dose on the ULK material properties and correlation of the degree of plasma damage to the ULK chemical, physical, and structural properties will be discussed. We demonstrate that balancing composition of the film to minimize process damage for needs to be coupled with improving electrical and mechanical integrity for packaging compatibility. Acknowledgment: This work was performed at the IBM Microelectronics Div. Semiconductor Research&Development Center, Hopewell Junction, NY 12533

ATMS [allyltrimethylsilane: CH2=CH-CH2-Si(CH3)3] was selected here as a precursor for SiCOH/CxHy dual-phase films, and it is expected that a allyl group and three methyl groups attached to silicon could be utilized effectively on a molecular scale to make SiCOH (thermally stable phase) films along with CxHy (labile phase) embedded in it. The allyl group and CHO (cyclohexene oxide) has been used as a porogen (porosity generator) precursor, and it was expected that the labile phase was formed more effectively from this group. The molecular structure of ATMS is similar to 3MS which is commercialized in Black diamond. ATMS is also able to have a good thermal, mechanical property in similar structure of 3MS having a good those property. Direct plasma reactor was used where radical oxygen was generated in the chamber. The refractive index and film thickness were measured and calibrated with an ellipsometer and a FE-SEM (Field Emission Scanning Electron Microscope). The films have been characterized as-deposited and after annealing at 420°C. ATMS/CHO low-k films showed a amorphous structure, very smooth and uniform surface. The formation of porosity was observed from annealing as confirmed by the difference of refractive index and removal of the thermally unstable carbon groups (CxHy). The structure and composition of the films were investigated by FT-IR (Fourier transform infrared spectroscopy) and XPS (X-ray photoelectron spectroscopy). The relative carbon content and dielectric constant were observed to decrease after annealing. It was observed that a thermally unstable phase (CxHy) is removed after annealing and the desorption of the labile phase makes additional porosity in the film. After annealing, the increase of porosity was 20 % against the as-deposited films, calculating from the Lorentz-Lorentz equation. The other properties of the films have been investigated by SIMS (Secondary Ion Mass Spectroscopy), TEM (Transmission Electron Microscope), AFM (Atomic Force Microscopy), EFM (Electrostatic Force Microscopy) and Nanoindentor, LCR meter, Hg probe. ATMS/CHO low-k films showed a low dielectric constant as low as 2.2 and high modulus of 8.4 GPa according to the ATMS/CHO ratio. This value is superior to that of other SiCOH materials. It was found that the properties of the annealed films depend on the deposition temperature and concentration of porogen. The solvent-less and low-energy PECVD make it attractive from an environmental safety, health perspective and easy compatibility with industry. In result, we demonstrate that the processing of a new PECVD low-k film, ATMS/CHO, creates a well-defined, material having a good thermal and mechanical properties, which is promising for low-k processing.

Most ultralow-k (ULK) dielectrics with dielectric constants k â?¤ 2.55 are porous pSiCOH type fabricated by the subtractive method, using a mixture of skeleton and porogen precursors. Low-k dielectrics have also been fabricated by the structural method but only with k values down to 2.55. Modifying the deposition conditions and using the precursor employed for the fabrication of dense SiCOH with k = 3.00 we have previously been able to reduce the dielectric constant to about 2.7. In the present work we have further combined a set of modified deposition condition with UV cure of the deposited films to obtain porous ULK films with k values down to 2.4 using the same precursor as for the dense SiCOH. The films contain large concentration of C, a significant fraction of it in Si-C-Si bonds, have high resistance to process induced damage, and are characterized by low leakage and high breakdown voltages. By modifying the UV cure time, the mechanical properties of the new ULK films can be adjusted to values similar to pSiCOH films fabricated by the subtractive method. The new films have a strong potential for integration in the interconnect and provide a cheaper solution for the interconnect insulator. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

Many IC manufacturers are currently integrating porous organosilicate materials (OSGâ?Ts) with a dielectric constant of 2.4 - 2.5 as back-end-of-line (BEOL) interconnect dielectrics. These materials incorporate 24-31% porosity in the films as measured by Elliposmetric Porosimetry (EP) using toluene as the probe molecule (1). Next generation materials will have dielectric constants in the range of 2.3 - 2.0. In order to achieve such ultra low dielectric constants the OSG materials will likely need to incorporate more porosity. At greater levels of porosity, the issues of pore interconnectivity and pore size distribution have been raised. A number of options to control the skeleton and pore structure of OSGs have been proposed (2), from adding alternative OSG precursors to alternative porogen precursors. In all these options there is a need to balance such pore structure modification with critical film properties such as dielectric constant and mechanical strength. In this context, this paper examines porosity and its impact on film properties for highly porous ultra low dielectric constant films. A series of PDEMS® porous OSG films were deposited by plasma enchanced chemical vapor deposition (PECVD) from DEMS® precursor (diethoxymethylsilane) and porogen ATRP (alpha-terpenine). The evolution and nature of porosity in films with k values from 2.0-2.5 was studied as a function of the UV cure time. The porosity and pore interconnectivity of these films were measured by both EP and positron annihilation spectroscopy (PALS) in order to understand how these techniques compare. The effect of polarity of the sampling solvent in EP experiments was examined utilizing both iso-propyl alcohol (IPA) and toluene as probe molecules. Porosity and pore-size distribution for films deposited using several different species (structure former or porogen precursors) were examined using EP in an effort to understand the impact of the chemical nature of the precursor on pore morphology. The consequent tradeoffs between all the interrelated compositional, mechanical, and electrical properties will be discussed. Such a fundamental understanding of structure-property relationships enables successful integration of these porous OSG films. (1)M.L. Oâ?TNeill, M.K. Haas, B.K. Peterson, R.N. Vrtis, S.J. Weigel, D.J. Wu, M.D. Bitner, and E.J. Karwacki, MRS Symposium Proceedings (2006) (2) S. M. Gates, G. Dubois, E.T. Ryan, A. Grill, M. Liu, and D. Gidley; J. Electrochem. Soc. 156 (10) G156-G162 (2009).

We present the first comprehensive investigation of the four aspects that define the characterization of candidate low-k (dielectric constant) materials suitable for implementation in back-end processing. These four properties are a quantification of the porosity and structure of a low-k candidate material, and that materialâ?Ts resultant dielectric and mechanical properties. Industrially, the goal is to lower the dielectric constant of the material below a value of 2, frequently by creating 1-2 nm diameter pores in oxide materials, without the current concomitant loss of mechanical strength. Our research focused on the development of a computational model of amorphous SiCOH material behavior under different thermal and mechanical stresses. This involved developing an algorithm that generates an atomic-scale model of an SiCOH film, which exhibits structural, mechanical and electrical properties in agreement with experimental studies. We have developed a unique two-step process for computationally defining the structure of SiCOH films. The first step defines the initial atomic layout and bonding structure of the film, using available experimental data on SiCOH materials to incorporate the full range of structural entities seen in chemical vapor deposited (CVD) SiCOH films. The second step allows the system to relax into a more energetically favorable configuration, while also allowing the rearrangement of an initial atomic arrangement, making the final result less dependent on initial system set-up. Once this process has generated a model SiCOH structure, we verified the key electronic and mechanical properties of the model, to ensure their agreement with experimental data. In order to study these properties, we first needed to develop computational methods capable of calculating them: We created an algorithm to introduce randomly placed porosity into the system and calculate the porosity and the pore size distribution of the model film. This method involves scanning through the atomic layout of the model and recording the location of empty spaces within the system, which has the advantage of providing detailed information about the systemâ?Ts pore structure on multiple length scales. We used density functional theory (DFT) to develop a library of data on the dielectric constant of a large SiCOH structure based only on its atomic composition and volume. We used this data library to create a correlation between composition and polarizability that reduces finding the dielectric constant for any model structure to a simple calculation, without the need for any additional simulations. Finally, we confirmed the mechanical properties of the model using established Molecular Dynamics techniques. With this complete suite of programs, we showed the difference in mechanical properties from spin-on versus CVD-generated materials and related this to the presence of terminal (pendant) methyl groups.

As the critical dimension of copper Damascene interconnects decrease, it has become more challenging to obtain acceptable coverage of all surfaces with the copper seed layer while at the same time avoiding pinch-off using physical vapor deposition (PVD) barrier-seed processes. The sidewalls of some features, in particular, may have a very thin layer of copper susceptible to complete conversion into copper oxide. Adding to this concern, a small amount of copper metal dissolution may occur at the initiation of electrodeposition in a state of the art acidic copper electrodeposition process. Removal in such regions will yield a discontinuous seed layer leading to void formation in the Damascene interconnects. The replacement of the PVD copper seed layer with one grown by chemical vapor deposition (CVD) or atomic layer deposition (ALD) is one possible solution. Although excellent coverage can be obtained with this approach, these films are prone to other issues including adhesive failure. However, the use of a barrier film stack grown with CVD or ALD including a semi-noble metal film such as ruthenium has garnered considerable attention as a copper seed layer can be grown electrochemically directly on this film stack. In this paper, we will focus our attention on the electrodeposition process associated with formation of this thin, continuous copper film describing the deposition chemistry, material characterization, and the associated integration schemes. Specifically, we will present results showing compatibility with the 2x nm node interconnect technology as well as variants that will allow extension to future technology nodes.

The efficient copper metallization of narrow lines which are used to create interconnections in damascene applications becomes more and more challenging with the decrease of the effective opening available for filling by copper electrochemical deposition (ECD). Among the elementary steps involved in the metallization sequence, besides the achievement of a minimum-thickness/non-overhanging barrier (such as on Ru-based PEALD barriers), the most critical will probably be the deposition of a copper seed layer necessary to initiate the bulk copper ECD. For future generations, physical vapor deposition (PVD) techniques that are currently employed will reach a limit, as they are not able to perfectly cover the sidewalls of the narrow and high aspect ratio features. The resulting discontinuous seed layers can cause defects such as bottom voids in the copper vias. To overcome poor copper seed coverage issues, a â?odirect on barrierâ? (DoB) copper deposition technique is proposed, which is able to completely replace the copper PVD step. Promising DoB experiments were carried out on 300 mm wafers on which PE-ALD Ru and RuTiN layers (in field thicknesses of ca. 3 nm) were deposited. A thorough optimization study in terms of current density, plating bath concentration and deposition time has been carried out. No delamination is observed after scotch tape test and non-uniformity lower than 4% is achieved for the DoB copper films. A multi-technique physical-chemical characterization of the Ru-based and Cu layers is carried out in order to understand material properties and morphology. The step coverage of the deposited conformal DoB copper layer is monitored and combined with the fill capability of standard damascene ECD chemistries. In this contribution, the benefits of our DoB approach, as a replacement for the PVD Cu seed in narrow damascene lines are evaluated, and the remaining challenges are discussed.

Copper (Cu) has recently been a popular interconnect material for advanced electronic and optical devices [1]. Recently, Kuo and Lee reported a novel plasma based Cu etch process [2, 3]. Instead of vaporizing the plasma reaction product, the Cu film was converted into a chloride or bromide compound, which was subsequently dissolved in a dilute hydrochloric acid to remove the reaction product. In practical applications, the metal film is often deposited on a dielectric step, which forms the cusp structure [4]. It contains high local stress and is easily attacked under the etching condition. In this paper, the effect of feed gas composition on the etch of the Cu line over a dielectric step was studied. The failure mechanism of the etched Cu line was also investigated using the electromigration (EM) test. The excessive attack of the cusp region can be minimized or eliminated by increasing the ion bombardment energy, lowering the Cl radical concentration, and forming a sidewall protection layer. This can be achieved by including a certain amount of N2 or CF4 in the Cl2 plasma. The lifetime of the electromigration of the etched Cu line were affected by the line pattern and topography. The step effect is reduced at the high temperature. Reference [1] Y. Kuo, Procs. 6th Intl. Conf. Reactive Plasmas and 23rd Symp. Plasma Processing, p. 29, 2006. [2] Kuo and S. Lee, Appl. Phys. Lett., vol. 78, p. 1002, 2001. [3] S. Lee and Y. Kuo, J. Electrochem. Soc., vol. 148, G524, 2001. [4] T. C. Tisone and J. B. Bindell, J. Vac. Sci. Technol., vol. 11, p. 72, 1974.

High performance RF technology is required for many communications applications, such as mobile phones. The interconnects for RF circuits are different from those for digital circuits in that very thick Cu wiring layers (> 3 um) are required to optimize inductor performance. Because the Cu wires are so thick, many of the reliability issues with conventional Cu interconnects are not a problem. The main reliability issue with thick Cu interconnects is the high mechanical stress. During development of a 3 um thick Cu interconnect process, a problem was observed with delamination of the SiN capping layer from the Cu. The delamination is due to the CTE mismatch between the Cu and the SiO2 dielectric, and the temperature cycle associated with SiN cap layer deposition (~ 400C). During cap layer deposition, Cu expands more than the surrounding dielectric. After cap layer deposition, the Cu is constrained and cannot return to itâ?Ts original shape, so there is a tensile stress in the Cu and at the Cu-SiN interface. Delamination occurs if the tensile stress at the interface is greater than the adhesion strength of the two layers. The delamination can be eliminated by either improving the adhesion of the interface or by reducing the tensile stress at the interface. A simple solution to the problem is to optimize the post-plating anneal. The stress in 4 um thick Cu films during thermal cycling from room temperature to 400C is strongly dependent on the post-plating anneal. When the post-plating anneal is increased from 100C to 250C, the room temperature tensile stress in the Cu is reduced. In addition, the total stress change during thermal cycling is also reduced, corresponding to a smaller change in Cu microstructure (for example, less hillock growth). Presumably, the higher temperature post-plating anneal stabilizes the Cu microstructure, thereby minimizing the tensile stress at the Cu-SiN interface, and reducing the driving force for delamination.

The downward scaling of integrated circuit technology is accompanied by increase in operating frequency. This has major impact on the design and manufacture of interconnects as they are required to maintain their performance and reliability to meet the increase in system operating frequency. Toward this end, we have embarked on a study of the RF characteristics of Cu via interconnects using a one-port Ground-Signal-Ground (GSG) structure fabricated on a silicon wafer [1]. A 0.2 μm thick silicon dioxide film is used to isolate the ground Pt/Ti (Ground) layer from the silicon substrate to minimize substrate losses. Low-aspect-ratio Cu vias with cross-section ranging from 0.5 x 0.5 to 1.0 x 1.0 μm2 and height 0.8 μm are used for this study. These vias were filled with copper using an electroplating process. Ground trenches are 40 μm wide to ensure very low resistance compared to those of the vias. The wafer was annealed to minimize the contact resistance between each Cu via and the Pt/Ti layer. The dc and RF (up to 50 GHz) characteristics of 18 Cu devices are measured in two and four-point dc and GSG configurations, respectively. The measured dc resistances for the Cu vias (10 mΩ - 50 mΩ) are in good agreement with values calculated using the known bulk resistivity of Cu. The dc resistances of the ground layer, ground pads, and signal pad are measured using four-point probe technique and then used to estimate their high-frequency impedance. The low impedance of the copper via results in the domination of the overall impedance by that due to the contact between the probe and contact pad, unlike the case of a two-port structure in which the device impedance can be extracted directly from measured S-parameters [2]. We have developed a methodology to de-embed the probe contact impedance from S-parameter measurements for the one-port test structure in order to extract the impedance of the copper via. A lumped-parameter circuit model is used to extract the resistance between the via and the ground plane [3]. [1] F.R. Madriz, J.R. Jameson, S. Krishnan, X. Sun, and C. Y. Yang, IEEE Transactions on Electron Devices 56, 1557-1561 (2009). [2] Y.P.R. Lamy, K.B. Jinesh, F. Rozeboom, D.J. Gravesteijn, and W.F.A. Besling, IEEE Transactions on Advanced Packaging 33, 1072-1079 (2010). [3] S.-P. Sim, S. Krishnan, D. Petranovic, N. Arora, K. Lee, and C.Y. Yang, IEEE Transactions on Electron Devices 50, 1501-1510 (2003).

Copper interconnects in a dual inlaid architecture and with low-K dielectrics are commonly employed in high performance integrated circuit technologies. Inlaid Cu lines offer higher conductivity, improved electromigration performance and a reduced cost of manufacturing over their Al predecessors; however, the damascene fabrication method and the introduction of low-K dielectrics to improve performance present a host of integration and reliability challenges to Cu interconnects and fundamentally change the mechanical stress state of the Cu lines used as interconnects. The fabrication of Cu-based interconnects involves numerous thermal excursions associated with the deposition and annealing of constituent materials that comprise the back-end-of-line (BEOL). The thermal expansion mismatch between Cu and the underlying Si substrate can induce significant tensile stress in the metallization after these thermal cycles. Because tensile stress in the Cu features can affect the reliability of Cu interconnects, conditions that accentuate tensile stress must be properly understood and controlled. In this presentation, the effect of the fabrication method on grain growth, mechanical stress and reliability will be reviewed. Recent work to understand the development of stress within Cu interconnects will be highlighted, including the effect of capping materials that act as diffusion barriers on the mechanical response Cu films and lines.

According to aggressive shrinkage of semiconductor feature size, both of the performance and reliability of copper (Cu) interconnects are becoming challenging issues. The characteristics of Cu interconnects strongly depend on its crystalline structure, such as grain size, crystal orientation and grain boundary conditions. A typical method used to obtain nano-scale crystalline structure is electron backscattered diffraction (EBSD). Although EBSD provides detailed information of metal films, the biggest drawback of the method is its long acquisition time. Backscattered electron (BSE) imaging by using scanning electron microscopy (SEM) would be a promising method to realize a quick analysis of metal films. The morphology of the grain distribution is obtained as crystallographic contrast in SEM images. An obvious disadvantage of SEM-based method, however, is a very small signal difference between different crystal orientations. Therefore, by optimizing the SEM imaging conditions, it is essential to maximize the crystallographic contrast in order to realize a â?oquick and reliableâ? analyzing tool for nano-scale interconnects. The purpose of our study is to develop a crystallographic contrast simulator so that one can effectively optimize the imaging conditions. The simulator is developed based on a Monte-Carlo method, and is verified by using our systematic experiments. The newly-developed code is capable of treating electron channeling and blocking effects by the lattice planes. The code is implemented into a commercial Monte-Carlo platform, CHARIOT. In order to evaluate the accuracy of our simulation model, relative variation of BSE signal intensity (Î"η) among various crystal orientations is introduced. Î"η is calculated for various electron beam energies and various thickness of top layer above the Cu surface. As for the material of the top layer, we considered carbon as a contamination layer, and amorphous Cu as a disordered surface layer. In the experiment, electro-plated Cu thin films were prepared on silicon wafers and inspected under SEM. The comparison between simulation and experiment shows that, the trend of Î"η obtained in the experiment indicates the existence of a disordered Cu layer of 1-5 nm in thickness. The cross-section imaging by using transmission electron microscope (TEM) is performed to verify this comparison.

The challenges on uniformity and defects post Cu CMP for 20 nm technology node and beyond were discussed in this paper. In uniformity, the global and local uniformity and the accumulative effects were discussed. The improvements of uniformity to meet the 20nm node different integration scheme requirements were studied and resolved through the evaluation of the Cu and barrier slurries and pads. In defects, the time dependent, liner dependent and pattern density dependent dendrite defects were discussed. The new post CMP clean chemicals were evaluated to solve these issues. Their effects on the Cu/ULK integration reliability were studied. The trade off between uniformity and defects during the slurries, pads and post Cu CMP clean chemicals evaluations were also discussed.

As the feature size of ULSI chip continue to shrink, Chemical Mechanical Planarization(CMP) process is gaining momentum in semiconductor chip fabrication. Recently, semiconductor chip manufacturers introduced around 20nm or less sized lithographic process to get low power consumption and higher speed. However, the effect of defect, especially CMP micro scratch, has increased dramatically due to the increased packing density. To control CMP micro scratches, smaller wet precipitation ceria particles, easy to maintain dispersion stability and particle size distribution, can be used in CMP slurry. On the other hand, smaller wet precipitation ceria particles are sensitive to pad surface condition. In this research, we used 30nm, 60nm wet precipitation ceria particles and 60nm grain sized calcined ceria particle to study the effect of particle size and crystallinity property. 3 different types of diamond disks with different crystal sizes, were employed to generate pad surface asperity. Oxide blanket wafer polishing and pattern wafer polishing were studied to understand the polishing rate, surface morphology, and step height reduction performance. Moreover, functionality polymers were introduced to bridge pad surface and ceria particle to enhance step height reduction polishing performance of wet precipitation ceria particle. Consequently, we confirmed that micro and macro asperity of pad surface are affected by the size of diamond crystals. In addition, it has been identified that the difference in surface roughness has an influence on the material removal rate and the step height reduction polishing performance with ceria particle properties. Additionally, we could enhance step height reduction polishing performance of ceria CMP slurry by using organic acid.

Chemical Mechanical Planarization (CMP) has been proven to be the best method to achieve within wafer and within die uniformity for multilevel metallization. The decreasing device nodes and increasing wafer sizes continuously demand better performance in planarization which requires better understanding on all the variables of the CMP process. Pad conditioning is one of the recently highlighted critical factors that impact the pad surface profile and consequently the wafer profile in addition to functioning as defect reducer through refreshing the pad surface during polishing. This work highlights the changes in the post polish wafer profile as a function of pad wear and introduces a wafer material removal rate profile model based on the locally relevant Preston equation by estimating pad thickness profile as a function of polishing time. The result is a dynamic predictor of how the wafer removal rate profile shifts as the pad ages. The model helps fine tune the conditioner operating characteristics without having to carry out costly and lengthy experiments. The accuracy of the model is demonstrated by experiments as well as data from a real production line.

Capillary type underfill is still the mainstream underfill for mass production flip chip applications. Flip chip packages are migrating to ultra low-k, Pb-free, 3D and fine pitch packages. Underfill selection is becoming more critical. This paper discusses the performance and potential of underfills using a novel organic-inorganic hybrid polymer technology. Compared to eutectic and high lead solder, tin-silver-copper solder has lower C.T.E., higher elasticity and greater brittleness. In light of these properties, it is generally better to select high Tg and lower CTE underfill in order to prevent bump fatigue during reliability testing. With the brittleness of low-k dielectric layers of flip chips, the destruction of low-k layers by stress inside the flip chip packages has become a major issue. Underfills for low-k packages should have low stress, and the warpage should be small. It is expected that as the low-k trend expands, the underfill is required to provide less stress. Low Tg underfill shows lower warpage. New chemical technologies have been developed to address the needs of underfills for low-k / Pb-free flip chip packages, specifically organic-inorganic hybrid polymer compounds. The organic-inorganic hybrid polymer provides excellent cure properties which enable a balanced combination of low stress and good bump protection. The material properties of the underfill were characterized using Differential Scanning Calorimetry (DSC), Thermo-Mechanical Analysis (TMA), and Dynamic Mechanical Analysis (DMA). A daisy-chained test vehicle was used for reliability testing. A detailed study is presented on the underfill properties, reliability data, as well as finite element modeling results.

As microelectronic devices continue to shrink, the Cu metallization employed in interconnect technology of integrated-circuits needs to survive in severe electrical and thermal working conditions. Recently, Cu films with high density nano-scaled twins show high strength, low resistivity and high electromigration resistance [1]. Extensive effort has been dedicated to modulate the microstructure of Cu films by varying current density, overpotential, and composition of electrolyte during electrodeposition. According to the deformation twinning mechanism, high strain rate and low processing temperature would increase the possibility of twinning in metallization. In this work, we intend to prepare nanotwinned Cu films by pulsed electrodeposition with different current density, polarity and duty cycle at low temperature. The crystallographic orientation and surface morphology of the Cu films were examined. The preliminary results indicate that the orientation of Cu films prepared by pulse electrodeposition have strong orientation compared to direct current mode. The influence of electrodeposition parameters on the mechanical and electrical properties of the nanotwinned Cu films will also be investigated. Reference: K.-C. Chen, W.-W. Wu, C.-N. Liao, L.-J. Chen, K. N. Tu, Science 321, 1066 (2008).

In packaging of devices, the removal of adventitious carbon and other contaminants is an important step prior to bonding to epoxies or other adhesives. X-ray photoelectron spectroscopy (XPS) have been used to characterize the effects of O2 and H2 plasmas, and corresponding free radicals on the removal of adventitious carbon from silicon nitride and oxynitride surfaces. Silicon nitrides and oxynitrides have been the subject of considerable research due to their superior reliability over conventional thermal silicon dioxide. Oxygen plasma and oxygen radicals induce rapid removal of carbon over layers at ambient temperatures with some hydroxylation of the surface. In contrast, H2 plasma causes incomplete removal of carbon and significant surface hydroxylation. Hydroxylation of the surfaces may enhance interactions with adhesives by enhancing hydrogen bonding across the substrate/adhesive interface. H radicals, however, have a negligible effect on carbon removal or surface composition, indicating that the effects of H2 plasma exposure are due primarily to ion and photon interactions with the surface, rather than chemical effects of atomic H. The results indicate that plasma cleaning based on either O2 plasma or O radicals is effective at removal of adventitious carbon for subsequent adhesion to epoxy. Acknowledgement: This work was supported by the Semiconductor Research Corp. under Task ID 2071.016. §Corresponding Author: [email protected] 2012 MRS Spring Meeting, San Francisco CA

Ruthenium has been considered as a direct plate material to achieve Cu interconnect gapfill at increasingly smaller dimensions without a seed layer. However, oxidation of the Ru layer leads to poor adhesion properties of the Cu layer. This effect may be attributed to increased Cu-Ru interface energy which is manifested in the observation of Cu agglomeration or de-wetting after thermal processes. The research approach is to employ plasma cleaning processes of Ru surfaces, followed by Cu deposition. In situ x-ray photoemission spectroscopy (XPS) is used to determine the effectiveness of the plasma cleaning and the stability of the Cu film as the sample is annealed to 450 °C. Detection of the substrate signal is an indication of de-wetting of the film. The XPS results show that either RT H2 plasma processing or vacuum annealing at 180 °C effectively removes the surface oxide of the Ru film. As-received and cleaned Ru substrates were capped with 10nm Cu films and annealed in vacuum to 450 °C. For the Cu coated, as-received Ru surface, the intensity of the Ru XPS peak increased upon annealing to 450 °C indicating Cu de-wetting. In contrast, the Ru signal remained low for Cu on clean Ru substrates for annealing to 450 °C. Atomic force microscopy (AFM) images confirmed that the Cu surface had formed into islands on the Ru as-received substrate while the rms roughness was ~1 nm for Cu on clean Ru. The results are analyzed in terms of the surface and interface energies of the clean and oxidized metals. The research is supported by the SRC.

Recently due to the development of modern technologies the more and more nanoscaled materials are used in different fields of material science. For example, to increase the speed of advanced integrated circuits the traditional SiO2 is replaced by low dielectric constant (low-k) materials. In the technology nodes 45-32 nanometers the most popular low-k materials are porous silicon oxycarbides (SiCOH) where part of oxygen atoms in SiO2 structure are replaced to less polarisable and hydrophobic CH3 groups [1]. The porous structure these materials allow easy penetration of active diffusing species into the film and change of their properties. These changes are often termed as â?oprocessing damageâ? and might happen during the different technological processes such as plasma etching, resist strip, wet cleaning and CMP, barrier deposition etc. In many cases this penetration leads to catastrophic degradation of low-k materials [2]. Another example of nanoscaled systems are zeolite materials, which have with highly stretched inner structure with nano-channels and nanovoids [3]. The transport in these systems are characterized by the following features: the small nano-scales of studied systems and finite number of particles, which participated in the processes of transfer. Confinement of atoms and molecules in restricted space of nano-voids and nano-channels lead to the unusual dependence of majority of bulk properties [3-5]. Very special confinement was observed in the case of metal and semiconductor cluster stabilization in the nano-voids of zeolite matrices [4-6]. In the same time, the simplest task â?" how the pressure changes in the nano-voids with the growing of number of particles in the nano-pore volume was not studied in a regular form and was not solved yet. The simple solution is not valid in such system, where n is a concentration of particles, k is a Boltmanâ?Ts constant, T is a temperature. In this report we consider case of nano-porous system with dense packing of molecules in this system and study dependence of pressure on the concentration of particles in this case. We show that pressure in porous system with complex branched structure at nano â?"scales sizes and in the approximation of dense packing has described by the new formula: Supported partially by Russian Foundation for Basic Researches grant 10-02-00573 and FTP 7 program EU-Russia in nanoelectronics grant N 5 References: [1] K.Maex, M. Baklanov et al., J. of Apl. Phys., 93, P. 8793 (2003) [2] M.A.Goldman, D.B.Graves et al., J. of Apl. Phys., 106, P. 013311 (2009) [3] V. Bogomolov, Y. Kumzerov, et al., Sov. Phys. Crystallogr., 35, 119 (1990). [4] P. Dubov, D. Korolkov, V. Petranovskii. Clusters and matrix isolated cluster superstructures. ISBN: 5288010382, St. Petersburg, Ed. House of St. Petersburg State University, 1995, 192 pp. [5] Stucky G., MacDougal J. Science 247, 669 (1990)

The damage induced in porous low-k films by the integration process, e.g., ashing, dry etching, or wet cleaning, is a bottleneck in producing high-performance interconnects. For SiOCH low-k film, in order to suppress the damage, carbon species such as methyl groups have been introduced into the Si-O skeleton. In this study, we evaluated whether sufficient carbon species are introduced into spin-on dielectric (SOD) films using hydrofluoric acid (HF) treatment. Since the HF treatment is often used to remove damaged layers of low-k films, the film with sufficient carbon species will survive longer in a HF solution. Here we demonstrate that HF-resistant SOD films, produced by sol-gel process, can be obtained by introducing an organosiloxane containing C_xH_y (x>2) groups, which interact weakly with methyl groups, into methyltrimethoxysilane-based (MTMS-based) precursor solution. The SOD films used in this study were prepared as follows. First, a precursor solution containing various silica sources (mainly alkoxysilanes), a catalyst, water, and a surfactant (to act as a pore template) was prepared by sol-gel process. Then the solution was deposited on a Si wafer by spin-coating, followed by pre-baking at 150 °C. Finally, the films were exposed to UV light at 370 °C in vacuum. The obtained film was dipped into a HF solution for several minutes. The simplest way to introduce methyl groups into SOD film by sol-gel process is the use of methyltrialkoxysilane as a silica source. Thus in order to simplify the interpretation of the results, three simple cases using MTMS-based precursor solutions were investigated and compared: (i) using only MTMS as the silica source, (ii) using MTMS and tetraethoxysilane (TEOS), and (iii) using MTMS, TEOS and an organosiloxane containing C_xH_y groups. When using only MTMS as the silica source, the film disappeared after 5 min HF etching. In addition, excessive film shrinkage occurred and the k-value became 2.2. The addition of TEOS to MTMS resulted in a reduction in film shrinkage, and the k-value decreased to 1.9 at 20% TEOS content. In the HF treatment, however, the film disappeared within only 2 min HF etching. When a moderate amount of an organosiloxane containing C_xH_y groups was added to the mixture of MTMS and TEOS, the HF resistance of the film was significantly improved without a large increase in the k-value. The film was almost insoluble in a HF solution for more than 10 min and the thickness change was less than 10 nm; the k-value was 2.0. Since the only difference among three cases is the combination of silica sources, it is suggested that these behaviors can be explained by considering side-chain interaction. The result indicates that controlling interactions among the side-chains of silica sources is an effective way of producing highly HF-resistant low-k films by sol-gel process. Further characterizations, including FTIR, AES, and XPS studies, will be discussed in detail.

Due to the decreasing width and thickness of interconnects with each integrated circuit generation, electromigration phenomena in the different monocrystalline parts of the interconnects become of increasing interest. We investigate how voids penetrating a monocrystalline silver film are affected by electromigration. Based on the kinetic Monte Carlo method, we developed a three dimensional, atomistic simulation model that is fast enough to access the desired time scales to investigate electromigration phenomena on an atomistic scale. A clear dependency between the strongly facetted non-equilibrium shape of the voids and the crystallographic orientation of the film is found, which is in accordance with experimental results on bicrystalline silver wires. This work has been supported by German Science Foundation within SFB 616: Energy Dissipation at Surfaces.

As critical dimensions decrease, key dimension-related dielectric etch challenges include critical dimension (CD) uniformity of via and trench and etch depth profile. Especially, the BDIII (black diamond; k=2.55) dielectrics requires the etching to consider the sensitivity of the films to compositional modification, polymer interactions with the pores, and diffusion effects possible. Using N2/O2 plasma at 60degree C to modify the M1 trench profile lowered the RC delay to 14% compare to the condition with CO2 plasma at 60degree C. Using the DHF solution to clean the etching residues in the dual damascene structure reveals >97% yield with the very tight range of via chain resistance.

Recently, the 3-dimensional structure having high aspect ratio has been introduced in DRAM and multi-stacked flash memory devices. Therefore, the source/drain and interconnect contacts should be formed vertically on side wall of trench. Typically, NiSi, CoSi2, and TiSi2 have been used for contact materials. Among them, NiSi has relatively low Si consumption ratio, low transformation temperature, and low sheet resistance rather than other silicides. The sputter or evaporator representing PVD method is good choice to deposit Ni thin film because of high quality film without impurities but not favorable in the structure having high aspect ratio. However, the chemical deposition method likes CVD or ALD exhibits good step coverage of films on the 3-dimensional structure. Therefore in this study, we will report the results of the plasma enhanced atomic layer deposition (PEALD) to deposit Ni thin films with low impurities for silicide formation. And we already carried out several analyses such as field emission scanning electron microscopy (FESEM), transmission electron microscopy (TEM), Auger electron spectroscopy (AES), four point probe (FPP), and X-ray diffraction (XRD) to investigate electrical and chemical properties. The nickel thin film was deposited on Si substrate by PEALD using a bis(ethyl-cyclopentadienyl)nickel; [Ni(EtCp)2] as a precursor and ammonia (NH3) plasma as a reactant at 250 °C. In order to investigate the properties of phase transformation, we annealed the Ni thin films deposited on Si at various temperatures. The process window of Ni PEALD was derived from linear growth rate vs. deposition cycle. The film thickness was calculated by X-ray reflection. The Ni films were deposited on both uncleaned Si and HF cleaned Si substrates. The linear growth rates were extremely low on both substrates. However, the initial growth rate of Ni film deposited on uncleaned Si substrate is faster than that on HF cleaned Si substrate. Therefore, the number density of Ni clusters was higher on uncleaned Si than that on HF cleaned Si substrate. For impurities, about 15 % of carbon and 8 % of nitrogen were detected in ~ 15 nm of Ni film by AES. After annealing at 400 °C, the sheet resistances of Ni film decreased and nitrogen concentration in the Ni film decreased. Over annealing at 400 °C, the nitrogen concentration was reduced and it resulted in the film resistivity recovered as much as bulk Ni. The Ni films were also deposited on a trench having 1:8 of aspect ratio and 50 nm hole diameter in order to observe the property of film step coverage.

Chemical Mechanical Planarization (CMP) is a critical process for semiconductor manufacturing. It is widely used to ensure planarity and, for many conventional semiconductor processing systems, it has been characterized experimentally in terms of critical polishing parameters (1) yet the new CMP applications on Ge, GaAs and polymeric dielectrics are still based on trial and error approach to deliver the best slurry formulations. CMP performance must be predictable in advance to design the most effective slurry compositions and optimized process performance (2). The aim of this study is to predict the CMP performance through chemically modified thin film characterization on new semicnductor materials and synthesize slurries containing surfactant systems to achieve optimal performance. While the new generation semiconductor film surfaces were studied through FTIR-ATR technique for the formation of the chemically modified surface layers, the affect of self assembled surfactant aggregates were evaluated through adsorption (total organic carbon analyses) and particle stability, CMP performance was evaluated through frictional evaluations as well as material removal rate and surface finish quality post polishing experiments. Key words: CMP, Slurry Design, Silica Nanoparticles 1) Robert, D., White, Andrew J., Mueller, Minchul S., Douglas G., Vincent P., and Chris B.R. (2011), Measurement of Microscale Shear Forces during Chemical Mechanical Planarization Tufts University, Medford, Massachusetts 02155, USA, Journal of The Electrochemical Society, 158 (10) H1041-H1051. 2) Basim, G.B., Vakarelski, I.U., and Moudgil, B.M. (2003), Strategies for Optimization of Chemical Mechanical Polishing (CMP) Slurries, The Journal of Dispersion Science and Technology, 36(6),pp. 43-48.

In poly-crystalline wires, the complex network of grain boundaries provides good diffusion pathes for electromigration (EM) [1]. In single-crystalline nanowires, however, other diffusion mechanisms carry the mass transport [2]. To understand the interplay of the different diffusion processes, it is necessary to study EM in test structures with a clearly defined and isolated grain boundary. Here we present a novel approach of fabricating Ag nanowires with a single grain boundary, using the combination of epitaxial growth and focused ion beam (FIB) milling. Depending on the growth parameters, bi-crystalline Ag islands with a single grain boundary between Ag(111) and Ag(001) areas can be grown on Si(111) surfaces [3]. Such islands can be structured into nanowires by eroding material with a Ga FIB. The conductance of the Si surface is dramatically increased by Ga doping during the FIB milling process. To avoid leakage current through the substrate surface, the Ag islands are grown on the device layer of a silicon on insulator substrate (SOI) and a novel method of structuring the wire by cutting through the device layer with trenches down to the insulating oxide layer, was developed. The EM in such bi-crystalline test structures can be monitored in-situ by capturing an image sequence with a scanning electron microscope (SEM) during electrical stressing. This allows to observe the time development of voids and hillocks. Amongst stationary, growing and shrinking, voids, some voids were found to propagate along the nanowire and merge with other voids. In particular, voids were observed to overcome the grain boundary. The shape of voids is strongly influenced by the crystal lattice symmetry. In the Ag(001) part of the wire, rectangular voids have been found, whereas voids in the Ag(111) part show a pronounced triangular top view shape. [1] B. Stahlmecke and G. Dumpich, J. Phys. Condens. Matter 19 (2007) 046210; [2] B. Stahlmecke et al. Appl. Phys. Lett., 88 (2006) 053122; [3] D. Wall et al. IBM J. Res. and Dev., 55 (2011) 9

While the spacing of interconnect structures has continued to scale with technology generation, operating voltages have remained almost constant. Consequently, the electrical field that dielectrics must support has increased and is approaching 1 MV/cm. At the same time, new lower dielectric constant materials with lower electrical breakdown strengths are being introduced to improve the R-C performance of interconnect structures. As a result of these combined factors, time dependent dielectric breakdown (TDDB) has become a critical aspect of the reliability of interconnect structures. In many of the models for TDDB the electron flux through the dielectric directly determines the lifetime of a structure. Hence, a fundamental understanding of the conduction mechanisms that operate is needed to determine how parameters such as bias and temperature influence breakdown. The talk will review the current understanding of dielectric leakage in Low K dielectrics. Previous studies have shown that a Poole-Frenkel mechanism in which trap mediated electron hopping controls the initial leakage current in many of the current Low K dielectrics. It is also known that the leakage mechanism can change during the breakdown process. We will show new data from a detailed study of the temperature and field dependent leakage currents that indicates that trap generation during the breakdown process results in a continuous reduction of the apparent trap depth and an eventual switch to a mechanism consistent with trap assisted tunneling. Results showing the impact of dielectric structure and extrinsic agents such as moisture and copper ions on the breakdown process will also be presented and used to discuss factors that limit breakdown lifetime in interconnect structures. Acknowledgement: This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

Electrical leakage in low-k/Cu interconnect structures is becoming a growing vital concern as the nano-electronics industry moves to increasingly tighter metal spacingâ?Ts for sub 16 nm technology nodes and continues to replace dense SiO2 and Si3N4 dielectrics with low density / porous SiOC:H and SiCN:H â?olow-kâ? dielectric materials. In order to understand the various possible leakage mechanisms in low-k/Cu interconnects, knowledge of the band gap and basic band alignment between low-k dielectric materials and Cu is needed but has gone largely unreported. Additionally, the energy levels of defects likely contributing to electrical leakage in low-k dielectrics is needed and has been largely unexplored. In this regard, we have utilized Reflection Electron Energy Loss Spectroscopy (REELS) to determine the band gap of numerous low-k dielectrics and X-ray Photoelectron Spectroscopy (XPS) to measure the Valence Band Alignment and Schottky Barrier at interfaces of importance to Cu/low-k interconnects. These measurements enable the determination of the â?oband diagramâ? for assessing the energy landscape for various different electrical leakage mechanisms in Cu interconnect structures. Specifically, we have utilized XPS to determine the Schottky Barrier between Cu and low-k dielectric SiOC:H interlayer dielectrics and low-k SiCON:H Cu capping layers deposited on Cu via Plasma Enhanced Chemical Vapor Deposition (PECVD). We have also utilized XPS to determine the valence band alignment at SiCN:H/SiOC:H interfaces. Lastly, REELS has also been utilized to determine the energy level of various defects in pristine and sputter damaged low-k SiOC:H dielectrics that are believed to contribute significantly to leakage in low-k/Cu interconnects.

Back end of line dielectrics with low dielectric constants are needed for current and future ULSI technology nodes. [1,2] However an understanding of the defects which limit reliability and cause increased leakage currents is not yet developed for these low-k films. As reported previously [3], we have observed several performance limiting defects with electron spin resonance (ESR) that correlate quite strongly to leakage current measurements. We have recently made significant progress in developing a fundamental understanding of how film composition and processing parameters affect specific defects and how these defects are related to leakage currents. In this new work we utilize ESR and leakage current measurements to investigate of fifty dielectrics with potential use as ILDs and ESLs. Films investigated include various compositions of SiOC, SiO2, SiN, SiCN, and SiC deposited with plasma enhanced chemical vapour deposition on 300mm (100) silicon wafers. They exhibit a wide range of dielectric constant, sample chemistry, and porosity. We examined multiple variations in processing conditions, including UV curing, post deposition anneals, and variations in film chemistry. In the case of films that contain nitrogen (SiN and SiCN) we observe silicon dangling bonds. When the nitrogen content is increased in these films we observe a decrease in ESR defect density (order of magnitude) and leakage currents (several orders of magnitude). We observe a very close correlation of defect density and leakage current in SiC films that receive different post deposition annealing temperatures. The close correspondence strongly suggests that the defects observed by ESR are almost certainly responsible for the leakage currents in general and possibly defects responsible for limiting the dielectric reliability, such as time dependent dielectric breakdown and stress induced leakage current. Additionally we have also linked electrically detected magnetic resonance (EDMR) spin dependent trap assisted tunneling measurements to the defect spectrum observed with conventional ESR. This close correspondence directly links the defects observed in conventional ESR with leakage current in general and likely reliability issues such as time dependent dielectric breakdown and stress induced leakage currents. [1] K. Maex, D. Shamiryan, F. Iacopi, S.H. Brongersma, and Z.S. Yanovitskaya, J. Appl. Phys, 93, 11 (2003). [2] W. Volksen, R.D. Miller, and G. Dubois, Chem Rev. 110, 56 (2010). [3] B.C. Bittel, P.M. Lenahan, and S.W. King, Appl. Phys. Lett., 97, 063506 (2010).

As the semiconductor industry strives to keep pace with Mooreâ?Ts Law, new materials with extreme properties are increasingly being introduced and tighter control of these material properties is being demanded. Low dielectric constant (i.e. low-k) materials are one specific example. Lower k materials are desired to replace SiO2 (k=4.0) as the interlayer dielectric (ILD) and SiNx:H (k = 7.0) as the Cu capping diffusion barrier layer in order to reduce resistance-capacitance (RC) delays in nano-electronic Cu interconnect structures. Typical methods for producing low-k materials consist of introducing controlled levels of nano-porosity via carbon doping during plasma enhanced chemical vapor deposition (PECVD) of SiO2 and SiNx:H matrix materials. While lowering k, the introduction of nano-porosity can seriously compromise the performance of these layers in their respective applications. In this presentation, we will demonstrate that critical thresholds in nano-porosity exist for the diffusion of water and solvents through low-k materials. Specifically, we utilize Fourier Transform Infra-Red (FTIR) spectroscopy, to show that the concentration and size of nano-pores formed in low-k a-SiC(N):H dielectric materials is controlled by the concentration of terminal Si-CH3 bonding versus Si-C/N network bonding. We further combine moisture / solvent diffusivity measurement with x-ray reflectivity (XRR) and positron annihilation lifetime spectroscopy (PALS) to demonstrate that low-k a-SiC(N):H dielectrics become poor moisture diffusion barriers at mass densities < 2.0 g/cm3 and when the pore size approaches that for the molecular diameter of water. Similarly, we show that low-k a-SiOC:H ILDs become easily penetrable by solvents and susceptible to downstream processing damage when the pore diameter approaches the size of the solvent and pores become interconnected. The implications of these critical nano-porosity thresholds on continued scaling of low-k diffusion barrier and ILD materials will be discussed as well as methods for overcoming these limitations.

Adhesion testing of low- κ thin films used in semiconductor manufacturing provides valuable information on the mechanical integrity of these film/substrate systems. During this test, samples are subjected to large lateral stresses which are representative of stresses encountered in the manufacturing process and thermal cycling in the use case of integrated circuits. The primary techniques for adhesion measurements are Four-point bend (4PB) and Nanoindentation (Scratch). The scratch test has an advantage over the 4PB technique; sample preparation process is simpler, can be performed on a wafer and the time required to perform the test is less. Further, scratch data analysis is much simpler unlike 4PB which is impacted by several parameters such as notch depth, pressing speed, specimen width, edge polishing etc. The purpose of this study was to identify key elements of variability in the scratch testing of thin films and to construct a test protocol that minimizes sources of variability. The developed scratch test is a three-step process consisting of a single-line original surface topography scan, the ramp-load scratch test, and a single-line residual deformation scan. Automatic failure detection has been incorporated into the test so that the tip is not dragged through the substrate material causing damage to the tip radius â?" a primary cause for variation in scratch results. In addition, this three-step scratch process allows clear identification of the failure point and allows the observation of deformation mechanisms leading up to initial failure. Finally, results from the scratch process on a new class of spin-on ultra low- κ films (1.8â?¤kâ?¤2.4), with film thicknesses of 350 nm, will be presented. These data show that using sharp tips with effective tip radii on the order of 300nm are ideal for measuring the evolution of failure on low-k films during a scratch test. Sharp tips allow the stress concentration to gradually evolve from the film to the interface during the scratch test and they provide an evolution of failure as the test progresses. Results on the low-κ materials show that the process provides minor failure in the films followed by interface separation and total film failure. The new scratch process provides a foundation for further evaluation of the mechanical integrity of low- κ films.

Porous thin films have a wide range of industrial applications, such as low-k dielectric materials for microelectronics, anti-reflective coatings, purification membranes, and sensors. To obtain high porosity, matrix precursors and porosity templating agents are usually co-deposited, and the porogen is subsequently removed. This one-pot thin film deposition process can limit the range of accessible properties, a possible drawback for applications which require divergent properties, such as insulators in the back-end-of-the-line. Indeed, interlayer dielectrics are required to have a low k while maintaining good mechanical properties, process damage resistance, low leakage and high breakdown voltage. In this regard, we believe independent control of both the matrix backbone and the pore surface chemistry is fundamental. We developed an alternative strategy to synthesize composite porous thin films, based on our recent work on Post Porosity Plasma Protection[1,2]. We first deposit the porous backbone and then coat the pore surface with a thin pore-surface-layer of a second material. This allows us to design films in which we can tune the chemical composition of the backbone and pore surface independently. We applied this concept to generate composite porous low-k films using a porous organosilicate as the backbone and a wide variety of materials, ranging from organic polymers to ceramics, as the thin pore-surface-layer. In this presentation we will detail the preparation of composite materials with isotropic compositions and retention of high levels of porosity. We will then describe how the thin pore-surface-layer can be tuned to control the properties of the composite film, including trends in electrical properties, mechanical properties, pore size distribution and plasma resistance. We believe this concept has huge potential wherever control of the pore surface is required. _[1] T. Frot, W. Volksen, T. Magbitang, S. Purushothaman, R. L. Bruce, S. Cohen, M. Lofaro, G. Dubois, Future Fab Intl 2011, 39, 67. _[2] T. Frot, W. Volksen, S. Purushothaman, R. Bruce, G. Dubois, Adv. Mater. 2011, 23, 2828.

CVD of Manganese Selective Capping Layers. Weak adhesion between copper and dielectric capping material can lead to rapid electromigration of Cu and early failure of the wiring. A self-aligned CVD-manganese (Mn) capping process can strengthen the interface between Cu and dielectric insulators without increasing the resistivity of the Cu. A vapor mixture of a Mn precursor and hydrogen deposits Mn selectively on copper but not on insulators. Deactivation of the insulator surfaces is accomplished by exposure to vapors containing reactive methylsilyl groups. Mn at the Cu-insulator interface greatly increases the strength of adhesion between the Cu and the insulator. The debonding energy is found to increase approximately linearly with the amount of Mn at the interface, up to values so large that the interface could not be broken apart. This selective CVD Mn capping process should increase the lifetime of advanced copper interconnections. Self-Aligned Barriers and Void-free Filling of Narrow Vias with Copper. We present a CVD process for void-free bottom-up filling of narrow trenches and vias with copper or copper-manganese alloy. A conformal, smooth and continuous layer of CVD Mn₄N is first deposited inside the trenches and vias. The Mn₄N serves as a barrier against diffusion of copper, water and oxygen, and also enhances the adhesion between Cu and dielectric insulators. In addition, the Mn₄N adsorbs iodine atoms and then releases them to act as a catalyst floating on the surface of a growing copper layer. As a result, void-free bottom-up filling of pure Cu or Cu-Mn alloy has been achieved in trenches narrower than 15 nm with aspect ratios up to 9:1. Upon post-annealing, Mn in the alloy diffuses out from the Cu and forms a self-aligned barrier in the surface of the insulator. The resulting pure copper returns to its expected low resistivity. This process should provide nanoscale interconnects with higher speeds and longer lifetimes. Highly Conformal Cu-Mn Seed Layers for Through-Silicon Vias. Through-silicon vias (TSV) will speed up interconnections between chips. We made conformal, smooth and continuous seed layers in TSV holes with aspect ratios greater than 25:1. Following a rapid ALD process that forms a conformal insulating layer of silica inside the silicon vias, Mn₄N is deposited conformally on the silica surface by CVD. Mn₄N forms a diffusion barrier and provides strong adhesion between the silica and the subsequently-deposited Cu. Conformal Cu or Cu-Mn alloy seed layers are then deposited by the iodine-catalyzed CVD process.

Due to the continuous improvements in Physical Vapor Deposition (PVD) technology, the industry-established PVD-TaN/Ta barrier will still continue to be used at the 22nm technology node. However, for further technology scaling, deposition techniques such as Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD) will most likely be needed to satisfy the challenging sidewall coverage and film continuity requirements for very thin barrier layers. Recently, CVD of Mn on dense silica substrates has been studied and proposed as an alternative because of its conformal step coverage and diffusion barrier properties. To use Mn-based barriers in advanced technologies, still it will need to be formed on low dielectric constant (low-k) materials. In this work, we have studied the formation of Mn-based layers on different low-k substrates (porous SiCOH) by CVD and PECVD-Mn using (EtCp)2Mn precursor. Based on physical characterizations, a Mn incorporation mechanism is proposed and the limitation of the layer formed as a copper diffusion barrier for advanced interconnect technology is discussed.

The continuous size shrinkage of ultra-large scale integration (ULSI) would require several innovations to device architectures and its materials. Cu/Low-k interconnects will be the main components in the back-end-of-line (BEOL) process, however, novel materials and processes should be developed to realize the reliable interconnect systems. For example, Ta/TaN layer are currently used as diffusion barrier to prevent copper atoms/ions from diffusing to low-k dielectrics. However, Ta/TaN barrier layers should be replaced with other materials because of the three issues associated with the shrinkage of Cu lines. One is the high resistivity of Ta and TaN, which increases the total resistivity of interconnects when the width of wire shrinks furthermore. The second issue is the high interface energy of Cu/Ta, which causes poor adhesion of Cu and will enhance the electro-migration (EM) failure. The third issue is the poor step coverage of PVD-Ta/TaN layer. In order to solve these issues, we have chosen the atomic layer deposition (ALD) cobalt film or cobalt film with tungsten addition [Co(W) film] as the novel diffusion barrier layer, because cobalt is thought to have low resistivity and low interfacial energy with copper. In fact, Co(W) film formed by electroless plating is applied as metal cap of Cu lines to enhance EM life time. In addition, ALD is favorable for forming conformal film, which is suitable for trenches with high aspect ratio. We demonstrated to form low-resistive Co and Co(W) films with W-composition of 10-20 % at 300-400 °C by ALD using oxygen-free precursors. We controlled the composition of Co(W) film by the substrate temperature and the ALD sequences. The resistivitis of Co(W) films were 30-60 µΩ-cm, which were smaller than that of TaN (136-200 µΩ-cm). We also studied the barrier property of Co and Co(W) films against Cu diffusion by annealing Co/Cu or Co(W)/Cu bilayer at 400, 500 and 600 °C. We found that the Co(W) films have better barrier property than Co film and comparable to TaN. Investigation of structure by transmission electron microscopy (TEM) revealed that tungsten atoms were segregated in inter-granular boundaries in Co(W) films. Therefore, the improvement of barrier property was derived from stuffing of grain-boundary. We have also examined the adhesion of Cu onto Co(W) film by observing the contact angle of small size Cu grain on liner metals. Co(W) showed better adhesion than Co and Ta. According to our results, low-resistive Co(W) film is one of the promising material for barrier/liner in further shrinking interconnects since it has good barrier property, good adhesion of Cu, and low resistivity.

Copper damascene technology has been widely used for interconnecting microelectronic circuits. Barrier layers such as tantalum nitride (TaN) or tungsten nitride (WN) can prevent the diffusion of copper into surrounding insulators and also protect copper from oxidation. As interconnects are scaled to smaller sizes, sputtering has more difficulty placing thin, conformal and continuous seed layers of copper on the barrier layers prior to electroplating. Chemical vapor deposition (CVD) can make thin, conformal and continuous seed layers of copper, but adhesion between CVD copper and nitride barriers has been found to be too weak. The adhesion at the interface between two metals is expected to be strong if their lattices match both in structure and size. Because of the near-perfect match between the lattice structures of copper and face-centered cubic (fcc) cobalt nitride (Co4N), copper adheres strongly to fcc Co4N. At the same time, cobalt nitride adheres strongly to nitride barriers. Thus fcc-Co4N can serve as an adhesion-enhancing layer between TaN or WN and copper seed layers. This fcc phase of Co4N was prepared by chemical vapor deposition (CVD) using a cobalt amidinate precursor and a reactant mixture of ammonia (NH3) and hydrogen (H2) at substrate temperatures from 100 to 200 oC. The N/Co atomic ratio and the phase of cobalt nitride films can be modified by adjusting the ratio of the co-reactant gases NH3 and H2. The cobalt nitride films prepared by CVD are smooth, highly conformal inside holes with aspect ratios over 30:1, and stable against intermixing with copper up to at least 400 oC. CVD fcc Co4N shows very strong adhesion to CVD copper deposited on top of it, as well as to substrate nitride barriers under it. These CVD copper films can be used a seed layers for filling the copper lines by electroplating. Alternatively, copper lines can be created by bottom-up filling of narrow trenches and vias using iodine-catalyzed CVD of copper. Thus CVD Co4N interlayers between copper and surrounding diffusion barriers can stabilize copper wires against failure by electromigration.

Recently, many platinoid metals like platinum and ruthenium have been used as an electrode and a directly electrochemical plateable copper seed layer of microelectronic devices because of their good electrical and chemical properties. However the material cost of Ru is very expensive and during chemical deposition it usually takes long initial nucleation time on SiO2. Therefore many researchers have focused on how to enhance the initial growth rate on SiO2 surface. There are two methods to deposit Ru film with atomic layer deposition (ALD); the one is thermal ALD using dilute oxygen gas as a reactant, and the other is plasma enhanced ALD (PEALD) using NH3 plasma as a reactant. Generally, the film roughness of Ru film deposited by PEALD is smoother than that deposited by thermal ALD. However, the plasma is not favorable in the application of high aspect ratio structure. In this study, we used a bis(ethylcyclopentadienyl)ruthenium [Ru(EtCp)2] as a metal organic precursor for both thermal and plasma enhanced ALDs. And we have tried to reduce the initial nucleation time with several methods such as Ar plasma pre-treatment for PEALD and usage of sacrificial RuO2 under layer for thermal ALD. In case of PEALD, some of surface hydroxyls were removed from SiO2 substrate during the Ar plasma treatment. And relatively high surface nitrogen concentration after first NH3 plasma exposure step in ALD process was observed with in-situ Auger electron spectroscopy (AES). This means that surface amine filled the hydroxyl removed sites by the NH3 plasma. Surface amine played a role as a reducing site and not a nucleation site. Therefore, the precursor reduction was enhanced but the adhesion property was degraded. In case of thermal ALD, a Ru film was deposited from Ru precursors on the surface of RuO2 and the RuO2 film was reduced from RuO2/SiO2 interface to Ru during the deposition. The reduction process was controlled by oxygen partial pressure in ambient. Under high oxygen partial pressure, RuO2 was deposited on RuO2/SiO2, and under medium oxygen partial pressure, RuO2 was partially reduced and oxygen concentration in RuO2 film was decreased. Under low oxygen partial pressure, finally RuO2 was disappeared and about 3 % of oxygen was remained. Usually rough surface was observed with longer initial nucleation time. However, the Ru deposited with reduction of RuO2 exhibits smooth surface and was deposited quickly because the sacrificial RuO2 has no initial nucleation time on SiO2 and played a role as a buffer layer between Ru and SiO2.

At the present time, the integration of ultra low-k (ULK) inter-layer dielectrics (ILD) is challenged by their fragility, and the consequent fractures induced in them by assembly with substrate. The cause for the fractures, referred to as "chip-package interactions" (CPI), or more importantly, the optimal package configuration to prevent them, are not fully understood at the present time. A part of the challenge is the availability of simulation tools that enable one to arbitrarily nucleate and propagate cracks in structures in general, and ILD structures in particular. Towards this end we utilize analytical models based on classical elasticity theory as well as sophisticated numerical techniques that are capable of nucleating cracks at arbitrary locations within a structure and propagating cracks along arbitrary paths to analyze risk of fracture in ILD stacks due to assembly with an organic substrate or a die stack. Specifically, we apply a recently developed meshless computational strategy to model cracks as enrichments on underlying continuous fields. We couple the numerical solution scheme with a cohesive zone model of damage to predict crack initiation sites as well as to predict the crack propagation path within the structure. We utilize the computational tool to relate the risk of fracture to groups of non-dimensional parameters that control the flexure of the die-substrate assembly as well as the shear deformation of the solder joints. We draw conclusions on flexure or shear being the primary cause for ILD fractures. We conclude with a discussion of related issues arising in 3-D stacked-die packages as well as wire-bonded ULK dies.

Through silicon vias (TSV) function as 3D interconnects that pass through a wafer or chip allowing electrical three-dimensional connection integrated circuits (3DICs). These 3DICs consist of vertically-stacked integrated circuits, achieving higher speed, better form factor, increased functionality, and heterogeneous functions all in one package. With the demand for TSVs growing, making reliable TSVs for 3DICs is important for integration success. The purpose of this work is to observe the effect of thermal stresses on through silicon vias using novel inspection techniques without cross sectioning the sample. Typically, TSVs contain high-aspect-ratio metals embedded in silicon and electrically isolated from the silicon by a layer of dielectric liner, hence forming a metal-oxide-semiconductor structure. Thus visible light and electron microscopy are not practical for inspecting defects in the metallization. The high penetrating power of x-rays, however, is well-suited for for penetrating all materials easily. The 8keV laboratory-based x-ray microscopy is demonstrated to have advantages over other methods of inspecting through silicon vias (TSVs), providing resolution as high as 50 nm for three-dimensional (3D), non-destructive imaging. This allows inspection on the same TSV structures after different treatments, such as before and after annealing. In addition, the combination of two-dimensional (2D) radiography and 3D computed tomography provides fast, reliable access to structural information. In this study, TSV structures with intentional defects (e.g. pre-existing void and incomplete filled) and complete filled without void were used. The intentional defects are observed by the x-ray microscope before annealing. The same TSV structures are subsequently annealed to 225oC and 300oC respectively and then inspected by x-ray microscopy. Delamination, extrusion, and void growth are observed in these TSV structures, while the completely-filled TSVs remained void free after annealing.

One key to enable the successful implementation of 3-D interconnects using Through-Silicon Via (TSV) is the control of the mechanical stresses. The synchrotron-sourced X-ray microdiffraction technique has been recognized to allow some important advantages compared to other techniques, namely stress measurement of individual Cu TSV as well as the silicon substrate surrounding it simultaneously at the submicron resolution, stress measurement in situ during annealing and while Cu TSV is still buried under the silicon substrate (mimicking the conditions of real device). Using this approach, we have studied Cu TSV samples from Hynix, Inc. as well as from SEMATECH and found interesting differences in the stress states of the Cu TSV. We studied the stress evolution throughout its thermal history, and proposed an explanation of the observed differences. This understanding could lead to improved stress control in Cu TSV as well as to reduce the impact to the silicon electron mobility.

Silicon interposer is introduced into advanced electronic packaging to meet the requirements for reducing data latency, enhancing power management, increasing I/O pin density with constricted footprints. In a typical silicon interposer configuration, various dies are placed laterally on top of a single interposer to perform different functions, e.g. logic, memory, and analog. The active silicon dies and the passive silicon interposer are integrated with arrays of micro-bumps. Multi-level damascene copper wires connect different dies horizontally in the interposer with dense connectivity. Through-Silicon-Vias (TSVs) provide the pathways through the passive interposer. The die-interposer stack is packaged on BT substrate using C4 bumps. The packaging process for this silicon interposer stack involves several thermal cycles within the intermediate structures. Due to the large difference in thermal expansion coefficients for the constituent materials, thermal mismatch stresses are generated at different process steps and rebalanced under different structural constraints during the packaging process. The residual stresses may lead to yield loss and reliability concerns. Thus it is important to understand the dependence of stress generation and evolution with respect to process conditions and stack geometries for reliable designs. A process oriented stress modeling methodology is developed to investigate the stress evolution during the silicon interposer packaging process. An FEM based 3D TCAD simulator is used to perform the process steps to construct the silicon interposer stack in chronological order. These steps include BEOL process steps for active silicon dies, TSV fabrication for passive silicon interposer, micro-bumping and reflow process for integrating active dies and passive interposer, C4-bumping and reflow for interposer BT substrate stacking, and epoxy mold curing for interposer encapsulation. Stress simulations are carried out for each process step to obtain accurate stress evolution history. To resolve micron features within millimeter structures, the modeling strategy employs symmetry conditions, and equivalent materials for regions away from structure features of interest. The detailed structure includes 3x3 arrays of micro-bumps, TSV arrays, and C4 bumps with multiple material layers at the stack corner. Important design parameters include die thickness, side edge clearance, diameters, and pitches. For different silicon interposer configurations stress hotspots are analyzed and compared. Packaging process and structure design guidelines are extracted for minimizing reliability risks.

Through-silicon via (TSV) 3-D packaging and integration present many new opportunities and challenges for copper (Cu) chemical mechanical polishing (CMP) applications. Increasingly popular via-middle TSV integration schemes often involve a CMP step for controlled planarization of Cu and dielectric pillar structures that result from upstream backside wafer thinning operations, including wafer bonding, followed by silicon grinding/polishing, followed by a silicon recess etch to expose the vias from the wafer backside, followed lastly by deposition of various dielectric layers for isolation. Pillar planarization during this CMP step can be a complicated process that depends substantially on many factors, which include pillar geometry, density and layout, as well as several salient CMP process parameters. To date, there has been little or no theoretical study undertaken to elucidate the mechanisms at play for this planarization process. This paper presents a pillar planarization model that yields insight into this Cu-dielectric via reveal CMP process, including the role of pillar size and aspect ratio, effective pattern density, the ratio of Cu to dielectric material comprising the pillar, and the effects of CMP parameters such as polishing downforce and slurry selectivity. Model predictions are compared to actual data from TSV wafers with good agreement. Our presentation discusses the predictive capabilities of the model regarding its ability to influence our CMP process and slurry development for this important and burgeoning TSV CMP application.

The semiconductor industry is witnessing a major shift towards heterogeneous 3D integration. Whether companies are active in high performance or consumer markets systems, 3D offers a myriad of opportunities. We will review the different opportunities, indicate process availability and remaining challenges, such as stacking and cooling, from a technology perspective.

Stretchable and robust conductors are key and inevitable elements in the development of wearable and ambient electronics, which have many potential applications in biological devices, robotic skins, wearable displays and power-generating systems. The conductive rubber composed of single walled carbon nanotube (SWNT) and fluorinated copolymer is one of the promising materials as elastic conductor for these applications with its mechanical stretchability and robustness. In this study we succeeded in the micro-fabrication of the conductive CNT rubber on the polydimethylsiloxane (PDMS) substrate by combining lithography technique and transfer process. This process is advantageous to implement the conductive CNT rubber interconnects into the integrated circuits containing the transistors, capacitors and/or sensors of nano-materials and organic materials. Firstly we deposited thin and flat film of conductive CNT rubber on Si substrate by spray coating of buckey gel. In the film, SWNT shows the configuration like trunks of a tree enabling simultaneous realization of a rubber-like mechanical properties and electrical conductivity. To achieve the surface flatness enough for conformal resist coating, the film is hot-pressed by mirror-like finishing plate. AFM observation revealed that the surface roughness is less than 50 nm after planarization. Then, micro-fabrication process is carried out on the SiO2/Si substrate. The conductive CNT rubber is patterned by reactive ion etching with oxygen plasma with FOX16 as etching resist. Finally the patterned conductive CNT rubber is transferred to a rubber substrate. In the transfer process, PDMS used as a stretchable substrate is spin-coated on the patterned structure. Then, the patterned conductive CNT rubber embedded in the PDMS is peeled off by dissolving SiO2/Si in KOH aqueous solution. In order to confirm the strechability and robustness of the conductive CNT rubber, we measured electrical resistance under various types of mechanical loadings, such as bending, twisting, tension and compression. We found that the resistance increase are in the range that transistor with thin CNT channel keeps normal performance up to the bending of 180 degree C, twisting of 720 degree C, tension of 50% and compression of 4 MPa, which is enough to withstand the loadings expected in the imminent environment. The fabrication process established here could be a key technology to realize the physically adaptable and durable integrated circuits with the conductive CNT rubber as interconnects.

We have succeeded in growing a multi-layer graphene (MLG) directly on SiO2 by annealing an amorphous carbon beneath a Co catalyst layer deposited by a conventional sputtering method. This method will enable us to form graphene interconnects directly on dielectric layers, and also have the possibility to form graphene channel for transistors without any complicated transfer processes. Cross-sectional transmission electron microscope (TEM) image clearly shows the lines of the graphene sheets like a highly oriented pyrolytic graphite (HOPG). X-ray diffraction (XRD) pattern (θ-2θ scan) shows (002) peak of graphite with (111) peak of Co, and the (002) peak of graphite exists even after a Co layer removal. These results suggest that the graphene sheets stack parallel to the SiO2/Si substrate plane due to the epitaxial growth aligned with the oriented Co layer. Furthermore, hard X-ray photoelectron spectroscopy (HAXPES) C1s spectrum reveals that the ratio of C=C sp2 peak is equal to nearly 100 %. The decrease of resistivity for the MLG film can be expected by the increase of sp2 fraction. In the conference, we will report on the latest data of resistivity for the MLG film. Acknowledgements This research is supported by the Japan Society for the Promotion of Science (JSPS) through its Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program). A part of this work was conducted at the AIST Nano-Processing Facility supported by Innovation Center for Advanced Nanodevices (ICAN), National Institute of Advanced Industrial Science and technology (AIST), Japan. References [1] M. Sato, M. Inukai, E. Ikenaga, T. Muro, S. Ogawa, Y. Takakuwa, H. Nakano, A. Kawabata, M. Nihei and N. Yokoyama; Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials (SSDM), Nagoya, 2011, pp763-764.

Jie Yu1, Guanxiong Liu1, Anirudha V. Sumant2 and Alexander A. Balandin1 1Nano-Device Laboratory, Department of Electrical Engineering and Materials Science and Engineering Program, University of California, Riverside, California 92521 USA 2Center for Nanoscale Materials, Argonne National Laboratory, IL, 60439 USA Graphene is a promising material for future electronics owing to its high carrier mobility, thermal conductivity, saturation velocity and ability to integrate with almost any substrate. Graphene nanoribbons have been predicted to be superior to Cu in terms of resistance per unit length for use as on-chip interconnects. Graphene field-effect transistors (FETs) and interconnects built on SiO2/Si substrates reveal the breakdown current density, JBR, of ~1 A/nm2, which is ~100 times larger than the fundamental electromigration limit for the metals but still lower the values reported for carbon nanotubes. Although graphene has extremely high intrinsic thermal conductivity [1] the current-carrying ability of graphene devices is limited by the thermal bottleneck created by the thermally resistive SiO2. Here we report a study of the current-induced breakdown in graphene-on-diamond devices, and demonstrate that by replacing SiO2 with the synthetic diamond one can increase JBR of graphene by an order-of-magnitude, to above ~10 A/nm2. We used recent advances in the chemical vapor deposition (CVD) and processing of diamond by collaborating with Argonne National Laboratory for fabricating graphene devices on ultrananocrystalline diamond (UNCD) and single-crystal diamond (SCD) substrates with the surface roughness below 1 nm. It was found that not only SCD but also UNCD with the grain size D~5-10 nm can improve JBR owing to the increased thermal conductivity of UNCD at higher temperatures. The obtained results are important for graphene applications in interconnects [2] and communication applications [3-4]. The work in Balandin group at UCR was supported, in part, by DARPA â?" SRC Center on Functional Engineered Nano Architectonics (FENA). The use of the Center for Nanoscale Materials was supported by the U. S. Department of Energy under the contract No. DE-AC02-06CH11357. [1] A.A. Balandin, Thermal properties of graphene and nanostructured carbon materials, Nature Mat., 10, 569 (2011). [2] Q. Shao, G. Liu, D. Teweldebrhan and A.A. Balandin, High-temperature quenching of electrical resistance in graphene interconnects, Appl. Phys. Lett., 92, 202108 (2008). [3] X. Yang, G. Liu, M. Rostami, A.A. Balandin and K. Mohanram, Graphene ambipolar multiplier phase detector, IEEE Electron Device Lett., 32, 1328 (2011). [4] See details of the characterization at the web-site: http://ndl.ee.ucr.edu/

Managing mechanical stress and the understanding of reliability-limiting degradation mechanisms becomes increasingly important for microelectronic products applying advanced packaging technologies. Chip-package interaction (CPI) is a particular concern for backend-of-line (BEoL) stacks with porous ultra low-k (ULK) dielectrics and for novel 3D integration processes which include the formation of metal through-silicon-via structures and wafer thinning to less than 100 micrometers. Multi-scale materials data and in-situ microscopy studies are essential to establish kinetic models for damage evolution in Cu/ULK on-chip interconnect stacks. Double cantilever beam (DCB) testing is a technique which allows us to determine the energy release rate of unpatterned thin films, but some studies at patterned films and stacks have been reported too. For the DCB configuration, the test results in nearly pure mode I loading of cracks. Nanoindentation experiments are usually used to measure the elastic modulus of thin films and structures. However, this technique can be used to provide fracture toughness information as well. A wedge shape indenter is used to delaminate ULK films locally. The fracture energy associated with the indentation induced delamination is evaluated considering the pore densification process. A specific focus of the present work is to image crack propagation in complex thin film systems to better understand damage mechanisms in BEoL stacks of integrated circuits. For X-ray imaging with multi-keV photons, e. g. with Cu-Kα radiation in a lab-based X-ray microscope, sample dimensions have to be about 50 micrometers to be transparent for X-rays. Therefore, we designed a scaled-down mechanical testing system which allows us to work with smaller samples, loads and displacements. We demonstrate in-situ micro-DCB measurements within a nano X-ray computed tomography system (nano-XCT) on BEoL test structures. The test structures contain metallization layers with different interlayer dielectrics. This novel experimental configuration allows us to image cracks and crack propagation under load nondestructively with sub-100nm resolution. Based on the experimental observations, we show the potential of 4D microscopy for the study of sub-critical crack growth, as a basis for the explanation of degradation mechanisms and eventual failure of Cu/ULK stacks under mechanical load. The significant effects of adhesive failure and cohesive failure are shown and related to the mechanical properties of the ULK and to the stress state in BEoL structures. Implications for CPI related to advanced 3D stacking and second level assembly are discussed.

Mechanical stresses induced into the wafer by the fabrication process have always been of concern to semiconductor manufacturing. Recently, this issue is again gaining importance as one of the major yield distracters in near future. The responses to the ongoing CMOS downscaling process in backend of line (BEoL) and packaging technologies like integration of ultra-low-k materials and through silicon vias (TSVs) as well as wafer thinning for 3-D chip stacking further increase the sensitivity to stress-induced defects dramatically. Hence, rigorous control of the stress level is mandatory throughout the process of wafer fabrication, assembly, test, and service. State of the art in stress examination during wafer fabrication is the measurement of wafer bow and x-ray diffraction assessment. Unfortunately, both techniques lack on spatial resolution and cannot characterize the details in multi-layer stacks. Wafer bow just provides integral figures across a few square-cm of wafer area, while x-ray diffraction is limited to about 100 µm in square. However, the critical structures are orders of magnitude smaller. Alternatives like x-ray diffraction on synchrotron beam lines or electron diffraction are too expensive and/or restricted to crystalline materials. The fibDAC stress analysis method has been developed recently to overcome these drawbacks. By means of focused ion beam (FIB), a small trench as narrow as 30 nm width is milled into the structure to trigger stress relief in its vicinity. Capturing the corresponding deformation by high resolution SEM images and local digital image correlation, the original stress can be determined by automated finite element analyses. This paper reports the qualification of the fibDAC stress analysis method for industrial use. The new method is benchmarked against the established wafer fab tools like bow measurement and R&D tools like Raman spectroscopy. The results show good agreement when single layer systems are assessed. Afterwards, the advantages of the fibDAC stress analysis method are demonstrated on samples with patterned structures. Substantial differences are found in the local stress field of typical BEoL systems. The fibDAC stress analysis method provides sub-micron resolution. It is applicable to all materials used on the wafer. Moreover, it offers the potential of detailed analyses within multi-layer stacks. Eventually, a fibDAC analyses will not take longer than regular FIB/SEM inspections. Applied to test patterns in the scrip line, the method may well become part of quality control in regular wafer production as well as of all R&D activities on 3-D stacks to analyze the internal stress state and chip/package interactions.

Packaging advanced silicon devices has become increasingly challenging because the effects of stresses exerted on interconnect and through silicon via structures during processing and package assembly are not well characterized or understood. Accordingly, we describe a microprobe metrology which can precisely impose both normal and shearing stresses to localized regions of these structures. The intent is to quantitatively measure local stiffness, strength, deformation, and damage processes and relate them to stresses that may be experienced during device packaging or assembly of 3D structures. The specific focus of the present work is to quantitatively characterize the effects of shear stresses on copper pillars on interconnect structures containing selected dielectric layers, and the effects of normal stresses on the deformation and damage processes in through-silicon vias (TSVâ?Ts). We demonstrate measurements on a 28 nm node test die with copper pillars. The test dies contain eight layers of metallization, prepared in three different stack configurations with different dielectric porosities. The shear strength of the underlying stack structure under the pillar was measured at a range of temperatures. The dependence of the stack shear strength on stack dielectric porosity and temperature are discussed. In addition, failure analysis results using FIB cross-sections of the stacks are shown. The Cu pillar shearing experiments were also conducted at different probe tip heights in order to vary load mode mixity (the ratio of tensile to shear stress). The effects of varying mode mixity are addressed. FEA simulations were conducted to model shearing with different mode mixities. We then show how the microprobe metrology can be extended to involve compressive loading on 20 micron diameter TSVâ?Ts at a range of temperatures. The significant effects of temperature on the deformation and damage processes of the TSVâ?Ts are shown and related to the temperature dependence of the TSV metal and silicon fracture behavior. Implications for advanced packaging and assembly of 3D structures are considered.

Debonding and cohesive cracking is a serious challenge for the processing yield, dicing, packaging and in-service reliability of next generation interconnect structures in complex microelectronic devices. Surprisingly little quantitative characterization has been conducted on fracture processes in such complex structures together with the role of more complex environments (moisture) and loading (fatigue) conditions. In this research, two different specimens with different loading mode mixity (ratio of normal to shearing stress) and three die structures with different interconnect multilayer structures were tested to quantify the fracture energy and the weakest "microstructural" path in the multilayer interconnect. Two of the die structures contained "die seal" (crack stop) structures intended to increase the fracture resistance and we demonstrate that the fracture resistance increased dramatically in the presence of the die seal. We also investigated the weakest fracture path in other die structures containing 10 layer copper metallization and different dielectric layers. The failure path was characterized using AFM and XPS. In addition to critical fracture loading, cyclic fatigue loading was also applied to assess the effects of die seal structures. Implications for the integration of fragile dielectric materials and failure criteria that can be used in thermomechanical modeling and understanding damage resulting from chip-package interactions are presented.

The adhesion of polymeric materials to inorganic substrates is of critical importance in flip chip packing and emerging 3D stacking technology. When packaging flip-chips, the delamination of an underfill epoxy from a natively oxidized silicon substrate can lead to joint damage or ILD damage due to increased thermomechanical strain on the solder interconnect. Moreover, the structural integrity of 3D integrated circuit devices is heavily dependent on strong organic to inorganic adhesion when performing wafer bonding with a dielectric polymer, such as BCB. These organic/inorganic interfaces are known to be susceptible to moisture-assisted debonding, even in the presence of well-known silane adhesion promoters. Often, the synergistic effects of mechanical loads due to thermal expansion coefficient mismatch, temperature cycling, and moisture, may further accelerate the degradation of these interfaces. It is also known that at elevated temperature and humidity, commonly used bisphenol-F based underfill epoxies exhibit an absence of a debond threshold, resulting in continued growth of interfacial defects even at very low loads. We demonstrate that the introduction of a compositionally and functionally graded organic/inorganic hybrid adhesion layer at the passivated silicon/ bisphenol-F based underfill epoxy interface can dramatically increase the adhesion energy. When such graded layers are properly optimized, the interface adhesion exceeds the cohesive fracture energy of the epoxy layer, and interfacial failure related to moisture-assisted debonding is almost completely inhibited. Subsequently, we find that this hybrid layer also prevents the kinetic phenomenon observed for the bisphenol-F undefill epoxy at high temperature and humidity, as it introduces a debond threshold at a value close to the critical cohesive fracture energy of the adjacent underfill epoxy layer. As a result, the implementation of this hybrid layer could lead to more reliable 3D structures and microelectronic packages, where moisture-assisted debonding of internal interfaces is largely eliminated.

Electromigration has been well-studied for traditional backend of line interconnects (such as Cu damascene trenches in low-k dielectric) over the last several decades. However, electromigration of interconnects in the far backend of line has been much less studied, even though the ever-increasing demands for current and miniaturization impacts all interconnects, including those used at package-levels. This presentation addresses the fundamental electromigration characteristics of lead-free flip-chip bumps and solder balls as a function of size-scaling, materials and integration schemes. Finally, the electromigration trends of package-level interconnects will be compared and contrasted with die-level interconnects.

With the trend of miniaturization for electronic devices in 3D IC packaging, electromigration failure poses great threats to the reliability of flip chip joints. Fast reaction between the solders and the underbump metallization (UBM) layers forms intermetallic compounds (IMCs). The IMCs grow rapidly and significantly occupy the joints. To investigate the electromigration behavior of the small joints is the purpose of this study. Sn2.5Ag solder was selected to comply with the Pb-free requirement. V-grooves were fabricated on Si chips as test vehicles; electrode/solder/electrode sandwich structures were fabricated in the grooves by lithography and electroplating. Different metallization systems could be selected as UBM layers. The gap between the electrodes was limited to less than 15μm. The samples were passed current with different current densities at various temperatures. The growth kinetics of the IMCs would be different when the compounds grew from both directions contacted each other. The void formed at the interfaces enhanced the failure time. This study focused on the kinetics of the compound formation and the failure mode in small solder joints under electromigration.

Limited numbers of grains are often observed in Sn-Ag-Cu solder bumps. The random orientations of these grains lead to a large fluctuation in solder bumpsâ?T mechanical properties limiting the product quality and product yield of the reflow process. Finer grain structures are preferred to average out the anisotropic mechanical properties of beta-Sn grains and achieve more stable mechanical properties in solder bumps. Nucleation suppression in Sn-Ag-Cu alloys is a leading cause of coarse grain structure in chip-to-package interconnects. In the literature, studies on the effect of adding impurities in the Sn-Ag-Cu ternary system have shown either undercooling reduction or microstructure refinement. Most of the researchers attribute the effect to intermetallic compound (IMC) formation between added element and native elements, Sn, Ag, and Cu, providing heterogeneous nucleation sites for beta-Sn nucleation. However most of the effective elements, such as Mn, Fe, Al and Zn are also active with oxygen. The presence of small amount of oxide particles might also offer potential nucleation sites. In order to better understand what the true nucleation promotion mechanism is and potentially provide the microelectronics industry an approach of achieving grain refinement, we study the nucleation behavior of Sn-Ag-Cu based alloy in atmospheres of different oxygen concentration. The result of this work will provide the microelectronics industry a better understanding of the nucleation behavior of SAC solder alloy and may suggest a viable grain refinement approach for industrial applications.

The reliability issues of the packaging products are of highly interest, especially while in microelectronic industry, a major paradigm change from two-dimensional integrated circuit (2-D IC) to three-dimensional integrated circuit (3-D IC) is occurring. Restricting the study of the flip chip joint to the traditional two-dimensional (2D) examination procedure (e.g. Scanning Electron Microscopy) can yield two problems. One is the difficulty in uncovering the kinetics in the real test vehicle during reliability tests, especially at the early stage, which requires nondestructively monitoring. The other one is that a 2D measurement will bring more uncertainties of the materials revolution measurement in a real three-dimensional (3D) structure. Therefore, as a nondestructively 3D imaging technique, synchrotron radiation based x-rays tomography or laminography can bring a significant impact on the in-situ characterization of flip chip solder joints or other 3D packaging parts during accelerated reliability tests, such as electromigration(EM) test. We have conducted tomography experiments in Advanced Light Source, LBNL, USA to measure the effective charge number of eutectic SnPb solders accurately, and also conducted laminography imaging experiments at the beamline ID15 at ESRF to reveal the new mechanism of the EM induced failure in Pb-free solder joints. In this study, there are four types of flip chip samples with different thicknesses of UBMs and SnAg solder joints (Type 1: Cu(5um)+Ni(3um)+SnAg(50um); Type 2: Cu(50um)+SnAg(20um); Type 3: Cu(50um)+SnAg(10um); Type 4: Cu(50um)+Ni(3um)+SnAg(10um)), being investigated by Synchrotron Radiation X-ray Micro-Tomography technique, at different electromigration testing time stages. We find that the voids induced by electromigration transfer from 2D pancake-shape growth to 3D growth by 3D nondestructive ex-situ imaging observation. With the finite element simulation results of the current distribution of these four sample structures, we are able to discuss the reasons of the change of the void growth from 2D to 3D. Additionally, a new physical model for rapid life-time prediction of Pb-free solder joints during EM tests was proposed basing on the nondestructively 3D imaging results. The quantitatively nondestructive measurements of the growth rate of EM induced voids in SAC1205 and SN100C solder joints were collected and analyzed by Johnson-Mehl-Avrami(JMA) phase transformation model. The characteristic times fitted by the JMA model are confirmed by the characteristic times produced by Weibull statistical analysis of the time-to-failures of a larger amount of solder joints under the same EM testing condition. Since the JMA model and Weibull distribution are of the same mathematical form, it indicates an intrinsic link between them. The proposed JMA model can offer a rapid life-time prediction of the solder joints during the EM tests, reducing the testing time down to 3% of the usual one. Also, a series of simulation results will be included to illustrate the effects of failure criteria in the life-time prediction.