Nitrogen incorporation into SiC-SiO₂ interface is known as a standard technique for improving the performance of SiC-MOSFETs. Post nitridation annealing with NO or N₂O ambient is widely used for this purpose. Recently we found that after this process, a large amount of nitrogen atoms are diffused into the channel region of SiC-MOSFETs. This fact has been revealed by EDMR (electrically detected magnetic resonance) [1] and XPS (x-ray photoemission spectroscopy) studies [2]. The low-temperature EDMR study revealed nitrogen shallow-donor signal in the MOSFET channel after post nitridation annealing. The XPS study confirmed that the nitrogen concentration after the nitridation process reaches to the order of 1e14 /cm2 in the SiC surface region. Accordingly, we consider that the â?odopedâ? nitrogen has several significant roles in the SiC-MOS system. One is to modify and remove the interface traps. Second is to behave as â?oshallow donorsâ? in the channel region, and third is to behave as â?odefectsâ? in the SiO₂ and SiC regions. Therefore, we planned to quantitatively investigate such behaviors of nitrogen by a combination of several spectroscopic techniques. In the first place, we performed MOS C-V analysis for nitrided 4H-SiC MOS samples. Without nitrogen incorporation, the density of shallow interface traps (Nit) was estimated to be 2e12 to 0.4e12 /cm2/eV at Ec â?" 0.2 to 0.5 eV. With nitrogen incorporation (nitridation temperature, Ta = 1430 °C), Nit was decreased to 0.5e12 to 0.06e12 /cm2/eV. At the same time, XPS measurements indicated 100~1000 times larger nitrogen incorporation into the SiC substrate (2.4e14 /cm2). Tentatively, one interface trap was eliminated per 100~1000 nitrogen atoms. In other words, only a small fraction of nitrogen atoms was effective for eliminating the interface traps and a major part of the incorporated nitrogen may play different roles. These behaviors were also strongly dependent on process parameters such as Ta. For instance, we found that the reduction in Nit could be only activated when Ta > 1100 °C. On the contrary, XPS measurements indicated that the nitrogen diffusion into the SiC substrate increased linearly with Ta: from 0.8e14 to 2.4e14 /cm2 for Ta = 800 to 1430 °C, respectively. To characterize different behaviors of nitrogen separately and quantitatively, we also performed ESR (electron spin resonance) observation on nitrogen in special 4H-SiC MOS samples. The special samples enabled us to distinguish the nitrogen atoms doped after post nitridation annealing. We measured ESR spectra of the samples both before and after removal of nitrided SiO₂ layer, and then estimated substitutional nitrogen atoms (nitrogen donors) and other nitrogen atoms in the SiO₂ and SiC regions. This work conducts to quantitative assessments on the roles of nitrogen atoms in SiC-SiO₂ interface systems. [1] T. Umeda et al. APL 99, 142105 (2011), [2] R. Kosugi et al. APL (2011) in press.

High carrier lifetime (>5 us) is essential to realize high power Silicon Carbide (SiC) bipolar devices in order to obtain conductivity modulation in the thick (>100 um) voltage blocking layers [1]. To achieve low on-state resistance a carrier lifetime of >5 us is required for 10 kV blocking layers and >20 us for 20 kV blocking layers [2]. However typical lifetime for SiC epilayers is still less than 1 us that is a few orders lower than silicon. Recently significant work has been done to improve the carrier lifetime in SiC by various oxidation and annealing techniques [3,4] that showed lifetime as high as 19.5 us. The ~20x lifetime improvements have been attributed to recombination of extrinsically introduced carbon interstitials, via high temperature treatment, with carbon vacancies, which in turn lower the Z_1/2 defect center. However, during epigrowth and also in the high temperature steps extended defects are formed regions of the epilayers, which impact the lifetime adversely. Previously, lifetime degradation has been shown in relatively thin epilayers resulting from in grown stacking faults, low angle boundaries, micropipes, and carrot defects [5,6]. In this work, we report on the influence of various other extended defects on carrier lifetime such as half loop arrays, slip bands, morphological defects, and single stacking faults in thick epitaxial layers.

We performed whole wafer non-destructive ultraviolet photoluminescence (UVPL) and microwave photoconductive decay (uPCD) mapping on commercially grown, 140 um thick epilayers grown on 4 degree offcut substrates. From the multiple sets of UVPL and uPCD images, we observed a one-to-one correlation between the extended defects and a decrease in carrier lifetime. Additionally, we observed lifetime degradation at the half loop arrays (HLA) even before any significant expansion of stacking faults from the HLAs. Another defect is the recently reported, [7] morphological defect that originates from a small 3C-SiC particle that generates a misoriented 4H-SiC region, which also causes severe lifetime degradation. Various other extended defects and their correlation to carrier lifetime will be also shown. The influence of these extended defects on lifetime is greater for thicker epilayers, where the spatial extent of many defects is larger, and some of the extended defects have a higher chance of generating during the long epigrowth.

[1] H. Lendenmann, et. al., Mater. Sci. Forum 338-342, 1423 (2000)

[2] T. Hiyoshi, et. al., Appl. Phys. Exp. 2, 041101 (2009)

[3] T. Miyazawa, et. al., Appl. Phys. Lett. 97, 202106 (2010)

[4] T. Kimoto, et. al., J. Appl. Phys. 108, 083721 (2010)

[5] J. Hassan, et. al., J. Appl. Phys. 105, 123518 (2009)

[6] S. I. Maximenko, et. al., Mater. Sci. Forum 645-648, 211 (2010)

[7] N. A. Mahadik, et. al., J. Electon. Mater. 40, 413 (2011)

Synchrotron topography studies are presented of the behavior of growth dislocations and deformation-induced dislocations in 4H-SiC single crystals. The growth dislocations include those in threading orientation with line directions approximately along c with Burgers vectors of a, c, and na+mc (where n and m are integers ) while the deformation-induced dislocations include those with line directions confined to the basal plane with Burgers vectors of a and Shockley partial dislocations with Burgers vectors of 1/3<1-100> as well as those with line directions in the {1-100} prismatic planes with Burgers vectors of a. Processes leading to the nucleation of the growth dislocations are discussed as well as their deflection onto the basal plane during crystal growth in a reversible process. This latter process can lead to the conversion of segments of the deflected growth dislocations into deformation induced dislocations. In some cases this can lead to dislocation multiplication via the Hopping Frank-Read source mechanism and in others to the motion of single Shockley partial dislocations leading to Shockley stacking fault expansion. Studies are also presented of interactions between threading growth dislocations with c-component of Burgerâ?Ts vector facilitated by climb processes which are mediated by interactions with non-equilibrium concentrations of vacancies. This can lead to reactions whereby complete or partial dislocation Burgers vector annihilation occurs. In addition, the nucleation of half-loops of deformation induced dislocations on both the basal and prismatic planes at micropipe cores is discussed. In some cases this can lead to Shockley stacking fault expansion. The capability of Synchrotron topography to provide information crucial to the understanding of the mechanisms leading to the defect configurations observed in SiC crystals is emphasized as well as its contribution to the development of strategies for engineering of the defect configurations.

Due to its biocompatibility, chemical inertness, and mechanical stability, SiC is attracting increasing interest as a promising material for bioelectronic, biosensing, and biomedical applications. However, in order to realize the full potential of hybrid inorganic/(bio)organic systems, it is necessary to identify methods for precisely tuning the physical and chemical properties of the semiconductor surface. To this end, we have developed processes for altering the terminal surface atoms of both hexagonal and cubic SiC in order to create well-defined chemical reactivities and significantly reduce surface state concentrations. Onto these surfaces, a wide range of organic molecules can be bound. In particular, self-assembled monolayers composed of simple carbon chains supply a means of studying bonding-induced defects, tuning interfacial energetics, and grafting complex biomolecules, such as proteins. Alternatively, the direct growth of functional polymeric layers from the surface provides myriad possibilities for the development of selective biosensors and implantable devices. Importantly, the surface polymerization reaction is strongly dependent on the substrate orientation and allows for the formation of nanopatterned functional polymer brush layers. Finally, the extension of these functionalization strategies to epitaxial graphene on SiC provides exciting opportunities for the realization of the next generation of biosensor technologies. Together, these advances have the potential to facilitate the direct integration of SiC into active biomedical devices.

The measurement of electron mobility in 4H-N SiC substrate and epilayers is reported, for the first time, up to 900°C. The electrical measurements were carried out on substrate and Schottky diodes with different nitrogen doping concentrations. The electrical mobility, along the c-axis as a function of temperature, was extracted by taking into account the partial ionization of nitrogen donors as a function of temperature and substrate conductivity in the case of Schottky diodes. A detailed empirical equation is developed which can be used to predict the electron mobility at a given temperature and doping which can be effectively used in numerical calculations for predicting device performance at extreme temperatures. In order to cover such a wide temperature range, samples with different active area had to be measured using Kelvin (4 wire) resistance measurements. Care was taken to accurately measure the sample temperature and prevent the samples from oxidation during the high temperature measurements.

The combined application of section and projection topography carried out using synchrotron white beam X-ray topography (SWBXT) can be a powerful tool for the determination of the three-dimensional configurations of defects in single crystals. In this paper, we present examples of the application of this combination of techniques to the analysis of defect configurations in PVT-grown 4H-SiC wafers cut perpendicular (c plane) and parallel (axial slice) to the growth axis. Amongst the defects analyzed are threading dislocations with c-component of Burgers vector. In studies carried out on axial slices, these can be deflected onto the basal plane via a process of macrostep overgrowth. Section topography shows that these threading dislocations can be converted into stacking faults in agreement with studies carried out on wafers cut perpendicular to the growth axis. On the section topographs, the classic hourglass contrast associated with the stacking faults is observed. Detailed correlation between section and projection topographs recorded of these threading dislocations is presented with particular emphasis being laid on the determination of the signs of the dislocations. Further, information can also be determined regarding the position of the dislocations within the crystal depth. This three dimensional geometrical analysis involving identification of the intersection of the dislocations with the Bormann Fan will be presented in detail. In addition, similar correlation is presented for threading edge dislocations and basal plane dislocations. The various dislocations images are shown to comprise direct, intermediary and dynamical contrast and the features associated with these contrast types and their formation mechanisms will be reviewed. Simulations of dynamic images of defects are also described.

Relatively little is known about the transition metal defects in silicon carbide (SiC), though some of them (like vanadium) are intentionally introduced to SiC in order to produce semi-insulating samples, or can enter SiC unintentionally during or after the growth process. There are unidentified photoluminescence centers that are presumably originated from transition metal defects, however, the number of detected centers does not follow the number of inequivalent substitutional sites in different polytypes unlike the case of vanadium or chromium. Combination of data from simulations and experiments can greatly contribute to understanding the nature of point defects in semiconductors. In this study we applied highly convergent and sophisticated density functional theory (DFT) based methods to investigate important transition metal impurities including titanium (Ti), vanadium (V), niobium (Nb), chromium (Cr), molybdenum (Mo) and tungsten (W) in cubic 3C and hexagonal 4H and 6H polytypes of SiC. We applied DFT with PBE functional in order to calculate the ground state of the defects. We calculated the electronic structure by a screened hybrid density functional (HSE06) which was very successful in the quantitative description of native defects in SiC. This functional contains a Fock-exchange term which could provide, at least, qualitatively right electronic structure of transition metal impurities. We found in our calculations that neither interstitial nor carbon substitution configurations of Ti, V, Nb, Cr, Mo and W impurities are relevant because silicon substitution is much more favorable (X_Si where X is the metal impurity) which is expected from the size of the impurities. We also studied the complex of silicon substitution near an adjacent carbon vacancy configuration. This may be described as a metal impurity substituting the divacancy where the transition metal makes shorter bonds with the nearest carbon atoms than to the nearest silicon atoms. We call this defect asymmetric split-vacancy configuration. While split-vacancy defects are known in other semiconductors this type of defects shows unique properties in hexagonal SiC. The asymmetric split-vacancy configuration exclusively prefers the hexagonal-hexagonal sites more than 0.6 eV compared to that of other possible configurations both in 4H and 6H-SiC. Two consequences are that i) only a single spectrum is expected from this type of defects in hexagonal SiC, ii) the probability of finding these defects in 3C polytype is much smaller than in hexagonal polytypes. Our calculations indicate that X_Si defects are more favorable in thermal equilibrium than split-vacancy configuration, in general, but with significantly different amount. We found two classes among the considered transition metal impurities: Ti, V and Cr clearly prefer the X_Si configuration while W, Nb, and Mo may fractionally form split-vacancy complex in hexagonal SiC even under thermal equilibrium in hexagonal SiC.

[Introduction] When silicon carbide thin film can be formed at low temperatures, various materials having low melting points can be coated with silicon carbide film. Thus, as an approach to achieve this purpose, an amorphous silicon carbide chemical vapor deposition process on a silicon surface entirely performed at room temperature (RT) has been developed [1]. This paper reports its detail. [Experimental] Experimental procedure is consisted of three steps. Step (A) is the reactive silicon surface preparation performed using argon plasma for 10-20 min at RT, Step (B) is the chemical vapor deposition using monomethylsilane gas in hydrogen ambient for 1 min at RT. Step (C) is the evaluation of the obtained film, which is performed by the exposure of obtained film to a gas mixture containing hydrogen chloride gas at 800 oC for 1 min. The surface morphology was evaluated using a scanning electron microscope (SEM). The chemical bonds contained in the film were analyzed using a time-of-flight secondary ion mass spectrometry (ToF-SIMS). The film thickness and the crystalline quality were obtained using a transmission electron microscope (TEM). [Results and Discussion] The surface after Step (B) was specular similar to the silicon substrate surface before the film formation process. The surface after Step (C) was still found to be specular. Thus, the obtained film was concluded to be robust to harsh environments, by this quick evaluation. Next, the film after Step (C) was evaluated. ToF-SIMS showed that the obtained film contained silicon-carbon bonds, such as Si-C and Si-C2, and carbon-carbon bond. This indicates that the obtained film included silicon and carbon bond network. The high-resolution TEM showed that the obtained film was amorphous and its thickness was about 5 nm which was thicker than monolayer. The mechanism for enabling the room temperature process is discussed. The argon plasma removes the native oxide and organic contamination existed on the silicon surface, in order to prepare a bare silicon surface which has silicon dangling bonds. When monomethylsilane molecule approaches to the surface, it can be smoothly accepted and chemisorbed with the silicon dangling bonds even at room temperature. This process is followed by the hydrogen molecule desorption from the chemisorbed monomethylsilane. During this hydrogen molecule desorption process, hydrogen radicals can remove another hydrogen atom from various positions of the monomethylsilane molecule, including its top position. Thus, the film formation process can continue to form silicon carbide multi-layer. [Conclusions] In conclusion, the amorphous silicon carbide thin film formation process entirely at room temperature was possible, using monomethylsilane gas on a reactive silicon surface prepared by argon plasma. The obtained thin film had silicon-carbon bonds and was robust to hydrogen chloride gas. References: [1] H. Habuka, Y. Ando and M. Tsuji, Surf. Coat. Tech., in press.

In this work, we report the influence of negative substrate bias on deposition of silicon carbide (SiC) thin films on (100) silicon substrate by dc magnetron co-sputtering without external substrate heating. Morphological and chemical properties of as-deposited films were investigated using Atomic Force Microscopy (AFM), Rutherford backscattering spectroscopy (RBS) and Raman spectroscopy. Mechanical and electrical properties were investigated through the use of Nanoindentation and Four Probe Method, respectively. The results of RBS and Raman showed that it is possible to obtain stoichiometric films with high formation of Siâ?"C bonds when they are grown with the action of high energy positive ions such as Ar+. As a result, it was observed a decrease in the material resistivity to values of about 0.1 Ω.cm (without bias the film resistivity is higher than 100 Ω.cm). This fact led us to perform measurements of nanoindentation which confirms the good qualities observed through measurements of high values of hardness (> 30 GPa) and Young's modulus (between 200 and 400 GPa depending on the condition of substrate bias). Additionally, it was noticed that these good results were achieved due to factors such as the incorporation of argon in film bulk, which in turn was shown to behave as a dopant.

Recently, many studies have showed the characterization of amorphous and crystalline silicon carbide films deposited onto an insulator layer on Si substrates aiming microelectronics and MEMS devices applications. The majority of these studies are focused on 3C-SiC films grown on SiO2/Si or Si3N4/Si substrates. On the other hand, less attention is placed on the investigation of SiC films on AlN/Si, especially in their amorphous form. The aim of this work was to develop a systematic study on the structural and piezoresistive characteristics of sputtered a-SiC thin films grown on AlN/Si (100) substrates under different deposition conditions. Fourier transform infrared absorption (FTIR) and scanning electron microscopy (SEM) analyses were used to investigate the structural characteristics of as-deposited films, whereas Rutherford backscattering spectrometry (RBS) allowed determining film composition. Thin-film resistors were fabricated in order to characterize the electrical and piezoresistive properties of SiC grown on AlN/Si. Gauge factor and TCR (temperature coeffient of resistance) measurements were performed and demonstrated the potential of the resistors fabricated to be used as sensing elements in MEMS devices for high temperature application.

Since the argon (Ar) atmosphere produced higher quality graphene films on silicon carbide (SiC) than in vacuum, the inert-gas mediated thermal decomposition of SiC is so far the most effective method for the controlled epitaxial graphene (EG) growth. Most studies and progress has been demonstrated with the Si-face of basal plane oriented SiC substrates because of its slow reaction kinetics, which results from higher surface energy than the C-face. Nevertheless, there is significant interest in obtaining few-layer, smooth EG on the C-face of SiC due to its superior electrical properties as compared to EG on the Si-face. In this work, we investigated the structural properties of EG layers grown on the C-face of 4H-SiC in vacuum or Ar environments by grazing incidence X-ray diffraction (GIXD) using synchrotron radiation. The presence of Ar during the growth process slowed the rate of graphene formation, which resulted in films with smaller thickness and more uniform morphology. Moreover, the rotational stacking faults of graphene layers were intensified with improved in-plane crystalline coherence length as compared to vacuum-grown layers. The strain relaxation of the graphene lattice was also indentified; as the Ar pressure was increased, this phenomenon became more prominent and contributed to an improvement in electronic mobilities.

Commercially available bulk silicon carbide (SiC) still has a high number (< 2000/cm2) of screw dislocations (SD) that have been linked to some degradation of high-field power device electrical performance properties [1, 2]. Recently, SiC growth perpendicular to the c-axis, has been shown to grow higher quality (lower defect density) bulk SiC [3]. Researchers at the NASA Glenn Research Center have proposed a method to mass-produce high quality bulk SiC. This technique starts by growing a long continuous single crystal SiC fiber in the c-direction, and then laterally (perpendicular to the c-direction) enlarging the fiber into a high quality boule via chemical vapor deposition growth [4]. In order for this bulk SiC growth method to become reality, a method for producing long single crystal SiC fibers must first be developed. To achieve this, a growth a method has been implemented that combines the advantages of two well know growth methods: Laser Heated Floating Zone (proven for oxide-based crystals) [5] and Traveling Solvent Method (demonstrated for SiC) [6], which we have named Solvent-Laser Heated Floating Zone (Solvent-LHFZ). While some of the initial Solvent-LHFZ results have recently been reported [7], this paper focuses on further characterization of grown crystals and their growth fronts, which have been observed over multiple experiments. Many of these crystals have been found to contain voids and solvent rich pockets as seen by focused ion beam / energy-dispersive X-ray spectroscopy (FIB/EDS), secondary ion mass spectroscopy (SIMS), and cross sectioning. At the same time synchrotron white beam X-ray topography (SWBXT) has shown these films to be epitaxial (4H polytype), but highly strained. Scanning electron microscope (SEM) images of these films reveal multiple growth fronts merging, webbing over forming pockets. When these growth fronts completely web over, they also form defects where the web closes. This leads to the hypothesis that the growth fronts propagate vertically (<000-1>) and then convert to lateral growth (perpendicular to the <000-1>) combining with other fronts, creating defects and sealing in voids and/or trapping solvent in the resulting grown crystal. [1] J. Zhang, et al., International Conference on Silicon Carbide and Related Materials, Cleveland, OH, September 11-16, 2011, -Submitted [2] R. Berechman et al., International Conference on Silicon Carbide and Related Materials, Cleveland, OH, September 11-16, 2011, -Submitted [3] Y. Urakami, et al., International Conference on Silicon Carbide and Related Materials, Cleveland, OH, September 11-16, 2011, -Submitted [4] J.A. Powell, et al., U.S. Patent 7,449,065 issued November 11, 2008 [5] C.A. Burris et al.�, App. Phys. Lett., 26, 318-320 (1975) [6] L. B. Griffiths et al., Electrochem. Soc., 111, 805 (1964) [7] A. A. Woodworth, et al., International Conference on Silicon Carbide and Related Materials, Cleveland, OH, September 11-16, 2011, -Submitted

4H Silicon Carbide (SiC) is the material of choice for fabricating low-loss power devices. Significant advances in the growth of homo-epitaxial layers on good quality substrates have led to the availability of high performance commercial SiC power devices. Good quality epitaxial layers free from morphological defects are very important for these power devices. Triangular defects are a commonly occurring defect that can affect device performance [1]. It can be created due to particles, poly-silicon deposition or defects/scratches on the surface of the substrates. In our previous work, we reported process enhancements that resulted in very smooth epitaxial layers at high growth rates [2]. Triangular defects have been observed under many process conditions, which span large areas of the wafer. In this work we present process changes implemented in our 6x4� reactor that reduce the nucleation of the triangular defects from particles, surface defects and other factors. The triangles that do nucleate are greatly reduced in size. The parameters most critical for achieving this reduction were found to be a combination of the Cl/Si ratio and the growth rate. Changing the growth rate also affected the size of the nucleated triangles. Nomarski images and full wafer Candela scans enumerating the triangles are presented. Differences in the triangular defects nucleated by the different processes are characterized. [1] G. Chung et al., Materials Science Forum Vols. 679-680 (2011) pp 123-126 [2] H. Das et al., Invited Poster-3, ICSCRM 2011

There is great need for neural prosthetics that are minimally invasive and that do not cause device encapsulation and scarring of neural tissue. This is especially true for patients with diseases such as ambiotrophic lateral sclerosis (ALS), whose motor neuron cells are already atrophied. This research, based on extremely promising in-vitro and preliminary in-vivo studies, involves the fabrication of silicon carbide (3C-SiC) needle-like shanks to test the material biocompatibility in the cortex of wild-type mice. Shanks for in-vivo implantation were prepared via photolithography from both Si and 3C-SiC on Si epi-wafers. 20 µm thick films of 3C-SiC were grown using a well established heteroepitaxial process on 2 inch (100) oriented Si wafers. (100)Si wafers were also processed so that a direct comparison between 3C-SiC and Si could be made in-vivo. The nominal probe thickness is 20 µm thick, 7 mm long, and both the 3C-SiC and Si shanks were fabricated with 250 µm silicon tabs which are used to handle the probes with tweezers (for ease of insertion into the mouse cortex). Photolithography and lift-off patterning was utilized to realize the metal and AZ® 4620 hard masks. Deep reactive ion etching (DRIE) was employed to pattern the 3C-SiC film and Si substrate. First, the 3C-SiC film was patterned using a SF6/ O2 dry etch chemistry. The dry etch-patterned 3C-SiC epi wafer was then photoresist bonded to a Si handle wafer. Then the high-aspect ratio of the handling tabs was created by using the Bosch process to etch through the full thickness of the Si substrate, resulting in released shank structures. The resulting 3C-SiC shanks exhibited high flexibility and fracture resistance when compared to similarly fabricated Si shanks.

Silicon carbide (SiC) is a material of interest for high-voltage and high-power switching device applications. Basal plane dislocations (BPDs) are a major concern for the SiC bipolar devices as they source Shockley-type stacking faults in the presence of an electron-hole plasma and reduce minority carrier lifetimes [1, 2]. Many researchers have investigated methods to reduce the BPD density by experimenting with pre-growth treatments [3-5], substrate orientation [6], growth parameters [6, 7] and growth interrupts [8]. It has been shown that the conversion of BPDs to threading edge dislocations (TEDs) continues throughout the epitaxial growth process in 4° off-axis SiC material and that a minimum thickness of ~16 µm is required to convert all BPDs to TEDs [9]. This work investigates the conversion of BPDs in a thin (5 µm), highly doped n+ buffer layer (BL) using a hydrogen etch procedure prior to epitaxial growth to enhance conversion. Unintentionally doped (UID) epilayers were grown on 4° off-axis substrates in a horizontal hot-wall reactor using the standard chemistry of silane (2% in H2) and propane. Prior to growth, a hydrogen etch was performed for 50 min at 70 mbar. Three etch temperatures were investigated, 1620, 1650 and 1665°C. All epitaxial films investigated were grown with the growth parameters maintained at T = 1620°C, P = 100 mbar and C/Si = 1.55. An initial 5 µm highly doped n+ BL was grown using ultra high purity nitrogen, followed by a 20 µm UID film. Ultraviolet photoluminescence imaging was used to identify the BPDs in the UID layer. Atomic force microscopy was used to determine the surface roughness. The density of BPDs at the BL/UID interface was ~ 15 cm-2 when a 5µm buffer layer was grown directly upon reaching the growth temperature without a hydrogen etch. When an etch was performed for 50 min at the growth temperature prior to a 5 µm BL, no significant reduction in BPD density was observed. However, when a 50 min etch was performed prior to the BL at elevated temperatures (1650 and 1665 °C), the density of BPDs at the BL/UID interface was reduced to < 2 cm-2. Similar BPD densities were seen for the two higher temperatures (1650 and 1665 °C) investigated. The surface prior to epitaxial growth will be evaluated to determine whether any surface features were created during the hydrogen etch which may have impacted the conversion. [1] J.P. Bergman, et al. Mater. Sci. Forum Vol. 353-356, 299 (2001). [2] R.E. Stahlbush, et al., J. Electron. Mater. 31, 370 (2002). [3] Z. Zhang, et al., Appl. Phys. Lett. 89, 081910 (2006). [4] J.J. Sumakeris, et al., Mater. Sci. Forum 527-529, 529 (2006). [5] H. Tsuchida, et al., Mater. Sci. Forum 483-485, 97 (2005). [6] W. Chen and M.A. Capano J. Appl. Phys. 98, 114907 (2005). [7] T. Ohno, et al., J. Cryst. Growth 271, 1 (2004). [8] R. E. Stahlbush, et al., Jr., Appl. Phys. Lett. 94, 041916 (2009). [9] R.L. Myers-Ward, et al., Mater. Sci. Forum 615-617, 105-108 (2009).

Investigation on the effects of post-deposition annealing temperatures (400, 600, 800, and 1000°C) towards physical and electrical characteristics have been carried out on metal-organic decomposed lanthanum cerium oxide (LaxCeyOz) film spin-coated on 4H-SiC substrate. X-ray diffraction analysis detected diffraction peaks associated to LaxCeyOz and lanthanum silicate (La9.33Si6O26) in all of the investigated samples. Intensities of the peaks increased with increasing annealing temperatures. Williamson-Hall plot was used to determine grain size and microstrains of LaxCeyOz films. An inverse relationship was demonstrated, whereby grain size increased while microstrains decreased as a function of annealing temperature. Surface morphologies of LaxCeyOz films were examined under scanning electron microscope while surface morphologies and roughnesses of the films were determined using atomic force microscope. Capacitance-voltage measurement showed that accumulation capacitance level of the samples decreased when annealing temperature increased from 400 to 1000°C with a negative flatband voltage shift. The lowest effective oxide charges, slow trap densities, interface trap densities, and total interface trap densities were obtained for sample annealed at 1000°C. This could be related to the acquisition of the highest breakdown voltage and lowest leakage current density for this sample. Detailed explanation was discussed in this paper.

The neuroscience community benefits greatly by studying in vitro (cells) and ex vivo (brain tissue slice) neurodynamics abd electrophysiology through long-term laboratory cultures. Typically these studies are performed using 2D micro-electrode array (MEA) devices fabricated on silicon substrates using traditional microfabrication techniques. Silicon has been documented to cause glial scarring and has shown to cause disruptions in neuronal cell cultures that may potentially skew obtained datalong-term. In our device the silicon substrate is replaced with cubic silicon carbide (3C-SiC) providing an inert biocompatible surface. The presented microfabricated neural activation device (NAD) consists of an array of 64 planar Ti/Au electrodes patterned directly onto a 3C-SiC substrate. The small size of these electrodes (10um) provides excellent spatial selectivity for neural recording and stimulation at the cellular level. The finished device was packaged in a 68-pin Pin Grid Array (PGA) style package and plugged into a custom interface board for signal processing and generation. The device and its associated support equipment are designed as a test bed for long-term neural recording and stimulation experiments in vitro and ex vivo. The experiments are performed in a custom incubator setup with specialty interface electronics that allow high-speed recording and stimulation of action potentials for each channel on the device. The device allows the testing of 3C-SiC substrates in active brain-like neuron environments as well as a test bed for brain-machine interface material studies.

We fabricated PZT thick film cantilever based on piezoelectric lead zirconate titanate (PZT) using SiC wafer. Electromechanical properties of PZT microcantilever such as nonlinear behavior under high voltage and behavior in liquid were investigated. The decrease in resonant frequency with an increase in electric field could be explained by the increase in elastic compliance of PZT thick film because of the elastic nonlinearity, and microcantilever dimension. Cantilever was tested in liquid using water-glycerol solutions of various proportion compositions. The viscosity and the density of liquids have characterized via oscillating-sphere model. The mass sensitivity through Au mass loading was discussed. Their advantages such as high mechanical strength, high thermal conductivity, high elasticity, high thermal stability and extreme chemical inertness in several liquid electrolytes has made SiC as attractive candidate for structural material in MEMS devices. The electrical properties were improved with the increase in sintering temperature. In case of the PCW-PZT thick films being sintered at 850 degree of centigrade, the dielectric permittivity (εr) was observed as 510 at the frequency of 100 kHz. â-³f (sensing or actuating resolution) of the piezoelectric micro-cantilever on the SiC membrane under the viscose damper was 50% higher than that on the Si membrane.

A statistical analysis of selected on- and off- electrical characteristics of junction field effect transistors (JFETs) measured at room temperature across a p-type Al-doped (1.0-5.0 Ω-cm) 2 inch-diameter 6H-SiC wafer is presented. JFETs fabrication details can be found elsewhere [1]. Tests of 229 JFETs with five different W/L ratios showed an overall yield of ~93%. Measurements from 45 transistors with W/L = 100 µm/100 µm from 45 dice showed an across-the-wafer threshold voltage (V_TH) mean of -7.74 V with standard deviation of 1.36 V, and zero-gate-voltage drain current (I_DSS) mean of 214.70 µA with standard deviation of 63.98 µA. Both parameters exhibited an increasing trend with distance of die location from the wafer center. Gate reverse current (I_GSS) and off-state drain leakage current (I_OFF) exhibited relatively large variation across the wafer, ranging from 2.54Ã-10^-4 µA to 1.99Ã-10² µA and 7.81Ã-10^-2 nA to 4.18Ã-10² nA, respectively. Punch through current from the substrate is surmised to be the cause of large magnitude of I_GSS than I_OFF. The measurement results of substrate leakage current, I_SUB, indicate there is a linear and high correlated relationship between I_GSS and I_SUB. It suggests that the high magnitude of I_GSS is indeed mainly contributed from the I_SUB. Overall, the V_TH and I_DSS for the five JFETs sizes show relatively close values of coefficient of variance (CV). Large variation in CV of I_GSS and I_OFF are observed across all five JFET sizes, and I_OFF has relatively lower magnitude than I_GSS. This wafer-level characterization of the basic building blocks of SiC-based integrated circuit (IC) electronics is the first of its kind and provides a set of experimental data to further the design and development of wafer-scale SiC ICs. [1] A.C. Patil, et al., â?o6H-SiC JFETs for 450 ^o C Differential Sensing Applications,â? Journal of Microelectromechanical Systems, vol. 18, pp. 950-961, 2009

There is a growing demand for SiC devices in high power and high voltage applications, e.g., in hybrid electric (HEV) and purely electric vehicles, for high power RF applications, high temperature sensor circuits that can be mounted on jet engine blocks, for robust and radiation-resistant UV photo-detectors and ionizing radiation detectors, and for very robust and corrosion-resistant MEMS and sensors. Over the last decade there has been a remarkable progress in the crystalline quality of SiC ingots, leading to improved device yields and reliability, as well as larger wafer diameters. The attractiveness of single crystalline SiC in a variety of device applications is counteracted by the very high cost of substrates. Being able to exfoliate multiple 1 to 10 μm thick single crystalline layers from one standard thickness SiC wafer and bonding such layers to lower cost substrates, such as silicon or polycrystalline SiC, would drive the material cost down and allow expanding use of single crystalline SiC. Such layer transfer would also permit better integration of various device technologies on composite substrates. It is known that a hydrogen ion implantation with a dose of about 5x10¹⁶ cm^-2 can cause formation of nano-voids and microcracks under the surface, at a depth corresponding roughly to the implantation range Rp, and at elevated temperatures these defects lead to exfoliation (and with suitable preprocessing to layer transfer to a new substrate). We present data on exfoliation of thin films of 4H-SiC (the 4H polytype is most relevant for power and high voltage device applications). To characterize the as-implanted samples we utilized ion channeling with 2.4 MeV He ions. This was correlated with optical reflectance in the 0.35-1.6 μm spectral region and with optical absorptance values derived from it. Samples implanted at 180 keV at room temperature with doses ranging from 3x10¹⁶ to 1x10¹⁷ H⁺ cm^-2 show a clear and distinct signature of lattice damage that increases monotonically with H⁺ fluence. The optical spectra, after an initial calibration by means of ion channeling, serve as a nondestructive tool for rapid characterization of H⁺ implant induced damage. Thermal anneals lead to at least partial damage removal at temperatures below 800°C for 30 min and for doses â?¤ 3E¹⁶ cm^-2. For higher doses and temperatures, surface blistering and exfoliation occur as expected. The interplay between damage annealing for lower doses and temperatures versus damage increase that leads to exfoliation at higher doses and temperatures will be presented and discussed. We acknowledge the financial support of the Semiconductor Research Corporation.

Membranes of silicon carbide (SiC) have been used in chemical and biological sensors and actuators intended for harsh environments. These membranes have the further potential for fabrication of metal/ SiC contacts on their upper surface. In this paper, we report for the first time on the electrical properties of metal contacts on n⁺-SiC membranes (0.285 μm thick). The membranes were fabricated with dimensions up to 15 x 10 mm by an initial reactive ion etching of a window region in the epitaxial layer n⁺-SiC on the backside of the wafer. The Si substrate was then removed in KOH solution. Finally, an array of metal dots and circular transmission line model (CTLM) [1] contacts was patterned on the upper surface of the n⁺-SiC membrane. Both Al and Pd contacts have been examined in these experiments. The results have shown a strong effect of the etching procedure on both the stoichiometry of the upper n⁺-SiC surface and the electrical properties of the metal contacts. The residual effects of the etching treatments have determined the effectiveness of subsequent thermal annealing in reducing the specific contact resistance. [1] G.K. Reeves, Solid State Electronics 23, 487 (1980).

One-dimensional silicon carbides (SiC), i.e., SiC nanorods, nanowires and nanofibers, has unique properties such as high mechanical strength, good thermal shock resistance, high wear-resistance, good chemical stability at high temperatures and so on. Owing to these properties, SiC have been studied extensively for use as reinforcements of metal- or ceramic-matrix composites, abrasives of cutting tools, wafer tray supports and paddles in semiconductor furnace. In addition, the tendency of SiC to crystallize into many different modifications and its wide band gap energy (2.4~3.2 eV) in combination with outstanding mechanical and thermal properties make SiC a material for blue light emitting diodes, high temperature electronics like field-effect transistors and unclear reactor or space electronics. In this study, novel synthesis method to produce the SiC nanofiber was proposed. The exfoliated graphite with an accordion-like shape with a large apparent volume between graphite layers and amorphous silica were used for starting materials. The silica particles were inserted into the space between graphite layers by soaking the exfoliated graphite in the SiO2 slurry under vacuum. Then the exfoliated graphite/SiO2 powder mixture was heat-treated in an alumina boat at 1425C in hydrogen atmosphere. Straight, relatively homogeneous and randomly oriented SiC nanofibers could be derived from the exfoliated graphite with 40 wt% SiO2. The lengths of the SiC nanofibers are estimated to be approximately a few hundreds micrometer, while the diameters are in the range of a few tens nm to 100 nm. From XRD pattern the SiC nanofibers includes a large amount of stacking faults, which means that the growth of the fiber was very fast. TEM images exhibited that the SiC fibers grow along to [111] direction. The growth mechanism will be discussed in terms of heat-treatment condition and silica contents.

To succeed in the fabrication of SiC bipolar diodes and other power devices, localized p-type doping must be mastered, especially for peripheral protection rings. The usual technique is ion implantation of Al but, unfortunately, it has several drawbacks which are still not solved like depth limitation, generation of defects which are very difficult to heal even after high temperature annealing. Since few years, VLS transport is studied not only for homoepitaxial SiC growth but also for SiC selective epitaxial growth (SEG). In this approach, a stacking of silicon and aluminum layers is deposited on the substrate and patterns are created by photolithography [1]. Upon melting, the Al-Si liquid droplets are fed by propane to obtain the SEG of p-doped SiC. In this work, the understanding of the growth was deeper investigated, in particular the influence of the carrier gas (H2 or Ar) and the growth temperature. The SEG experiments were performed using Al70Si30 melt (Si~0.8µm + Al~1.5 µm stacking) on commercial 4H-SiC(0001), 8°off substrate. The samples were then heated under Ar or H2 at different temperatures of 1100, 1150 and 1200 °C under propane flow of 1 sccm, which was added in the reactor to start the VLS growth for 5 min. Additional growths with different C3H8 flow or growth duration were made to precise the SEG mechanisms. Patterns with various shapes and sizes were used in order to study the wetting behavior and the growth rate variations. The thicknesses were measured by mechanical profilometry. After wet chemical etching of the remaining alloy on the grown samples, the surface morphology is usually highly step bunched, typical of epitaxial growth from a liquid phase. The shape and size of the patterns remain unchanged. The morphology was found to clearly depend on the growth conditions. For the thicker films, Raman spectroscopy allowed detecting the highly p type doping of the grown material. These results will be more detailed and discussed at the conference. Authors would like to acknowledge the financial support from French ANR in the framework of VHVD-SiC project (ANR-08-BLAN-0191-02). [1] M. Soueidan, G. Ferro, C. Jacquier, P. Godignon, J. Pezoldt, M. Lazar, B. Nsouli, Y. Monteil, Diamond & Related Materials 16 (2007) 37â?"45

In recent years, growth and processing of silicon carbide has rapidly improved. Although this enabled the utilization of this wide bandgap semiconductor for applications in harsh environments, practical ways of chemical and electrical passivation of its surfaces are still scarce. In particular, etching in hydrofluoric acid, which results in hydrogen terminated surfaces for silicon, yields hydroxylated SiC surfaces with high defect densities. In this work, we utilize straightforward plasma processing methods to achieve chlorine-terminated n-type (0001) 6H-SiC surfaces. The structural, chemical and electronic properties of the surfaces are characterized using a variety of techniques. Static water contact angle and atomic force microscopy show a transition of the wetting behavior from hydrophilic to hydrophobic surfaces following chlorine termination without affecting the surface roughness. Accordingly, X-ray photoelectron spectroscopy reveals rising chlorine core level intensities upon halogenation while a significant reduction of oxygen is observed. Chlorine desorption at elevated temperatures of up to 425°C and reoxidation upon extended storage in ambient atmosphere proves saturation of terminal atoms rather than near surface incorporation of chlorine. In order to examine the electronic properties of the plasma treated surfaces, contact potential difference and surface photovoltage measurements are performed and show the formation of negative surface dipoles as well as approximately flat band surface potentials (built-in voltage Vbi < 20 meV), which is indicative of a successful termination of electrically active surface defect sites. Finally, we demonstrate that the halogenated surfaces enable the formation of functional self-assembled organic monolayers providing controlled chemical functionalities for both bioelectronic and biosensor applications.

The Z1/2 center (Ec â?" 0.65 eV) has received increasing attention, because it is now recognized as a carrier lifetime killer in 4H-SiC. Though the origin of this defect has not been conclusively identified, a carbon vacancy has been suggested. In this paper, understanding of the Z1/2 center behavior is reviewed. < Generation of the Z1/2 center > 1. Growth of SiC under Si-rich condition leads to the high Z1/2 concentration. The Z1/2 concentration is changed by a factor of 50-100, when the C/Si ratio during CVD is varied from 0.7 to 1.5. The growth rate (5-90 μm/h) does not affect the Z1/2 concentration very much. 2. High-temperature process, growth or annealing, induces generation of the Z1/2 center. For example, the Z1/2 concentration in epilayers grown with a fixed C/Si ratio exponentially increases with increasing the growth temperature. In a similar way, when SiC with low Z1/2 concentration is annealed in Ar at different temperatures, the Z1/2 concentration exponentially increases with temperature. This trend may follow the equilibrium concentration of a carbon vacancy in SiC, activation energy of which was determined as 6.5 eV. 3. The Z1/2 concentration is also increased by irradiation of high-energy particles: Implantation of any kinds of ions, dry etching, and electron irradiation lead to significant increase of the defect. Low-energy (120-200 keV) electron irradiation is attractive to precisely control the Z1/2 concentration, which can be employed for lifetime control. < Elimination of the Z1/2 center > 1. Carbon ion implantation and subsequent annealing at 1600-1700oC is effective to eliminate the Z1/2 center (< 1E11 cm-3), as Tsuchida et al. reported. A part of implanted ions may diffuse into the bulk region and recombine with carbon vacancies. 2. The Z1/2 center can be also eliminated by thermal oxidation. Oxidation at higher temperature and longer time is effective for defect elimination. During oxidation of SiC, excess Si and C atoms may be emitted into SiC and diffuse into the bulk region. The authors investigated the Z1/2 reduction as a function of oxidation temperature, time, and the initial Z1/2 concentration, and developed an analytical model, which describes diffusion of interstitials and recombination with carbon vacancies. The activation energy of the interstitial diffusion was determined as 0.6 eV, which agrees with the migration barrier for a carbon interstitial obtained by theoretical study. Using this model, the authors succeeded to predict the depth profile of Z1/2 concentration after oxidation (any temperature, time, and initial defect concentration). After elimination of the Z1/2 center, the carrier lifetimes could be improved to 10-20 μs. Carrier recombination in such materials is also discussed. This work was supported by a Grant-in-Aid for Scientific Research and the FIRST Program from the JSPS.

Recently, some device venders have started to fabricate high performance SiC power devices, such as MOSFETs under mass production. At this situation, SiC wafer cost is still expensive, so 150 mm size wafers are strongly expected to reduce the wafer cost and some wafer venders announced that theses would be released. On the other hand, reducing epitaxial defects such as triangle defects are also important issue to increase device yield and reliability. In this study, we carried out epitaxial growth on 4H-SiC Si-face substrates with the size corresponding to 150 mm and investigated the influence of growth parameters for epitaxial defect density by adopting statistical experimental design. 3Ã-150 mm horizontal low-pressure hot-wall type CVD reactor with SiH₄ - C₃H₈ - H₂ â?"N₂ system was used in this study. 150 mm size is realized by using two 76.2 mm wafers lined up to radial direction. Density of triangle defects was investigated using confocal microscope with differential interference contrast. In the confocal microscope, image can be efficiently obtained from sample surface in focus by rejecting out-of-focus signal. Thickness and doping concentration were investigated by using conventional FT-IR and mercury probe C-V measurement respectively. In this study, we selected four parameters such as temperature, pressure, SiH₄ flow, and C/Si ratio and we found that C/Si ratio was major parameter for controlling density of triangle defects. The density of triangle defects was decreased from 44 cm^-2 to less than 0.6 cm^-2 by decreasing C/Si ratio. Under this condition, the doping concentration could be controlled with the range from about 1Ã-10¹⁵ cm^-3 to 5Ã-10¹⁷ cm^-3 by controlling N₂ flow rate. The growth rate of 8μm/h and the thickness uniformity of δ=±1% were also obtained. Growth rate and thickness uniformity were not depended on C/Si ratio. The growth rate was depended on SiH₄ flow only. Detail will be presented in this conference. This work is supported by Novel Semiconductor Power Electronics Project Realizing Low Carbon Emission Society under Ministry of Economy, Trading Industry (METI) and New Energy and Industrial Technology Development Organization (NEDO).

High quality SiC single crystal without defects is essential for the achievement of highly-efficient SiC power device. Although crystal quality of commercial SiC substrate grown by sublimation method is gradually improved, a large density of basal plane dislocations (BPDs) and threading screw dislocations (TSDs) remains within the crystal. Solution growth has achieved high quality SiC crystal without BPDs, but TSDs are still propagated from seed crystal. Recently we found reduction mechanism of TSDs by step-flow growth during solution growth. Here we demonstrate the enhancement of the dislocation reduction in 4H-SiC using off-axis seed crystal during solution growth. Single crystals of SiC were grown on off-axis seed crystals by top-seeded solution growth method for 1 hour. Off-angles of seed crystals were 1.25, 2 and 4 degrees respectively. The glazing X-ray topography images of the grown crystals on the off-axis seed crystals suggest that the contrasts of TSDs are converted into linear defect contrasts on the basal planes along the off-cut direction. The ratio of this conversion is enhanced with increasing off-angle of seed crystal. In the grown crystal on 4 degrees off-axis seed crystal, almost all TSDs are converted into basal plane defects and the density of TSDs are amazingly reduced to 50 cm^-2 for only 1 hour growth. Since the defects on the basal planes do not propagate through the grown crystal, high quality crystal without any dislocations can be obtained with increasing growth thickness by solution growth on off-axis seed crystals. The solution growth on off-axis seed crystal has the potential to more efficiently obtain ultrahigh quality SiC crystal than repeated a-face (RAF) growth method.

In last decades, silicon carbide (SiC) has been the subject of intense studies motivated by the particular electrical, thermal and mechanical properties of this material. If its electrical and thermal properties make SiC a promising candidate for high power and high temperature electronic devices, its mechanicals properties combined with its chemical inertness are of great benefit for the elaboration of MEMS devices that may operate in harsh environment. The cubic polytype, 3C-SiC, is only one that can be hetero-epitaxially grown on cheap silicon substrates, opening potentiality for these fields that will be presented. Nevertheless, the differences in lattice parameters and thermal expansion coefficients between SiC and Si results in highly defective and stressed layers that may be redhibitory for devices. First, the defect electrical activity knowledge becomes then crucial for the development of reliable power devices. We investigated this point using Atomic Force Microscopy (AFM) through its electrical modes and showed that the defect electrical activity is high and drastically affects power applications. Our results enlighten that defects need to be reduced or avoided to limit their prejudicial impact on devices. In the case of MEMS applications, the mechanical properties of 3C SiC, and particularly stress, must be mastered. Indeed, a stress gradient leads to a deformation of self-supported microstructures, restricting the interest for 3C-SiC/Si. In this case, cantilevers are perfect tools to explore mechanical properties through their static and dynamic behaviors. We have evaluated the influence of parameters such as film orientation, film thickness, defect density on the material properties using clamped free beam structures micro-machined by plasma etching. Our results first indicate a stress gradient inversion phenomenon, which can be explained by the creep occurring in 3C-SiC film, but also demonstrate that stress can be controlled. Application of these results for realization of NC-AFM high frequency nano-cantilevers, integrating both actuation and detection, will be presented. Recently, we have also demonstrated that a continuous monocrystalline silicon thin film can be grown on 3C-SiC epilayers deposited on silicon substrates. On such structure, epitaxy may be used again. This work demonstrates the feasibility of elaborating original monocristalline multi-stack heterostructures that could be beneficial for the development of SiC MEMS structures.

Defect Selective Etching (DSE) is a very common method to detect dislocations intersecting the sample surface and to distinguish between different types of dislocations by means of shape and size of the etch pits. In case of 4H-Silicon Carbide (SiC), it is usually expected that Basal Plane Dislocations (BPDs) are decorated by oval shaped etch pits and that Threading Edge (TEDs) and Threading Screw Dislocations (TSDs) are related to smaller and larger hexagonally shaped etch pits, respectively. It will be shown in this paper that the sampleâ?Ts doping state (dopant and its concentration) must be taken into account for correct interpretation of hexagonally shaped etch pits with respect to the type of threading dislocations. In this study, 4H-SiC substrates and homoepitaxial layers were etched in molten potassium hydroxide (KOH) at about 500°C for several minutes. The highly doped n-type substrates together with the epilayers cover a wide range of doping, i.e. n-type samples with electron concentrations in the range from 5 x 10¹⁴ cm^-3 to 5 x 10¹⁸ cm^-3 as well as p-type samples with 1 x 10¹⁵ cm^-3 < p < 1.4 x 10²⁰ cm^-3 were used. First, different etching regimes are identified by means of analysing the size distribution of hexagonally shaped etch pits for a large number of samples having different doping states. Then, the dislocation types are identified by Synchrotron X-Ray Topography (SXRT) for several samples representing the different etching regimes. This method was chosen as it is a direct and non-destructive method for the identification of dislocation types. Besides the well-known TEDs and TSDs, so-called TED II and TED III dislocations are identified in 4H-SiC for the first time. Finally, the SXRT samples were defect selectively etched in order to assign each etch pit to the underlying dislocation. For all etching regimes, each etch pit corresponds to a certain dislocation and vice versa, i.e. the etch pit density (EPD) fits the dislocation density at the sample surface. For p-type samples as well as for low n-type samples, small hexagonally shaped etch pits are correlated to all kinds of TEDs, larger hexagonally shaped etch pits are clearly linked to TSDs. For medium n-type samples, TED II dislocations are decorated by a specific etch pit type. For highly n-type SiC samples, the size of hexagonally shaped etch pits does not correlate to the type of threading dislocations anymore. Acknowledgements: This project was funded by the Bavarian Research Foundation (BFS) under contract number AZ- 720-06. We acknowledge the synchrotron light source ANKA at Karlsruhe, Germany, for the provision of beamtime at the TOPO-TOMO beamline and the beamline team, especially J. Wittge (Crystallography, University of Freiburg, Germany) for supporting the measurements.

During forward bias operation in 4H-Silicon Carbide (SiC) bipolar devices, basal plane dislocations (BPDs) fault to form Shockley Stacking fault (SSF), which expand and cause forward voltage drift in these devices [1,2]. Reverse bias breakdown voltage degradation with SSF expansion has also been reported [3]. In order to mitigate the influence of these SSFs in the active drift layer, a high doped buffer layer was grown to convert most of the BPDs to threading edge dislocations (TED) within it. This confines the BPD to the buffer and only the relatively benign TED passes through the drift layer. Previously it was thought that SSF expansion would not occur in these high doped epilayers and propagate into the drift layer. However, this assumption that BPDs within the buffer do not affect the drift layer during carrier injection has not been previously studied. In this work using electron-hole creation by UV excitation, we image the motion and faulting of BPDs in the buffer layer and show that SSFs originating in that layer expand into the drift region.

A 25 um thick n-type (3x10¹⁸ cm^-3) SiC buffer layer was grown on 4^o offcut SiC substrate, followed by a 30 um thick n-type (1x10¹⁵ cm^-3) drift layer using standard propane and silane chemistry in a commercial chemical vapor deposition reactor. Whole-wafer ultraviolet photoluminescence (UVPL) imaging was performed using the 351 nm excitation line of an Ar ion laser. The UVPL images were taken in the emission wavelength range of 600 -1000 nm. BPDs in the higher doped buffer region appeared as dark regions, and were contrasted to the BPDs in the drift layer that appeared as bright lines. Greater than 80% of the BPDs that had entered the buffer layer had been converted to TEDs before reaching the drift layer. Selected regions of the wafer having BPDs only in the buffer were imaged at higher magnification to observe their motion in the buffer region. Variable UV illumination power densities (100-4000 W cm^-2) were used to introduce minority carriers within the buffer layer. Upon high power UV illumination of >~1000 W cm^-2, the buffer buried BPDs faulted to form SSFs. These SSFs expanded throughout the buffer regions and into the drift layer, which would then result in device degradation. Note that once SSFs from BPDs in the buffer entered the drift layer the SSFs extended up to the sample surface at a much faster expansion rate. The BPDs faulting in the buffer region was correlated with the carrier density in the buffer to understand the effects of the buffers minority carrier lifetime and thickness. These correlations provide an insight into device operation conditions that lead to buffer layer BPD faulting and SSF propagation into the drift layer.

[1] J. P. Bergman, et al., Mater. Sci. Forum 353-356, 299 (2000)

[2] R. E. Stahlbush, et al., Mater. Sci. Forum 389, 427

(2002)

[3] A. Agarwal, et. al., IEEE Electron Dev. Lett. 28, 587 (2007)

SiC â?oSuperâ? Junction Transistors (SJTs) are high current gain SiC NPN BJTs developed by GeneSiC in 1200 V -10 kV ratings. 1200 V-class, 2.97 mm² active area SiC SJTs with current gains as high as 88, low on-resistance of 5.8 mâ"¦-cm² and ultra-fast switching times of < 15 ns were recently reported. This paper examines the stability of the SJT electrical characteristics during long-term DC or pulsed-mode operation with varying duty cycles (0.1 â?" 0.9), switching frequencies (100 Hz â?" 1 MHz) and at actively controlled case temperatures ranging from 25 °C to 150 °C. Specifically, the stability of the SJT current gain (β), on-state voltage drop (V_F), carrier lifetime in the p-base and n- blocking layers are examined under long-term SJT operation. The stability of the leakage currents in blocking mode after forced-avalanche and short-circuit operation of the SiC SJT are also investigated in this study. The current gain, β of a TO-220 packaged 1200 V/ 2.97 mm² SJT decreased from 70 to 55 and the V_F increased by 175 mV after 9 hours of common-Source DC operation (accumulated charge, Q_acc = 370.4 kC) at a Drain current of 7 A (233 A/cm²) and a Gate current of 0.5 A. In contrast, a minimal change in β and V_F were observed when the same Drain and Gate currents were applied at a frequency of 15 kHz and at a duty cycle of 30% for 17 hours (Q_acc of 238.1 kC), indicating a temperature dependence of the gain compression. Open circuit voltage decay measurements yielded (bulk) carrier lifetimes of 0.8-1 µs and 1-2 µs for the Source-Gate and Gate-Drain n-p and p-n diodes respectively. The carrier lifetimes were unchanged after either long-term DC or pulsed operation, in sharp contrast to the observed β compression. An examination of the Gate-Source and Gate-Drain I-V characteristics after the 9 hour DC testing revealed a higher Gate current in the sub-threshold region, and a an increase in the differential on-resistance of 12% and 7% for the constituent Gate-Source and Gate-Drain diodes, respectively after the 9 hour DC operation. These results indicate that the current gain compression is possibly due to carrier traps at the passivation layer-SiC interface. Almost full recovery of the SJT characteristics is achieved by a 300 °C/4 hour annealing treatment. More detailed results including long-duration biasing of the constituent Gate-Source and Gate-Drain junctions of the SJTs in addition to the common-Source configuration at various base-plate temperatures and leakage current stability under repeated forced-avalanche and short-circuit SJT operation will be presented in the full paper.

Synchrotron white beam X-ray topography (SWBXT) in various geometries has been successfully utilized to image nc+na dislocations in axially cut 4H- SiC crystals. Although molten potassium hydroxide(KOH) can be used to reveal the location of such dislocations on the crystals, it is not possible to determine their senses or their Burgers vector magnitude. We propose to implement the Ray Tracing simulation technique to simulate the Burgers vector of these nc+na dislocations. This technique has been successfully implemented previously in revealing the dislocation sense and magnitude of Micropipes (MP), closed core threading screw dislocations (TSD) and threading edge dislocations (TED) in 4H- SiC[1,2]. The procedure is based on the initial calculations given by Dudley et al[3] and involves comparing dislocation images obtained by Synchrotron X-ray Topography with those obtained by the Ray Tracing simulation technique. These results will be verified by using Section X-ray Topography or Reticulography to reveal the senses of these dislocations, which can be used together with the technique proposed. The threading nc+na dislocations were consistently observed throughout the axial slices nucleating right from the seed growth interface and replicating to the top of the crystal. The dislocations observed were confirmed to have Burgers vector of the type nc+na (n=integer) by Transmission X-ray Topography because of their presence in both (0001)- type reflections and (01-10)- type reflections. Grazing incidence X-ray Topography using pyramidal reflections was performed at top surface of the axial slice to image the various nc+na dislocations replicating to the top of the crystal and comparing it with the simulated images in order to determine their sense. Revealing the dislocation sense and burgers vector magnitude of these threading nc+na dislocations can provide further insight into their propagation during bulk and epitaxial growth and may shed light on strategies designed to mitigate their deleterious effects on growth. [1] M. Dudley, X. Huang and W. M. Vetter, J. Phys. D: Appl. Phys. 36, A30 (2003) [2] Yi Chen and M. Dudley, Appl. Phys. Lett. 91, 071917 (2007) [3] X.R. Huang, M. Dudley, W.M. Vetter, W. Huang, S. Vang, C.H. Carter, Appl. Phys. Lett. 74, 353(1999)

We have investigated the time dependence and physical mechanisms of the activation and relaxation of positive-bias temperature stress (PBTS) induced damage in SiC MOSFETs, which leads to more-positive shifts in threshold voltage ( V_T) at high temperature and a time-dependent recovery of V_T at room temperature. Room temperature bias-stress induced V_T instability of SiC MOSFETs has been well documented, with most devices showing positive shifts following positive gate bias stress and negative shifts following negative gate bias stress. This V_T instability can negatively impact device performance and reliability, and is of particular concern when developing devices for use in high power applications. The instability, which increases logarithmically with time, is consistent with electrons tunneling to and from oxide traps near the SiC/SiO₂ interface. An Eâ?² center defect in the oxide, which has been identified by electrically detected magnetic resonance (EDMR) techniques, is the likely cause of this instability. When SiC MOSFETs are stressed with both bias and temperature (oxide fields of ~2â^'3 MV/cm at ~150 °C, typical of desired operating conditions), the magnitude of the back-and-forth threshold voltage instability worsens. This high temperature instability increases with bias stress time and has not been observed to saturate, even out to stress times of more than 10⁵ s. Since tunneling rates are not strongly dependent on temperature, another explanation for this high temperature effect is necessary. One possible explanation is that additional trapping centers are being activated by the combination of bias and temperature, which is supported by recent EDMR results on Si and SiC. Initial V_T instability measurements following negative-bias temperature stress (NBTS) have shown a permanent degradation in device characteristics. However, following PBTS a device can quickly recover over a period of 1-2 hours with little permanent effect. This relaxation effect occurs on short enough time scales that it can obscure accurate characterization of V_T instability when applying existing reliability qualification test standards. Therefore, we have investigated the time dependence and physical mechanisms of the activation and relaxation of PBTS-induced damage through V_T instability characterization and in-situ charge pumping analysis.

Growth stresses in amorphous SiO2 scales formed during Hi-Nicalon-S SiC fiber oxidation were calculated by a numerical method, using Deal-Grove oxidation kinetics parameters previously measured for SiC fibers. Initial compressive stresses in SiO2 of ~25 GPa from the 2.2Ã- oxidation volume expansion are very rapidly relaxed to much lower levels by shear stress-dependent SiO2 viscosity. At >1200°, viscous flow of amorphous SiO2 further relaxes stress to negligible levels. At 700° - 900°C, axial and hoop stress at the GPa level persist. Increase in growth stress with decrease in temperature is a direct consequence of larger activation energy for SiO2 viscosity than parabolic oxidation kinetics. Radial stresses are negligible for scales thinner than ~0.1 fiber radii. Radial expansion of the outer scale causes hoop stress to become tensile, and eventually axial stresses become tensile by the Poisson effect. These tensile stresses can be >1 GPa for thick scales formed at <900°C. Approximate analytical expressions for some limiting cases are discussed. Growth stress-states for crystallized SiO2 scales are considered and compared to evidence of stress in crystalline SiO2 scales on Hi-Nicalon-S SiC fibers. Assumptions and limitations of the calculation method are discussed, along with implications for fiber strength, and the potential effect of growth stress on SiC oxidation kinetics.

The SiO2/SiC interface presents lower channel mobility and higher interface state density (Dit) than those typically found in SiO2/Si. These facts have been mainly attributed to the presence of C in the SiO2/SiC system, which increases the complexity of the thermal growth process compared with the SiO2/Si one. In order to improve the electrical characteristics of SiC-based structures a variety of post-oxidation annealings were already reported, such as N-containing atmospheres and annealings in H2. The use of nitric oxide (NO) reduces Dit and improves devices reliability as compared to thermal growth in O2. Concerning H2 annealings, large channel mobilities have been observed [1]. Besides, capacitors fabricated with sequential NO/H2 annealings using Pt electrode presented even better electrical results [2]. However, in order to achieve further improvement in the electrical properties of dielectric/SiC-based devices it is mandatory to understand the consequences of these combined treatments in their physico-chemical and electrical characteristics. In this work, the incorporation of H in SiO2/SiC samples annealed in NO and H2 with and without Pt electrode was investigated. To increase sensitivity and selectivity in H quantification, H2 enriched in deuterium (2H or D) was used and samples were characterized by nuclear reaction analyses. Additionally, effects of nitridation and hydrogenation on electrical characteristics were inspected by high-frequency capacitance-voltage (HFCV) measurements. Results indicate that the H incorporation in dielectric/SiC structures is highly dependent on the NO annealing and on the presence of the Pt electrode. D quantification reveals the catalytic effect of Pt in dissociating D2, since higher D incorporation was observed in Pt/dielectric/SiC structures. C-V measurements evidenced variation in the flatband-voltage shift from the ideal value depending on the annealing sequence employed pointing to a distinct passivation behavior due to NO and H2 annealings. Mechanisms of passivation provided by each sequential treatment and correlation with H incorporation will be also presented. [1] J. Senzaki, , K. Kojima, S. Harada, R. Kosugi, S. Suzuki, T. Suzuki, K. Fukuda, IEEE Electron Device Lett. 23, 13 (2002). [2] S. Wang, S. Dhar, S.R. Wang, A.C. Ahyi, A. Franceschetti, J.R. Williams, L.C. Feldman, S. T. Pantelides, Phys. Rev. Lett. 98, 026101 (2007).

One of the more promising new material systems in the semiconductor industry is SiC/SiO2, with the 4H SiC polytype among the most promising. For many years, we have utilized electrically detected magnetic resonance (EDMR) to investigate electrically active defects which affect the performance of 4H SiC metal oxide semiconducting field effect transistors (MOSFETs). We have investigated a wide range of devices and have consistently observed a dominating isotropic g â?^ 2.003 spectrum with very broad hyperfine side peaks. Although our earlier work establishes the importance of the defect associated with the spectrum, until quite recently, we were unable to definitively identify the spectrumâ?Ts physical origin, though we tentatively had linked the EDMR spectrum to a silicon vacancy. With improvements in EDMR spectrometer resolution and sensitivity, and utilizing new techniques such as electrically detected fast passage resonance, we have been able to clearly observe 13C hyperfine interactions in the g â?^2.003 spectrum, which provide an essentially definitive identification of the EDMR spectrum, since these interactions had previously been observed and convincingly interpreted in conventional electron paramagnetic resonance (EPR) measurements of silicon vacancies in large volume 4H SiC samples. Our fast passage measurements reveal an additional EDMR spectrum in the SiC devices. The additional spectrum is clearly not involved in the g â?^ 2.003 defectâ?Ts resonance. The newly observed EDMR spectrum is strongly orientation dependent and is consistent with a 100% abundant magnetic nucleus with a nuclear spin no higher than 1 and a relatively small, but measurable, contribution to the spectrum from spin orbit coupling. Preliminary observations demonstrate that the newly observed spectrum consists of multiple lines, at least two and possibly three. The hyperfine interactions lead to a splitting of the outer lines of 70 Gauss when the magnetic field is perpendicular to the crystalline c axis and approximately 54 Gauss with the field parallel to the c-axis. The g is also orientation dependent. With the magnetic field approximately parallel to the c-axis, g â?^2.002; with the c-axis perpendicular to the field g â?^2.004. Although a full map of g and hyperfine parameters has yet to be completed, the results strongly suggest that the second defect is a complex involving a nitrogen atom. (Nitrogen has a 100% abundant spin 1 nucleus and is the only obvious candidate.) Since both of these EDMR virtually certain spectra appear in devices subjected to significantly different processing parameters, they are virtually certain to be quite important in the emerging SiC/SiO2 technology.

Silicon carbide (SiC) is one of the few semiconducting materials that combine biocompatibility and great sensing potentiality. SiCâ?Ts chemical inertness, superior tribological properties, hydroxyapatite-like osseointegration, and well-known hemocompatibility make it a very promising material for an intelligent implantable sensor, which will be bio-compatible in nature, have a longer operational lifetime and sensing capability, and will not require additional encasing. This implantable sensor is basically a high frequency (GHz) SiC antenna. The hypothesis of a SiC based antenna, to be used for glucose monitoring for instance, is that the changes in the medium surrounding the antenna affect the antenna properties such as input impedance and resonance frequency, and these changes can be used to estimate the patientâ?Ts plasma glucose level. This hypothesis is based on the assumption that the changes in other minerals in the blood (calcium, chloride, potassium, and magnesium) will have a minor effect on antenna parameters. In reality, this assumption is quite reasonable. Ansoft simulation results show a resonance frequency shift dependency on the permittivity change surrounding the antenna sensor. In our simulations, the relative permittivity of the boundary conditions were changed from 6 (fat) to 12 (bone) for the antenna. As a result, the resonance frequency of the high permittivity surrounded antenna was shifted toward a smaller frequency by 0.35 GHz. The development of a fully SiC based implantable RF antenna is part of the critical path for a continuous glucose monitoring system. A simple patch antenna is selected for this antenna sensor. A simulation of the patch structure using heavily doped (10 ²⁰ cm^-3) SiC shows very promising antenna performance. Several approaches have been used to get a highly doped antenna radiating element. 4H-SiC semi-insulating wafers were used as substrates to grow highly doped 4H-SiC epitaxial layers (homoepitaxial) using a chemical vapor deposition (CVD) system, where nitrogen (N₂) was used as n type dopant. After growing the highly doped epilayer, the device was fabricated using a designed antenna mask. The patterned doped epilayer defined the antenna electrode. Other approaches (ion implantation and activation annealing) were also used for this sensor. Finally, a highly doped poly 3C-SiC, well known for its hemocompatibility, was used as the antenna electrode. Here the same 4H-SiC semi-insulating substrate was used for the antenna substrate. The native oxide SiO₂(5 µm) was deposited using PECVD followed by a 100 nm poly-Si deposition. Nitrogen-doped poly-3C-SiC films were deposited by LPCVD at 1225° C and 400 Torr using 10% SiH₄ (48 sccm) and 100% C₃H₈ (2 sccm) as the Si and C precursor gases, and 100% N₂ (25-50 sccm) as the dopant gas. This process is ideal for realizing antenna structures on semi-insulating substrates, which is needed to create an all-SiC, and therefore completely bio-compatible, sensor.

Silicon Carbide (SiC) has long been recognized as being an excellent semiconducting material for high power, high frequency and high temperature electronics due to its outstanding electrical, mechanical and thermal properties. SiC has emerged as the leading structural material for harsh environment microelectromechanical systems (MEMS) due to a combination of exceptional electrical, mechanical and chemical properties that make SiC particularly well suited for high temperature, high wear and chemically aggressive applications. Fabrication techniques that were originally developed for Si MEMS have been readily adapted to fabricate micro- and nanoelectromechanical systems (NEMS) from SiC. SiC is a particularly attractive structural material for mechanical resonators owing to its high Youngâ?Ts modulus-to-density ratio which enable the realization of simple, clamped beam resonators with fundamental frequencies in the GHz range. The chemical inertness of SiC greatly aids the fabrication of the structures. Suspended diaphragms fabricated by bulk micromachining were among the first MEMS structures fabricated from SiC and such structures have been extensively used for fundamental materials characterization as well as structural elements in pressure transducers. SiC diaphragms have since found use in a wide range of application areas including bioMEMS and imaging. This presentation will review the development of SiC as a structural material in diaphragm-based MEMS as well as recent advances by our group to develop these structures for use in electromechanical resonators.

Polycrystalline 3C-SiC films have been grown on 100 nm thick CVD polysilicon seed-layers that were previously deposited on an oxide-coated (001) Si substrate. This polysilicon-on-oxide substrate offers an innovative method to overcome the difficulties of fabricating MEMS structures from poly-SiC films grown directly on Si substrates. The oxide layer functions as a MEMS sacrificial release layer and provides some degree of stress control through the relaxation of the stress present within the SiC film during growth[1,2]. However, in order to fully realize the benefits of the polysilicon-on-oxide substrate, the understanding and control of the residual stress-dependent deformation of MEMS structures are of primary importance for SiC-MEMS devices. Polycrystalline 3C-SiC films were deposited on polysilicon-on-oxide substrates via CVD at 1150°C using a silane and propane precursor chemistry. Depositions were conducted using a low and high total precursor concentration, measured relative to the carrier gas, while maintaining the same temperature, pressure, and carrier gas flow for both growth processes. Growth times were adjusted to compensate for growth rate differences in order to produce the same film thickness for all films grown. Atomic force microscopy (AFM) imaging of the film surfaces demonstrated noticeably different morphology between the films grown at the low and high precursor concentrations. Optical profilometry, scanning electron microscopy (SEM), and micro-Raman measurements were used to assess the film stress via stress-sensitive structures micromachined from the polysilicon carbide films. The stress present within the polysilicon carbide films grown using the precursor-reduced process displayed tensile stress values monotonically decreasing from +250 MPa to +60 MPa when the Si/ C ratio was varied from carbon-rich to silicon-rich, respectively. In contrast, the poly-SiC films grown using the precursor-enriched deposition process exibited a compressive film stress value of -300 MPa for carbon-rich and silicon-rich Si/ C ratios, but had a minimum compressive stress value of -200 MPa for near-stoichiometric Si/ C ratios. Interestingly, the precursor-reduced and precursor-enriched growth processes produced films with opposite strain gradients, independent of the Si/ C ratio. The resulting free-standing structures fabricated from the films exhibited upward or downward deflections depending on the growth process. The results may lead to a growth process aimed at producing nearly stress-free polycrystalline SiC-MEMS structures suitable for advanced MEMS applications. [1] G.M. Beheim, L. Evans, Deep Reactive Ion Etching for Bulk Micromachining of Silicon Carbide, in M. Gad-el-Hak(ed.), MEMS: Design and Fabrication, second ed., Taylor & Francis Group, Boca Raton, FL, 2006 [2] J. Ayers, "Compliant Substrates for Heteroepitaxial Semiconductor Devices: Theory, Experiment, and Current Directions." J. of Electron Mater., 37, no. 10 (2008): 1511-1523

Current methods to monitor certain physiological parameters tend to require labeling procedures that are time consuming and produce results after a couple hours [1]. Moreover, in the intensive care unit, many physiological parameters require continuous and real time monitoring, especially for patients suffering from acute myocardial infarction (AMI). Several proteins can be used for the diagnosis of AMI, including Troponin I, Creatine kinase (CK1) and Myoglobin (Myo). However, Myo concentrations in blood rise quickly after 1 hour after the onset of AMI [2]. Silicon Carbide (SiC), more specifically 3C-SiC, has been proven to be a bio- and hema-compatible substrate [3], [4], that could be used in longer term applications. Our goal is to use the excellent electrical and chemical properties of 3C-SiC [5] in order to build an electrode array for Myo detection. In this work we describe the characterization of anti-myoglobin (anti-Myo) immobilization on 3C-SiC (100) by means of surface modification with 3-aminopropyltriethoxysilane (APTES). Surface water contact angle measurements were used to compare the wettability of 3C-SiC (100) before (12.6°±3°) and after (50.8±3°) APTES layer formation. Atomic force microscopy (AFM) was used to confirm the homogenous formation of APTES and anti-Myo immobilization with EDC-sulfo NHS coupling. For APTES no significant change on the surface roughness was obtained whereas with anti-Myo surfaces, particles on the order of ~60 nm in diameter with globular shape were observed as in [6]. With Impedance spectroscopy, changes in the interface for the subsequent layers (3C-SiC, APTES/3C-SiC, anti-Myo/EDC-sulfo NHS/APTES/3C-SiC) were monitored. In addition an equivalent electronic circuit was obtained in order to describe the parameters that control the semiconductor/biomolecule interface at different frequency ranges. References [1] E. P. Diamandis and T. K. Christopoulos, Immunoassay. Academic Press, 1996. [2] R. H. Christenson and H. M. Azzazy, â?oBiochemical markers of the acute coronary syndromes.,â? Clinical chemistry, vol. 44, no. 8 Pt 2, pp. 1855-64, Aug. 1998. [3] N. Schettini, M. Jaroszeski, L. West, and S. Saddow, â?oSiC hemacompatibility for cardiovascular applications,â? in Silicon Carbide Biotechnology, S. E. Saddow, Ed. Elsevier Ltd. [4] S. E. Saddow et al., â?oSingle-Crystal Silicon Carbide: A Biocompatible and Hemocompatible Semiconductor for Advanced Biomedical Applications,â? Materials Science Forum, vol. 679-680, pp. 824-830, Mar. 2011. [5] S. Saddow and A. Agrawal, Advances in Silicon Carbide Processing and Applications, First. Norwood, MA: Norwood: Artech House, 2004, p. 205. [6] L. Yang and Y. Li, â?oAFM and impedance spectroscopy characterization of the immobilization of antibodies on indium-tin oxide electrode through self-assembled monolayer of epoxysilane and their capture of Escherichia coli O157:H7.,â? Biosensors & bioelectronics, vol. 20, no. 7, pp. 1407-16, Jan. 2005.

One of the more promising techniques for forming graphene has been the thermal decomposition of SiC at high temperatures in UHV (1). In this approach Si atoms sublimate at high temperatures (TG) creating a C rich surface that slowly forms graphene layers. One advantage is that graphene can be formed over large areas on underlying SiC that can be insulating/semiconducting and thus suitable as a device fabrication substrate. One disadvantage, in addition to the high processing temperatures, is that conventional techniques that are required for fabricating graphene-based devices can expose the graphene to chemicals, polymers, or other processing steps that unintentionally dope the graphene, reduce its mobility or otherwise alter surface properties. In this talk we report on an ion beam lithography (IBL) approach that: 1) selectively forms graphene where the SiC is implanted with ions; 2) forms graphene only in these implanted regions, and at processing temperatures lower that TG; and 3) can simultaneously perform nanoscale patterning for nanoelectronic device features where desired, without conventional masking and associated processing steps. The University of Florida multi-ion beam lithography, nanofabrication and engineering (so-called MionLiNE) system was used to implant 60 keV Au and Si ions into commercially available 4H and 6H SiC single crystals that were subsequently annealed in a quartz tube oven at 0.5-1 X 10â^'6 Torr pressure to 1200-1300 C. At temperatures 100 C below TG graphene was formed only where the ions were implanted. Large area graphene features 20μm x 20μm were synthesized for subsequent analysis, as well as 2 â?" 200 nm wide and 5 µm long graphene nanoribbons (GNRs). Analysis with AES at 3 keV, SEM, and micro-Raman with a 532 nm laser source verified that the ion implanted and annealed regions were uniform graphene films or GNRs. Details of the implantation, annealing, and analysis of this approach for synthesis of GNRs on SiC will be presented and mechanisms controlling the results will be discussed. 1. C. Berger, Z. Song, T. Li, X. Li, A. Y. Ogbazghi, R. Feng, Z. Dai, A. N. Marchenkov, E. H. Conrad, P. N. First, and W. A. de Heer, J. Phys. Chem. 108, 19912 (2004)

Silicon carbide (SiC) thin films and their unique physical (electrical, optical, mechanical, and thermal) properties offer strong promises for a wide spectrum of critical applications ranging from high-temperature microelectronics to nano and microelectromechanical systems (NEMS/MEMS) suited for harsh environments. Today in many cases the nanostructural processing limits the realization of nanoscale SiC devices. For example, making NEMS/MEMS and enabling three-dimensional structures and integration with nanoscale precision in various SiC materials, especially in bulk single crystal SiC (e.g., 4H- & 6H-SiC) â?" which could be desired from the materials perspective â?" remain challenging. Bulk and surface nanomachining of SiC demands more innovations to fully realize the materialsâ?T potential and promises. Recent advances in focused ion beam (FIB) microscopy and programmable nanomachining open new possibilities in high-resolution FIB nanofabrication and refinement of SiC nanostructures and functional devices. This work presents a systematic investigation of the fundamentals of FIB nanomachining of SiC nanodevices, from understanding of the key physical effects to probing the ultimate and practical limits of such processes. We combine carefully designed FIB nanomachining calibration experiments, with analytical and numerical modeling. First, we have performed thorough measurements on patterns specifically designed for FIB, and quantitatively measure the sputtering yield of SiC with Ga+ ions in FIB, at different ion beam conditions and for different target materials (SiC polytypes). We compare the obtained sputtering yield of SiC with those of other materials. It is known that accelerated FIB at different energies has different effects on the target material: beam at lower energies has a much higher elastic, nuclear interaction with the target material â?" nuclear stopping â?" compared to the inelastic electronic stopping. However, as the ion beam energy increases, the situation converses. The energy at which this change of major energy loss factor happens is found using Monte Carlo simulator, SRIM. Then, using an FEI Nova dual beam SEM, we explore and quantify the dependency of sputtering yield on ion beam energy and current, with beam energy at 30keV, having currents of 0.1nA, 0.3nA, 0.5nA and 1nA, and with beam current being 0.5nA but having beam energies of 30keV, 20keV, 15keV and 10keV. The sputtering yield Y is found using the relation, Y=(A*q*d*N_T)/(I*t) where N_T, I, A, t and q are respectively density of the target material, ion beam current, exposure time, exposed area and Ga+ beam charge. Beyond the deterministic measurements of sputtering yield, this work also describes measurements and analyses of dimensional, geometrical, and surface roughness effects on sputtering yield, the doping and damaging profile, and the variation of SiC filmâ?Ts conductivity and devicesâ?T performance.

This paper presents the application of the novel Thermal Laser Separation (TLS) dicing technology which allows for an ablation free separation of 4H-SiC wafers with feed rates up to 200 mm/s without chipping. Results of this work play an important role in improving the SiC dicing process regarding throughput and edge quality. TLS process parameters were developed for separating 4H-SiC wafers. Separated SiC dice were analyzed and compared with results of state of the art blade dicing technology. For the first time, fully processed 100 mm 4H-SiC wafers with a thickness of 450 μm, including epi-layer and back side metal layers, could be separated with feed rates up to 200 mm/s. Besides the vastly improved dicing speed, the TLS separation process results in two important features of the separated SiC-devices: First, the edges are free of chipping and therefore of higher quality than the edge quality produced by blade dicing. Second, the TLS process is ablation free, which allows for reducing the necessary dicing street width. TLS is a two-step process: a diamond tip or an ablation laser is used to produce an initial scribe as a predetermined separation point. Laser-based heating and subsequent cooling locally induces mechanical stress inside the SiC wafer. This mechanical stress is capable of guiding a crack through the SiC wafer starting at the initial scribe following the path of the heating/cooling spot. The TLS process is an ablation free and hence a kerf free dicing process which generates edges of higher quality compared to blade dicing and laser ablation techniques. For the experiments we used 100 mm highly N-doped 4H-SiC wafers with a thickness of 450 μm including epi-layer and back side metal layers. The wafers were passivated with a polyimide layer; the dicing streets were free of polyimide in a range of approx. 80 μm. Chip dimensions were approx. 4x4 mm^2. The test wafers were mounted on dicing frames with adhesive tape. The TLS process was performed using a 200 W continuous wave (cw) fiber coupled fiber laser system at a wavelength of 1064 nm. Cooling was done by a water aerosol with an amount of water of 7-9 ml/min. We achieved feed rates between 50 mm/s and 200 mm/s at laser powers between 110 W and 200 W. Resulting edges were identified with scanning electron microscopy (SEM) to be free of front side and back side chipping as well. The chip side walls are very smooth. Compared to blade dicing results we could demonstrate that TLS has the potential to increase the throughput by a factor of up to 200 and concurrently avoiding the unwanted chipping. Therefore TLS is a promising technique for future SiC-based electronic devices. Further investigation will focus on smallest chip dimensions and improving the contour accuracy. Photo elastic studies of stress are planned to verify that no stress remain in the separated SiC dice. The authors would like to thank our partners from Infineon who provided test wafers and fruitful discussions.

Basal plane dislocations (BPDs) in 4H-SiC epilayers are a limiting factor of making SiC bipolar devices. Under forward bias, stacking faults expand from the BPDs and cause the voltage drop across the p-i-n diodes to increase over time. To eliminate them from the epilayers, different strategies have been pursued. The direct way is to grow epilayers on on-axis substrates, which eliminates the possibility of BPDs in the substrates intersecting the interface and entering the epilayers. The other approach is to utilize the phenomenon of BPDs converting to TEDs (threading edge dislocations) during off-axis epitaxy. The conversion mostly happens at the interface and ~90% BPDs convert in unoptimized epitaxy. Several processing steps have been proposed to enhance the conversion ratio, including patterning or etching the substrate surface and adding growth interruptions. While the growth/processing parameters are being tuned and optimized, physical understanding of the phenomenon has also been improved. This paper reports our discovery of conversion of BPDs to TEDs in 4H-SiC epilayers by simple high temperature annealing. The epilayers, which were grown on the Si-face of n-type conductive 4H-SiC wafers 8° off-cut towards [11-20], of ~10 μm in thickness with unintentional doping were used as samples. Grazing incidence reflection synchrotron X-ray topography (g=-1-128 and λ=1.541 â"«, at SPring-8) was used to image the dislocations in the epilayers. By comparing the X-ray topographs before and after annealing, we found that simply increasing the temperature to 1800 °C in argon ambient can convert BPDs to TEDs. Before annealing, BPDs appeared as line contrasts propagating in the epilayers and reaching the epilayer surface. After annealing, dot contrasts typical of threading dislocations were observed at the down-step ends of some BPDs. Meanwhile the projected lengths of those BPDs to the step-flow direction were shortened. Such observations indicate those BPDs have converted to TEDs starting from the epilayer surface and proceeding to certain depths, which formed BPD-TED structures. The conversion depth for annealing at 1800 °C for 5 minutes was about 5 μm in average. The conversion was further proven by molten KOH etching of the annealed samples. Hexagonal etch pits representing TEDs were observed at the down-step ends of the BPD-TED structures. The conversion ratio was affected by several factors, including the temperature and surface protection during annealing, and the nitrogen doping concentrations in the epilayers. Our preliminary results showed that ~40% conversion can be achieved by annealing undoped 4H-SiC epilayers without surface protection at 1800 °C for 30 minutes. Acknowledgement: This research is partly supported by the Japan Society for the Promotion of Science (JSPS) through its â?oFunding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program)â?.

SiC is a promising semiconductor for applications in next-generation high-performance power devices. The common technique to produce a SiO2 layer on SiC is oxidation at high temperatures. High density of interface states and low carrier channel mobility have been the challenging obstacles in SiC-based MOSFETs. It is known that post processing with nitric oxide (NO) at high temperatures significantly improves the electrical properties of SiC MOS devices. However, improvement of the channel mobility using the NO post-process is limited due to the complexity of interactions and reactions between NO and SiC on the interface. New techniques for further improvement of the dielectric/SiC interface need to be developed. We report the surface structures and compositions on SiC after annealing at 1350°C pure N2 at different nitrogen pressures, and discuss the surface chemical reactions with SiC. SiC was placed at 900°C in low pressure H2 for removal of surface oxides. After pumping out H2, N2 is used to fill the growth chamber and the temperature is increased to 1350°C with 20°C/min rate. The sample was annealed for 30 minutes at 1350°C in N2 at 0.1, 50, 100, and 760 torr. Analysis using X-ray photoelectron spectroscopy (XPS) shows that nitrides were not detected when the N2 pressure is 0.1 torr, but their concentration increases as the nitrogen pressure is increased from 50 to 760 torr. Silicon nitride (Si3N4) with carbon-nitrogen containing species are the main products at high nitrogen pressure. At low nitrogen pressure, graphitic carbon with a small amount of silicon nitrides are the main products. Also, at low nitrogen pressure, SiC thermal decomposition and oxidation by residual oxygen become the dominating reactions and the SiC surface is covered by graphitic carbon similar to the known growth of graphene/SiC structures in vacuum in this range of temperatures. Comparing with the NO processed SiC at 1175°C, the pure N2 process results in reduced amounts of oxides and oxynitrides. Acknowledgements: This work is supported by National Science Foundation (NSF).

SiC has attracted a lot of attentions on high-voltage, high power applications. SiC lateral devices with different functions have the advantage of being integrated on the same chip, and power ICs based on SiC have been successfully demonstrated in recent years. In this talk, a novel concept of designing 4Hâ?"SiC lateral devices on semi-insulating substrates based on charge compensation principle will be introduced and the design issues will be discussed. In the simulation, field plates are critical in relieving the electric field crowding at junction corners at high reverse biases. By incorporating field plates with proper lengths, breakdown voltage of a single zone reduced surface field (RESURF) device with a 100 um drift region can be improved from 3360 V to 5880 V. The breakdown voltage can be further enhanced to 8000 V by using a two-zone RESURF structure. The reduction in breakdown voltage by 10% charge imbalance variation is also improved from 49% for a single zone structure to 36% for a two-zone structure. Simulation also shows that oxide charges and other surface charges will offset the optimized charge imbalance conditions and, therefore, should be considered in design if the amount is significant. Several types of devices based on this concept have been fabricated. A lateral SiC PN diode with 80 um drift region length shows a breakdown voltage of 3130 V with a differential Ron of 400 mΩ-cm2. A lateral SiC MOSFET with 80 um drift region length and 5 um gate length shows a breakdown voltage of 3520 V with a Ron of 600 mΩ-cm2. A lateral SiC JFET with a 100 um, single zone RESURF drift region and 9 um gate length shows a breakdown voltage of 3510 V with a Ron of 390 mΩ-cm2. The improved Ron of a JFET is attributed to the better channel mobility compared with a MOSFET. The breakdown voltage of JFETs is further improved to 4200 V by using a two-zone RESURF in the structure. The Ron is 454 mΩ-cm2, yielding a BV2/Ron of 38.8 MW/cm2

The realization of modern metal-oxide-semiconductor (MOS) power devices based on silicon carbide (SiC) has shown impressive progress. However, SiC power devices have been suffering from the low interfacial quality of as-oxidized SiO2/SiC, which makes the devices exhibit high interface trap density (D_it). This leads to the significant degradation of channel mobility and increases the deviceâ?Ts on-resistance (R_on). Several interface passivation techniques were proposed to alleviate this problem. Considering another issue of SiC-MOS devices beyond the interface quality, some studies on bias-temperature instability (BTI) in SiC-MOS capacitors and SiC double-implanted MOSFETs (DMOSFETs) reported electrical characteristic instabilities of the devices operated at high-temperatures. They suggested that performing negative/positive bias-temperature stress (BTS) on SiC-MOS devices induces flatband voltage (V_FB) and threshold voltage (V_TH) shifts due to trapped charges and/or mobile ions in thermal oxides [1,2]. Even though, BTIs (i.e. NBTI and PBTI) in SiC-MOS devices at high-temperature have been heretofore reported, it has been believe that the mechanism of BTIs in SiC-MOS devices is obviously different as compared with Si. Moreover, the concrete evidence of mobile ion phenomena in SiC is still unclear and needed further investigation. Our studies on BTIs in 4H-SiC MOS capacitors revealed the spontaneous generation of positive mobile ions in thermal oxides which could be considered as an intrinsic phenomenon in 4H-SiC MOS devices with thermally grown oxides. These mobile ions can move and then cause V_FB instability only at high-temperatures (typically T>100°C). Bidirectional C-V characteristics of the fabricated capacitors measured at high-temperatures showed counter-clockwise C-V hysteresis indicating the existence of mobile ions in the oxides. We also compared the result with Si-MOS capacitors fabricated with same device fabrication conditions and equipment, but no mobile ion effect was observed in these Si-MOS capacitors. Because of this reason, we conclude that intrinsic mobile ion phenomena generally occurs in only SiC-MOS devices, which is probably due to C-related mobile charge species formed in SiO₂ dielectrics during thermal oxidation of SiC substrates. As well, we can exclude the extrinsic mobile ionic contamination in this study. Moreover, we have found that although these mobile ion effects can be alleviated by post-oxidation annealing (POA) in Ar, passivation of the interface defects by high-temperature hydrogen annealing recreates additional mobile ions despite the improved interface quality. Furthermore, we have recently proposed a novel technique for overcoming BTIs in SiC-MOS devices. The details of the recovery method will be discussed in the meeting. [1] M.J. Marinella et al., Appl. Phys. Lett. 90, 253508 (2007). [2] A. J. Lelis et al., Master. Sci. Forum 600-603, 807 (2009).

Threshold voltage (VT) instability remains an important issue for the development, performance and reliability of large-area (> 0.5 cm2) SiC power MOSFET devices. A large number of near-interfacial oxide defects are present in these devices, and appear to cause the VT instability generally observed in state-of-the-art SiC MOSFETs. Recent studies have shown the effects of DC bias temperature stressing on the performance and reliability of SiC MOSFET devices, but DC stress conditions do not accurately simulate the AC stresses observed in power conversion applications. Since these devices are used primarily as switching components in power electronic circuits, it is important that we investigate the effects of AC switching on the high temperature reliability performance of power SiC MOSFET devices. Therefore, an AC test bed which simulates application-specific environmental conditions has been developed to evaluate power MOSFET devices configured as a single phase-leg. Preliminary results show an increase in oxide-trap activation following high temperature AC stressing, which is in good agreement with our DC stress results. Additionally, we observe an increase in the OFF-state drain leakage current as the stress time is increased. Pre-cursor oxide defect sites may become electrically active oxide trapping centers as a result of AC stressing at high temperature. The number of these active defects depends on the magnitude of the stress bias, temperature, and time. As the number of active traps increase, more charge is able to change charge state during switching events and shift VT accordingly. In the full paper, we will compare AC and DC high-temperature stress results and determine if the simpler DC test results can be used to predict device reliability under more complex AC test conditions.

A number of experimental studies in recent years have demonstrated the threshold-voltage instability effect in SiC MOSFETs. This effect has been attributed to the direct tunneling of electrons into and out of near-interfacial oxide traps, and the significant increase in this instability under high-temperature bias stress conditions has been attributed to the activation of additional oxide traps over time. This work reports the development of a simultaneous two-way tunneling model, based on an existing one-way tunneling model, to simulate the time-dependent and field-dependent charging and discharging of the near-interfacial oxide traps in response to an applied gate-bias stress. It is important that a two-way model be used, since depending on the electric field in the oxide and the distribution of charged and uncharged traps at a given spatial depth, electrons are likely to be both tunneling in and out simultaneously during a given period of time. Therefore, the model determines the new distribution of charged oxide traps at every increment of time by finding this net difference, with the tunneling probabilities calculated using the WKB approximation. This model is applied to both the bias stress periods, as well as during the measurement periods, when the gate-to-source voltage is being ramped. The two-way tunneling simulations successfully match experimental results, both with respect to measurement time and to bias-stress time as a function of gate bias. The model can illustrate the evolution of the charged oxide-trap distribution versus time during a long-term stress, indicating the effect of the tunneling front wherein traps in its wake (and closer to the semiconductor interface) have settled on a new steady-state balance of electrons tunneling in and out whereas traps beyond the front have yet to be affected. It can also show the dramatic change in the charged oxide-trap distribution during a ramped measurement. For a fast sweep simulation, only traps relatively close to the interface change charge state during the simulated measurement, whereas for longer sweep times states further in change state as well. This explains the strong dependence of measurement time on the total threshold-voltage instability observed experimentally. The full paper will also explore the more complicated possibility that the charging and discharging of the near-interfacial oxide traps involves a two-step process with interface traps acting as an intermediary. This is because oxide trap states that lie well below the Si valence band edge may very well lie within the wider bandgap of SiC.