Chris Bower RTI International
Phil Garrou RTI International
Kenji Takahashi Toshiba Corporation
Peter Ramm Fraunhofer Institute IZM
Y1: Fabrication of 3-D ICs
Monday AM, November 27, 2006
Room 305 (Hynes)
9:30 AM - **Y1.1
CMOS-Compatible Silicon Through-vias for 3D Process Integration.
Cornelia Tsang 1 , Paul Andry 1 , Edmund Sprogis 2 , Chirag Patel 1 , Steven Wright 1 , Bucknell Webb 1 , Dennis Manzer 1 , Raymond Horton 1 , Robert Polastre 1 , John Knickerbocker 1 Show Abstract
1 , IBM T. J. Watson Research Center, Yorktown Heights, New York, United States, 2 , IBM Systems and Technology Group, Essex Junction, Vermont, United States
As the limits of traditional CMOS scaling are approached, process integration has become increasingly difficult and resulting system-level performance is less effective. Consequently, the search for new two- and three- dimensional solutions has been pursued. One such solution is a silicon carrier-based System-on-Package (SOP) that enables high-density interconnection between heterogeneous devices beyond current first level packaging densities. Silicon carrier packaging contains electrical through-vias, fine pitch Cu wiring and high-density solder pads/joins, all of which are processed using traditional semiconductor methods and tools. These same technology elements, especially the through-via process, can enable three dimensional stacking and integration. An approach to fabricating electrical through-vias in silicon is described, featuring annular-shaped vias instead of the more conventional cylindrical via. This difference enables large-area, uniform arrays to be produced with high yield as it is simpler to integrate into a conventional CMOS back-end-of-line (BEOL) process flow. Furthermore, the CTE-matched silicon core provides improved mechanical stability and the dimensions of the annular via allows for metallization by various means including copper electroplating or CVD tungsten deposition. Two processes will be described, one containing a conductor metal filled within the insulated annulus and the other containing conductor metal in the core of the via between the inner annular walls. In the case of the annular conductor, plated copper and CVD-deposited tungsten fill will be compared with regards to ease of process integration, yield and reliability under thermal cycling. Silicon carriers (45 mm x 48 mm) containing more than 51,000 electrical through-vias were built to measure yield and determine process feasibility and robustness. Via resistance, current carrying capacity and thermo-mechanical reliability are discussed. Electrical characterization before and after deep thermal cycling was performed on collections of modules as well as at wafer level. Through-via resistances of ~10 milli-ohms are typical, and through-via yields in excess 99.9% have been demonstrated.
10:00 AM - **Y1.2
Recent Advances in 3D Integration at IMEC
Piet De Moor 1 , Wouter Ruythooren 1 , Philippe Soussan 1 , Bart Swinnen 1 , Kris Baert 1 , Chris Van Hoof 1 , Eric Beyne 1 Show Abstract
1 MCP, IMEC, Leuven Belgium
The 3D integration developments at IMEC are split in 3 different types, based on the different technologies available in different industrial technology platforms: packaging & assembly, wafer level packaging and CMOS foundry services. The corresponding 3D technologies are 3D System-in-a-package (3D-SiP), 3D Wafer level packaging (3D-WLP), and 3D Stacked IC (3D-SIC).In 3D-SiP technology the stacking of the different components is performed on packaging level (e.g. using printed circuit boards with through vias) and interconnected using wire bonding and/or solder ball placement and flip-chip. The interconnect density that can be achieved is rather limited: 2-3 per millimeter (peripheral) up to 5-10 per square millimeter when using area redistribution. The resulting 3D stacks typically contain different dies with different functions such as sensors, read-out electronics, wireless transceivers, power management. We have been realizing a 14x14 square millimeter autonomous wireless node for EEG/ECG sensing applications.3D-WLP integration technology uses fully finished wafers as a starting material. Two different form factors are developed: die stacking and thin chip embedding. In die stacking technology, through wafer vias are realized using deep reactive ion etching, conformal dielectric deposition, and (partial) filling using electroplated Cu. This via process is carried out before or after wafer thinning to a final thickness of 50 – 100 micron. After dicing, the dies are flip-chip assembled using solder or an intermetallic compound as the electrical interconnect. In the die embedding flow, the wafers are thinned down to 10 – 20 um, and subsequently transferred to a host substrate. The electrical interconnection is realized by MCM processing using thick dielectric layers and Cu electroplating. Both methods allow vertical interconnect densities of 10 – 20 per millimeter and 100 – 500 per square millimeter. In terms of interconnect density, 3D-SIC is the most advanced technology. It requires a modified CMOS process flow: at the level of the first Cu interconnect layer in the back-end process, deep vias are being etched in the Silicon substrate. After deposition of an insulating oxide layer, the vias are filled using electroplated Cu and subsequently planarized using CMP. After completion of the full back-end process, the wafers are thinned to 20 micron thickness, and the bottom of the Cu nails is accessed. Then the connection to the next thin layer is realized using thermocompression bonding of Cu. Via pitches of 10 micron have been achieved, resulting in a vertical interconnect density of up to 10000 per square millimeter. Yielding daisy chains have been obtained, indicating a via resistance close to the theoretical value calculated using bulk Cu resistivity.A state-of-the art of the different developments and their results will be given.
10:30 AM - **Y1.3
Integration Technologies for 3D Systems
Armin Klumpp 1 , Peter Ramm 1 , Robert Wieland 1 , Karl-Reinhard Merkel 1 Show Abstract
1 Si & VSI, Fraunhofer Institute IZM-Munich, Munich Germany
3D-Integration is a promising technology towards higher interconnect densities and shorter wiring lengths between multiple chip stacks, thus achieving a very high performance level combined with low power consumption. This technology also offers the possibility to build up systems with high complexity just by combining devices of different technologies. For ultra thin silicon is the base of this integration technology, the fundamental processing steps will be described, as well as appropriate handling concepts.Three main concepts for 3D integration have been developed at IZM. The approach with the greatest flexibility called Inter Chip Via - Solid Liquid Interdiffusion (ICV-SLID) is introduced. This is a chip-to-wafer stacking technology which combines the advantages of the Inter Chip Via (ICV) process and the solid-liquid-interdiffusion technique (SLID) of copper and tin. The fully modular ICV-SLID concept allows the formation of multiple device stacks. A test chip was designed and the total process sequence of the ICV-SLID technology for the realization of a three-layer chip-to-wafer stack was demonstrated. The proposed wafer-level 3D integration concept has the potential for low cost fabrication of multi-layer high-performance 3D-SoCs and is well suited as a replacement for embedded technologies based on monolithic integration. To address yield issues a wafer-level chip-scale handling is presented as well, to select known-good dies and work on them with wafer-level process sequences before joining them to integrated stacks.
11:30 AM - **Y1.4
High Density Direct Bond Interconnect Technology™ for Three Dimensional Integrated Circuit Applications.
Paul Enquist 1 Show Abstract
1 , Ziptronix, Inc., Morrisville, North Carolina, United States
Three dimensional integrated circuits (3D ICs) have the potential to increase performance by reducing signal delays with vertical interconnects and reduce cost by partitioning integrated circuit design and fabrication into separately optimized process nodes. Many 3D IC applications will require a high density of vertical interconnections to replace conventional horizontal interconnections. For bulk silicon CMOS 3D ICs, the highest density of vertical interconnections can be achieved when vertical interconnections are formed when two partitions are bonded to construct a 3D IC. Copper thermo-compression bonding has demonstrated the highest density of vertical interconnections, however this technique is typically limited to wafer-to-wafer bonding. In order to realize the 3D IC cost benefit potential, a known good die-to-wafer bonding solution is required.Direct oxide bonding has been proposed as a preferred technology for the fabrication of 3D ICs using known good die-to-wafer bonding. However, this bonding technique is not able to form electrical interconnections when used to construct a 3D IC. A Direct Bond Interconnect (DBI™) technology has thus been developed that uses direct oxide bonding to form a very high density of electrical interconnections when two chemomechanical polished (CMP) planarized surfaces are bonded together.The scalability of the DBI™ technology has been demonstrated at 1,000,000 connections and less than a 10um pitch, or a connection density in excess of 1,000,000 / cm2. A DBI™ connection yield in excess of 99.999% and bare die reliability in excess of JEDEC standards have been achieved.The DBI™ technology has been designed for manufacturability as it requires a small number of process steps including only a single mask layer, can be implemented with standard production tools, and can be integrated with a standard foundry process flow.
12:00 PM - **Y1.5
3-D Integration Latest Developments at LETI.
Barbara Charlet 1 Show Abstract
1 LETI/DIHS/LTFC, CEA/Grenoble, Grenoble France
12:30 PM - **Y1.6
Through Wafer Interconnects for 3-D Packaging.
Amy Moll 1 , Rex Oxford 1 , William Knowlton 1 Show Abstract
1 Materials Science and Engineering, Boise State University, Boise, Idaho, United States
Y2: Modeling and Design for 3-D Integration
Monday PM, November 27, 2006
Room 305 (Hynes)
2:30 PM - **Y2.1
Exploration of the Scaling Limits of 3D Integration.
Scott Pozder 1 , Robert Jones 1 , Vance Adams 1 , Hui-feng Li 2 , Michael Canonico 1 , Stefan Zollner 1 , Sang Hwui Lee 2 , Ronald Gutmann 2 , Jian Lu 2 Show Abstract
1 Technology Solutions Organization, Freescale Semiconductor Inc., Austin, Texas, United States, 2 Interconnect Focus Center, Rensselaer Polytechnic Institute, Troy, New York, United States
3:00 PM - **Y2.2
Modeling and Simulation of Parasitic Effects in Stacked Silicon.
Gunter Elst 1 , Peter Schneider 1 , Peter Ramm 1 Show Abstract
1 EAS, FhG-IIS, Dresden, Saxony, Germany
4:30 PM - **Y2.3
Contactless and Via'd High-Throughput 3D Systems.
Paul Franzon 1 , Rhett Davis 1 , Michael Steer 1 , John Wilson 1 , Jian Xu 1 , Hua Hao 1 , Steve Lipa 1 , Korey Schoenfliess 1 Show Abstract
1 ECE, NC State University, Raleigh, North Carolina, United States
5:00 PM - **Y2.4
Thermo-Mechanical Reliability of 3D-integrated Microstructures in Stacked Silicon
Bernhard Wunderle 1 , Eberhard Kaulfersch 3 , Peter Ramm 2 , Bernd Michel 1 , Herbert Reichl 4 Show Abstract
1 MMCB, Fraunhofer IZM, Berlin Germany, 3 , AMIC, Berlin Germany, 2 VSI, Fraunhofer IZM, Munich Germany, 4 , Technical University Berlin, Berlin Germany
Stacked silicon dies allow an unparalleled integration density using low-cost back-end processes for maximum device functionality. Therby, inter-chip vias assure short electrical interconnections for high frequency response and ultrafast devices. The technology therefore employed uses inter-chip vias and solid-liquid inter diffusion processes for vertical interconnect formation between thinned silicon dies (ICV-SLID). Thereby, thin metallic and intermetallic layers are created with dimensions in the micron to submicron range. On integrating microelectronic systems with these new technologies, material combinations and dimensions it is of great importance to assure the function of these systems and its individual constituents. So it is necessary to analyse and evaluate systematically their reliability under given boundary conditions in order generate lifetime-models and design guidelines for lifetime prediction. These models need to reflect the physics which lies behind the failure mechanisms and which has to be reproduced consistently by experiment and simulation.This paper investigates the reliability of such systems under external thermal loads relevant for the envisaged field of application (mobile, automotive) by simulation and experiment. First the materials are characterised. This is a challenge, as materials behave differently in their mechanical properties in smaller dimensions of a just a few microns. So advanced methods like nano-indentation to determine elasto-plastic material behaviour are applied. Finite Element simulations are used to reproduce these measurements to obtain local material properties like E-modulus and yield stress. Finally, developing plastic strain is used as failure indicator under periodic thermal loading of the package. This is demonstrated for a pressure sensor and integrated ICV-structures. From the experimental side localised process-induced (residual) stresses are detected by using a focused-ion beam set-up in conjunction with a grey-scale correlation algorithm. In-situ REM pattern tracing allows nano-metre accuracy in deformation measurements, from which stresses can be derived which also decisively influence reliability. Again, corresponding FE-simulations take this into account.
Chris Bower RTI International
Phil Garrou RTI International
Kenji Takahashi Toshiba Corporation
Peter Ramm Fraunhofer Institute IZM
Y3: Applications of 3-D Integration
Tuesday AM, November 28, 2006
Room 305 (Hynes)
9:30 AM - **Y3.1
3D Integration of Silicon Chips for Automotive Applications- Getting Started -
Werner Weber 1 Show Abstract
1 AIM TI MUC FP, Infineon Technologies, Munich Germany
3D integration of Silicon chips is a hot research topic since about 15 years. In this long time span two extreme application domains evolved. One is the performance-optimized integration of chips usually manufactured in the same state of the art logic process. This concept heads for performance improvements on the chip system level. The number of interconnects is large and consequently testing of single dies impossible; it is only performed after stacking. The disadvantage is that the whole stack will have to be discarded if only one die is bad. This fact reduces the overall yield. However, there exist major chances to largely improve electronic performance by replacing long horizontal by short vertical contacts forming a true 3D electronic structure.The other extreme is cost and formfactor-optimized integration of chips from different or equal processes into one stack. Communication between them usually also means communication between different logic blocks. As a consequence the number of interchip connections is small and testability of the single die is feasible. Only good single dies are selected for stacking and overall yield is much better. Thus, this approach will be less technologically challenging and likely initiate the first big wave of exploitation on the markets. Indeed, the first available 3D stacked products are cost- and formfactor-optimized systems in the communication and memory sector. Presently, however, the product volumes are rather small. In the following, the discussion will be restricted to the latter case only. A list of different stacking concepts is presented which is wide-scoped and thus takes the great variety of automotive applications into consideration:● The mainstream development today is the formation of interchip vias built from the top to the bottom of the wafer or vice versa. Different concepts are investigated varying the temporal sequence of via formation, thinning process and bonding of chips/wafers. ● A process with limited innovation risk is stacking of chips and wire-bonding to a substrate or larger-size chip. ● The package-on-package approach leads to medium formfactor systems.● A Molded Interconnect Device (MID) can be formed to hold several chips on top of one another. Various examples for stacked application systems will be discussed with different performances in parameters such as speed and cost. Examples are ● the separation of 'System on Chip'-based controller with embedded memory into a controller and a memory chip forming a 'System on Package'● the stacking of a controller and its emulator● special advantages of stacking in small volume applications Finally, a vertically integrated autonomous wireless sensor node will be discussed in detail. It operates autonomously over many years. The number of interconnects is small and power consumption low. These facts have important consequences for the optimal system integration architecture to be discussed in the paper.
10:00 AM - **Y3.2
Design and Fabrication of 3D Microprocessors.
Patrick Morrow 1 , Bryan Black 1 , Mauro Kobrinsky 1 , Sriram Muthukumar 1 , Don Nelson 1 , Chang-Min Park 1 , Clair Webb 1 Show Abstract
1 , Intel Corporation, Hillsboro, Oregon, United States
10:30 AM - **Y3.3
Three Dimensional lsi Integration Technology by ``chip on chip", ``chip on wafer" and ``wafer on wafer" with ``system in a package".
Manabu Bonkohara 1 2 , Makoto Motoyoshi 1 Show Abstract
1 President, ZyCube Co., Tkoyo Japan, 2 Collaborative research Center for Advanced Science and Technologies, Osaka Univ., Suita Japan
11:30 AM - **Y3.4
3-D Integration Technology for High Performance Detector Arrays
Dorota Temple 1 Show Abstract
1 Center of Materials and Electronics Technologies, RTI International, Research Triangle Park, North Carolina, United States
3-D integration revolutionizes the architecture of high performance detector arrays by enabling massively parallel signal processing at the pixel level. In the 3-D approach, the detector array layer is integrated with multiple layers of Si ICs which provide readout and signal processing functions. This greatly relaxes the IC real estate limit per pixel, resulting in unprecedented performance characteristics of the detector device. In this talk, 3-D integration technologies under development at RTI will be described with the focus on bonding techniques and the fabrication of high aspect ratio 3-D interconnects. Vias-last and vias-first approaches will be compared. The discussion will then include a specific application of the 3-D integration technology to high resolution infrared focal plane array detectors.
12:00 PM - **Y3.5
Three-Dimensional Integrated Circuit Fabrication Technology for Advanced Focal Planes.
Craig Keast 1 , Brian Aull 1 , James Burns 1 , Chenson Chen 1 , Jeff Knecht 1 , Brian Tyrrell 1 , Keith Warner 1 , Bruce Wheeler 1 , Vyshi Suntharalingam 1 , Peter Wyatt 1 , Donna Yost 1 Show Abstract
1 , MIT Lincoln Laboratory, Lexington, Massachusetts, United States
12:30 PM - **Y3.6
Development of 3D-Packaging Process Technology for Stacked Memory Chips
Toshiro Mitsuhashi 1 , Yoshimi Egawa 1 , Osamu Kato 1 , Yoshihiro Saeki 1 , Hidekazu Kikuchi 1 , Shiro Uchiyama 2 , Kayoko Shibata 2 , Junji Yamada 2 , Masakazu Ishino 2 , Hiroaki Ikeda 2 , Nobuaki Takahashi 3 , Yoichiro Kurita 3 , Masahiro Komuro 3 , Satoshi Matsui 3 , Masaya Kawano 3 Show Abstract
1 , Oki Electric Industry, Tokyo Japan, 2 , Elpida Memory, Kanagawa Japan, 3 , NEC Electronics, Kanagawa Japan
1. Introduction Elpida Memory, NEC Electronics and Oki Electric Industry collaborate to develop stacked memory chips technology supported by NEDO (The New Energy and Industrial Technology Development Organization). It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package. Interconnect between stacked chips will be done by Through-Silicon-Via (TSV) for the requirement of 3Gbps operation. The prototype of 4Gb stacked DRAM will be completed within FY2006.2. Process technologies for the stacked memory chips with TSV electrodes The core process technologies for the stacked memory chips are as the following.2-1. TSV electrodes fabrication Poly-Si was chosen as TSV filling material because of preventing contamination and the TSVs are fabricating before DRAM core formation by using dry etching. As default value for TSV, diameter is around 20um, via pitch is 50um and the depth (= chip thickness) is 50um.2-2. Wafer thinning A wafer is grounded to the thickness of 50um by using a grinder and CMP. At this time, supporting substrate is mounted on the front side of a wafer.2-3. Microbump structures After TSVs fabricated, micro-bumps are fabricated both side of thinned chip. In order to prevent crush the metal layers under the bumps, it is necessary to make bonding force lower. For this reason, SnAg/Cu was chosen as bump materials. As default value for bump, diameter is 30um, bump pitch is 50um and the height is a maximum of 20um.2-4. Chip stacking Flip-chip bonding system was used for bump interconnection. Flip-chip bonding system requires highly precise control (alignment between chips, heating temperature and height during chips). There are Chip to Chip (C2C) and Chip to Wafer (C2W) as the Flip-chip bonding method, we try C2W method, and in that case, heating temperature control is especially important. After bonding, the Cu-Sn inter metallic compounds (Cu3Sn and Cu6Sn5) were observed. These inter metallic compounds enhance bump bonding strength, however, micro-cracks are observed by the interface of Cu and SnAg. The cause is because the oxide film on the surface of Cu has barred the reaction of Cu and Sn. The improvement of the bump surface state is necessary to prevent the micro-cracks.2-5. Underfill resin injection After stacked memory chips, underfill resin is injected between chips. The distance between chips is very short about 20um, so it is difficult to fill the underfill resin without void. We can clear the issue by using a resin of low viscosity type.3. Conclusion TEG chips for the process evaluations were successfully stacked to the maximum 8-layers based on the above process technologies, and the electric characteristics of TSV such as daisy chain resistance are being evaluated.
Y4: Wafer Bonding Technology
Tuesday PM, November 28, 2006
Room 305 (Hynes)
2:30 PM - **Y4.1
Silicon Layer Stacking Enabled by Wafer Bonding
Chuan Seng Tan 1 Show Abstract
1 Electrical Engineering, MIT, Cambridge, Massachusetts, United States
Three-dimensional integrated circuits (3-D ICs), in the form of a vertical stack of several interconnected device layers, have many performance, form factor, and integration advantages. The main objective of this work is to develop reliable process technology to enable the fabrication of a vertically interconnected silicon multi-layer stack. Low temperature wafer bonding processes, both copper thermo-compression bonding and silicon dioxide fusion bonding, are studied extensively as key enabling technology. Cu thermo-compression bonding is studied for its feasibility as a permanent bond between active layers in a multi-layer stack. It is found that pre-bonding anneal in forming gas can remove surface oxide on Cu wafers and reduce the oxygen content in the bonded layer. The quality of bonded Cu layer is adversely degraded by the formation of interfacial voids. Void nucleation and growth are studied and counter-measures for void suppression are proposed and implemented. Silicon dioxide wafer bonding, on the other hand, is used as a temporary bond to attach a donor wafer to a handle wafer during donor wafer thinning and subsequent layer transfer. Sufficiently high bond strength is obtained with careful surface preparation and activation prior to bonding. Silicon layer can be stacked either in a “face down” or “face up” orientation. Using a combination of wafer bonding and thinning, double-layer stacks in both orientations are fabricated. By repeating these steps on two “face down” double-layer stacks, a four-layer stack is successful demonstrated.
3:00 PM - **Y4.2
Damascene Patterned Metal/Adhesive Redistribution Layers.
Ronald Gutmann 1 , J. Jay McMahon 1 , Jian-Qiang Lu 1 Show Abstract
1 Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York, United States
Wafer-level three-dimensional (3D) integration holds promise for both reducing interconnect delay by shortening wiring lengths and providing a heterogeneous integration path for a wide variety of micro- and nano-fabricated systems. The two principal platforms for wafer-level 3D integration are Cu-Cu bonding using a via-first process flow and polymer adhesive bonding using a via-last process flow. An alternative via-first 3D integration platform utilizing wafer-bonding of damascene-patterned metal/adhesive layers provides a redistribution layer between strata in a multi-wafer 3D stack. The feasibility of this via-first platform is demonstrated on 200-mm silicon wafers with a one-step wafer bonding of damascene-patterned copper/benzocyclobutene (Cu/BCB) redistribution layer, which combines the wafer-level packaging advantages of the inter-wafer redistribution layer technology, the thermal-mechanical advantages of BCB wafer bonding, and the electrical and process integration advantages of direct copper-to-copper inter-wafer interconnect bonding. Key challenges and processing results with this new platform will be highlighted.
3:30 PM - Y4.3
Capillary Assisted Wafer-Level Alignment
Michael Tupek 1 , Kevin Turner 1 Show Abstract
1 Mechanical Engineering, University of Wisconsin-Madison, Madison, Wisconsin, United States
Wafer-level 3-D integration via bonding is an attractive route to manufacture high-density microelectronics as well multifunctional microsystems. The achievable alignment between wafers is a key factor that influences the design of bonded 3-D integrated systems. The alignment tolerance directly affects the density of interconnects that is feasible at the interface and hence, approaches that allow sub-micron alignment are essential. Traditional alignment approaches, based on translating two substrates to align surface markers, are well established and can provide micron level registration. While these methods have been used to achieve sub-micron alignment, it is not easy to obtain uniform alignment across an entire wafer. Achieving sub-micron alignment across large diameter substrates (100-300 mm) by aligning two surface markers is difficult because elastic deformations of the wafers during bonding result in in-plane distortions of the wafers that can be hundreds of nanometers or more.The alignment challenges introduced by elastic deformation during bonding can be overcome by controlling the alignment of the wafers at multiple points (~10-1000 points) across the wafer rather than at just two locations, as is done in traditional approaches. The current work reports the development of an alignment scheme that manages interactions between the wafers at multiple points using patterned hydrophobic and hydrophilic regions on the wafers and water droplets as an initial bridge. Mechanics models have been used to demonstrate the effect of elastic deformation on traditional alignment schemes and to quantify the benefits of using multiple alignment pads. A process specific model for the capillary assisted alignment has been developed and includes two stages: a local and global model. The local model considers the droplet geometry and fluidic properties to predict the normal and the restoring force provided by each droplet. The global wafer-level model uses the results from the local model and predicts overall wafer alignment. Parametric studies have been completed and give the tradeoff between drop size, pattern layout, number of drops, and achievable alignment accuracy. Experiments, in which 100-mm wafers with patterned surfaces were aligned via capillary forces, have been completed to verify the model results.This work not only reports the development of capillary-force assisted alignment, but also provides insight into challenges in traditional alignment approaches. Modeling and experimental results as well as practical considerations in capillary assisted alignment will be discussed.
3:45 PM - Y4.4
Room-Temperature Cu-Cu Bonding: Implications for 3D ICs.
Rajappa Tadepalli 1 , Carl Thompson 1 Show Abstract
1 Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States
Creation of Cu-Cu thermo-compression bonds provides a route to 3D integrated circuits, with bonded Cu interconnects providing inter-level adhesion as well as a high density of inter-level electrical interconnection. A critical technology issue is fabrication of bonds with reproducible and uniform strengths over large areas, and high mechanical strengths for both yield and reliability. Cu-Cu bonding is typically carried out at elevated temperatures (about 400C). However, as feature sizes decrease, wafer-to-wafer alignment control during heating and cooling will become more critical and difficult. Moreover, thermal stability of low-k dielectrics is a problem at high bonding temperatures. Therefore, reduction of the bonding temperature required for high strength Cu-Cu bonds is essential. In earlier studies, we studied the strength of Cu-Cu bonded interfaces created in a conventional wafer bonding tool with a base pressure of about 0.001 Torr. We showed that surface preparation to remove copper oxide along with bonding after exposure to a reducing ambient (5% H2, 95% Ar) allowed the creation of high-strength bonds at temperatures as low as 300C. However, further improvements could not be realized in the commercial bonder. Here we report on new experiments designed to explore the ultimate limit of low temperature bonding. We have carried out Cu-Cu adhesion under ultra-high vacuum (UHV) conditions. 20nm-thick Cu films (with diffusion barriers) were deposited on Si substrates and Si AFM cantilever tips using e-beam evaporation. Through force-distance measurements made using the AFM cantilevers, the work of adhesion between the freshly Cu-coated AFM tip and the freshly deposited Cu film was measured at different temperatures, including room temperature. These measurements show that the room temperature Cu-Cu adhesion value is ~ 2J/m2. Deliberate pre-adhesion exposure of the Cu surfaces to 10-6 Torr O2 lead to a dramatic reduction in adhesion (to 0.1J/m2), suggesting the formation of a Cu oxide that is detrimental to the Cu-Cu bonding process, even at this low pressure. In order to compare AFM adhesion values to wafer-level Cu-Cu bonds, we have developed a novel Chevron fracture toughness test methodology to study the latter. Both test methodologies measure tensile bond strength, in contrast to the mixed-mode (tensile + shear) strength measured in a four-point bend test. The strength of wafer-level Cu-Cu bonds created at 300C is ~ 2.5J/m2. In comparison to the UHV-AFM measurements, it is evident that strong Cu-Cu bonds can be created by bonding clean Cu surfaces at room temperature, thereby eliminating several thermal stability issues in the thermocompression bonding process. This work suggests the need for HV or UHV bonding tools, with in situ surface cleaning capabilities for fabrication of 3D ICs based on use of Cu-Cu bonding.
4:30 PM - **Y4.5
Vertical Integration: A Confederacy of Alignment, Bonding, and Materials Technologies.
Shari Farrens 1 Show Abstract
1 , Suss Microtec, Waterbury Center, Vermont, United States
Vertical or 3D integration is taking hold in both the CMOS IC industry and the MEMS industry. The need for smaller devices, lower power, increased functionality, and lower cost are driving the market toward chip and wafer level stacking. Equipment suppliers have been faced with numerous challenges to meet the demands of these emerging bonding applications. This paper will discuss the confederacy of alignment, bonding and materials unions that can lead to successful outcomes in integrated manufacturing.ALIGNMENT STRATEGIES:Alignment strategies build on the fundamentals from mask alignment lithography systems. Therefore it is well known that the quality of the alignment marks, separation distance (proximity versus contact), and mechanical positioning systems all contribute to final alignment accuracy. In wafer bonding, the challenge is compounded by the lack of substrate transparency for most 3D integration applications. The options include alignment to live images with transparent substrates using top side alignment techniques or transmission IR imaging in opaque substrates. Back side alignment methods and face to face alignment methods are used when the substrates do not transmit in the visible or IR frequency range.3D BONDING CHOICES:There are three bonding methods that are evolving into production processes. These include metal to metal, silicon direct or fusion, and polymer bonding. Without a doubt the best bonds must aspire to these criteria:a)limit thermal processing time and temperature since thermal expansion of the substrates relative to one another is among the major contributors to post bond alignment accuracy,b)limit the possibility for sliding of the wafers relative to one another during the annealing process when force is applied to maintain intimate contact of all points on the surface,and c)allow for tacking of the wafers during alignment when the chance is available.The trade offs between both alignment and bonding methods conspire to achieve the best possible post thermal bond alignment. Additional errors may come from the mechanical and optical components of these systems and understanding the interrelationships are critical to moving 3D integration strategies into production.
5:00 PM - Y4.6
Characterization and Requirements for Cu-Cu bonds for 3D Integrated Circuits.
Rajappa Tadepalli 1 , Carl Thompson 1 , Kevin Turner 2 Show Abstract
1 Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States, 2 Mechanical Engineering, University of Wisconsin-Madison, Madison, Wisconsin, United States
Cu-Cu thermo-compression bonding can be used to create interlayer bonded interconnects, to create interlayer adhesion layers, and to seal integrated microchannels for thermal management. In all of these roles, bonds must have high strengths with low strength variations. High strengths are required for post-bonding processing (e.g. diesaw cutting and chemical mechanical polishing) as well as for reliable operation. Strengths of thin-film metal-metal thermo-compression bonds are most often characterized using ‘razor-blade’ tests or through measurements of crack propagation in samples stressed through 4-point bending. Razor-blade tests are often inaccurate, suffer from poor reproducibility, and have limited precision. Four point tests are more quantitative and reproducible, but characterize the bond toughness under mixed mode loading (shear and tension). Bond toughness under shear loading is strongly affected by plasticity in the metal layers, and is therefore affected by many factors in addition to the actual adhesive strength of the bonded interface. Moreover, while the ability to survive chemical mechanical polishing might depend on the bond toughness under shear loading, sealing and adhesion for diesaw cutting survivability and impact testing is expected to depend strongly on the bond toughness under tensile loading.We have developed a technique that allows quantitative measurement of the strength of thin film metal-to-metal thermo-compression bonds loaded in pure tension as well as in mixed mode. This technique, the ‘Chevron test,’ involves loading of the sample in a double-cantilever mode, and patterning of one of the films into chevron structures. We have used this technique to measure Mode I (Tensile) toughness of wafer/die-level Cu bonds made with continuous and patterned films. Nominal toughness values for film-film Cu bonds created at 3000C as measured by Chevron and Four-point bend tests are 2.5 J/m2 and 17J/m2, respectively. The difference can be attributed to plastic deformation of the Cu stack during mixed-mode loading. Effects of critical process parameters such as bonding ambient (including UHV), wafer bow, and pattern size/density on the bond toughness have been evaluated using the Chevron test. In addition, by varying the relative thicknesses of the two bonded layers, the Chevron test has been extended to study mixed-mode loading, thereby providing a single convenient test technique to evaluate bond strengths over a range of loading conditions.
5:15 PM - Y4.7
Low Temperature Copper-Nanorod Bonding for 3D Integration
Pei-I Wang 1 , Tansel Karabacak 1 , Jian Yu 1 , Hui-Feng Li 1 , Gopal Pethuraja 1 , Jian-Qiang Lu 1 , Toh-Ming Lu 1 Show Abstract
1 Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York, United States
Wafer bonding is an emerging technology for fabrication of complex three-dimensional (3D) structures; particularly it enables monolithic wafer-level 3D integration of high performance, multi-function microelectronic systems. For such a 3D integrated circuits, low-temperature wafer bonding is required to be compatible with the back-end-of-the-line processing conditions. Recently our investigation on surface melting characteristics of copper nanorod arrays, which are grown by an oblique angle deposition technique, showed that the threshold of the morphological changes of the nanorod arrays occurs at a temperature significantly below the copper bulk melting point . With this unique property of the copper nanorod arrary, wafer bonding using copper nanorod arrays as a bonding intermediate layer was investigated at low temperatures (400 degree C and lower). Wafers, each with a copper nanorod array layer, were bonded at 200 – 400 degree C and with a bonding down-force of 10000N in a vacuum chamber of a wafer bonder. Bonding results were evaluated by razor blade test, mechanical grinding and polishing, and cross-section imaging using a focus ion beam/scanning electron microscope (FIB/SEM). The FIB/SEM images show that the copper nanorod arrays fused together accompanying by a grain growth at a bonding temperature of as low as 200 degree C. A dense copper bonding layer was achieved at 400 degree C where copper grains grew throughout the copper structure and the original bonding interface was eliminated. The sintering of such nanostructures depends not only on their feature size, but also significantly influenced by the bonding pressure. These two factors both contribute to the mass transport in the nanostructure, leading to the formation of a dense bonding layer. Detailed processing variables and bonding results will be presented and discussed. Tansel Karabacak, James S. DeLuca, Pei-I Wang, Dexian Ye, Gregory A. Ten Eyck, Gwo-Ching Wang, and Toh-Ming Lu, Journal of Applied Physics, 99, 064304 (2006).
5:30 PM - Y4.8
3D Process Integration – Wafer-to-Wafer and Chip-to-Wafer Bonding.
Thorsten Matthias 2 , Markus Wimplinger 2 , Stefan Pargfrieder 1 , Paul Lindner 1 Show Abstract
2 , EV Group Inc., Tempe, Arizona, United States, 1 , EV Group, St. Florian/Inn Austria
5:45 PM - Y4.9
High-Performance Temporary Adhesives for Wafer Bonding Applications
Rama Puligadda 1 , Sunil Pillalamarri 1 , Chad Brubaker 2 , Markus Wimplinger 2 , Stefan Pargfrieder 3 Show Abstract
1 R&D, Brewer Science,Inc., Rolla, Missouri, United States, 2 , EV Group, Tempe, Arizona, United States, 3 , EV Group, Scharding, St. Florian , Austria
Myriad structures for stacking chips, power devices, smart cards, and thin substrates for processors have one thing in common: thin silicon. Wafer thinning will soon be an essential process step for most of the devices fabricated and packaged henceforth. The key driving forces for thinned wafers are improved heat dissipation, three-dimensional stacking, reduced electrical resistance, and substrate flexibility. Handling of thin and ultrathin substrates however is not trivial because of their fragility and tendency to warp and fold. The thinned substrates need to be supported during the backside grinding process and through the subsequent processes such as lithography, deposition, etc. Using temporary adhesives to attach the processed device wafer to a rigid carrier wafer offers an efficient solution. The key requirements for such materials are ease of application, coating uniformity with minimal thickness variation across the wafer, good adhesion to a wide variety of surfaces, thermal stability in processes such as dielectric deposition and metallization, and ease of removal to allow high throughput. An additional requirement for these materials is stability in harsh chemical environments posed by processes such as etching and electroplating. Currently available materials meet only a subset of these requirements. None of them meet the requirement of high-temperature stability combined with ease of removal. We have developed adhesives that meet a wide range of post-thinning operating temperatures. Additionally, the materials are soluble in industry-accepted safe solvents and can be spin-applied to required thicknesses and uniformity. Above all, the coatings can be removed easily without leaving any residue. This paper reports on the development of a wide range of temporary adhesives that can be used in wafer thinning applications while applying both novel and conventional bonding and debonding methods.
Chris Bower RTI International
Phil Garrou RTI International
Kenji Takahashi Toshiba Corporation
Peter Ramm Fraunhofer Institute IZM
Y5: 3-D Packaging
Wednesday AM, November 29, 2006
Room 305 (Hynes)
9:30 AM - **Y5.1
Silicon Through-hole Interconnection for 3D-SiP Using Room Temperature Bonding
Naotaka Tanaka 1 , Yasuhiro Yoshimura 1 , Takahiro Naito 2 , Takashi Akazawa 2 Show Abstract
1 , Hitachi, Ltd. Mechanical Engineering Research Laboratory, Hitachinaka, Ibaraki, Japan, 2 , Renesas Technology Corp., Kodaira-shi, Tokyo, Japan
The wire bonding technique has been used for conventional 3D-stacked packages. Since this technique provides a high degree of freedom for connecting a chip to a substrate, it is well suited for connecting multiple LSI chips to a substrate. However, it requires an additional bonding area on the substrate and long wires for connecting a chip to a substrate. Therefore, among the several options for 3D stacking, chip-stacking using through-hole electrodes is an attractive technology for fabricating ultra-slim, high-performance SiPs in the near future because of the extremely short wiring length between chip electrodes. In this study, we proposed a new concept for interconnecting between stacked chips formed through-hole electrodes. Multiple through-hole electrodes are formed on the backside of the lower chips. Gold stud bumps on the upper chips are filled in the through-hole electrodes on the lower chips by applying a compressive force, which causes plastic flow in the gold bump. Therefore, a contact force is generated at the interface between the bumps and the electrodes on the sidewall. That is, the use of “mechanical caulking” technique makes possible electrical connection between stacked chips at room temperature by compressive force alone. The conventional through-hole electrode interconnection using solder or similar metallic bumps are required high-temperature bonding (more than at least 200 degree Celsius). This new method is not only green technology but also simplifies manufacture by enabling bonding at room temperature. To verify the operation of 3D-SiP with through-hole electrode interconnection, we manufactured an ultra-thin stacked SiP composed of existing MCU chip, interposer chip and SDRAM chip by using mechanical caulking technique at room temperature. By using this technology, the package thickness was reduced to less than 0.5mm from 1.25 mm (3D-SiP using wire bonding). However, two problems exist for forming through-hole electrodes in the existing MCU. One is that the multi-insulation layers (SiO2 layers) are very thick (about 7 micron) compared to the interposer wafer with a thermally oxidized film of 0.2 micron. This causes a longer TAT and greater temperature increase for etching the SiO2 layer. The other is that aluminum electrodes on the top-side are very thin (about 0.6 micron) compared to the interposer wafer with Au electrodes of 5 micron. This complicates the etching process of SiO2 because aluminum electrodes can be easily etched during the SiO2 etching process at the same time. The difference of etching rate of SiO2 between electrodes sometimes causes the two types of through-hole electrodes. One is that the through-hole electrode penetrates the aluminum electrodes, and the other types remain the SiO2 layers at the bottom of contact area. Therefore, to establish a stable mass-production process, a new customized LSI design for through-hole electrodes interconnection needs to be developed.
10:00 AM - **Y5.2
Current Status of LSI Micro-fabrication and Future Prospect for 3D System Integration.
Kazuya Okamoto 1 Show Abstract
1 Center for Advanced Science and Innovation, Osaka University, Osaka Japan
10:30 AM - **Y5.3
Active Interposer : Combination of Through-Si Vias and Redistribution.
Kazumi Hara 1 Show Abstract
1 Advanced technology development center, Seiko Epson corporation, Fujimi-machi,Suwagun,, Nagano-ken, Japan
As is known widely in the electrical packaging area, through-Si vias technology enables usage of the backside of chips as mounting areas, as well as shortening the wiring length. They provide extremely smaller packages and better transmission efficiency. Until recently, this was merely an issue confined to the field of research and development. However, due to significant advances reported in the last year, it may be not an exaggeration to say that the application of this technology to mass production will occur in several companies one of these days.Typical products to which through-Si vias technology could be applied are memory stacks and CCD modules. Their function can be greatly enhanced per size by applying through-Si vias technology compared to packages assembled by existing technologies.However, we can expect further expansion in their application. This is due to the fact that an IC chip now has through vias, and that an IC can serve as an interposer and be connected to various types of devices in a package. Technically, that can be attained by combining through-Si vias with redistribution wirings.From our viewpoint, we have been developing wafer-level-CSP-type interposer modules which are actual ICs with through Si vias and redistribution wirings. A redistribution layer including a stress buffer layer is formed on a wafer where integrated circuits are fabricated, and then through-Si holes are opened from the backside of the wafer and are filled with Cu to create terminals on the backside of the wafer so that they are connected to Al pads on the active side respectively. Another device can be mounted on the backside of the IC to form a package. The structure provides adequate bonding reliability due to the stress buffer layer of the redistribution layer when it is mounted on an organic board, as well as an extremely small outer shape.In this paper, the process study of the module, the influence of the process on the function of IC after process, and reliability of connection are discussed.
11:30 AM - **Y5.4
Multi-Stacked Flip Chips with Copper Plated Through Silicon Vias and Re-distribution for 3D System-in-Package Integration.
Ricky Lee 1 2 , Ronald Hon 1 Show Abstract
1 Center for Advanced Microsystems Packaging, Hong Kong University of Science and Technology, Kowloon Hong Kong, 2 Advanced Materials, Nano and Advanced Materials Institute (NAMI), Kowloon Hong Kong
In the past decade, compact components such as chip scale packages and flip chips are commonly used in many microelectronics products for miniaturization. However, emerging applications require an even higher density of packaging. In order to fulfill this requirement, three dimensional packaging has to be implemented. 3D integrated systems can reduce chip areas and optimize component partitioning. In addition, three dimensional packaging (3DP) structure may lead to minimal conductor length and eliminate speed-limiting inter-chip interconnects. In the microelectronics industry, there are various know-hows for implementing 3DP structures. One of the major technologies is microvias for vertical interconnection. In the past, microvias were mainly made on printed circuit boards or substrates. More recently, the emerging trend is to fabricate through silicon vias (TSVs) on wafers for stacked die applications. In the past few years, some efforts have been made in this area. In general, the forming of TSVs is not a major issue as long as the deep reactive ion etching (DRIE) facility is available. People are able to make TSVs with a diameter less than 5 microns. However, the aspect ratio of microvias is still a concern. Usually substantial wafer thinning is required in order to make through hole microvias. Also, the plugging of microvias is a rather difficult task. People usually use sputtering and plating of copper to fill the TSVs. However, due to the small size of microvias, it is quite difficult to get good quality filling of TSVs. The process development for 3DP remains a challenging area. In this paper, a new configuration is introduced for the 3D packaging of stacked flip chips. The proposed through holes on wafer are rectangular through silicon slots instead of the conventional round hole vias. The through silicon slots are formed by DRIE. These through silicon slots are distributed along the periphery of chips and go across the saw street between adjacent chips. The through silicon slots are plugged by copper plating. Furthermore, a wafer level re-distribution process is performed to connect the chip I/Os to the through silicon slots and to route I/Os from the through silicon slots to new locations for solder bumping and chip interconnection, which are required for the subsequent 3D die stacking assembly. After the re-distribution and solder bumping processes, the wafer is diced and each chip has half of the original through silicon slots (with plugging and redistribution) as through hole interconnects along its periphery. Afterwards, these chips can be stacked up to form modules with a 3DP structure. In addition to the design, prototypes have been fabricated during the present study. The package structure and the fabrication processes will be illustrated in details in this paper. Cross-sectioning and SEM micrographs will be presented as well to demonstrate the features of the proposed 3D stacked flip chip packaging.
12:00 PM - **Y5.5
CMOS Proximity Wireless Communications for 3-D Integration
Tadahiro Kuroda 1 Show Abstract
1 EE, Keio University, Yokohama Japan
Performance gap between computation in a chip and communication between chips is widening. System-in-a-Package (SiP) reduces chip distance significantly, enabling high-speed and low-power interfaces. Electrical interfaces using inductive/capacitive coupling have advantages over mechanical interfaces that employ Through Silicon Vias (TSVs) and micro bumps for 3D stacking of chips. In this presentation, CMOS proximity wireless communications via inductive coupling for 3-D integration is discussed. A 1Tb/s 3pJ/b transceiver in 0.18μm CMOS is developed. It exhibits the highest data rate and the lowest energy consumption with the smallest Si area in the world. Experimental results demonstrate that for ranges of 100μm (i.e. only 0.1% of the wave length), proximity wireless communication bears comparison with wired communication in terms of data rate, reliability, power, size, and connectivity. In our chip, 1024 data transceivers are arranged with a pitch of 30μm. Measured BER is lower than 10e-13. Data is received by a clock that is also transmitted by inductive coupling. Chips under different supply voltages can be interfaced without level converters. As for power dissipation, wireless communications consumes even less power than the wired counterparts. Using inductive coupling based implementation, considerable cost reduction compared to the TSVs and micro bumps is possible without sacrificing performance, since this circuit solution is implemented in a conventional technology. Furthermore, if the same transceivers are implemented in a test head of an LSI tester, at-speed test can be performed by placing the test head close to a wafer. Know-Good-Die problem can be solved and yield is improved significantly. Yield degradation due to damage on PAD caused by a probe needle can be avoided by the non-contact interface. If the active test head are arranged in array, wafer test in a lump may be able to be performed, yielding reduction in test time and cost substantially. Techniques for high-speed and low-power data communications will be discussed at various levels of hierarchy including signaling (e.g. bi-phase modulation and time interleaving), circuit design, IC layout, and magnetic field design. Cross talk analysis through measured results and its countermeasures to mitigate cross talk will be discussed. Furthermore, a constant magnetic field scaling will be proposed to further improve cost performance ratio.
12:30 PM - Y5.6
Fabrication and Evaluation of 3-D SiP with Through Hole Via.
Dong Min Jang 1 , Byeong Hoon Cho 1 , Kwang Yong Lee 2 , Chung Hyun Ryu 1 , Gun Ho Chang 2 , Min Seung Yoon 4 , Yang Ho Kim 3 , Won Jong Lee 1 , Tae Sung Oh 2 , Jae Ho Lee 2 , Young Ho Kim 3 , Joung Ho Kim 1 , Young Chang Joo 4 , Jin Yu 1 Show Abstract
1 Center for Electronic Packaging Materials, KAIST, Daejeon Korea (the Republic of), 2 Center for Electronic Packaging Materials, Hongik University, Seoul Korea (the Republic of), 4 Center for Electronic Packaging Materials, Seoul National University, Seoul Korea (the Republic of), 3 Center for Electronic Packaging Materials, Hanyang University, Seoul Korea (the Republic of)
System in package (SiP) is a superb candidate to enhance the area efficiency and performance of electronic packaging. Here, recent work on stacked chip type 3-D SiP with vertically interconnected through hole vias are reported. The process includes; formation of 50µm-diameter via holes, conformal deposition of SiO2 dielectric layer, deposition of Ta and Cu barrier layers, via filling by Cu electroplating, Cu/Sn bump formation for multi-chip stacking, and finally chip-to-PCB bonding using Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3-D SiP stacked up to 10 layers was successfully fabricated. High frequency electrical model of the through hole via was proposed and the model parameters were extracted from the measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. Especially the effect of through silicon via was analyzed in terms of waveforms of signals. The improved power distribution network (PDN) of through hole via was demonstrated comparing with that of conventional wire bonding. Mechanical reliability of the fabricated SiP samples was also evaluated by drop, thermal cycling tests.
12:45 PM - Y5.7
Filling of Very Fine via Holes for 3-D SiP by Using Ionized Metal Plasma Sputtering and Electroplating.
Byung-Hoon Cho 1 , Jae-Jin Yoon 1 , Jae-Seung Moon 1 , Won-Jong Lee 1 Show Abstract
1 Center for Electronic Packaging Materials (CEPM), KAIST, Taejon Korea (the Republic of)
System in package (SiP) is a superb candidate to enhance the area efficiency and performance of electronic packaging. One of the key technologies for developing 3-D SIP with vertical interconnection is the interlayer metallization using formation and filling of through hole via. We deal with filling of via holes of diameters of 4~10 µm and depths of 50~70 µm with Cu electroplating. Prior to electroplating, the insides of the via holes are needed to be coated with Ta layer as a barrier against the Cu diffusion and with Cu layer as a seed layer for the subsequent Cu electroplating process. In this study, Ta and Cu thin layers are deposited by using ionized metal plasma (IMP) sputtering. IMP sputtering utilizes an inductively coupled plasma to ionize sputtered metal atoms and the resulting metal ions are then accelerated towards the substrate by applying bias to the substrate. The flux and energy of these ions can be controlled independently. The deposition profiles of Cu seed layers have a significant effect on the via filling in the subsequent electroplating. The IMP sputtering enables more conformal deposition of Cu seed layer on the sidewall as well as the bottom of the via holes than conventional sputtering, and it is much easier to control, more cost-effective and more compatible with large-scale mass production systems than chemical vapor deposition. The deposition profiles of Cu seed layers inside the via holes are precisely examined by measuring the intensity ratios of Cu/Si x-rays emitted from the deposited Cu seed layers as functions of inductively coupled plasma power and substrate bias, and they are also related with the characteristics of inductively coupled plasma. The via holes coated with Cu seed layer are then filled with Cu using a periodic pulse reverse current electroplating. Copper-sulfate-based electroplating solution that contains chloride ions, bis(sodiumsulfopropyl)disulfide (SPS), polyethylene glycol (PEG) and Janus Green B (JGB) is used. We study the effects of the deposition profiles of Cu seed layers and the various electroplating parameters on the filling of electroplated Cu for the via holes with various diameters and aspect ratios. Complete filling of very fine via holes can be achieved without defects by using IMP sputtering and electroplating.
Y6: Enabling Materials and Processes for 3-D Integration
Wednesday PM, November 29, 2006
Room 305 (Hynes)
2:30 PM - **Y6.1
Materials Aspects to Consider in the Fabrication of Through-Silicon Vias.
Susan Burkett 1 , L. Schaper 2 , T. Rowbotham 2 , J. Patel 2 , T. Lam 2 , I. Abhulimen 2 , M. Gordon 3 , L. Cai 2 Show Abstract
1 , NSF, Arlington, Virginia, United States, 2 Electrical Engineering, University of Arkansas, Fayetteville, Arkansas, United States, 3 Mechanical Engineering, University of Arkansas, Fayetteville, Arkansas, United States
The formation of vertical interconnects to create three-dimensional (3D) interconnects enables integration of dissimilar electronic material technologies. These vertical interconnects are metal filled blind vias etched in silicon and are formed by a series of processing steps that include: silicon etch; insulation/barrier/seed layer deposition; electroplating of Cu to fill the via; wafer grinding and thinning; and back side processing to form contacts. Deep reactive ion etching (DRIE) is used to etch silicon vias with attention given to process parameters that affect sidewall angle, sidewall roughness, and lateral etch growth at the top of the via. After etching, vias are insulated by depositing 0.5 µm of silicon dioxide by plasma enhanced chemical vapor deposition (PECVD) at 325C. A barrier film of TaN is reactively sputtered after insulation deposition followed by a Cu sputtered seed film allowing electroplated Cu to fill the blind via. Reverse pulse plating is used to achieve bottom-up filling of the via. Once void-free electroplated vias are prepared, the process wafer is attached to a carrier wafer for silicon back grinding. Vias on the process wafer are “exposed” from the back side of the wafer with a combination of processes that include mechanical grinding, polishing, and reactive ion etching (RIE). Contact pads are then formed by conventional IC processes. Cu posts are used to connect the electronic devices and to address thermal management issues as well. Material aspects of the through-silicon via process and modeling of the Cu-filled vias and Cu posts to investigate thermal management schemes as well as mechanical reliability will be presented. Via diameters are in the range of 10-30 µm and aspect ratios of 3-5 are of interest in this study.
3:00 PM - **Y6.2
Through-Silicon-Via Copper Deposition for Vertical Chip Integration.
Bioh Kim 1 Show Abstract
1 ECD Division, Semitool, Inc., Kalispell, Montana, United States
Consumers are demanding smaller, lighter electronic devices with higher performance and more features. The continuous pressure to reduce size, weight, and cost, while increasing the functionality of portable products, has created innovative, cost-effective 3D packaging concepts. Among all kinds of 3D packaging techniques, through-silicon-via (TSV) electrodes can provide vertical connections that are the shortest and most plentiful with several benefits (1). Connection length can be as short as the thickness of a chip. High density, high aspect ratio connections are available. TSV interconnections also overcome the RC delays and reduce power consumption by bringing out-of-plane logic blocks much closer electrically. The technologies engaged with TSV chip connection include TSV formation, insulator/barrier/seed deposition, via filling, surface copper removal, wafer thinning, bonding/stacking, inspection, test, etc. Process robustness and speed of copper deposition are among the most important technologies to realize TSV chip integration. There are generally three types of via filling processes; lining along the sidewall of vias, full filling within vias, and full filling with stud formation above the via. Here, the stud works as a mini-bump for solder bonding. Two methodologies have been generally adopted for via filling process; (a) via-first approach : blind-via filling with 3-dimensional seed layer, followed by wafer thinning and (b) thinning-first approach : through-via filling with 2-dimensional seed layer at the wafer bottom after wafer thinning. Currently, the first approach is more popular than the second approach due to difficulty in handling and plating thinned wafers (2).We examined the impact of varying deposition conditions on the overall filling capability within high aspect ratio, deep, blind vias. We tested the impacts of seed layer conformality, surface wettablity, bath composition (organic and inorganic components), waveform (direct current, pulse current, and pulse reverse current), current density, flow conditions, etc. Most deposition conditions affected the filling capability and profile to some extent. We found that reducing current crowding at the via mouth and mass transfer limitation at the via bottom is critical in achieving a super-conformal filling profile. This condition can be only achieved with a proper combination of aforementioned process conditions. With optimized conditions, we can repeatedly achieve void-free, bottom-up filling with various via sizes (5-40um in width and 25-150um in depth). References1.R. Chanchani, 55th ECTC, Professional Development Course, No. 2, Slide page 7 (2005).2.B. Kim and T. Ritzdorf, SEMI Technology Symposium (STS) Proceedings, Semicon Korea, p. 269 (2006).
3:30 PM - Y6.3
Grinding and Mixed Silicon Copper CMP of Stacked Patterned Wafers for 3D Integration.
Koen De Munck 1 , Jan Vaes 1 , Lieve Bogaerts 1 , Piet De Moor 1 , Chris Van Hoof 1 , Bart Swinnen 1 Show Abstract
1 , IMEC vzw, Leuven Belgium
3D integration promises to reduce system form factor through direct stacking and interconnection of chips, made using different technologies, into a single system. In our case, these interconnects consist of small and deep through wafer vias in the form of Cu nails. One of the enabling technologies to achieve this, is thinning on carrier. It involves backside grinding of patterned wafers down to 20 to 50 microns, while temporarily glued to a carrier. Still on-carrier, the device wafers subsequently are polished in a CMP step. The thinning module as it has been developed at Imec, extends established solutions for grinding and bulk silicon CMP.Success of thinning on carrier strongly depends on temporary glue layer properties and bonding quality. Non-uniformities in glue thickness cause large TTV (total thickness variation) of the thinned wafer, even in case of uniform grinding (i.e. grinding induced TTV <1 micron). Voids in between device wafer and carrier can cause failure during further processing. Glue thickness thus needs to be uniform, without any edge exclusion. In our experiments, voids have been observed, originating either from thick edge beads, small defects, particles or wafer labels. We determined that open voids at the wafer stack edge due to the mere rounded shape of the wafer edge, cause thin wafer delamination and catastrophic breakage when thinning down below 50 micron. By improving sealing at the wafer edge, we enabled a uniform bonding compatible with standard grinding and CMP techniques. Patterned wafers require additional care. Their wafer edge topography can induce edge chipping during and after thinning and CMP.CMP is done to remove any damage induced by the grinding. An additional goal is to expose the Cu nails at the thin wafer backside. As such, nail length variations associated with the via etch non-uniformity and glue, carrier and grinding TTV’s are flattened out. After applying the first Si polish step, the TTV of a plain silicon wafer is maintained. On patterned thinned wafers, a second polish step was introduced to remove the Cu debris that was generated during the first polish step. Within wafer TTV before and after polishing is comparable. Within die non-uniformity after CMP is of the same order as within wafer TTV. Local topography of about 2 micron is found to correlate with the local Cu nail density variations within the die. The Cu nails themselves are found to be recessed into the silicon. Resulting topography is interpreted in terms of slurry selectivity and pad stiffness. High Cu nail density regions polish more slowly because of the non-oxidizing nature of the Si-slurry. The Cu is deformed but not abraded. In the second polish step the silicon is rounded near the Cu nails, and the Cu is recessed into the silicon. The compliance of the polish pad gives rise to the within die non-uniformity and the Cu dishing. Despite this micron-level topography, successful die-to-die bonding of the Cu nails was achieved.
3:45 PM - Y6.4
Superconformal Film Growth: Mechanism and Quantification.
Thomas Moffat 1 , Daniel Wheeler 1 , Soo-Kil Kim 1 , Daniel Josell 1 Show Abstract
1 , NIST, Gaithersburg, Maryland, United States
State of the art manufacturing of semiconductor devices involves electrodeposition of copper for device wiring. The current Damascene process depends on the use of electrolyte additives that affect the local deposition rate thereby resulting in superconformal, or bottom–up “superfilling” of trenches and vias. This remarkable growth process is examined in the context of the recently developed curvature enhanced adsorbate coverage (CEAC) mechanism. The model stipulates that 1.) the growth velocity is proportional to the local accelerator, or catalyst, surface coverage and 2.) the catalyst remains segregated at the metal/electrolyte interface during copper deposition. For growth on non-planar geometries this leads to enrichment of the catalyst on advancing concave surfaces and dilution on advancing convex sections; thereby giving rise to bottom-up superfilling of sub-micrometer trenches and vias. The mechanism is applicable to any growth process that is mediated by an interfacial chemical reaction such as electrodeposition, electroless deposition or chemical vapor deposition. The talk will focus on the quantitative application of the CEAC mechanism to connect kinetic measurements performed on planar surfaces with 3-D shape evolution during feature filling. This protocol has been applied to a variety of chemically distinct systems although the talk will focus on its utility for understanding and optimizing the copper Damascene process that is used in the fabrication of microelectronic devices.
4:30 PM - **Y6.5
Novel Wafer Dicing and Chip Thinning Technologies Realizing High Chip Strength
Shinya Takyu 1 , Tetsuya Kurosawa 1 , Noriko Shimizu 1 , Susumu Harada 1 Show Abstract
1 , Toshiba Corpration, Kawasaki, Japan
Accompanying the rapid progress of the digital network information society, there is strong demand for high functionality and miniaturization of mobile personal digital assistance. The realization of chip thickness under 50 um is demanded. However, the chip bending force is decayed dramatically as the decay of chip thickness.Wafers are thinned by means of mechanical in-feed grinding using a grindstone containing diamond particles, so there are spiral grinding saw marks on the backside of the wafer. Dicing wafers always causes surface chipping, dicing saw mark on chip side and backside chipping. These damages remained on chip faces become source of cracks, as a result chip strength decrease. Therefore, the manufacturing process of thin chip must achieve the requirement of no damage on all around chip faces.Chip strength is measured by 4 point bending measuring method. It is estimated the actual chip strength because the result of 4 point bending measuring method accounts the dicing effect. First, the influence of chip strength and grinding saw marks, surface chipping, dicing saw mark and backside chipping was studied. As it turned out backside chipping is the worst damage that decreased the chip strength followed by grinding saw mark, dicing saw mark, surface chipping is followed.Second, we established novel dicing and chip thinning technologies followimg steps. Step1:Backside chipping suppression by DBG. DBG process is as follows. 1) Half-cut blade dicing 2) Laminating the wafer surface protection tape 3) Grinding until the final thickness + 5 um 4) Removing the wafer surface protection tape. DBG process could make the maximum backside chipping size from 50 um to 5 um smaller. The average chip strength of conventional process is 253 MPa and the strength of DBG is 541 MPa. Step2:Removal of grinding saw marks by DBG + CMP. DBG + mirror finish process could make grinding saw mark free. There are many kinds of mirror finish process. We made DBG + Dry Polish chips, DBG + Plasma Etching chips and DBG + CMP (Chemical Mechanical Polishing) chips and measured the chip strength. The average chip strength of DBG + Dry Polish, DBG + Plasma Etching, DBG + CMP is 675 MPa, 752 MPa, 1082 MPa, respectively. CMP proves to be the best process of mirror finish after DBG. DBG + CMP is not only able to make backside saw mark free but also make backside edge round shape (round chamfer become larger). step 3:Removal of dicing saw marks by RIE − DBG + CMP. We studied several types of removal method of dicing saw marks for instance, larger blade mesh size, laser dicing, RIE, then we selected RIE process instead of half − cut dicing. RIE half-cut dicing can make chip side saw mark free and surface chipping free. The average chip strength of RIE - DBG + CMP is 1312 MPa. The novel wafer dicing and thinning technologies that can make chip damage on all around faces free.The average of chip strength has increased from 253 MPa to 1312 MPa.
5:00 PM - Y6.6
Assembly and Integration of Thin Bare Die Using Laser Direct-Write.
Alberto Pique 1 , Ray Auyeung 1 , Heungsoo Kim 1 , Scott Mathews 2 Show Abstract
1 Materials Science & Technology Division, Naval Research Laboratory, Washington, District of Columbia, United States, 2 Department of Electrical Engineering, The Catholic University of America, Washington, District of Columbia, United States
Laser-based direct-write (LDW) processes offer unique advantages for the transfer of unpackaged semiconductor bare die for microelectronics assembly applications. Using LDW it is possible to release individual devices from a carrier substrate and transfer them inside a pocket or recess in a receiving substrate using a single UV laser pulse, thus per-forming the same function as pick-and-place machines currently employed in microelectronics assembly. However, conventional pick-and-place systems have difficulty handling small (< 1mm2) and thin (< 100 micrometers) components. At the Naval Research Laboratory, we have demonstrated the laser release and transfer of intact 1 mm2 wafers with thicknesses down to 10 microns and with high placement accuracy using LDW techniques. Furthermore, given the gentle nature of the laser forward transfer process it is possible to transfer semiconductor bare die of sizes ranging from 0.5 to 10 mm2 without causing any damage to their circuits. Once the devices have been transferred, the same LDW system is then used to print the metal patterns required to interconnect each device. The use of this technique is ideally suited for the assembly of microelectronic components and systems while allowing the overall circuit design and layout to be easily modified or adapted to any specific application or form factor including 3-D architectures. This presentation will describe how the LDW process can be used as an effective laser die transfer tool and will present analysis of the laser-driven release process as applied to various types of silicon bare dice.This work was supported by the Office of Naval Research.
5:15 PM - Y6.7
Crystallization of semiconductor islands on amorphous substrates.
Filip Crnogorac 1 , Daniel Witte 1 , Qiangfei Xia 2 , Shashank Sharma 3 , Amir Yasseri 3 , Stephen Chou 2 , Ted Kamins 3 , Fabian Pease 1 Show Abstract
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 Electrical Engineering, Princeton University, Princeton, New Jersey, United States, 3 Quantum Science Research, Hewlett-Packard Laboratories, Palo Alto, California, United States
In monolithic 3-dimensional integration of semiconductor devices each successive circuit layer is fabricated directly on top of pre-existing layers. This 3-D scheme has the potential to increase circuit density, and reduce power consumption and wire delay by reducing wire lengths. Two challenges unique to monolithic 3-dimensional integration are (1) obtaining device-quality single-crystalline semiconductor material on top of the amorphous isolation region separating lower layers, i.e. with controllable crystallite location and size to avoid grain boundaries within the device channel; (2) limiting the temperature of processed devices underneath (eg, to 450 C) to preserve device integrity Here, we propose a method for building high quality semiconductor islands of controllable crystal orientation on an amorphous substrate.Surface relief grating structures of 3-5µm pitch in amorphous substrates have previously been found to define the crystallographic orientation of deposited silicon films. We aim to improve the preferentially orientation by employing nanoimprinted gratings of 190nm pitch in SiO2. The grating pattern was generated using nanoimprint lithography (NIL) and etched into 1µm thick thermally grown SiO2 by CHF3/O2 reactive ion etching. In our initial experiments germanium was deposited onto patterned SiO2 covered with a self-assembled monolayer of octadecyltrichlorosilane (OTS). The Ge was deposited at 400 C and reduced pressure using GeH4 in hydrogen ambient. We observed that heterogeneous crystal nucleation occurs preferentially at the corners of the nanograting. We are investigating the effect of the pattern shape and radius of curvature on crystal orientation both during deposition and during melting and solidification after deposition. To achieve melting and solidification of semiconductor islands within the thermal constraints of monolithic 3-D processing, transient laser heating is used to control the amount of heat deposited into the substrate. Simulation software has been developed to model heat diffusion from a laser pulse, through an island and into the substrate, to predict the thermal profiles, melt durations, and crystallization rates involved. Using a 0.12MW/cm2 laser pulse of 15µs duration, this model shows it is possible to melt the upper layer of amorphous silicon while maintaining the temperature of layers underneath 5µm of SiO2 below 450 C. Arrays of amorphous silicon islands, 2µm to 10µm in diameter, were melted and crystallized using a 10W frequency doubled Nd:YAG laser beam modulated and focused to a 25µm FWHM diameter spot. Initial X-ray diffraction results of the laser melting and solidification process show polycrystalline formation within silicon islands, as well as evidence of preferential out-of-plane orientation of the crystallites.
5:30 PM - Y6.8
The Deposition Kinetics of Thin Ruthenium and Copper Films in Supercritical Carbon Dioxide for 3-D Structures.
Christos Karanikas 1 2 , James Watkins 2 Show Abstract
1 Chemical Engineering, University of Massachusetts - Amherst, Amherst, Massachusetts, United States, 2 Polymer Science and Engineering, University of Massachusetts - Amherst, Amherst, Massachusetts, United States
The preparation of nanostructured elements for future generations of microelectronic and optoelectronic devices will require the deposition of high purity, conformal, thin metal films within narrow (<100 nm) and/or high aspect ratio (>10) features. Recently, we demonstrated that a new deposition process, which involves the hydrogen assisted reduction of soluble organometallic compounds in supercritical carbon dioxide, can meet these challenges. Implementation of the technology requires an understanding of the deposition kinetics and reaction mechanisms. This presentation will describe recent progress in this area.To build a 3-D structure, the deposition kinetics must be fully understood in order to deposit precise thicknesses while maintaining good step coverage. In recent studies, we deposited high purity Ruthenium films via the hydrogen assisted reduction of bis(2,2,6,6-tetramethyl heptane-3,5-dionato)(1,5-cyclooctadiene) ruthenium, (Ru(tmhd)2cod) in supercritical CO2. It was found that conformal Ru films could be deposited onto the native silica surface of an etched silicon wafer with an aspect ratio of 20. This is enabled by the high fluid phase precursor concentrations in supercritical fluid solution.The deposition kinetics of this process have now been studied using a differential cold wall batch reactor over a temperature range from 260 °C to 320 °C at precursor concentrations ranging from 0.01 to 0.2 wt %. In addition, the influences of hydrogen concentration as well as precursor byproduct concentration were determined. This allows for development of a proposed mechanism as well as a Langmuir – Hinshelwood rate expression. Attainment of zero-order kinetics over a broad concentration range promotes the exceptional step coverage, which has been observed.
5:45 PM - Y6.9
Highly (100) Oriented Si Thin Films onto Insulator Substrates using Ultra-thin γ–Al2O3 by Oxidized (002) AlN Buffer Layer.
Wenxu Xianyu 1 , Hyuck Lim 1 , Huaxiang Yin 1 , Hans s Cho 1 , Junho Lee 2 , Youngnam Kwon 2 , Junghyun Lee 3 , Youngsoo Park 1 Show Abstract
1 Semiconductor Device & Material Lab, Samsung Advanced Institute of Technology, Suwon, Gyunggi-Do, Korea (the Republic of), 2 AE Center, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of), 3 Nano Fabrication Technology Center, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of)