Bhushan L. Sopori National Renewable Energy Laboratory
Bernhard Dimmler Würth Solar GmbH & Co. KG
Jeffrey Yang United Solar Ovonic LLC
Thomas Surek Surek PV Consulting
Q1: Crystalline Silicon Technologies
Monday AM, November 30, 2009
Room 306 (Hynes)
9:30 AM - **Q1.1
Hydrogen Passivation for Crystalline Silicon Solar Cells.
Michael Stavola 1 Show Abstract
1 Department of Physics, Lehigh University, Bethlehem, Pennsylvania, United States
The Si substrates that are often used for the fabrication of solar cells to reduce cost give rise to defect issues that must be addressed. Hydrogen is commonly introduced into silicon solar cells to reduce the deleterious effects of defects and to increase cell efficiency . A process that is used by industry to introduce hydrogen is by the post-deposition annealing of a hydrogen-rich SiNx layer that is used as an antireflection coating . A number of questions about this hydrogen introduction process and hydrogen’s subsequent interactions with defects have proved difficult to address because of the low concentration of hydrogen that is introduced into the Si bulk.Fundamental studies of hydrogen-containing defects in silicon provide a foundation for addressing issues of interest to the Si solar-cell community. Strategies have been developed by which hydrogen in silicon can be detected by IR spectroscopy with high sensitivity [3,4]. The introduction of hydrogen into Si by the post-deposition annealing of a SiNx coating has been investigated to reveal hydrogen’s concentration, diffusivity, and reactions with defects. The effect of processing variations on the concentration of hydrogen that is introduced into the Si bulk has also been studied. The contributions of F. Jiang, S. Kleekajai, V. Yelundur, A. Rohatgi, L. Carnel, J. Kalejs, and G. Hahn to our studies are gratefully acknowledged. This work has been supported by the Silicon Solar Research Center SiSoC Members through NCSU Subaward No. 2008-0519-02 and NSF Grant No. DMR 0802278. J. I. Hanoka, C. H. Seager, D. J. Sharp, and J. K. G. Panitz, Appl. Phys. Lett. 42,618 (1983). F. Duerinckx and J. Szlufcik, Sol. Energy Mater. Sol. Cells 72, 231 (2002). F. Jiang et al., Appl. Phys. Lett. 83, 931 (2003). S. Kleekajai et al., J. Appl. Phys. 100, 093517 (2006).
10:00 AM - Q1.2
A New, Ultrafast Technique for Mapping Dislocation Density in Large-area, Single-crystal and Multicrystalline Si Wafers.
Bhushan Sopori 1 , Przemyslaw Rupnowski 1 , Mathew Albert 2 , Chandra Khattak 2 , Mike Seacrist 3 Show Abstract
1 , National Renewable Energy Laboratory, Golden, Colorado, United States, 2 , GT Solar, Merrimack, New Hampshire, United States, 3 , MEMC, St. Peters, Missouri, United States
Average dislocation density and spatial distribution of dislocations are routinely used as a measure of crystal quality of single- and multicrystalline Si (mc-Si) wafers. A variety of techniques have been developed to generate dislocation maps, including X-ray imaging, Cu decoration, and chemical delineation. The most common method is to defect etch the wafer with a suitable chemical etchant and then count the etch pits using an optical microscope. Commercial camera systems, with image analysis software, are available as microscope attachments that can count etch pits within the field of view and combine that information to produce maps of dislocation distribution over a wafer. An improved technique uses light scattered by etch pits to statistically count dislocations. The wafer is illuminated by a laser beam and the total scattered light, which is proportional to the number of etch pits in the illuminated region, is measured. An instrument based on this technique takes 30–60 minutes to map a 6-in x 6-in wafer.This paper describes a new technique that uses scattering from a defect-etched wafer to map dislocation distribution of the entire wafer in a single image. The measurement is very fast and compatible with large-area wafers. In this technique, the single- or multicrystalline wafer is polished to produce a damage-free polished surface. The wafer is then defect etched using Sopori etch (HF:CH3COOH:HNO3 in a 36:15:1 ratio) for 30 s to produce etch pits at dislocation sites. The shape of the etch pit depends on the direction of dislocation at the surface and does not depend on the orientation of the wafer or grain (in mc-Si). The wafer is then placed in a reflectometer where a set of lights, symmetrically placed around the wafer, illuminate it at an oblique incidence. The light scattered normal to the wafer is collected by a camera and imaged. The image corresponds to the local reflectance of the defect-etched wafer. Because local scattering is proportional to the density of etch pits, the camera image is proportional to the local variation in the dislocation density of the wafer. The system is calibrated by using a reference sample to convert the reflectance map into a dislocation map. This technique allows a fast (< 1 s) mapping of dislocations. An interesting feature of this etch is that the scattering cross-section of all dislocations (which can have circular, elliptical, or comet shapes) is the same. Thus, all dislocations are counted. An instrument based on this technique is now commercially available. We will show results that demonstrate: (i) repeatability of defect etching of large mc-Si wafers, (ii) variation of dislocation patterns over selected parts of a mc-Si ingot, (iii) a correlation between defect maps and photocurrent maps of commercial Si solar cells, and (iv) a correlation between defect distribution and the solar cell performance.This abstract is subject to government rights.
10:15 AM - Q1.3
Low-cost, High Efficiency Solar Cells on Scrapped CMOS Silicon.
Daniel Inns 1 , Joel de Souza 1 , K. Saenger 1 , H. Hovel 1 , D. Sadana 1 Show Abstract
1 T. J. Watson Research Centre, IBM, Yorktown Heights, New York, United States
The cost of scrapped Si from the CMOS industry is extremely low which makes it an attractive material for solar industry. However, the minority carrier lifetime of this material is very low and variable, typically ~ 1 µs compared to the lifetime of the original prime-Si wafer which is > 500 µs. Solar cells made on scrapped wafers therefore result in efficiencies which are inferior to that from a prime CMOS grade Si. We have developed a novel and effective low-cost metal gettering anneal process which allows the minority lifetime of the scrapped wafer to recover to close to its original value, a 100-500 fold increase. Since the efficiency of a solar cell is directly impacted by the minority carrier lifetime, cell efficiency of the improved scrapped Si is nearly equivalent to that from a prime-Si wafer. In order to erase the processing history of the wafer, surface etching is performed to remove ~ 20 µm of surface Si. Following this is a unique impurity gettering step that is performed at > 1300°C with chlorine-containing gas to enable efficient gettering of metals out of the substrate. An efficiency of ~15% has been demonstrated on both prime and improved scrapped wafers using rudimental device design to study the validity of our unique metal gettering process. This efficiency is being improved to much higher values by refinements in device design, anti-reflection coating(s) and surface passivation schemes.
10:30 AM - **Q1.4
Crystalline Silicon Technology for Solar Applications.
Aditya Deshpande 1 , Mike Seacrist 1 , Steve Kimbel 1 , Gang Shi 1 , Jihong Chen 1 Show Abstract
1 , MEMC Electronic Materials, St Peters, Missouri, United States
The use of crystalline silicon in solar applications exceeds the silicon consumed in semiconductor applications. Further, the growth rate of silicon use in solar applications has been higher than the growth rate of use in semiconductor applications over the past several years. Many similarities and synergies exist between manufacturing silicon for semiconductor and solar applications. These include producing polysilicon raw material, growing silicon crystals, and converting crystals into silicon wafers by wire slicing. For these reasons there is a strong motivation for silicon suppliers to participate in the crystalline silicon solar market. Crystalline silicon solar cells are the workhorse of the photovoltaic industry and have a significant portion of the market share of the world production of solar cells. The key driver and challenge for crystalline silicon in solar is cost which is influenced by both the silicon material cost and silicon performance. For silicon to maintain and improve on solar cell market share, further reductions in production cost as well as improvements in solar cell efficiency are necessary. The approach of a vertically integrated silicon supplier to the challenge of improving solar cell efficiency performance while also improving silicon manufacturing productivity and reducing cost will be described. A technical roadmap for crystalline silicon material will be presented and discussed. Key components of the cost are silicon feedstock, crystallization, and slicing. The approaches for commercial production of all these steps will be contrasted with other available methods. The use of directional solidification (DS) methods to grow multi-crystalline silicon (mc-Si) is a large fraction of the crystalline silicon market. The efficiency of mc-Si solar cells is usually lower than for single crystal silicon because of a high degree of material defects that include dislocations, random grain orientations, grain boundaries, impurity precipitates, and inclusions. Typical defects and impurities in mc-Si wafers and their influence on the device performance are reviewed. Detailed characterization of these defects is not straightforward. Methods developed for characterization of these defects will be presented.
11:30 AM - **Q1.5
Developments in Crystalline Silicon-based Photovoltaic Product Architecture and Manufacturing.
Juris Kalejs 1 Show Abstract
1 , American Solar Technologies, Chelmsford, Massachusetts, United States
Solar electric (Photovoltaic) crystalline silicon (c-Si) product diversity has changed very little over three decades of development, including the last decade of unprecedented expansion of the industry. The dominant module product comprising over 90% of cumulative installations, which exceed 15 GW worldwide, still employs an ubiquitous configuration, a platform based on a planar laminate. This paper will review trends in module architecture and manufacturing methods for this currently dominant PV c-Si commodity module platform. The commodity flat-plate module contains typically 60-72 solar cells cut from multicrystalline blocks as 156 mm square areas, or 156 mm dimension pseudo-squares cut from single crystal boules. New module design and manufacturing approaches different from those of the commodity PV product are now in development and piloting. Developments which use innovations in manufacturing processes, i.e., stringing of cells and packaging in a laminate, will be discussed.
12:00 PM - **Q1.6
Contactless Measurement of Carrier Lifetime on As-Grown or Shaped Ingots, Sections, and Blocks.
Ronald Sinton 1 , Tanaya Mankad 1 , M. Forsyth 1 , James Swirhun 1 Show Abstract
1 , Sinton Instruments, Inc., Boulder, Colorado, United States
This work will describe recent developments in measurement techniques for assessing the bulk lifetime of ingots, sections, and blocks without surface preparation. This permits detailed characterization of the materials as they exist in the production environment. Prior to sawing into wafers, it is possible to characterize the quality of the feedstock and growth parameters of bulk silicon. This allows quick feedback in order to fully optimize the growth. This can also be used to qualify the quality and suitability of the crystalline silicon for particular solar cell processes. Measurement at this stage, compared to after wafering, is extremely useful and cost effective. The measurements are more sensitive to true bulk parameters before wafering, the entire ingot can be assessed quickly, and the cost of wafering can be adverted or modified if all or a portion of the piece “fails”. Therefore measurements in the ingots or blocks prior to sawing into wafers present an unusual combination of industrial and scientific advantages compared to measurements of wafers. After sawing, the unpassivated surfaces of the wafers can compromise electronic material measurements until at least the phosphorus-diffusion step in the process which acts to passivate the surface recombination.The parameters that are determined by Quasi-Steady-State Photoconductance, QSSPC, or transient photoconductance measurements on as-grown or shaped material are the bulk lifetime, the resistivity, and the “trapping” which can be a measure of crystalline quality. Patterns in any of these parameters, from top to bottom of the grown piece or across the diameter of a sectioned CZ ingot give valuable information concerning feedstock, external contamination during growth (from the crucible or growth furnace), and the thermal growth conditions.Three special cases will be described in some detail.1) Boron-doped CZ. The special characteristics of this material are the strongly injection-level-dependent lifetime and the B, O, and Fe spatial dependences that gives can give rise to strong lifetime variations in both the growth direction and radially. Typical ranges of bulk lifetime are 10-500 microseconds.2)B-doped multicrystalline silicon. This material, like B-CZ, has strong spatial dependence of the lifetime, ohm-cm, and trapping as a function of both the growth direction and the position of the block relative to the crucible.3)The highest efficiency cells in the industry use n-type CZ or FZ silicon. The desired sensitivity for these processes requires the accurate discrimination of differences between silicon in the 1-10 ms range. In this range, a significantly different measurement and analysis technique will be presented in detail.
12:30 PM - Q1.7
Commercial Production of Silicon Solar Cell Feedstock by Upgrade of Metallurgical Grade Silicon.
John Mott 1 , Julio Bragagnolo 1 , Michael Hayes 1 Show Abstract
1 , Ohio Solar Energy, LLC, Alliance, Ohio, United States
Introduction. The relationship between impurity content in Solar Grade Silicon (SGS) and solar cell quality is the subject of intensive research. The PV industry has developed around the use of silicon made by the Siemens process for the semiconductor industry, with impurity levels typically in the parts per billion by weight (ppbw) range. There is a growing consensus that SGS with impurities in the parts per million range (ppmw) can be obtained cost effectively from Metallurgical Grade Silicon (MGS) and used to yield solar cells with comparable performance (see for example ‘Beneficial Effects of Dopant Compensation on Carrier Lifetime in Upgraded Metallurgical Silicon’ by S. Dubois et al. in the 23rd European Photovoltaic Solar Energy Conference, Valencia, September, 2008). This provides insight on the success encountered by Timminco, an early SGS market entrant, in commercializing silicon material with [P] levels of the order of 2 ppmw. Current Work. Analysing data from 16 UDS runs on samples taken from the melt, before and after UDS, and a solid sample taken from the silicon frozen on the cold silicon collection surface, we note that the average values of [P] in the molten silicon samples increase from 11.9 ppmw before UDS to 15.9 ppmw after UDS. The average value of [P] in the solid silicon sample is 4.9 ppmw. This demonstrates an effective refining ratio of 0.41, even at a 50% solid fraction. This is important as UDS, by its nature, implies a loss of silicon, while little or no silicon is lost in B reduction. Performing a secondary UDS on silicon obtained from these primary UDS runs yields [P] around 2 ppmw.In addition to P and B reduction, in this paper we also discuss the hardware designed to implement this process in commercial production in volumes exceeding 4,000 MT per year. MB Scientific, the original process developer, and NC Consulting, an engineering company, have developed a plant design that can produce SGS at an estimated cost that will allow for profitable large scale production, and have joined in a new company, Ohio Solar Energy, to commercialize the large-scale production technology. Future Work. While the UDS equipment design is completed, we have so far succeeded in decreasing the B concentration to 30% of the initial value by using glass slagging, wherein molten glass devoid of boron is vigorously mixed with the silicon metal and made to ‘getter’ the boron in the silicon and is then removed from the silicon metal. Repeated with new glass each time, the number of steps is dependent on the starting concentration of the boron in the silicon. The difficulty with reducing B is related to the P levels in the glass constituents due to back-contamination with successive washes. A new furnace, with more powerful agitation and designed to prevent recontamination of the UDS-processed silicon, and purer glass will enable B removal to ≤1ppmw target levels.
12:45 PM - Q1.8
Efficient Single-crystal Black Silicon Solar Cells with Anti-reflection by a Nanocatalyzed One-step Etch.
Hao-Chih Yuan 1 , Vernon Yost 1 , Matthew Page 1 , Howard Branz 1 Show Abstract
1 , National Renewable Energy Lab, Golden, Colorado, United States
Without using silicon nitride or another dielectric anti-reflection (AR) layer, we have fabricated confirmed 16.8%-efficient prototype solar cells on 2.7 ohm-cm, 300 um p-type single-crystal Si (100) substrates. Aside from the use of an inexpensive single-step nanocatalyzed liquid etch [Branz, Appl. Phys. Lett. 94, 231121 (2009)] to produce a nanoporous black silicon surface layer, processing of these cells is nearly identical to the present practice in PV silicon manufacturing, including a POCl3-diffused emitter and aluminum back-surface field. Open-circuit voltage (612 mV) and fill factor (80%) of the single-crystal black silicon cells is comparable to a planar control. The weighted average reflectance from 350 to 1000 nm of the single-crystal black silicon cells is below 2% compared with 34.3% of the planar control with no AR. As a result, the short-circuit current of the black silicon solar cells is 38% higher than the planar control. Nonetheless, the 34.7 mA/cm2 short-circuit current density of the black silicon solar cells is about 3 mA/cm2 below that predicted by the reflectance reduction alone. Our modeling shows that the current deficit is due to high recombination in the nanoporous layer, which impacts the short-wavelength spectral response. We also study the optical properties of the nanoporous black silicon surface layer and our measurements reveal some scattering in the nanoporous surface layer, but little internal reflection (light trapping). The studies on the optoelectronic and optical properties enable us to describe not only possible improvements to our solar cells, but general design considerations for high-efficiency solar cells based on density-graded black-silicon surfaces. Finally, we estimate the potential cost advantage of eliminating the vacuum-coated silicon-nitride anti-reflection equipment from the PV manufacturing line.
Q2: CdTe and GaAs Based Technologies
Monday PM, November 30, 2009
Room 306 (Hynes)
2:30 PM - **Q2.1
Present Status of Research and Industrial Development of CdTe/CdS Solar Cells.
Ramesh Dhere 1 , David Albin 1 , Xiaonan Li 1 , Timothy Gessert 1 Show Abstract
1 , National Renewable Energy Lab, Golden, Colorado, United States
Thin-film solar cells have attracted considerable attention due to their potential for low-cost production. CdTe has been one of the main contenders in this arena because its bandgap of 1.5 eV is ideally matched to the solar spectrum and the binary compound allows the freedom to choose a variety of fabrication techniques. This presentation will highlight key developments during the last forty years that have been stepping stones for progress in device performance. Industrial activity began in the early 1980s when Matsushita introduced screen-printed modules, and there were several players in the field. The field has expanded tremendously in the last five years with First Solar leading the way. First Solar is already the largest producers of photovoltaics in the United States, and with a planned expansion to 1 GW by the end of 2009, they will be contending for the top spot worldwide. We will present an overview of different industries involved in the field and their approaches. In addition, we will present the ongoing research at our laboratory (NREL) and others and will analyze the status of the research. The efficiency of the champion CdTe cell is 16.5%, and module efficiency based on present knowledge is expected to reach around 12.5%, which is well below its potential. We will present the analysis of the device performance and the main parameters affecting the performance. Further improvement in module performance is unlikely without better understanding these parameters. Other area of emphasis is the long-term reliability and accelerated life testing that is necessary to understand the effect of processing changes on product reliability. NREL is developing the Process Development and Integration Laboratory (PDIL) to facilitate interaction among industry and research groups. The presentation will provide an overview of the CdTe tool being developed and provide some details about the capabilities of the tool, in particular, and PDIL facility, in general. This abstract is subject to government rights.
3:00 PM - Q2.2
Study of the Electrical Properties of Cross Sections of CdTe/CdS Solar Cells Measured with Scanning Kelvin Probe Microscopy.
Helio Moutinho 1 , Ramesh Dhere 1 , Chun-Sheng Jiang 1 , Mowafak Al-Jassim 1 Show Abstract
1 , National Renewable Energy Laboratory, Golden, Colorado, United States
We apply scanning Kelvin probe microscopy (SKPM) to analyze cross sections of working CdTe/CdS solar cells under different bias conditions. This technique is performed inside a scanning probe microscope (SPM), and it provides the distribution of the electrical potential inside the device with high spatial resolution. The SKPM and topographic images are compared to associate variations of the potential with topographic features. For instance, it is possible to compare the position of the p-n junction with the metallurgical junction between CdTe and CdS. In SKPM, we apply AC and DC bias between the tip of the SPM and the sample. The signal measures the difference between the work functions of the tip and sample surface, and it is proportional to the surface potential of the sample. By biasing the cell during measurement (reverse and forward polarizations), we avoided artifacts such as Fermi-level pinning, and we were able to investigate the distribution of the electrical potential inside a live device polarized under different conditions. By taking the derivative of the potential, we determined the distribution of the electric field, and by locating the maximum of the electric field, we located the position of the p-n junction.This work complements our other work presented in the 2009 Spring MRS Meeting that investigated different ways to prepare cross sections of samples, compared two different SKPM measurement procedures (using the first and second resonance cantilever peaks), and determined the position of the junction for a standard CdTe/CdS solar cell. In this work, we investigate the change in the electrical potential using different bias, forward and reverse, showing the change in the width of the depletion region. By calculating the derivative of the potential, we observed the distribution of the electric field inside the device and noticed the following: the field has a strong value concentrated on a thin layer of the device at the junction, and a much smaller value moving away from the junction, showing that there is a change on the electrical properties of the device at the interface. To investigate whether interdiffusion of Te and S is responsible for this effect, we analyzed solar cells without CdCl2 heat treatment, as well as cells produced without the CdS layer. In both cases, the distribution of the electrical potential and electric field was different than for a standard device. In this work, we will also present results of the distribution of the electrical potential on the back contact of the solar cells. In our case, we use graphite paste deposited on the CdTe film followed by the deposition of Ag film. We will show that, in general, the potential drop between the CdTe/graphite interface is much smaller than in the junction region. This abstract is subject to government rights.
3:15 PM - Q2.3
Finite Element Model to Understand the Effect of O2 on Closed Space Sublimation of CdTe.
Nirav Vora 1 , Ramesh Dhere 1 Show Abstract
1 National Center for Photovoltaics, National Renewable Energy laboratory, Golden, Colorado, United States
Incorporating O2 in the closed space sublimation (CSS) of CdTe thin film has resulted in improved cell efficiencies. Many studies have been undertaken to understand this effect on cell efficiency. In this work we study the effect of oxygen on lateral uniformity of the deposited CdTe film. A finite element model has been developed to represent the mass and heat transfers involved in the CSS process. The model takes into consideration the effect of O2 by modeling its reaction with Cd vapors in the space between the source and the substrates. This reaction can decrease the amount of Cd available for condensation near the substrate if the diffusion of Cd from the source to the substrate is not fast enough. One of the factors affecting this reaction rate is the concentration of O2. So a gradient of O2 from the edges to the center of the substrate can result in a laterally non-uniform film. This gradient can be formed if the rate of diffusion of O2 is lower than that of its reaction with Cd. A steady state model will be solved at various temperatures, pressures, and separation distances to determine the optimum conditions for depositing a CdTe film with uniform thickness. Experiments will be carried out at these conditions and results compared with the simulation results. The comparison will help in determining the reaction rate constants, as there is a lot of variation in the values reported in the literature. A transient model will also be developed to better represent the experiments. Finally the model will be modified to represent the vapor transport deposition of CdTe. This abstract is subject to government rights.
3:30 PM - Q2.4
CdTe Thin Film Growth Using High Rate Sputtering for Photovoltaic Applications.
John Walls 1 , Paresh Nasikkar 1 , Hari Upadhyaya 1 Show Abstract
1 Electronic and Electrical Engineering, Loughborough University, Loughborough United Kingdom
Magnetron sputtering has a number of important advantages for the deposition of thin films for use in photovoltaic devices. Sputtering provides control over thin film thickness with sub-nanometre precision using time only. This allows the thickness of the CdTe absorber layer to be optimized thereby minimizing materials usage and process manufacturing time. Using the closed field configuration, the thin films are super-smooth (< 1 nm rms roughness). This is especially important in the TCO base layer since roughness of the TCO can break through the CdS layer and cause “shunting” across cells. This paper describes a flexible reactive sputtering process in which adjacent unbalanced magnetrons are constructed of opposite magnetic polarity. The resulting closed magnetic field maintains a high density reactive plasma. In contrast to previous reactive sputtering strategies, the process does not require an auxiliary ion or plasma source and the associated use of high voltage ion acceleration. As a result, the deposition energy is optimized and insufficient to cause damage in the growing thin film. The substrate temperature is typically maintained below 100°C without the need for direct cooling. The thin films exhibit bulk optical properties, they are also dense and super-smooth. The thin films also have typically low compressive stress. The magnetron targets are simple metals or semiconductors for high rate deposition and are converted to compound thin films when required by using the appropriate reactive gas. This paper provides data derived from a medium throughput batch system with a 0.4 m diameter drum substrate carrier and four 0.6m linear magnetrons. However, the process geometry is scalable and adaptable to in-line deposition. The optical and electrical performance of each layer in the CdTe thin film photovoltaic stack will be presented together with preliminary device performance.
3:45 PM - Q2.5
Fabrication and Modeling of Three-Dimensionally Structured CdTe Thin Film Photovoltaic Devices with Self-Aligned Back-Contacts.
Jonathan Guyer 1 , Daniel Josell 1 , Carlos Beauchamp 1 , Suyong Jung 2 , Behrang Hamadani 2 , Lee Richter 3 , John Bonevich 1 , Nikolai Zhitenev 2 , Tom Moffat 1 Show Abstract
1 Metallurgy Division, NIST, Gaithersburg, Maryland, United States, 2 Center for Nanoscale Science and Technology, NIST, Gaithersburg, Maryland, United States, 3 Surface and Microanalysis Science Division, NIST, Gaithersburg, Maryland, United States
Our goal is to provide industry with test structures and models ofnext-generation photovoltaics, with an initial focus on CdTe andCuInxGa1-xSe2 (CIS or CIGS) materials. These tools will enableinterpretation of measured external properties affected by geometry, grainstructure, and nanoscale phase separation, which will support improvedprocessing and design