Symposium EP09—Devices and Materials to Extend the CMOS Roadmap for Logic and Memory Applications

Standby power becomes much more serious than dynamic power with the technology scaling and becomesone critical issue of IC development, particularly for the power constrained applications, such as Internet of things (IoT) and implantable chips which have stringent ultra-low-standby-power requirements. Different from conventional MOSFET, novel device concepts with new operation mechanisms which can achieve ultra-steep subthreshold slope, free from the conventional thermal limitation of subthreshold slope (SS), have attracted immense attention for ultra-low-voltage and ultra-low-power applications. Among all kinds of steep-slope devices, Tunnel FET (TFET) utilizing band-to-band tunneling (BTBT) mechanism and Negative Capacitance FET (NCFET) with ferroelectric (FE) gate are the two of the most promising candidates, with reported demonstrations of their capability of sub-60mV/dec SS at room temperature. However besides the steep SS, the devices need further comprehensive investigation as well as further physical clarification for device design optimization and future circuit applications.
TFET devices with the gated p-i-n structure can theoretically achieve steep SS and ultralow off-state leakage current. However, they face the fundamental low on-current issue due to the relatively low tunneling efficiency. Moreover, it is difficult to obtain high on-current, steep SS and ultralow off-current simultaneously, even adopting narrow bandgap materials. From the perspective of mechanism engineering, a new kind of hybrid operation mechanism of Schottky injection and BTBT is presented, fundamentally addressing the issue of low drive current in conventional TFETs and obtaininghigher on-current and lower SS while maintaining ultralow off-current. The proposed multi-finger-gate Schottky barrier TFET (MFSB-TFET) exhibits superior performance with the steep SS of 29mV/decade and large on-off current ratio of >10⁸. The ON-current is improved by 2.5 decades compared with conventional TFET. In addition, the MFSB-TFET also experimentally demonstrates comprehensive electrical properties enhancement in terms of output behavior, capacitance, delay, gain, noise, variability and reliability, showing its great potential for ultralow-power digital and analog circuits applications.
The other possible solution for sub-60mV/dec SS isNCFET. Integrating the FE layer into the gate stack of conventional FET, the voltage amplification effect induced by the NC of FE can lead to the steeper SS than conventional FET without on-current penalty. However, the FE film usually exhibits hysteretic loops of polarization-voltage, and most NCFETs experimentallydemonstrate the confliction between SS and hysteresis. Besides, the theoretical explanations of NC effect and hysteresis in NCFETs are still controversial. We presentthe first direct experimental observation of NC effect in a standalone FE capacitor, proving that the NC is generated from the dynamic polarization switching instead of steadyswitching of FE. A new dynamic polarization matching condition is derived and provides new understanding of the steep-slope in the NCFETs. In addition, the physical origin of hysteresis behavior in NCFETs is analyzed, theoretically explaining the SS and hysteresis optimization confliction, which indicates a big challenge for logic applications of NCFETs.
Due to the voltage amplification effect of NC, by further integrating NC to TFET, NC-TFET devices are expected to obtain higher on-current and steeper SS without off-current degradation. A novel NC-TFET design with striped gate configuration is proposed and experimentally demonstrated with sub-60mV SS and nearly non-hysteresis behavior. Benefiting from the hybrid modulation of NC effect and junction depleted-modulation effect, the proposed new NC-TFET design shows great potentials for some standby-power constrained applications.

More than ten years ago, ferroelectric negative capacitance has been proposed [1] to overcome the basic limitations of the voltage scalability in complementary metal oxide semiconductor circuits (CMOS) imposed by the fact that the subthreshold swing cannot be reduced below 60 mV/dec. However, to realize this proposal it was necessary to overcome the massive issues associated with integrating a ferroelectric into a CMOS process [2]. The first report on ferroelectricity in doped hafnium oxide in 2011 [3] therefore quickly turned this idea into a possibly mass manufactural option for future CMOS scaling. However, although the benefits of voltage amplification achieved by the integration of the ferroelectric into the gate stack can be easily shown using fundamental Landau theory, the possibility of a practical implementation of the effect into CMOS devices is still under discussion in the scientific community. When measuring ferroelectric properties, in general the voltage is forced and therefore the negative capacitance region cannot be observed. Using a series resistor, first indications of negative capacitance could be observed in doped HfO₂ [4]. Recently, a pulse measurement technique together with dielectric layer in direct contact to the ferroelectric, finally made it possible to extract the S-shaped curve predicted by Landau theory [5,6]. Already in [1] the idea of introducing a suitable dielectric capacitor in series has been described and used as the basis for subsequent investigations by many groups. However, an important feature of ferroelectrics, namely domain formation, is often neglected in basic simulation work, where Landau theory is used in a way that implies a single domain state [7]. When introducing domains into the theory, it still seems possible to stabilize the negative capacitance region [8]. However, the metal electrode introduced between the dielectric and the ferroelectric in many experimental demonstrations will be detrimental and limit the stabilization to extremely small devices. Coming from the practical side, encouraging data on hafnium oxide based ferroelectrics integrated into state of the art devices have been shown [9], but the connection to the basic material work and theory is often missing. In this presentation the authors will give an overview on their own findings of negative capacitance in hafnium oxide and connect these to literature results on fully integrated devices.
References
[1] S. Salahuddin and S. Datta, Nano Lett. 8 (2008), pp. 405-410
[2] C.-U. Pinnow and T. Mikolajick, J. Electrochem. Soc. 151 (2004), pp. K13-K19
[3] T. S. Böscke et al., Appl. Phys. Lett. 99 (2011), p. 102903
[4] M. Hoffmann et al., Adv. Funct. Mater. 26 (2016), pp. 8643-8649.
[5] M. Hoffmann et al., IEDM (2018)
[6] M. Hoffmann et al. Nature (accepted for publication).
[7] H. Ota et al., IEDM (2016), pp. 12.4.1-12.4.4.
[8] M. Hoffmann et al., Nanoscale 10, 23 (2017), pp. 10891-10899
[9] Z. Krivokapic et al., IEDM (2017), pp. 357-360

A ferroelectric semiconductor field-effect transistor (FeS-FET) was proposed and experimentally demonstrated for the first time. In this novel FeS-FET, a 2D ferroelectric semiconductor α-In₂Se₃ is used to replace conventional semiconductor as channel. α-In₂Se₃ is identified due to its proper bandgap, room temperature ferroelectricity, the ability to maintain ferroelectricity down to a few atomic layers and the feasibility for large-area growth. An atomic layer deposited (ALD) Al₂O₃ passivation method was developed to protect and enhance the performance of the α-In₂Se₃ FeS-FETs. The fabricated FeS-FETs exhibit high performance with a large memory window, a high on/off ratio over 10⁸, a maximum on-current of 671 μA/μm, high electron field-effect mobility with μ_FE= 312 cm²/Vs in forward sweep and μ_FE= 488 cm²/Vs in reverse sweep, and the potential to exceed the existing Fe-FETs for non-volatile memory applications.

Two dimensional (2D) materials are being investigated very intensively, some of them holding great promise as emerging semiconducting materials for future nano-electronics, beyond current semiconductor technology which faces hard limitation in performance enhancement due to excessive power dissipation during high frequency operation, while they present ultra-thin body and short channel effect-free state with efficient electrostatic control. These properties enable 2D materials to be very promising candidates that can meet major requirements for high performance memory and logic applications using CMOS and also for electronic and photonic devices operated in emerging future mobile and IoT environment. However, research towards the realization of the 2D materials based CMOS semiconductor devices faces serious challenges which require various innovative technical breakthroughs. In this talk, I would like to firstly address prospects of 2D devices for the future semiconductor applications. Then, I would like to address challenges from the semiconductor device point of view, mainly on crystalline growth of large scale 2D materials, doping of charge carriers into 2D substrates, strong Fermi level pinning from surface defects sensitive material properties, high contact resistance at the interfaces with metal electrodes, and inefficient power dissipation along ultra-thin 2D structures leading to early breakdown.

Acknowledgments: This work was supported by the Global Research Laboratory (GRL) Program (2016K1A1A2912707) and Global Frontier R&D Program (2013M3A6B1078873), both funded by the Ministry of Science, ICT & Future Planning via the National Research Foundation of Korea.

References:
[1] F. Ahmed et al. “Impact ionization by hot carriers in a black phosphorus field effect transistor” Nature Communications 9, 3414 (2018)
[3] M. Huang et al. “Highly Oriented Monolayer Graphene Grown on a Cu/Ni (111) Alloy Foil” ACS Nano 12, 6177 (2018)
[1] C. Kim et al. “Fermi Level Pinning at Electrical Metal Contacts of Monolayer Molybdenum Dichalcogenides” ACS Nano 11, 1588 (2017)
[4] M. S. Choi et al. “Electrically Driven Reversible Phase Changes in Layered In₂Se₃ Crystalline Film” Advanced Materials, 29, 1703568 (2017)
[5] D. Qu et al. “Carrier Type Modulation and Mobility Improvement of Thin MoTe₂” Advanced Materials, 29, 1606433 (2017)
[6] X. Liu et al. “Modulation of Quantum Tunneling via a Vertical Two-Dimensional Black Phosphorus and Molybdenum Disulfide p–n Junction” ACS Nano 11, 9143-9150 (2017)

There is an intense search for materials that enables energy efficient schemes for charge-to-spin conversion and magnetization switching. I will discuss various proposals in relying on topological effects for the realization of efficient charge-to-spin conversion, such as the Rashba Edelstein effect in topological insulator and the intrinsic spin-Hall effect in topological materials. Next, I will discuss the possibility of maganetization switching via voltage controlled magnetization anisotropy, in ultrathin ferromagnetic layers stacks.

Nanoscale mechanisms of memristors and electronic synapses fabricated from vertical graphene/MoS₂ van der Waals heterostructures remain largely unexplored. We used scanning tunneling microscopy (STM) and spectroscopy (STS) to investigate the electronic properties of these devices at the atomic scale. We were able to resolve the contributions from defects, specifically to the formation of atomic-scale conductive regions during switching events in these devices. We were also able to induce switching through these devices using the STM tip and to tune the performance of memristors and electronic synapses. We will discuss these results along with theoretical calculations.

Two-dimensional (2-D) semiconductors exhibit excellent device characteristics, as well as novel optical, electrical, and optoelectronic characteristics. In this talk, I will present our recent advancements in defect passivation, contact engineering, surface charge transfer doping, ultrashort transistors, and heterostructure devices of layered chalcogenides. We have developed a defect passivation technique that allows for observation of near-unity photoluminescence quantum yield in monolayer MoS₂. The work presents the first demonstration of an optoelectronically perfect monolayer. Forming Ohmic contacts for both electrons and holes is necessary in order to exploit the performance limits of enabled devices while shedding light on the intrinsic properties of a material system. In this regard, we have developed different strategies, including the use of surface charge transfer doping at the contacts to thin down the Schottky barriers, thereby, enabling efficient injection of electrons or holes. We have been able to show high performance n- and p-FETs with various 2D materials, including the demonstration of a FET with 1nm physical gate length exhibiting near ideal switching characteristics. Additionally, I will discuss the use of layered chalcogenides for various heterostructure device applications, exploiting charge transfer at the van der Waals heterointerfaces.

Moving beyond the limits of silicon transistors requires both a high-performance channel and high-quality electrical contacts. The type of barrier at a metal/TMD junction is one of the key issues in TMD field-effect transistors (FETs). It is important to design contacts such that the transmission is dictated by intrinsic properties of the TMD channel rather than by details of the contacts. In this work, we report a systematic study of metal/TMD contacts, with monolayer channel materials WSe2 and MoS2 grown by chemical vapor deposition. We show how the contact barrier can be modulated by the work function of contact metals, defects, and contact geometry on “clean” surface of TMD. The Fermi level pinning can be effectively mitigated or eliminated through the proper contact engineering. The end-bonded contact, formed through the reaction of transition metals with the TMD channel, exhibited no Schottky barrier and holds great promise for high-performance TMD FETs, enabling future ultimately scaled device technologies.

A major factor limiting the performance of devices is their contact resistances which depend on Schottky barrier heights (SBHs). Fermi level pinning (FLP) by a high density of states in the semiconductor band gap generally limits the ability to vary the contact work function to minimize the SBH. Recently, it was found that contacts with Bi or Sb between the main contact metal and Si [1] would be less strongly pinned than those with direct contact to Si. To understand the cause of this effect, the SBH of metals on Sb were calculated by DFT. It was found that the low density of states at E_F allows a SB pinning factor S of 0.2 - 0.4, depending on Sb thickness. This suggests that the SBH follows the MIGS /Cowley-Sze [2] model where only the density of states at E_F matters. On the other hand, the SBHs of silicides on Si are easier to interpret in terms of the polarization of interfacial bonds (‘Tung model [3]’). This indicates how the control of Schottky barriers, critical to one of the simplest limits to device performance, are still not well understood.
[1] T Nishimura et al, SSDM K1-05 (2017)
[2] A M Cowley, S Sze, J App Phys 36 4212 (1965)
[3] R T Tung, App Phys Rev 1 011304 (2014)
[4] H Li, Y Guo, J Robertson, Sci Rep 7 16669 (2017)

In recent years, an incredible increase in the number of transistors per chip has been observed, which has led to an increasing demand for more power efficient electronics. Additionally, recent studies of two layered materials such as graphene and some transition-metal dichalcogenides (TMDs) have shown strong potential for future use in electronics. One useful property of TMDs is that their electrical and optical properties are highly sensitive to strain. Furthermore, Micro-Electro-Mechanical System (MEMS) can be designed to provide a high level of stress. A low-power switch was recently proposed using a MEMS actuator to strain a MoS₂ bilayer with switching energies as low as E = 1.0733 aJ [1].
In this work, we present the design and fabrication process of a MEMS-TMD switch designed to provide strain up to 6%. A comb-drive architecture is used for the MEMS actuator. A fabrication process for the MEMS is developed using SiGe technology. Finally, a process to transfer and clamp the TMD onto the MEMS is presented.


[1]A. Vidana et al., (2018) "Conductivity Modulation in Strained Transition-Metal-Dichalcogenides via Micro-Electro-Mechanical Actuation", Manuscript submitted for publication.

Crystalline metal-oxide thin films are an attractive group of materials for a wide variety of device applications. Among these, the perovskite family of complex oxides have experienced extensive research and development efforts due to their unique multifunctional properties. Despite numerous advances in the field, it is still a challenging task to create a high-quality epitaxial heterostructure on silicon where the intrinsic properties and functionalities of the perovskite oxides are preserved. Additionally, the practical, application-driven methodology to best tune their properties remain relatively unexplored. In this work, these two challenges are addressed by adopting an advanced oxide-MBE technique and controlling the amount or density of the oxygen vacancies, respectively. The flagship perovskite oxide, STO (SrTiO₃),was grown directly on top of silicon in an oxide-MBE chamber by co-deposition of Sr, Ti, and molecular O₂, and our preliminary analysis indicates that formation of an amorphous SiO₂layer at the interface was well suppressed (ensuring the epitaxy) and oxygen deficiencies (defects) were created inside the STO layer (ensuring tunability). Thetwo-step annealing process was applied to control both the crystallinity and oxygen vacancy of the 8.6 nm-thick perovskite thin film. Based on the structural and electrical testing results on the STO/Si heterostructure thin films prepared by oxide-MBE, we propose that STO has great potential to advance the next-generation memory and storage device applications. Its ultra-high dielectric constant (100 to 300) that can be accomplished by eliminating the oxygen vacancies inside the STO layer can significantly improve the EOT for the purpose of developing a high-capacity DRAM. The hysteretic resistance change in the very low operating current regime (a few to a few hundred amperes) suggests that the STO thin film can also contribute to the development of low-power memristor devices.

To develop brain-inspired neuromorphic computing systems, the artificial synaptic devices were investigated using synaptic transistors with single- and double-gate thin-film transistor (TFT) structures. Distinguishable from a two-terminal memristor-synapse, the synaptic transistor enables the synaptic weight to be tuned and then updated by gate biasing during signal processing by drain biasing at the same time. In this study, we demonstrated various synaptic motions with single- and double-gate TFT consisting of an oxygen-deficient TaOx gate insulator and an indium-gallium-zinc oxide (IGZO) semiconductor channel layer, i.e., an Al-top-gate/SiOx/TaOx/n-IGZO on a SiO₂/n⁺-Si-bottom-gate substrate through concurrent changes in gate oxide capacitance, channel mobility, and threshold voltage. This synaptic TFT exhibited the tunable drain current, corresponding to synaptic weight modulation in biological synapse, upon repeatedly applying gate and drain voltages. The drain current modulation features to be analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (~10⁴), as a consequence of the changes in mobility of IGZO channel and gate oxide capacitance, and threshold voltage. The drain current modulation responsive to timing of voltage application emulates synaptic potentiation, depression, paired-pulse facilitation, and memory transition behaviors depending on the voltage pulse amplitude, width, repetition number, and interval between pulses. The synaptic motions could be realized also by double-gate operation that separately tuned the drain current by top-gate biasing and sensing it by bottom-gate biasing. It provided the modulated synaptic weight with wide level of synaptic weight with respect to read condition using bottom-gate stack without read-disturbance. It demonstrated an operation scheme that the signal processing can be performed using the bottom-gate biasing during simultaneous updating of synaptic weight with the top-gate biasing. In addition to the application of this synaptic TFT to artificial synapse for neuromorphic system, its analog, reversible, and nonvolatile changes in drain current as a result of gate biasing can be applied to the operation for nonvolatile memory and field-programmable logic devices.

Atomically thin 2D materials have ushered in a new era in the field of materials science and has been translated to notable advancements in the design of sensors, optoelectronic devices, flexible electronics [1]. These atomically thin materials are predicted to replace conventional bulk materials, Si and Ge, for transistor channels and extend the complementary metal oxide semiconductor technology road-map beyond the ultimate scaling limit [2]. Constant efforts are being made to synthesize devices based on some of the recently discovered van der Waal's materials such as graphene, hexagonal boron nitride, MoS₂, phosphorene [3,4,5]. Density functional theory (DFT) calculations have suggested a large number of 2D materials and their derivatives for device applications [6]. In order to narrow down the material and design selection space for time- and cost-heavy experimental device fabrication, atomic level DFT calculations need to be coupled with device-level physics models. Thus, starting from first principles DFT calculations, we propose a multiscale computational framework to extract important electronic parameters, such as effective mass, band gap, real and complex band dispersion, and phonon spectrum, which are then used to construct the material Hamiltonian. A self-consistent solution of the Schrodinger and the Poisson's equations through the non-equilibrium Green’s function approach [7] is then obtained to describe the complex, spatially heterogeneous intrinsic carrier transport and resulting device performance in both ballistic and dissipative regimes. Modeling studies on three devices: (i) monolayer germanane metal oxide semiconductor field effect transistors (MOSFETs), (ii) monolayer GeSe based tunneling field effect transistor (TFET), and (iii) phosphorene based MOSFET and TFET, will be presented and their design and performance limits will be evaluated to guide future material selection and device fabrication.

References:
[1] S. Das, R. Gulotty, A. V. Sumant, and A. Roelofs "All two-dimensional, flexible, transparent, and thinnest thin film transistor.", Nano Lett., vol. 14, no. 5, pp: 2861-2866, 2014.
[2] S. Thiele, W. Kinberger, R. Granzner, G. Fiori and F.Schwierz "The prospects of transition metal dichalcogenides for ultimately scaled CMOS." Solid State Electron., vol. 143, pp: 2-9, 2018.
[3] C. R. Dean, A. F. Young, I. Meric, C. Lee, L. Wang, S. Sorgenfrei, K. Watanabe, T. Taniguchi, P. Kim, K. L. Shepard and J. Hone "Boron nitride substrates for high-quality graphene electronics." Nat. Nanotechnol., vol. 5, no. 10, pp: 722-726, 2010.
[4] B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti and A. Kis "Single-layer MoS 2 transistors." Nat. Nanotechnol., vol. 6., no. 3, pp: 147-150, 2011.
[5] L. Li, Y. Yu, G. J. Ye, Q. Ge, X. Ou, H. Wu, D. Feng, X. H. Chen and Y. Zhang "Black phosphorus field-effect transistors." Nat. Nanotechnol., vol. 9, no. 5, pp: 372-377, 2014.
[6] N. Mounet, M. Gibertini, P. Schwaller, D. Campi, A. Merkys, A. Marrazzo, T. Sohier, I. E. Castelli, A. Cepellotti, G. Pizzi and N. Marzari "Two-dimensional materials from high-throughput computational exfoliation of experimentally known compounds." Nat. Nanotechnol., vol. 13, no. 3, pp: 246-252, 2018.
[7] S. Datta " Quantum transport: atom to transistor". Cambridge university press, 2005.

High mobility SiGe is promising for p channels in CMOS. Successful integration of SiGe into CMOS necessitate low defect SiGe/gate oxide interfaces for practical device operation. The existence of Ge on SiGe surface is problematic as it forms GeOx during gate oxide deposition and induces defects at the interface. Selective oxidation of Si is challenging especially during ALD deposition at elevated temperatures. In this study, a novel method to form low defect interface is demonstrated to deposit monolayers of Si on SiGe with plasma assisted ALD. In this method, HF cleaned SiGe wafer is subjected to 2 super cycles of SiCl₄(g) and Ar/H₂ downstream plasma at high temperature (350C). Hydrogen atoms from the Ar/H₂ plasma interact with SiClx(s) on the SiGe producing Si(s) and HCl(s). HCl desorbs from the surface at high temperature and is purged out. This leaves behind one monolayer of Si(S). This step is followed by N₂/H₂ downstream plasma to help passivate the interface. The downstream plasma operates at high pressure (> 1 torr) which ensures negligible ions flux thereby preventing ion induced defect formation. It is hypothesize that N₂/H₂ downstream plasma results in Si-N, Si-H, and N-H bond formation and SixNy prevents outdiffusion of Ge while Si-H and N-H forms a good nucleation layer for subsequent gate oxide ALD. Experiments with Al₂O₃, HfO₂ and ZrO₂ ALD gate oxide deposition after this Si monolayer deposition and N₂/H₂ downstream plasma passivation show up to 50% decrease in interface defect density; for example with approximate 5 nm ZrO₂ gate oxide deposition, the Dit = 1.0 x 10¹² eV^-1cm^-2 compared to samples with monolayer of Si (~ Dit = 1.9 x 10¹² eV^-1cm^-2) and compared to samples with just HF treatment (~Dit: 3.6 x 10¹² eV^-1cm^-2).

The interface of CoFeB with MgO that forms a Magnetic Tunnel Junction (MTJ) is a critical element of Perpendicular Magnetic Anisotropy (PMA) in STT-RAM devices. The TMR and RA product, which is a key figure of merit for these devices, is very sensitive to the quality of this interface. Intermixing and wettability of the CoFeB on MgO are two critical parameters that are of interest in evaluating this interface. In this work we report the fabrication of MTJ stacks and characterization of this interface. Ion Beam Sputtering (IBS), a very low rate deposition process in which one can control both energy and angle of deposition, is used to fabricate these MTJ structures. We probe intermixing by estimating the magnetic dead layer (MDL) of a stack using magnetic measurements and report a MDL of 0.2 nm after annealing the MTJ stacks at a temperature greater than 300 °C. We also report the impact of some key IBS process parameters on the value of MDL.

Amorphous oxide semiconductor thin-film transistors (TFTs) have achieved enough technological advances to be applied to mass-produced display products. However, the technological development of the oxide TFTs is limited to n-type, and only a few researches on p-type oxide TFTs have been reported due to the lack of p-type oxide materials and rigorous fabrication conditions. Furthermore, since p-type oxides have many localized states near the valence band maximum, it makes control of the amount of metal vacancy, which is the origin of the hole carrier, difficult.¹ Due to the above issues, researches on p-type oxide TFTs have become increasingly challenging. Nevertheless, researches on p-type oxide TFTs are essential due to a demand on all oxide semiconductor-based complementary metal oxide semiconductor (CMOS) logic circuits.
Herein, we propose a simple method to enhance the switching characteristic of the p-type copper oxide (CuO_x) TFTs via the oxidation effect of hypochlorous acid (HClO). HClO is a relatively inexpensive material to manufacture by reacting chlorine gas with water, and a useful oxidant because of generating oxygen radical (O*), one of the strong reactive oxygen species with heat or light conditions.² Because of this radical-generating property, HClO is widely used in the fields of sterilization, disinfection, and bleaching in industry. In this study, the HClO treatment was carried out to optimize the hole carrier concentration through the suppression of the copper vacancy (V_Cu) in the CuO_x thin film. Also, we investigated the effects of O* on the CuO_x thin film generated from HClO, and the variations of chemical composition were verified by chemical analysis. Through the robust oxidation by HClO, the amount of Cu-O bonds increased and the amount of V_Cu acting as the origin of hole carriers decreased within the CuO_x. In the modified CuO_x TFT, the superior switching characteristic was achieved with the subthreshold swing of 0.70 V/dec., the on/off current ratio of 4.86 x 10⁴, and the field-effect mobility of 2.83 x 10^-3 cm²/Vs, while pristine CuO_x TFT did not show switching characteristic.

[1] O. Porat and I. Riess, Solid State Ionics 81, 29-41 (1955).
[2] J. Fan, H. Mu, H. Zhu, J. Du, N. Jiang, J. Wang, and X. Peng, Industrial & Engineering Chemistry Research 54, 8842-8846 (2015).

Electronic devices made with alternating layers of undoped and doped chalcogenide materials, Ge₂Se₃/Ge₂Se₃-M (M = Sn, Al, Ti, W, Cr, Pb, Cu, C) exhibit transistor-like current-voltage (I-V) curves when illuminated. These devices, referred to as optically-gated transistors (OGTs), have two electrodes: a source and drain. Current is measured between the source and drain electrodes when the chalcogenide material (which acts as a ‘gate’) is illuminated. In this work, the effect of the metal dopant on the transistor characteristics are measured. The transistor materials are characterized using UV-Vis to explore the band gap and electronic structure. Raman spectroscopy is used to verify incorporation of M into the Ge₂Se₃ material. Photoconduction is investigated using electrical characterization as a function of wavelength, light intensity, and temperature. The devices were tested from 385 to 1260 nm and were operational over that entire range.
The metal dopant is shown to clearly influence the transistor optical responsivity, maximum current, threshold voltage, electrical switching speed, and optical band gap. A transistor fabricated with M = Al is demonstrated in three applications: as an access transistor to a memristor memory element for cross point array element isolation; as an optical amplifier; and in an optical wavelength converter circuit.

MoTe₂ is a promising two dimensional material due to phase transition and ambipolar transport with a band gap of 1.0 eV.^[1] But MoTe2 is sensitive to environment and easy to oxidize.^[2] Here, we demonstrated one-dimensional edge contact to MoTe₂ covered with h-BN passivation layer and etched by SF₆/O₂ plasma. The Schottky barrier height of edge contact is found to be 0.01-0.03 eV for various metals (titanium, chromium and palladium). Additionally, MoTe₂ edge contact with h-BN passivation shows good stability under ambient environment and oxygen plasma. But MoTe₂ without h-BN passivation layer is oxidized and changed to strong p-type. Based on the n-type characteristics from edge contact and p-type characteristics from oxidization, we were able to fabricate MoTe₂ p-n junction with a rectifying ratio of 10⁴.

[1] S. Cho, S. Kim, J. H. Kim, J. Zhao, J. Seok, D. H. Keum, J. Baik, D.-H. Choe, K. J. Chang, K. Suenaga, S. W. Kim, Y. H. Lee, H. Yang, Science (80-. ). 2015, 349, 625.
[2] B. Chen, H. Sahin, A. Suslu, L. Ding, M. I. Bertoni, F. M. Peeters, S. Tongay, ACS Nano 2015, 9, 5326.

This work was supported by the Global Frontier R&D Program (2013M3A6B1078873) at the Center for Hybrid Interface Materials (HIM), both funded by the Ministry of Science, ICT & Future Planning via the National Research Foundation of Korea (NRF).

Nonvolatile capacitance changes in metal-oxide-semiconductor (MOS) device with floating-gate structure by resistive switching through filament formation were investigated for the application to nonvolatile memory and programmable logic devices. In general, the electrical charging of the floating-gate located inside the gate oxide has been utilized to shift the threshold voltage for nonvolatile memory and programmable logic devices. However, the approach to use the threshold voltage shift by electrical charging has faced difficulties in further scaling due to undesirable cell-to-cell crosstalk. Instead of using the electrical charging of floating-gate, the device performance such as drain current, threshold voltage, and transconductance can be altered by changing the capacitance of gate oxide. In this study, we demonstrated the change of gate oxide capacitance in MOS device with floating-gate structure, i.e., an Ag-control-gate/CeO₂/Pt-floating-gate/HfO₂/n-Si substrate, where the formation of conducting filament in Ag-control-gate/CeO₂/Pt-floating-gate stack by voltage application increased the gate oxide capacitance as reducing the effective oxide thickness. For example, the accumulation capacitance corresponding to the serial capacitance of CeO₂ and HfO₂ was increased considerably from ~40 pF before applying positive programming voltage in Ag-control-gate to ~55 pF after applying the voltage while preserving the typical shape of capacitance-voltage curve. The increase of capacitance was induced by the voltage-driven migration of Ag ions through CeO₂ layer, leading to the formation of filament between Ag-control-gate and Pt-floating-gate and subsequent reduction of effective thickness of gate oxide. In contrast, the reference device with a structure of an Al-control-gate/CeO₂/Pt-floating-gate/HfO₂/n-Si did not exhibit the increase of capacitance because Al atoms did not migrate through CeO₂ layer. Rather, it showed little decreased capacitance as increasing voltage possibly due to the migration of oxygen ions from CeO₂ to Al-control-gate that reduced the relative permittivity of CeO₂. Since the gate oxide capacitance could be changed by programming voltage applied to control-gate, which subsequently changes the threshold voltage and drain current, it could be applied for nonvolatile memory and programmable logic devices without the use of electrical charging in floating-gate. These results demonstrated the novel scheme of memory and logic device operations through the change of gate oxide capacitance through resistive switching by filament formation in floating-gate MOS device structure.

In this work, self-directed channel (SDC) memristor devices [1] with a Sn-Ch layer (Ch = O, S, or Se) were fabricated and electrically characterized in order to determine the role of the chalcogen atom in the Sn-Ch layer on the memristor properties. The SDC device structure is a sandwich structure consisting of the following layers (from bottom to top electrode): W/Ge₄₀Se₆₀/Sn-Ch//Ge₄₀Se₆₀/Ag//Ge₄₀Se₆₀/W. The device is fabricated by depositing all layers via in-situ sputtering. The final W electrode layer effectively caps the device.

Current-voltage (I-V) curves of the devices were obtained. The I-V curves were analyzed to study the conduction mechanisms of each device type. This includes the analysis of Schottky emission, Space-charge limited Conduction [2], and Poole-Frenkel emission [3]. In addition, the first and second write threshold voltage of these devices are compared. The response of each device type to a sinusoidal input signal was also measured and used to classify the memristor type [4].
References:
[1] K.A. Campbell, Microelectronics J. 59, 10 (2017).
[2] H. Sun, Q. Liu, S. Long, H. Lv, W. Banerjee, and M. Liu, J. Appl. Phys. 116, 1 (2014).
[3] J. Frenkel, Phys. Rev. 54, 647 (1938).
[4] L. Chua, Semicond. Sci. Technol. 29, 104001 (2014),

Black phosphorus (BP), one of the allotropes of phosphorus, is a promising candidate for future nano-electronics and nano-photoelectronics. Unlike conventional two dimensional semiconducting materials which show n-type property and high electron mobility, BP shows p-type property and high hole mobility [1]. However, BP faces limitations in application to future electrical devices since BP is easily degraded in air atmosphere, and therefore studies to prevent BP from being oxidized in air atmosphere are required. Here, we suggested a via method for suppressing degradation of BP, which uses metal embedded hexagonal boron nitride (hBN) on BP. The fabricated devices showed good electrical properties because of the suppression of degradation of BP. The devices also showed low contact resistance since ultra clean surface between metal and BP was formed. Furthermore, through the applying force on contact between metal and BP by atomic force microscopy (AFM) probes, the performance of the devices were increased because contact between metal BP become better.

[1] Likai Li, Yijun Yu, Guo Jun Ye, Qingqin Ge, Xuedong Ou, Hua Wu, Donglai Feng, Xian Hui Chen, and Yuanbo Zhang, Black phosphorus field-effect transistors, Nature Nanotechnology, 9, 372-377, 2014

Acknowledgements
This work was supported by the Global Research Laboratory (GRL) Program (2016K1A1A2912707) and Global Frontier R&D Program (2013M3A6B1078873), both funded by the Ministry of Science, ICT&Future Planning via the National Research Foundation of Korea (NRF).

One of the most prominent features of the ferroelectric domain walls (DWs) is their electrical conductivity, which was observed in a number of ferroelectric materials, such as BiFeO₃, Pb(Zr,Ti)O₃, ErMnO₃. Here, we combine scanning transmission electron microscopy (STEM) and local probe techniques to investigate the conducting properties of the charged DW in the ion-sliced single-crystalline LiNbO₃ thin films with sub-µm thickness. STEM shows large inclination of the electrically-generated 180° DWs away from the polar z-axis (with inclination angles reaching 16°) suggesting that these DWs are strongly charged. Atomic column STEM imaging reveals the dipolar-kinked configuration of the Nb atoms along the inclined DWs. By using piezoresponse force microscopy (PFM) in combination with conductive atomic force microscopy (CAFM) performed both on z- and x-cut surfaces, it was shown that head-to-head DWs exhibit much higher conductivity than the tail-to-tail DWs, suggesting an electronic type of conductance. One of the most important findings is a possibility of DW conductivity modulation by an external voltage. It is demonstrated that the resistance of the LiNbO₃ thin film capacitors can be changed continuously by 5 to 9 orders of magnitude by controlling the DW perimeter allowing development of multi-level resistive switching devices. Resistance states can be altered by exposure to cumulative voltage pulses (resistance plasticity), suggesting that these domain wall memristors might be useful in the context of artificial synapses.

Energy issue is one of the most important things for us humankind. To reduce the energy waste and decrease the emission of greenhouse gases, people try to develop high energy efficiency units for power supply systems, for example, for EV and HEV. Therefore, we need an accurate and reliable model to help us develop and design the power devices. For this purpose, being one of the most promising materials for high power applications, 4H-SiC will be investigated in detail for improving performance of existing technology using in-house full-band Monte Carlo device simulator that is a subject of this work. The commercial TCAD tools are always based on effective mass approximation, however, most of the power electronic devices are operated under high electric field, so the non-parabolic band approximation cannot hold anymore. Hence, we need full-band analysis.

First ingredient in the process of building a device simulator is calculation of the band structure. In that respect, the empirical pseudopotential method (EPM) provides an effective way to get the band structure since we can adjust parameters to fit measurements (optical gaps). Here we refer to findings of G. Ng et al. to re-build the band structure. 205 eV cut-off energy was adopted; hence 527 plane waves were considered. The first Brillouin zone in reciprocal space of 4H-SiC is hexagonal. The full band structure of 4H-SiC is calculated, the indirect band gap is found to be 3.2464 eV and is between Γ point and M point. It is quite close to the commonly known value of 3.26 eV.

Next task in the sequence is calculation of the scattering rates for which a Density of States (DOS) function is needed. The most widely used method for DOS calculation was proposed by Gilat and Raubenheimer in 1966. They extended the original method in 1967 also to hexagonal close-packed crystals. The first step in the DOS calculation is to discretize the k-space into smaller volumes. We only consider the irreducible wedge, which is 1/24 of the first Brillouin zone, because of symmetry. The wedge can be discretized into rectangular meshes and smaller wedge meshes. If we assume that linear extrapolation works good in every mesh, then the intersections of constant energy surfaces inside meshes are replaced by parallel planes S(k_c,n) which are perpendicular to the gradient ▽_kE(k_c,n). If w is the distance of a particular energy plane from k_c inside a mesh, the range w determines the possible cross-section area S(w). λ_m are defined as λ_m=l_mα_m. We rearrange them in a decreasing sequence λ₁ ≥ λ₂ ≥ λ₃ ≥ 0. All possible S(w) for both rectangular meshes and smaller wedge meshes are found. After calculating all cross-section area and relating equations, we obtain the DOS function.

Once the DOS function is calculated, to analyze 4H-SiC devices, we have to consider acoustic, non-polar optical and polar optical phonon scattering. Thus, we create a scattering table using the information from the DOS. For the typical doping level in 4H-SiC device applications, the Brooks-Herring model is not valid. Hence, both electron-electron and electron-ion interactions are calculated. To save the runtime, we use the particle-particle-particle-mesh (P³M) method to get an efficient analysis procedure. The P³M divides the Coulomb force into two parts, the short-range force and long-range force (mesh force). We only need to consider the short-range forces for the carriers and ions close to the carrier we are tracing during each time step; the long-range force will be included via the solution of the 3D Poisson's solver.

We present at the conference simulation results of a N⁺-n-N⁺ resistor from where we extract the results for the low-field electron mobility dependence upon Coulomb scattering in 4H-SiC devices, and the high-field electrons behavior where band structure effects are important.

Electrochemical metallization (ECM) memories have the potential to replace today's technology, enabling novel memory and computing architectures circumventing the von Neumann bottleneck. Typically, the operation of ECM cell is based on the electrochemical redox reactions of the cation supplying active electrode. However, the possibility of utilizing new materials for the active electrode remains largely undiscussed. In addition, the ECM cell kinetics are strongly determined by the electrolyte, which can hardly be altered after the cell has been fabricated. Therefore, it is necessary to investigate the influence of the electrode and electrolyte on the ECM cell kinetics. In this work, we engineers the anion supplying active electrode and tunable electrolyte into the electrochemical metallization cell. First, to investigate the electrode dependent switching characteristics of the ECM cells, we fabricates the ECM cell with Te active electrode. It is found that the SET operation of the device occurs under negative voltage on the active electrode. This behavior is opposite to that of the device with Ag electrode, indicating that Te supplies anions by the ECM mechanism. Different modes of switching between the two types of cells, namely, unipolar switching for Pt/GeS/Te cell and bipolar switching for Pt/Ge2Sb2Te5(GST)/Te cell are observed. These phenomena can be attributed to the rupture of the filament by Joule heating for the former and by ECM for the latter in the RESET process. Next, we fabricate the ECM cell with solid phase tunable GST electrolyte to investigate the electrolyte dependent switching characteristics of the ECM cells. The resistive switching characteristics of the cells with different GST phases are examined. The magnitude of the high resistance, the SET voltage and the on/off ratio are found to be considerably affected by the solid phase of GST, whereas the magnitude of the low resistance is least affected. Moreover, a transition from volatile to nonvolatile SET switching is only observed for crystalline GST based cell under prolonged voltage sweep, but not for amorphous GST based cell. This work provides a springboard for more studies on the manipulation of the ECM cell kinetics by tunable electrode/electrolyte and the resulting unprecedented device functionalities.

Non-volatile memristor crossbar arrays have great potential in brain inspired computing and next generation high-density memories. Diffusive devices with volatile threshold switching (TS) behavior, which are based on the phenomenon of spontaneous rupture of filaments in dielectrics, are of importance in selector applications to suppress the sneak current issue of memristor arrays. Besides, their rich synaptic dynamical behaviors can also enable novel designs in neuromorphic computing to extend the circuits based on the complementary metal-oxide-semiconductor. In this work, we have realized reproducible bidirectional and multilevel TS behavior on Ag-dielectrics diffusive devices. The ON/OFF ratio and the OFF current of the device TS behavior are ~ 10⁷ and ~ 10^-12 A, respectively, which are suitable for selector applications. And we also realize stochastic and multilevel TS by optimizing the device structures. For neuromorphic applications, we integrate the stochastic TS into the stochastic learning process of deep neural networks, and demonstrate the multilevel TS into short-term and long-term plasticity for electronic synapses. Simulations of nanoparticles diffusion are also carried out to study the mechanism of this bidirectional and multilevel TS process. The simulations show that these phenomena are mainly caused by the diffusion and redistribution of Ag nanoparticles. This work illustrates that Ag-dielectrics diffusive devices are promising candidates for neuromorphic computing applications.

Substantial increase of output current, and I_on / I_off ratio, for sub-7nm low power CMOS transistors can be accomplished using a novel optoelectronic technology, which is 100% compatible to existing CMOS process flow. For RF or mixed signal ASICs, adding photonic components may improve the cut-off frequency, and reduce series resistance. Products that utilize power regulating devices, such as power MOSFETs, will benefit from the optoelectronic configuration to achieve much lower R_dson and high avalabche breakdown voltage at the same time. For semiconductor memories, including DRAM or FLASH, the photonic technique may reduce the ERASE / WRITE / access time and improve the reliability.

Photon generating and sensing devices can be integrated in the drain region of a MOSFET, FINFET or power MOSFET as one transistor. The laser diode is turned on only when the MOSFET is switched to on. The laser is off when the MOSFET is switched off. When both laser and MOSFET are on, light is absorbed by the APD (Avalanche Photo Diode), which is fabricated in the drain / well regions of the MOSFET, and generates avalanche breakdown currents as part of the output drain current. In this paper we will discuss how to implement this optoelectronic technique for low power, high speed sub-7nm CMOS, memories (DRAM, SRAM, FLASH), and high power MOSFETs.

Sub-7nm CMOS Transistors. Process integration of a laser in the drain region of a MOSFET or FINFET may be simplified. Cross section of an optoelectronic MOSFET shows device configuration, where part of the drain is etched and redeposited with lasing films. An equivalent circuit of the device provide step-by-step detailed operatons. Please notice that if the substrate is silicon, the lasing films (direct band gap materils) can be deposited selectively on silicon through low temperature epitaxy. If the substrate is GaAs, or other compound semiconductors, a thin silicon film may be deposited on the compound substrate. MOSFET is build in the top thin silicon film, and laser is formed on the compound substrate after selective etching of silicon.

Similar integration techniques can be applied to FINFETs, with low temperature selective epitaxy of lasing semiconductor films in the drain area of a FINFET. The fin can be silicon or GaAs. If the fin is GaAs, a thin silicon epi layer needs to be deposited on GaAs, then selectively removed right before the lasing films are deposited.

In order to further simply the process integration, it is feasible to integrate the laser in the contact 1 or via between metal 1 and silicide.

Improvement of MOSFET output current depends on laser external quantum efficiency and the APD absorption rate. To achieve optimized CMOS drive current, high laser quantum efficiency and APD absorption rate are needed.

Power MOSFETs. Cross section of a discrete vertical power MOSFET illustrates how a laser diode is integrated. For this type of devices, the drain is located in the back side of the chip. Source is on the top of the chip. Deposition of compound lasing semiconductor films in the back side of the chip creates a laser. When a high voltage is applied to the drain, a large depletion region is formed along the drain junction in order to sustain a high breakdown voltage. High-intensity light is produced from the laser in the backside, and absorbed in the depletion region to produce light current, which reduces R_dson.

Nonvolatile Memories: SRAM, DRAM, FLASH, SONOS, EEPROM – Light Assisted Very High Speed Operations. An optoelectronic Flash memory is a SONOS memory (NOR Flash) with a laser integrated in the drain area. For the Write operation, typically with hot carrier injection, a gate voltage is applied to turn on the word line transistor, and a drain voltage is applied to turn on the laser – light is produced and absorbed in the depletion regions in the channel and drain. Hot carrier injection is enhanced by the light current, and the Write operation is much faster.

This paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and CMOS-based magnetic devices. Random access is accomplished with the magnetic fields generated from ring-gate MOSFETs. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

A fast non-volatile dynamic random access memory is different from NAND Flash, for which random access is not possible, and NOR Flash, which is relatively slow and high operation voltages are required. Traditional MRAM (Magnetic Random-Access Memory) uses the material properties of magnetic films, which might not be reliable after many operational cycles. A magnetic nonvolatile DRAM (MNV-DRAM) consists of a main gate on top of a silicon substrate with implanted source and drain regions, a floating phonon gate above the main gate, and a control gate above the phonon gate. In between the gates there are vacuum gaps of a few Å. The floating phonon gate consists of polarized ferromagnetic thin films. The control gate is made of a conducting layer on top of a ferromagnetic thin film. The main gate is made of a ferromagnetic thin film on top of a conducting layer. The ferromagnetic films in the phonon gate are implanted with positive or negative charges. As the result, there is an electro-magnetic field with dual quantum wells in between the control and main gates from atomic forces, where the floating phonon gate switches from one quantum well to the other with very high frequency. The layout design of the 3 gates may be rectangular, or circular (3 loops on top of each other), in order to achieve random access with magnetic fields from the currents in the loops. Due to the currents flowing in the loops, magnetic fields from each loop couple with each other, forming two magnetic dipoles. Motions of the loops depend on the polarity of the dipoles. When currents flow in the same direction, there is an attracting force between the two loops. If currents flow in opposite directions, there is a repelling force. The channel length of the ring gate MOSFET is approximately the length of the ring, as described by a cross section (cut along the ring). If the device is cut across the ring, this shows the width of the MOSFET.

Conclusion: A novel atomic force magnetic nonvolatile memory is presented in this paper. Nonvolatile functions are achieved by high frequency phonons and quantum wells. Random access is accomplished with coupling of magnetic dipoles. This type of memory requires very low voltages for Write / Erase / Read operations and no Refresh is necessary. The speed is much higher than traditional FLASH memories. Manufacturing of the memory is low cost, without exotic materials, and compatible to deep nanometers CMOS technology. Access time vs. current and memory device dimensions are presented in this paper.

AlGaN/GaN heterojunction FETs (HFETs) possess unique properties such as a wide band-gap, high drift velocity and high critical electric field which make them uniquely suitable for high voltage power devices. Unique properties of Gallium nitride (GaN) such as a wide band gap significantly reduces band to band tunneling making it suitable for sub-10 nm transistors. Ballistic transport is also possible in GaN devices because of the high optical phonon energy. Presence of a 2DEG at the AlGaN/GaN hetero-interface contributes to a high sheet charge density, and subsequently high mobility. However, this very presence of polarization-induced charge density leads to poor turn-off characteristics. In the past decade, 3D FETs, such as FinFETs and Gate-all-around (GAA) FETs, have been developed as viable alternatives to traditional planar transistors. Recent works demonstrate such an approach to AlGaN/GaN HFETs as well. Introduction of non-planarity such as a fin has shown to improve off-state characteristics and push the threshold voltage into the positive. Previous works have shown experimentally the dependence of threshold voltage and the electron density on the width of the nanowire channel. The focus of this work is to develop a generic 2D Schrödinger-3D Poisson solver for GaN Nanowire FETs. A 3D Poisson solver coupled with a 2D Schrödinger solver allows us to accurately map the charge density in the channel. The solver can also help us model the dependence of electron density in 2DEG and sidewalls on geometry of the nanowire channel. The electron wavefunctions generated by the solver is used to compute overlap integrals in the Ensemble Monte Carlo (EMC) algorithm. Three scattering mechanisms: acoustic phonon scattering, polar optical phonon scattering, and piezoelectric scattering are considered to account for the electron phonon interactions in the system. The EMC solver is then used to determine the low field electron mobility and drift velocity in the channel.

Resistive random access memory (RRAM) has been extensively investigated due to its great potential in synaptic and neuromorphic computing applications. In the crossbar array of RRAM architecture, threshold switching selector devices are one of the crucial components to cut off the sneak current path of the unselected cells. This work reported the first observation of threshold and resistive switching behaviors in epitaxially regrown vertical GaN p-n diodes by MOCVD. They showed excellent thermal reliability up to 300 °C, which is a significant improvement over traditional oxide-based devices. The device can be integrated with mature III-nitride high electron mobility transistors (HEMTs) technology and facilitate the development of GaN-based integrated circuits, especially for harsh environments.

The epilayers were grown homoepitaxially on bulk n⁺-GaN substrates by MOCVD. The device structure consists of a 0.5 µm n⁺-GaN buffer layer, a 7 µm unintentionally doped (UID) GaN drift layer, 1 µm n⁺-GaN contact layer, 0.3 µm regrown UID-GaN and 1 µm regrown p-GaN after the etching of 1.5-µm-deep trenches in the UID-GaN drift layer and n⁺-GaN contact layer. The regrown layers on top of the n⁺-GaN contact layer were removed to form the top n-contact. The top p-contact was formed on the regrown p-GaN, and the bottom n-contact was on the backside of the substrate. The forming process was completed by the soft breakdown of either lateral p-n diode between the top n- and p-contact or the vertical p-n diode between the top p-contact and bottom n-contact. After the forming process, we observed the threshold switching process in the vertical diodes with a high resistance state (HRS) and a low resistance state (LRS). Reliability study showed that the devices can operate stably up to 1000 cycles at both room temperature and 300 °C, indicating the excellent thermal stability of the threshold switching behaviors.

The I-V characteristics of the devices was analyzed in log-log scale to explain the operation mechanism. At the LRS, the I-V curve was similar to that of a conventional p-n diode. At the HRS, there are two regions, which follow the trap-assisted space charge limited current (SCLC) theory. At low voltage region, it is dominated by the ohmic law where I V; at high voltage region, it is dominated by the Child’s square law with defects where I V^2.3. As shown by the TEM study, the regrowth interface was highly disordered with defects. We hypothesized that after the soft breakdown, the regrowth interface layer may behave like a thin insulating layer with trap states which leads to the HRS. It’s reported that these traps can form/rupture a conductive path by trapping/detrapping carriers. From 0 V to the set voltage, the traps at the interface will be filled with carriers to form a conductive path, resulting in the transition from HRS to LRS. carriers. From the reset voltage to 0 V, the traps will be depleted of carriers to cut off the conductive path, and the devices change from LRS to HRS. We also observed an increase in set voltage with increasing temperature, which can be explained by the enhanced detrapping effect at high temperatures. Furthermore, the memory behavior can also be observed if the voltage is large than the turn-on voltage of the p-n diode. This is analogous to a diode and a RRAM cell connected in series.

In summary, we demonstrated threshold switching and memory behaviors in epitaxially regrown GaN vertical p-n diodes. This physical mechanism was attributed to the forming/rupturing of the conductive path formed by traps through trapping/detrapping carriers at the regrowth interface. The device showed excellent reliability up to 1000 cycles and thermal stability up to 300 °C. In addition, memory behaviors can be observed when the reset voltage was higher than the turn-on voltage. These results open up opportunities for the development of GaN-based memory devices and integrated circuits.

Conventionally, resistive RAM memory is manufactured in a cross-point architecture. A cross-point at which a memory cell is located, is an intersection of vertical and lateral metal lines for the active and inert electrodes of the resistive memory cell. Here, we investigate the thermally induced degradation of Cu/TaO_x/Pt/Ti ReRAM devices. When one cell is repeatedly switched on and off, a certain amount of heat is being deposited in the cell. The local temperature to rupture a Cu filament has been estimated to be 600-800^oC. The lingering heat affects not only the device itself, but the heat dissipated along the electrode metal lines causes performance degradation of the neighboring cells. To monitor the cell degradation we choose specific set condition to form a marginal, i.e. weak, highly resistive Cu filament by imposing low I_cc of 10μA and ramp rate rr=1.2V/s, while the reset is performed at low rr=0.1V/s with no I_cc imposed in order to maximize the Joules heating. Such a fragile Cu filament acts as a canary in the coal mine with respect to ambient heat. The heat deposited in a stressed device leads to a limited number of switching cycles, usually 11-14. When the device is preheated, the maximum number of cycles may decrease to zero and thus serves as a measure for performance degradation of the neighboring cell. Within 3-4 minutes, after reaching maximal cycles for a given device, we test the switching behavior of the neighboring cells, one at a time. We find that only the cells that share either metal line of the heated device, suffer performance degradation. Direct neighbors (like a cell at the intersection of the adjacent Cu and Pt line) to the heated cell thus not sharing any the electrode of the heated device, are not affected at all by the heat, provided that the intermediate cells are in off-state. However, when the intermediate cells are programmed to the on-state and provide thus a direct heat conduction path to the heated device via copper line, Cu filament of the intermediate cell, and the Pt line, the diagonal neighbors suffers performance degradation. We find that the neighbors along the common Cu electrode line are affected more than the neighboring cells along the Pt electrode line. The heat transport along the Cu layer line is more effective and reaches further neighbors than for Pt line. Although the heat conductivity of Cu is roughly 5 higher than of Pt and the Cu metal line is 150 nm while the Pt line is 50 nm thick, we found this result surprising because it challenges the conventional assumption that the shape of the Cu filament is that of a sharply tipped cone with a broad base forming an interface with the Pt line and the tip of the cone touching the Cu line. This shape would imply very small contact of the filament with Cu and large contact with Pt, favoring heat transfer to the Pt line rather than to the Cu line. The observed more efficient heat transfer from the filament to Cu than to Pt line implies that the shape of the Cu filament appears to be more likely that of hour glass rather than a cone. When the tested neighboring cells are allowed to cool off for sufficiently long time (20 min or more) they return to the original performance levels of 11-14 cycles. We find also that the minimum cooling off period is shorter for cells disposed along the Cu lines rather than along the Pt lines.
The width of Cu and Pt lines in our arrays varies between 5 μm and 35 μm and the distance between the lines is ca 150 μm. We find more pronounced degradation of the neighboring cells along the Pt lines, for 35 μm wide Pt lines than for 5 μm wide Pt lines, indicating that metal lines with smaller cross-section are less effective in heat dissipation to the surroundings. In commercial arrays, the thickness, width, and line pitch of the electrode metal lines are of the order of couple 10s of nm. We therefore expect much more pronounced heating effects and over a longer time period in commercial memory arrays.

In this work, we demonstrate single-gate feedback field-effect transistors (FBFETs) consisting of p⁺-n⁺-i-n⁺ silicon nanowires (SiNWs). SiNWs were derived from a bulk-Si wafer including ion implantation and crystallographic wet etching processes, and the SiNWs were then transferred onto a plastic substrate. The SiNWs had a diameter of 100 nm. BF₂⁺ and As⁺ ions were implanted for the formation of p⁺ and n⁺ regions in the p⁺-n⁺-i-n⁺ SiNWs, respectively. The aluminum electrodes were formed on top of the SiNW in p⁺-drain and n⁺-source regions. The i-regions of the channels were covered with Al₂O₃ high-κ dielectric layers. Tungsten top-gate electrodes with widths of 2 μm were also formed via photolithography and thermal evaporation processes. The SiNW FBFET exhibits good switching characteristics in terms of an on/off current ratio, a subthreshold swing, and gate-induced drain leakage (GIDL) current. Specifically, the GIDL can be effectively suppressed because the p⁺ potential barrier in p⁺-n⁺-i-n⁺ silicon nanowires can block the injection of tunneling electrons, unlike the conventional metal oxide semiconductor FETs (MOSFETs).

Conducting-bridge resistive random access memory (CBRAM) is attracting attention thanks to its advantages such as low power consumption and high applicability to multi-bit data storage. However, CBRAM has issues to be solved, ex., large deviation of switching voltage and resistance, for putting it into practical use. Above all, semiconductor technology is facing a miniaturization limit that prevents the density of memory devices higher. Metal organic frameworks inherently have periodically and densely aligned subnano-scale pores due to self assembled phenomena. We propose replacing a metal oxide film in a CBRAM cell that works as a memory layer with MOF. This is because we expect that the subnano-scale pores of MOF enhance ionic diffusion and the directionality of the diffusion along the pores, leading to superior performance including the improvement of the deviations of a switching voltage and resistance. In this paper, to introduce MOF into actual CBRAM devices, we established a method to grow a single MOF crystal selectively at a via. We also show resistive switching behavior observed in the MOF-CBRAM.
SiO₂ was deposited on a Cu(50nm)/Pt(20nm)/TiN(20nm)/SiO₂/Si substrate, followed by the formation of vias with the diameter of 100 nm, through which the surface of the Cu layer was exposed to the solution, using electron beam lithography. 1,3,5-Benzenetricarboxylic acid (BTC) of 1.8 g was dissolved into the mixed solution of ethanol of 15 ml and dimethylformamide (DMF) of 15 ml. The processed substrate was soaked into the solution to synthesize HKUST-1 [1] that is one of most popular MOF due to its high stability in the atmosphere. Finally, we fabricated top electrodes of Au(20nm)/Ti(20nm), filling the vias, by EB evaporation. Electric characteristics were measured using a semiconductor parameter analyzer (B1500A, Keysight).
In our proposed method, HKUST-1 synthesis advances by dissolving Cu from the Cu layer of the processed substrate into the solution through the vias. Since no Cu is contained in the synthesis solution, HKUST-1 can be synthesized only at the via region, at which Cu ions and BTCs encounter. To keep the concentration of dissolved Cu around the via high, another substrate was placed facing the processed substrate through thin glass sheets that works as a spacer. In fact, we confirmed by SEM that a single HKUST-1 crystal was selectively synthesized at the via region. As for electric characteristics, our MOF-CBRAM showed relatively low resistance in an initial state. This may be attributed to the presence of residual Cu ions that were not incorporated into the crystal and were left in the pores. Accordingly, electrical preparation process similar to reset, which is resistive switching from a low to high resistance state, is necessary for the development of resistive switching phenomena. After the preparation process, bi-polar resistive switching, which means that bias voltages with different bias polarities are necessary to cause set and reset switching, respectively, was confirmed. Therefore, resistive switching phenomena in a single MOF crystal was achieved as a microfabricated electric device, for the first time.
In conclusion, we newly developed a method that enables a selective synthesis of MOF crystal accurately at desired points. Combining this method with conventional microfabrication technic that is familiar with silicon process, micro CBRAM cells containing a single MOF crystal each as a memory layer could be fabricated successfully. In addition, our result strongly indicates MOF crystal can be introduced widely into CMOS process.
[1] A. S. Münch and F. O. R. L. Mertens, J. Mater. Chem. 22, 10228 (2012).

What physical quantities determine behavior of multistable electronic devices and circuits, especially when multiple stable configurations exhibit identical current, voltage, power input and heat output? This question has been discussed in different forms over several decades. For instance, in 1963 Ridley postulated that under certain bias conditions circuit elements exhibiting a current- or voltage-controlled negative differential resistance will separate into coexisting domains with different current densities or electric fields, respectively. Landauer then postulated that all circuit theorems are in essence heat-generation theorems. These debates were never resolved because of the lack of analytical and experimental techniques to resolve the underlying issues. These issues now assume vast importance especialy with the tapering down of Moore's law and the concurrent interest in nonlinear electronic devices such as memristors.
We address these issues by using thermal and chemical spectro-microscopy to directly imaged signatures of current-density and electric-field domains in several metal oxides. The local activity theorem successfully predicts initiation and occurrence of spontaneous electronic decomposition, accompanied by a reduction in internal energy, despite identical power input and heat output. This is a process similar to spinodal decomposition of a homogeneous liquid or disproportionation of a metastable chemical compound. This result reveals a thermodynamic constraint required to properly model all nonlinear circuit elements. Our results explain the electroforming process that initiates information storage via resistance switching in metal oxides and has significant implications for improving neuromorphic computing based on nonlinear dynamical devices.
Reference: Kumar and Williams, Nature Communications, 9, 2030 (2018)

HfO₂-based resistance switching random access memory (RRAM) with 1 transistor-1 resistor (1T1R) architecture represents a strong candidate for future non-volatile memories to compete with NAND Flash as well as for the wireless sensor networks and neuromorphic computation applications.[1] HfO₂-RRAM possess various advantages including the compatibility with complementary metal oxide semiconductor (CMOS) processing, fast and low power switching and excellent scaling capability [2-6] etc. The resistive switching (RS) in HfO₂ RRAM is widely accepted to be related to nanometer-sized conductive filaments (CFs) in the metal-insulator-metal structure and the electrode/HfO₂ interface is also considered as a significant factor to severely impact RS. With the continuous scaling of RRAM devices, in-depth understanding of material issues including the interface, the filament nature and other factors like carbon contamination, become more and more important to further improve the device performances. It will also be highly valuable to directly study integrated cells and arrays in a statistic way to unambiguously clarify material effects on scaled device performances. Moreover, it is urgent to identify solutions to confine the nanoscale filament in order to possibly further increase the device reliability.

In this report, we will show our recent progress in understanding the materials insights and in improving the device performance of HfO₂ based RRAM devices. We will demonstrate firstly a detailed study on TiN/Ti/HfO₂/TiN/Si 1T1R RRAM (single devices and 4kbit arrays processed in a standard 0.25 μm CMOS process line) with the combination of statistic electrical measurements in pulse mode and a systematic materials characterization to correlate key material factors (nano-crystallites and carbon impurities) with the filament type RS behaviour. It is found that, while the crystallites and grain boundaries could influence the forming/set/reset voltage, carbon residues play a key role to determine the RS property particularly the programming characteristics. Subsequently, by using synchrotron radiation based bulk sensitive synchrotron photoemission spectroscopy (HAXPES), we report an operando diagnostic detection of the oxygen “breathing” behavior at the oxide/metal interface, namely, oxygen migration between HfO₂ and TiN during different RS periods. This highlight the significance of oxide/metal interfaces in RRAM, even in filament type devices. Finally, we developed a RRAM device with geometric confinement of the oxygen vacancy distribution and nanofilament location. The nanotip based devices show good RS properties including forming-free, stable endurance and retention. This demonstrates a route to CMOS compatible devices and an effective way to control cycle-to-cycle resistance switching in RRAM technology.
Our progress in understanding the materials issues and RS mechanism, as well as the development of filament confinement solutions, will certainly facilitate the possible regulation of RS modes and thus the further optimization of RRAM device performances.

[1] K.Zhang, Embedded Memories for Nano-Scale VLSIs (2009, Springer).
[2] R.Waser, Nanoelectronics and Information Technology 3rd edn, 692 (2012, Wiley-VCH).
[3] G.Niu et al. Sci. Rep. 6 (2016) 25757.
[4] G.Niu et al. Sci. Rep. 6 (2016) 28155.
[5] G.Niu et al. J.Phys. Chem. C, 121 (2017),7005–7014.
[6] G.Niu et al. Nanotechnology, 28(2017),215702.

As the physical limitations of Si material are faced, the performance improvement of charge storage memories enabled by conventional scaling rules is noticeably slowing. In the meantime, emerging memories that are theoretically advantageous for device scaling based on resistance changes in oxides and chalcogenides driven by spin orientation, phase change, and atomic filament formation have begun to be implemented for a storage class memory, which is a newly introduced technology in the traditional memory hierarchy. Particularly, by employing a cross-point architecture, the memory is sandwiched by perpendicularly located word line and bit line. This passive array allows the highest memory density at the smallest cell size, but is inherently affected by unwanted sneak-path currents generated from adjacent cells, causing read errors. Therefore, a two-terminal threshold selector (TS) that can prevent the sneak-path current below a threshold voltage (V_th) and provide a sufficient current instantly above the V_th is required for each memory (1TS-1R) in the cross-point array.
From a material perspective, the TS can be realized using certain transition-metal oxides such as VO₂ and NbO₂. Applying electrical stimulus accompanied by heat drives an insulating crystal structure of the material to be converted to another metallic crystal structure. However, a small on/off ratio of about 10² is achieved by this structural phase transition mechanism, which is insufficient to prevent the sneak-path current. Instead, the combination of Cu or Ag electrode and oxide allows a large on/off ratio of greater than 10¹⁰ due to the formation of metallic Cu or Ag filament across the oxide, which can be rapidly dissolved with removing bias. However, improvements of reliability and uniformity relevant to the repeatedly formed and ruptured filament remain a primary concern. For these reasons, ovonic threshold switches (OTS) in chalcogenides, which are believed to be related with intrinsic properties of chemical bonding in chalcogen atoms such as Se or Te, have recently gained considerable attention. Based on the understanding of the role of each element in multicomponent chalcogenides, excellent switching and reliability characteristics of the OTS have been demonstrated. Therefore, we aim to present design guidelines of the OTS that vary depending on the memory technology to be used through array level analysis performed in SPICE simulations.
Specifically, when a magnetic RAM (MRAM) generally exhibiting a set voltage (V_set) of about 0.5 V is used with the OTS, the V_th of the OTS less than 0.5 V should be used to achieve a reasonable read voltage (V_read) margin between V_th and V_set for reading a memory window. However, most of the OTSs showed non-linear current-voltage (I-V) relation in a sub-threshold regime due to trap-related conduction mechanisms. Thus, as the V_th is appropriately adjusted to the smaller value, an off-current in the sub-threshold regime directly relevant to the sneak-path current is inversely increased. We therefore examine how the parameters of the OTS affect the maximum allowable array size.
Meanwhile, since a resistive switching memory (RRAM) or phase change memory (PCM) has usually the V_set greater than 1 V, the V_read is boosted in the 1TS-1R. The memory showing robust endurance under a small V_read of 0.1 V may be disturbed by the boosted V_read. Thus, instead of the conventional read operation, a recently proposed sub-threshold read operation enabled by the OTS having V_th much greater than the V_set of 1 V and strong I-V non-linearity in the sub-threshold regime is alternatively taken into account. Here, it is an important to read the memory window at the voltage where the OTS has not yet been turned on in the 1TS-1R, which helps minimize the disturbance. By analyzing how large scale cross-point array can be built, we show a particular circumstance, where the sub-threshold read operation is favorable.

In today’s data-centric world, where some of the most useful computing tasks are to extract meaningful information from massive amount of unstructured data, neuromorphic computing can provide low-energy high throughput computing. The challenge in data-centric computing with the conventional computing architecture lies in the energy and latency bottleneck of off-chip memory access (i.e. “memory wall”) which do not scale down with the scaling of the technology node.
Deep neural network (DNN) is a class of artificial neural networks (ANNs) that benefits from both the availability of big data (large amount of multi-media data for model training) and the continual performance improvement of semiconductor technologies in the past decade. However, the memory hiararchy of today’s computing architectures is not specifically designed to leverage the predictable dataflow and potential data reuse of DNN processing, resulting in longer latency and insufficient energy-efficiency for memory access. To reduce these expensive memory access, hardware accelerators for DNNs are designed to employ more fine-grained local memory hiararchy and more specialized dataflow design, which improves the energy efficiency and throughput while maintaining DNN’s inference accuracy. However, the "memory bottleneck" in modern DNNs may not be fully addressed by the acceleration architectures alone. Emerging memory technologies have the potential to play an important and unique role. As these technologies can potentially offer up to tera-bytes of on-chip data storage with a wide range of energy-delay optimization opportunities, they may complement SRAM and DRAM for more efficient DNN inference acceleration. A possible application of the emerging non-volatile memory (NVM) devices is to serve as in-memory computing element where multi-level resistance response of an NVM can store the analog synaptic weights of a DNN on-chip. In another in-memory computing scheme, a crossbar array of non-volatile memory devices can perform the multiply-and-accumulate (MAC) operation at a lower energy cost when the input vector is encoded as an analog voltage and the weight matrix is encoded as analog resistance (conductance) values stored in the memory devices. The ability of the NVMs like RRAM, PCM, CBRAM to change its resistance values gradually as a function of the applied voltage pulse across its electrode is the key to performing analog in-memory MAC operation.
This paper provides an overview of the current state-of-the-art non-volatile memory devices used for neuromorphic hardwares in applications ranging from biology based learning models to conventional machine learning algorithms solved using neural networks. Furthermore, a more focused overview of the device-level trade-offs required for hardware acceleration of neural network architectures using analog in-memory MAC operation is presented. In general, larger conductance range, more intermediate states, and higher resistance are desirable for both inference and traning. For inference, an ideal device should also have linear I-V relationship and long retention time. For training, symmetric and linear pulse response, small device-to-device and cycle-to-cyle variation, and good endurance are crucial.
Our review reveals that controlling the oxygen ion movement during pulsed switching in RRAM can be a promising way to achieve the aforementioned performance goals. Placing an oxygen ion barrier to make a bilayer RRAM and confinement of the generated heat during switching have shown significant improvement in analog switching. Better thermal management in RRAM can also provide filament stability that could improve reliability like retention and endurance. If the ideal device can be achieved, the MAC array using NVMs can provide ultra-low energy, high throughput computing without compromising bit precision that is currently missing in the neural network accelerator landscape.

The conventional computing systems based on the von Neumann architecture have reached limits in terms of computational time and power dissipation due to increasing computational complexity.¹ To circumvent these issues, new computational architectures are explored, among which neuromorphic computing based on emulating the human brain stands out. It is known that the human brain supercedes a supercomputer by 6-9 orders of magnitude in power dissipation. The superior features of the brain, such as ultra-high density, low-energy consumption, parallelism, robustness, plasticity, and fault-tolerant operation need to be emulated by computing systems for perception and learning.¹ These qualities are enabled by the brain’s synapses which form a highly complex and efficient interconnection between neurons in the brain. Therefore, a nano-electronic device which emulates the synaptic properties is a crucial building block for brain-inspired computational systems.
It is observed that the programming current in a memristor is decreased by using 2D materials^2-3 as the switching medium, and by using graphene electrode instead of conventional metals.^4,5 However, these ultra-low power memristors are realized by exfoliated 2D materials which makes large-scale production implausible.^2-3 In this work, we use MoS₂ as the switching medium to fabricate a memristive synapse. MoS₂ is grown on monolayer graphene forming a vertical heterojunction by the sulfurization of Mo film. Graphene (Gr) is used as the bottom electrode while Ni/Au contact on MoS₂ is the top electrode.
The MoS₂/Gr memristors exhibit forming-free non-volatile switching behaviour with a low programming current of 1 nA. In addition, these devices exhibit sub-nW reset power and low energy consumption of ~2 pJ/spiking event which makes them highly energy-efficient. Synaptic characteristics such as multiple conductance states between 1 nA and 1 μA with a minimum reset current of 16 pA is also observed. Furthermore, the MoS₂/Gr memristors exhibit excellent data retention characteristic of 10⁴ s at multiple conductance states viz., 1 nA and 1 μA. Also, MoS₂/Gr memristors exhibit biological synaptic characteristics like plasticity, multi-state conductance tuning, short and long-term potentiation, long term depression and spike timing dependent plasticity rule. Additionally, sustained switching at 1 nA and 100 nA programming currents is observed in these devices for 100 DC cycles indicating their robustness. Filamentary switching with low programming reset power observed in these devices unravel the prospects of developing nano-scale crossbar arrays of energy-efficient synaptic devices for neuromorphic applications.

1. Kuzum, D.; Jeyasingh, R. G.; Lee, B.; Wong, H.-S. P., Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing. Nano Lett. 2011, 12 (5), 2179-2186.
2. Tian, H.; Zhao, L.; Wang, X.; Yeh, Y.-W.; Yao, N.; Rand, B. P.; Ren, T.-L., Extremely Low Operating Current Resistive Memory Based on Exfoliated 2D Perovskite Single Crystals for Neuromorphic Computing. ACS Nano 2017, 11 (12), 12247-12256.
3. Zhao, H.; Dong, Z.; Tian, H.; DiMarzi, D.; Han, M. G.; Zhang, L.; Yan, X.; Liu, F.; Shen, L.; Han, S. J., Atomically Thin Femtojoule Memristive Device. Adv. Mater. 2017, 29 (47).
4. Tian, H.; Chen, H.-Y.; Gao, B.; Yu, S.; Liang, J.; Yang, Y.; Xie, D.; Kang, J.; Ren, T.-L.; Zhang, Y., Monitoring oxygen movement by Raman spectroscopy of resistive random access memory with a graphene-inserted electrode. Nano Lett. 2013, 13 (2), 651-657.
5. Chakrabarti, B.; Roy, T.; Vogel, E. M., Nonlinear Switching With Ultralow Reset Power in Graphene-Insulator-Graphene Forming-Free Resistive Memories. IEEE Electron Device Letters 2014, 35 (7), 750-752.

Ferroelectrics as phase-transition materials have promising applications in both logic and memory technologies beyond CMOS. Neuromorphic architectures, such as neural networks and artificial brains [1][2], requires synergy among neurons and synapses to achieve cognition and classification functionalities. In spite of the fact that traditional CMOS technologies provide cumbersome topologies to achieve these functionalities, emerging devices, such as ferroelectrics field-effect-transistors (FEFETs), offer significant benefits in terms of power, performance, and area as physical platform for implementing neural networks due to their unique properties—hysteresis, non-volatility, multi-state, and etc. In the past a few years, FEFETs have demonstrated great potential in implementing artificial synaptic devices [3]-[5]; however, the demonstration of artificial neurons built on ferroelectric devices is still pending. In this talk, we will present experimental demonstration of ferroelectric spiking neuron based on a compact 1T-1FEFET structure and projected performance of spiking neural network based on ferroelectric neurons for unsupervised clustering on MINST dataset [6]. Ferroelectric spiking neurons utilize abrupt hysteretic transition feature of ferroelectrics such that there are unstable states in the current-voltage characteristics of FEFETs [7]. FEFET hysteresis can be dynamically tuned by bias conditions which allows for inhibition functionality. Artificial neurons based on other emerging devices, such as metal-insulator-transition (MIT) devices [8], suffer from a fundamental shortcoming--all these neurons are excitatory. In contrast, ferroelectric spiking neurons have built-in excitatory and inhibitory input connections, which are essential to enable high accuracy in unsupervised learning, increases sparsity in spiking, and efficient implementation of synaptic weights.
In summary, spiking neurons based on FEFETs provide compact and efficient implementation of artificial neurons and have great potential in developing spiking neural networks and other neuromorphic applications.

Reference:
[1] A. Merolla, et al. Science, vol. 345, no. 6197, pp. 668-673, 2014.
[2] C. Eliasmith, et al. Science, vol. 338, no. 6111, pp. 1202-1205, 2012.
[3] Y. Nishitani, et al. J. Appl. Phys., vol. 111, no. 12, pp. 124108, 2012.
[4] M. Jerry, et al. 2017 IEEE International Electron Devices Meeting, 2017.
[5] S. Oh, et al. IEEE Electron Device Lett. Vol. 38, no. 6, pp. 732-735, 2017.
[6] Z. Wang, et al. 2018 IEEE International Electron Devices Meeting, 2018.
[7] Z. Wang, et al. IEEE Electron Device. Lett., vol. 38, no. 11, pp. 1614–1617, 2017.
[8] M. Jerry, et al. Proc. 2017 Symp. on VLSI Tech., pp. T186-T187, 2017.

When executing neural algorithms, neuromorphic computers can overcome efficiency bottlenecks inherent to digital computers by parallel processing of synaptic weights in memory. Despite the possibility of improved efficiency, accurate and parallel programming is challenging to realize due to strict requirements for high write linearity and low write current. Redox transistors based upon lithium-intercalation oxides[1] or semiconducting polymers[2] combine linear programming and low write current in a single device. However, programming at the array level requires an additional selector device. Here, we demonstrate that the sharp ON threshold and high OFF resistance of a Ag-based selector[3] enables addressable programming of redox transistors and state retention. Combined, these two devices comprise an ionic floating-gate memory (IFG) similar to flash but with electrochemical mechanisms for charge injection and memory storage. With an IFG crossbar array we demonstrate accurate and parallel synaptic weight updates that are "blind" and therefore require no feedback mechanisms or multi-pulse schemes. Prototype IFG devices exhibit >1 MHz switching rates, >10⁹ write-read endurance and read currents of 5-10 nA that could enable scaling to crossbars with > 1000×1000 elements. Architectural analysis projects a hybrid IFG-CMOS accelerator to have an energy, latency, and area advantage of 476×, 16×, and 9.5×, respectively, compared to an optimized 8-bit digital accelerator.
[1] E. J. Fuller, et al., Advanced Materials, 2017
[2] Y. van de Burgt, et al., Nature Materials, 2017
[3] Midya, et al., Advanced Materials, 2017

We demonstrated gradual conductance update during the RESET process of Ti/HfO₂/TiN memristive device under different device conductance update schemes. These schemes include varying voltage pulse amplitudes and pulse widths. The reported devices exhibited ~50 dynamic ratio of conductance with switching speeds of 100ns and 400ns for SET and RESET processes respectively. 7 different voltage amplitudes were used to switch the devices from their highest conductance to lower conductance at 1000 cycles each. It was observed that the distribution of these 7 conductance states overlapped with one another, owing to the stochasticity nature of device switching dynamics. One of the most critical stochasticity aspects of memristive devices is the presence of random telegraph signal (RTS), in the form of either bimodal or multilevel current fluctuation during read operations. Despite its undesired properties resulting in conductance instability during read operation, bimodal RTS generated from the back and forth movement of an electron between one electrode to an intrinsic oxide trap has been proven useful in characterizing traps behaviour and location in oxide-based memristive devices. Based on classical theory, the electron capture and emission time of this specific RTS have opposite bias polarity dependence. In the capture of this RTS, the measurement was performed by varying the read voltage from ±0.02V to ±0.20V in steps of ±0.01V under different sampling rates, i.e. 8 ksps, 80 ksps, and 800 ksps for each of the write sequence. The measured signals were investigated by analyzing its time lag plot and bias dependence polarity of capture/emission time constants. It was observed that at higher read voltages, the probability of multilevel RTS occurrences increased (from ±0.15V to ±0.20V), hence the read voltage was optimized in the lower regime rather than the higher regime. The absolute value of RTS amplitude was found to increase as the read voltage increased, while its relative percentage to the mean current decreased. The bimodal signal with opposite polarity dependence is further analyzed to extract the defects location in the oxide structure. The estimated defects location before and after the writing process indicated the movement of the defects within the oxide region, resulting in the conductance change of the device. Different jump distances were extracted from the two conductance update schemes to provide an insight on its correlation with gradual conductance change in Ti/HfO₂/TiN memristive device.

Continuous enhancement of performance and processing powers of computing devices will soon reach a technological and physical limit and to overcome this, systems emulating the human brain are being developed. Presently, mathematical models known as artificial neural networks (ANNs) are designed to simulate the computational abilities of the brain. Due to large simulation times, the current digital ANNs cannot be efficiently scaled. By contrast, analog (ad opposed to digital) neuromorphic devices with dedicated and adaptable synapses are expected to rival the scale and efficiency of the brain. Phase change materials (PCMs) enables us to fabricate synapses through their memristive behavior. Memristors are two-terminal electrical component where the resistance is a function of the amount and direction of current. Here, we discuss memristive behavior of W/WO₃/Ag, Cu/CuWO₄/W, and Ti/HFO₂/Pt systems for neuromorphic architectures and their potential application as ANNs. In prior studies, memristive architectures for neuromorphic computing are connected through a crossbar array of neurons. With a limit on the number of neurons and regular connectivity, the networks lack sparsity and randomness. As a result, they have high wiring cost and poor functional connectivity. To address such limitations, we have fabricated a random array of core-shell memristive wires to form the connectivity matrix for neuromorphic hardware. In the systems listed above, the conductive core (W or Ti) serves as the bottom electrode with a memristive shell (WO₃ or HfO₂) that can be electroformed with a set of top electrodes (Ag or Pt) deposited on the surface. Prior to miniaturization, the core-shell wire networks were fabricated using 20 μm tungsten fibers as conductive cores with tungsten oxide as memristive shells. After imprinting of top silver electrodes and electroforming, IV measurements revealed memristive behavior with switching between resistive states (i.e., LRS-HRS) at ±1 V. Subsequently, nanowire networks based on the Ti/HFO2/Pt system were fabricated using electron beam lithography (EBL). Over 90 overlapping core (40 nm)-shell (5 nm) nanowires were written on a 200 μm × 200 μm write field. To complete the connectivity matrix, 64 nodes and individual vias connecting the resulting network to electrode pads were written and deposited. Network quantifying simulations revealed a small-world coefficient of 2.89, shortest path length of 3.61 and clustering coefficient of 0.057. When electroformed, this system exhibited switching between LRS and HRS at ±7 V. To investigate the role of electrode-memristor interfaces, copper tungstate films were deposited on copper substrates using chemical solution deposition. After sputtering top tungsten electrodes and electroforming, IV measurements revealed memristive behavior and exhibited switching between LRS and HRS at ±0.7 V. In this presentation, the fabrication process and the memristive characteristics (endurance, resistance retention, pulse measurements, etc.) of the above listed systems will be discussed in detail.

Inspired by neural computing, the pursuit of ultralow power neuromorphic architectures with highly distributed memory and parallel processing capability has recently gained more traction. However, emulation of biological signal processing via artificial neuromorphic architectures does not exploit the immense interplay between local activities and global neuromodulations observed in biological neural networks, and hence are unable to mimic complex biologically plausible adaptive functions like heterosynaptic plasticity and homeostasis. Here, we demonstrate emulation of complex neuronal behaviours like heterosynaptic plasticity, homeostasis, association, correlation and coincidence in a single neuristor via a novel dual-gated architecture. This multiple gating approach allows one gate to capture the effect of local activity correlations and the second gate to represent global neuromodulations, allowing additional modulations which augment their plasticity and enabling higher order temporal correlations at a unitary level. Moreover, the dual-gate operation extends the available dynamic range of synaptic conductance while maintaining symmetry in the weight-update operation, expanding the number of accessible memory states. Finally, operating neuristors in the sub-threshold regime enables synaptic weight changes with high gain, while maintaining ultralow power consumption of the order of femto-Joules.

Every atom in two-dimensional semiconductors from the group of Transition Metal Dichalcogenides (TMDs) belongs to the surface. Because of that, TMDs are strongly affected by their microenvironment. In this talk we show that excitons, bound electron/hole pairs, in TMDs can serve as exquisite probes of the physical and chemical properties of that microenvironment.

First, we show that TMD excitons are strongly screened by nearby dielectrics. In suspended TMD, the behavior of pristine material is approached. We also examine frequency-dependent screening of excitons in TMDC and show that the frequency-dependent dielectric function of the environment can be effectively “sampled” by examining spectral shifts and intensity redistribution between neutral, charged, and defect-bound excitons. Second, we examine near-field energy transfer between TMDs and nanoscale quantum emitters (semiconductor quantum dots or dye molecules) near it. We show that such energy transfer is very efficient, and that its rate can be controlled through electrical gating. Finally, we examine binding of excitons in TMDs to charged molecules on their surface. We demonstrate new molecule-specific excitionic species produced by such binding.

Two-dimensional transition metal dichalcogenides (TMDs) are expected to have significant contributions to the future electronic and optoelectronic devices due to their unique features, such as sizable bandgaps, uniform thickness, absence of dangling bonds, lower interface trap density, reduced short channel effects, etc. Molybdenum disulfide (MoS₂), one well-known TMD, has drawn interest for high speed, flexible, low power electronic devices since it has a tunable bandgap, reasonable carrier mobility, excellent strength and large surface to volume ratio. One of the key reasons for dominance of silicon over all other semiconductors is the high quality interface between Si and SiO₂. Any semiconductor system should possess an interface comparable in quality with the Si/SiO₂ interface for its reliable application in electronic and optoelectronic devices.

In this work, we studied the interface quality of 2D/2D and 2D/3D interfaces by developing MoS₂ based field effect transistors (FET) having hexagonal boron nitride (h-BN) and high-k top gate dielectrics (Al₂O₃ and ZrO₂). For the 2D/2D MoS₂/h-BN FET, 13 nm h-BN flake was dry transferred over exfoliated MoS₂. For the MoS₂/high k gate dielectric structure, two different nucleation layers SiO_x and AlO_x were e-beam evaporated over exfoliated MoS₂, prior to atomic layer deposition of high k gate dielectrics Al₂O₃ and ZrO₂. One of the most direct, precise and sensitive techniques called the conductance method is adopted for extraction of the interface trap density (D_it) [1]. The subthreshold swing for the devices are in the range of 95 mv/decade to 160 mV/decade. In this comparative study, transistors with the MoS₂/h-BN 2D/2D interface exhibited lowest trap density in the range of 7×10¹⁰ states/cm²-eV at midgap. This superior quality interface is attributed to the absence of dangling bonds at 2D/2D interface [2]. The interface between MoS₂ and Al₂O₃ exhibited lower trap densities compared to MoS₂/ZrO₂ interfaces. In the mid gap, the highest trap density (1.35×10¹² states/cm²-eV) is obtained for ZrO₂ gate dielectric with AlO_x nucleation layer, while the lowest one (7×10¹⁰ states/cm²-eV near valence band) is obtained for Al₂O₃ gate dielectric with SiO_x nucleation layer. For both Al₂O₃ and ZrO₂ gate dielectrics, the SiO_x nucleation layer offered lower D_it compared to the AlO_x nucleation layer. The interface trap densities obtained by the conductance method are compared with the numbers obtained using other D_it extraction techniques, such as the Terman method and high-low frequency methods. This study shows that the MoS₂/h-BN and MoS₂/SiO_x/Al₂O₃ interfaces are at par with the state-of-the-art Si/high-k interface, extending the promise of 2D materials for future high-performance electronics.

References:
1. Nicollia. Eh, and Goetzber. A. Bell System Technical JournaL 46.6 (1967): 1055-+
2. Dev, Durjoy, et al. Applied Physics Letters 112.23 (2018): 232101.

One outstanding issue for state-of-the-art silicon devices is achieving high levels of dopant activation for shallow junctions, particularly for 3D device architectures in which processes like solid-phase epitaxial regrowth cannot be easily integrated. Helium ion implantation offers an intriguing potential method of vacancy engineering that is made possible by the stabilizing effect of helium on vacancy clusters, as well as the ability to subsequently desorb the implanted helium upon low-temperature annealing. However, much is still unknown about the dynamic interactions between helium, vacancies, and self-interstitials in silicon during implantation. In this study, these interactions were investigated by systematically varying the dose rate of an elevated temperature helium implant. 10 keV He⁺ was implanted into (100) Si at a dose of 4 x 10¹⁶ cm^-2 and an implant temperature of 450°C. Beam currents were varied from 2.6 to 10.4 mA. Transmission electron microscopy studies show that extended defects are present in the as-implanted state, and the density of these defects decreases with decreasing dose rate, which is unusual for non-amorphizing implants. In addition, cavities are present and their size and density vary systematically with dose rate as well. Thermal helium desorption spectrometry reveals differences in helium retention. These results are compared to those of silicon self-implantation performed using similar conditions. Implantation damage from silicon does not show the same dose rate effect, indicating the unique role of helium in self-annealing of implantation damage and suggesting that helium-vacancy interactions prevent some fraction of self-interstitials and vacancies from recombining. This study is an important step toward understanding the atomic processes that control the creation of excess vacancies in silicon through helium implantation.

This contribution deals with the first time fabrication of graphitic based memories using oxidized carbon nanofibers (ox-CNFs). In our case what we have obtained are Metal-Insulator-Metal (MIM) structures where the ox-CNFs are the layer sandwiched between two metal contacts. Thanks to that we are able to fabricate Resistance Random Access Memories (ReRAMs) where the resistance of the layer sandwiched changes in a non-volatile way as a function of the bias applied. Indeed thanks to spray-gun deposition method we are able to deposit thin layer of ox-CNFs on 2 metallized inches substrates. The thickness is around 100nm. The bottom contact is based on Pt and the top contacts are achieved using Cu/Al pads. The change of the resistance is related to the alignment of the oxygen vacancies and therefore to the creation of conductive paths inside the ox-CNFs layers. These paths are disaggregated cycling the bias. Moreover the oxygen is moved to the top contact and therefore this last is oxidized moving from a low resistance state (LRS) to a high resistance state (HRS). This change is reversible. The results show a typical shape of bi-polar memories when the voltage is cycled between around -2 and 2 Volts. We fabricated hundreds of structures and 2/3 showed this behavior. The switching phenomenon is not reproducible if we use CNFs with metal impurities. Indeed in this case the voltage is at the origin of the alignment of the metal impurities that lead to the short circuit of the structure linking the two metal contacts (creating sort of dendrites). For this reason the purification of the fibers is a very important step. The results obtained are extremely interesting and promising result considering that this was the first time in the world that this kind of memories were fabricated and tested. Moreover the ox-CNFs are deposited using spray-gun technique where the CNFs are in stable suspensions in deionized water. This is very important in case of the implementation of the process on very large surface of through roll-to-roll fabrication in order to achieve a low-cost but also operator-friendly process suitable for industrial application.

Resistive Random Access Memories (ReRAM) have huge possibilities for contributions to emerging nonvolatile memories. ReRAM cells exhibit reversibly transitions between high resistance states (HRS) and low resistance states (LRS), which is called resistive switching (RS) phenomenon. Set and reset processes mean the transition from HRS to LRS and that from LRS to HRS, respectively. RS operations are classified as either unipolar- or bipolar-type based on polarities of applied voltage at set or reset processes. ReRAM cells with an asymmetric stack structure usually exhibit bipolar RS operations based on valence change mechanism (VCM) [1]. However, why the asymmetric structure results in bipolar RS characteristics have not been clarified yet completely. In this work, we investigated impacts of an asymmetric stack structure in TaO_x-based ReRAM cells on resistive switching characteristics.

Pt/Ta₂O₅/Pt and Pt/TaO_x/Ta₂O₅/Pt stack structures were fabricated. The oxide layers were deposited on Pt/Ti/SiO₂/Si substrates as bottom electrodes (BEs) by reactive radio-frequency sputtering. The oxygen composition x in the TaO_x layers were controlled to be less than 2.5 by adjusting the oxygen gas flow rate. Then, the Pt layers with a diameter of 100 μm were deposited by electron beam evaporation as top electrodes (TEs). The resistance of Pt/Ta₂O₅ (5 nm)/Pt cells at 0.1 V in an initial state was roughly 10¹¹ Ω. On the other hand, that of Pt/TaO_x (10 nm)/Ta₂O₅ (5 nm)/Pt cells was approximately 10⁴ Ω. The reduction of resistance by introducing the TaO_x layer indicates that diffusion of oxygen vacancies (V_Os) from the TaO_x layer to the Ta₂O₅ layer caused film thickness distribution of V_Os in the Ta₂O₅ layer. Consequently, the Ta₂O₅ layer was effectively composed of a sub-stoichiometric layer (Ta₂O_5-δ) and a stoichiometric layer (Ta₂O₅).

When a positive voltage was applied to the TEs in the initial states, transition to a particular HRS occurred. We have reported the transition from the initial state to the particular HRS by overcurrent suppression in Pt/TiO₂/Pt cells [2]. The particular HRS is referred to as semi-HRS. In the semi-HRS of Pt/TaO_x/Ta₂O₅/Pt cells, as a negative bias increased, the resistance decreased discretely once, and then increased continuously to reach similar resistance to the initial state. These phenomena originate from the migration of V_Os by drift due to electric field and diffusion due to Joule heating. After the gradual reset, a set process occurred as a positive bias increased. The characteristics observed in the semi-HRS are quite different from those of conventional bipolar RS. Moreover, the transition to the semi-HRS is necessary for the bipolar RS operations in Pt/TaO_x/Ta₂O₅/Pt cells.

These results suggest that understanding of characteristics observed in the semi-HRS is highly significant for elucidation of bipolar RS operations in VCM-type cells. We will discuss characteristics in the semi-HRS and mechanism of the bipolar RS operations in detail.

[1] R. Waser et. al., Adv. Mater., 21, 2632 (2009).
[2] R. Matsui et. al., Mater. Res. Soc. Spring Meeting, EP01.07.05 (2018).

Non-volatile, electrically tunable memories like flash, phase-change, and filament forming metal oxides are desirable as synapses for neuromorphic analog computation with the potential to significantly lower power compared to digital processors. Reducing the switching voltage of non-volatile memories is important both to reduce energy consumption and to prevent dielectric breakdowns. Due to the Boltzmann distribution of electrons, it is unclear if any memory can switch significantly below 1V; developing non-volatile memory operating near the thermal voltage limit is a grand challenge.

In this work, we integrate two silicon-free electrochemical devices to demonstrate non-volatile memory that operates as low as 170 mV, just six times the thermal voltage limit. The first device is an ion insertion transistor which electrochemically shuttles lithium ions and electrons between the gate and the channel, analogous to a battery. Because the ions are mobile and move with the electrons, the process is charge neutral, and up to 10²¹cm^-3 of electrons and ions can be reversibly shuttled between the gate and channel without electrostatic charging. The second device is a diffusive memristor operating based on facile Ag⁺migration and filament formation only in the ON state. This volatile memristor ensures that the ion insertion transistor maintains its state when not electrically addressed. The combination of high charge density of the ion insertion transistor and low leakage current of the diffusive memristor enables these two electrochemical devices to retain memory. Because both devices operate at low voltage, we can linearly tune the electronic conductance using sub-200-mV voltage pulses. This device is also compatible with a V/2 crossbar select scheme without a select transistor, and demonstrates that non-volatile synaptic memory near the thermal voltage limit is attainable for low-power electronics.

Characteristic resistance changes are observed in two-terminal metal-oxide-metal (MOM) structures when subjected to large electric fields or current densities and are of interest as the basis of nonvolatile memory and neuromorphic computing devices. These resistance changes are often mediated by filamentary conduction, either in the form of a semi-permanent filament created by compositional changes in the oxide or as a transient filament created by inhomogeneous current or field distributions (e.g. current bifurcation). Knowledge of the filament location and morphology, and how these are affected by device geometry and material processing is important for understanding device operation and scaling. For example, enhanced filament formation is expected around the edges of cross-point devices due to local field enhancement or variations in oxide thickness. To gain an understanding of such effects it is desirable to have a simple, robust method of detecting and mapping filaments and to use this to study the statistics of filament formation.

To this end we have developed a simple technique for detecting the location of both permanent and transient filaments based on thermal denaturing of a thin photoresist layer. The efficiency of this approach is demonstrated by applying it to a MOM cross-point structure comprised of a Pt (25 nm)/Cr (10 nm) /NbO_x (45 nm)/Pt (25 nm) heterostructure, with cross point areas of 4-400 µm². A thin positive photoresist layer is deposited on top of fabricated cross-point devices by spin coating and then patterned using photolithography to open access to probe pads. The photoresist is then baked for 2 minutes in air using a hot plate kept at a temperature of 85 ^oC. After electroforming, a dark spot appeared in the photoresist on the top electrode due to local Joule heating, clearly identifying the filament location. Such analysis is subsequently employed to investigate the number and spatial distribution of filaments produced by electroforming.

Statistical analysis of the filaments shows that forming generally produces one dominant filament but that the spatial distribution of the filaments depends on the area of the cross-point device, with an increasing fraction of filaments located at the electrode edges as the device area is reduced. Evidence for transient filaments is also reported and discussed in relation to current bifurcation models. These results demonstrate the importance of filament mapping for understanding the relationship between device structure and performance and highlight the utility of resist-denaturing as a means of identifying and mapping conductive filaments.

Forming is an initial stage required to create conductive filaments in binary transition metal oxides (TMOs) before resistive switching (RS). The dissolution and reformation of the filaments have been widely accepted as an origin of the RS operation. However, where the filaments are created by forming remains unclear. In this study, we investigated correlation between the crystallinity and oxygen composition of TMOs and forming characteristics in TMO-based RS cells.
Pt/NiO/Pt and Pt/TiO₂/Pt cells were prepared. Pt bottom electrodes were deposited by sputtering (SP) or electron beam (EB) evaporation, which is referred to as SP-Pt or EB-Pt, respectively. NiO and TiO₂ thin films as binary TMOs were deposited by reactive sputtering. Pt top electrodes were deposited on the TMO layers by EB evaporation. In-plane X-ray diffraction and transmission electron microscopy reveal that NiO layers on the SP-Pt or EB-Pt include columns or granules with a grain diameter of tens of nm, respectively. On the other hand, the crystal orientation of TiO₂ layers on the SP-Pt is greater than that of TiO₂ layers on the EB-Pt even though the grain size of both TiO₂ layers is the almost same. These results indicate that the crystallinity of TMO layers strongly depends on the crystallinity of Pt bottom electrodes [1].
Next, characteristics of the initial cell resistance (R_ini) were investigated. In both cases of NiO and TiO₂, the R_ini values on the SP-Pt were greater than those on the EB-Pt, and the variation of R_ini on the SP-Pt were much smaller than that on the EB-Pt. These results suggest that the grain boundary density in TMO layers on the SP-Pt is lower than that in TMO layers on the EB-Pt resulting from the difference of TMO crystallinity. Moreover, TMO layers on the SP-Pt contains fewer oxygen vacancies than those on the EB-Pt, as estimated from our previous results of the segregation of oxygen vacancies at grain-boundary triple points in NiO layers [2]. As a result, the oxygen composition of TMO layers on the SP-Pt is larger than that of TMO layers on the EB-Pt.
Finally, the time to forming (t_form) in the cells was measured while keeping a constant applied voltage. All of the cells were confirmed to show repeatable RS operations after forming. Although the variation of t_form decreased as the variation of R_ini decreased in the case of TiO₂ layers, the variation of t_form increased as the variation of R_ini decreased in the case of the NiO layers. The distribution of forming characteristics depends on both crystallinity and oxygen composition of TMO layers because of the different deposition methods of the Pt bottom electrodes. These clear difference might originate from differences in the oxide deposition mode during reactive sputtering.
[1] Y. Nishi, et al., J. Appl. Phys. 120, 115308 (2016).
[2] Y. Nishi, et al., J. Mater. Res. 32, 2631 (2017).

We report on nearest neighbor hopping (NNH) in MgO-based resistive switching memory (RSM) devices in the high resistance state (HRS). NNH was found to be the dominant conduction mechanism in both Pt/MgO/Cu and Pt/MgO/Ta RSM devices. In the temperature-dependent linear fittings, extracted parameters and statistical results have shown that both RSM devices exhibited a small parameter standard deviation. Further temperature dependence investigations on reduced activation energy of the metal-dielectric conductance were performed to validate NNH in the RSM devices. NNH was found to occur when electrons obtained sufficient thermal energy to hop to the nearest trap. As the conduction mechanism studies was performed at 300K and above, NNH is shown to be the dominant conduction mechanism in both Pt/MgO/Cu and Pt/MgO/Ta RSM devices. The conductive filaments in electrochemical metallization (ECM)-based Pt/MgO/Cu RSM devices were investigated using TEM, as Cu atoms provide better visibility under TEM as compared to oxygen vacancies in valence change memory (VCM)-based Pt/MgO/Ta RSM devices. The EDX results suggest the presence of Cu filaments as a considerable amount of Cu atoms was found within the MgO layer. Current-voltage (I-V) measurements indicated that Pt/MgO/Cu RSM devices have better cycle-to-cycle variability as compared to Pt/MgO/Ta RSM devices. 100 cycles of I-V box plots of multiple devices indicated that Pt/MgO/Cu and Pt/MgO/Ta RSM devices exhibited good cycle-to-cycle variability. DC endurance exceeding 20,000 cycles was obtained, while retention of more than 10 years at 125°C were performed at elevated temperatures using an Arrhenius extrapolation plot. A 10³ to 10⁴ ON/OFF ratio between the low resistance state (LRS) and HRS was also achieved for both Pt/MgO/Ta and Pt/MgO/Cu RSM devices. The high ON/OFF ratio led to additional investigations of multi-level resistance state properties, in which the cumulative probability representations revealed at least 4 multi-level resistance states observed in the LRS for both Pt/MgO/Ta and Pt/MgO/Cu RSM devices.

Resistive Random Access Memories (ReRAM) have excellent characteristics such as high density integration, low power consumption, fast switching speed, robust endurance, and multilevel data storage. Therefore, they have been expected to be emerging candidates for next-generation nonvolatile memories, such as synaptic devices for neuromorphic computing [1]. ReRAM cells show resistive switching (RS) phenomena, which repeat transitions to the low resistance state (SET) and the high resistance state (RESET). Previous reports proposed mechanisms for the RS phenomena as a filament-type or an interface-type in different oxide layers; a filament-type RS phenomenon has been observed in binary oxides, while an interface-type in ternary oxides with perovskite structure. However, the details of both mechanisms remain unclear.

In this study, ReRAM cells with a Ti/Pr_0.7Ca_0.3MnO₃ (PCMO)/Pt stack structure were fabricated. PCMO layers were deposited on Pt (60 nm)/SiO₂/Si substrates by radio-frequency sputtering with Ar gas at room temperature. In-plane X-ray diffraction (XRD) revealed that the crystallinity of PCMO layers was almost amorphous. Ti (25 nm) layers were subsequently deposited on the PCMO layers by electron-beam evaporation as top electrodes (TEs). RS characteristics of the cells were investigated by DC voltage or current sweeping. PCMO-based ReRAM cells show an interface-type RS when TEs are active metal layers, such as Ti [2]. In this case, RESET occurs by positive voltage sweeping to TEs, and SET by negative voltage sweeping. However, the cells in this study exhibited not only the interface-type gradual RS but also abrupt RS like a filament-type.

At first, gradual RS was observed by DC voltage sweeping. Dependence of the conductance on the size of TEs indicates the interface-type RS. Secondary ion mass spectrometry (SIMS) analysis reveals redox reaction near Ti/PCMO interface, which corresponds to the formation of TiO₂ layers and the change of the thickness by DC voltage sweeping. On the other hand, abrupt RS occurred at a certain voltage, as shown in filament-type ReRAM cells. This phenomenon was observed at lower voltage as the size of the TEs was larger, indicating the formation of a conductive filament (CF) in the PCMO layer. RS characteristics of the cells with various PCMO thicknesses showed that the voltage at which gradual RESET occurred (V_RESET) and the CF created (V_form) decreased as the thickness of the PCMO layer decreased.

In the case of V_RESET > V_form, peculiar phenomenon was observed by DC current sweeping to the cells with approximately 30-nm-thick PCMO layers. In the conventional interface-type RS in the cells, the resistance ranged from 10⁶ Ω to 10⁸ Ω, V_RESET was approximately 10 V, and the on-off ratio was at most 2. On the other hand, after the CF formation, the resistance tended to range from 10² Ω to 10³ Ω, and a gradual RS with relatively lower resistance range (~10⁴ Ω) was shown by positive voltage sweeping. V_RESET in this case was reduced to approximately 2 V, and the on-off ratio was as high as 7~8. These results indicate the possibility to control the values of resistance and V_RESET of RS phenomena and to obtain further multilevel ReRAM cells.

[1] G. C. Adam, et al., IEEE Trans. Electron Devices., 64 (2017) 312.
[2] Z. L. Lia, et al., Appl Phys Lett., 94 (2009) 253503.

The emergence of ferroelectricity in doped HfO₂ thin films has attracted a great deal of attention since its discovery in 2011 ¹. Their full compatibility with the complementary metal-oxide semiconductor (CMOS) process make them viable candidates for application in non-volatile memory devices. Amongst hafnia based materials, Hf_xZr_1-xO₂ (HZO) has shown to be one of the more promising candidates ². The reason for selecting HZO is a wider and hence more forgiving composition window in mixing HfO₂ and ZrO₂ to obtain ferroelectricity, compared to e.g. Si doped HfO₂ ³. The ferroelectricity in thin doped HfO₂ films is generally accepted to originate from the crystallization of a non centro-symmetrical orthorhombic phase with the space group Pca2₁ ^4,5. During the crystallization, the temperature profile needs to be well controlled in order to favor the formation of the metastable ferroelectric orthorhombic phase against other non-ferroelectric phases ⁶. Here we report on the utilization of millisecond Flash Lamp Annealing (ms-FLA) for the stabilization of ferroelectric Hf_xZr_1-xO₂ (HZO) films. The thin film characterization structures are of MIM type and consist of a bottom TiN electrode, a 3-10 nm thick HZO layer and a top TiN electrode, deposited by atomic layer deposition in the same order. For the 10 nm thick HZO sample, the combination of a 120 s long preheat step at 375°C with a 20 ms xenon flash lamp pulse results in ferroelectric characteristics comparable to those obtained when using a 300 s long rapid thermal anneal (RTA) at 650°C. This statement is supported by X-ray diffraction, capacitance voltage, polarization hysteresis and cycling measurements. In 10 nm thick HZO layers a remanent polarization (P_r) of ~21 µC/cm² and a coercive field (E_c) of ~1.1 MV/cm are achieved. Cycling analysis shows an increase of endurance for the ms-FLA compared to RTA by one decade, up to 10⁷ bipolar cycles. An additional SiO₂ encapsulation of the TiN/HZO/TiN stack further increases the endurance up to 10⁸ cycles. For the 3 nm thin HZO sample the preheat temperature of the ms-FLA was increased to 550°C to successfully crystallize HZO in the orthorhombic/tetragonal phase. Unlike for standard anneals, the ms-FLA annealed films do not show any parasitic monoclinic phase, as confirmed by X-ray diffraction measurements. This illustrates the benefits of a fast thermal process to stabilize ultra-thin ferroelectric films, which are promising candidates for non-volatile memory and neuromorphic hardware applications when used as tunnel junctions.

¹T.S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger, Appl. Phys. Lett. 99, 0 (2011).
²J. Müller, T.S. Böscke, U. Schröder, S. Mueller, D. Bräuhaus, U. Böttger, L. Frey, and T. Mikolajick, Nano Lett. 12, 4318 (2012).
³L. Xu, T. Nishimura, S. Shibayama, T. Yajima, S. Migita, and A. Toriumi, J. Appl. Phys. 122, 124104 (2017).
⁴S. Clima, D.J. Wouters, C. Adelmann, T. Schenk, U. Schroeder, M. Jurczak, and G. Pourtois, Appl. Phys. Lett. 104, 092906 (2014).
⁵M. Pešić, F.P.G. Fengler, L. Larcher, A. Padovani, T. Schenk, E.D. Grimley, X. Sang, J.M. LeBeau, S. Slesazeck, U. Schroeder, and T. Mikolajick, Adv. Funct. Mater. 26, 4601 (2016).
⁶M. Hyuk Park, H. Joon Kim, Y. Jin Kim, W. Lee, T. Moon, and C. Seong Hwang, Appl. Phys. Lett. 102, 0 (2013).

HfO₂-ZrO₂ composites and alloys are of growing interest as dielectrics in advanced DRAM capacitors and ferroelectrics in emerging non-volatile memory and negative-capacitance FET technology. These versatile oxide materials express dramatically different physical properties depending on their crystal structure, which can be selected by tuning film thickness, processing conditions, or substrate material. In thin films or nanostructures, the P4₂/nmc tetragonal (t) phase, which is a high-k dielectric material, and the Pca2₁ orthorhombic (oFE) phase, which is ferroelectric, can be stabilized relative to the low-energy P2₁/c monoclinic (m) phase. Establishing predictive relationships between thin film processing and device performance therefore requires accurate measurement of the crystal phase distribution. While possible crystal phases can be inferred by electrical testing, the structure may be changed by electric field-induced transformation. X-ray diffraction (XRD) is the workhorse method of non-destructive crystal phase analysis, but the t and oFE phases are notoriously difficult to discriminate. However, differences in the short-range order of t-(Hf,Zr)O₂ and oFE-(Hf,Zr)O₂ are readily distinguished using extended X-ray absorption fine structure (EXAFS) measurements. Using a novel EXAFS analysis method, we resolve the t-, oFE-, and m-phase fractions to within 10% in 6 nm nanolaminate bilayers grown by atomic layer deposition (ALD). This structural analysis technique could inform device processing workflows that favor either ferroelectric or high-k dielectric ultrathin (Hf,Zr)O₂ films.

Ferroelectric behavior of doped-HfO₂, discovered for microelectronics applications [1], has recently attracted a lot of attention mainly for two types of devices: FE-FET [2] and NC-FET [3]. Both require the basic understanding of ferroelectricity at small scale with a variable level of dopants: usually a ferroelectric behavior is detected for thin films below 10 nm with a few percent of (Si, Al, La, Gd) or with more than 50% of Zr in substitution of Hf. For example, HfO₂ obtained by ALD deposit and doped by Si ion implantation (1.2% at.), effectively shows a typical ferroelectric behavior with a remnant polarization Pr of 8 mC/cm² and a coercive field E_c extracted in between 1.5 and 2 MV/cm [4]. Moreover, XRD and grazing incidence GIXRD show a polycrystalline mixture of monoclinic/P21c and orthorhombic/Pca21 symmetries, with a pronounced (111) orientation. By Scherrer’s analysis, the height of the non-centrosymmetric grains is equal to the thickness of the thin film [4]. We propose to model the corresponding ferroelectric switching by ab initio simulation, using the density functional theory. We focus our attention on a thin slab of Pca21 HfO₂:Si (1% at.) with thicknesses of 2, 5 and 8 nm respectively. First, by applying a strong electric field E of several tens of MV/cm, we reveal an original switching mechanism with a characteristic angle of 90° which fully reverses the polarization along the projected (111) direction. Then, by using the electric displacement field D as a basic variable [5], combined with an activation energy evaluation technique, we put in evidence a progressive ferroelectric switching of a unique domain with a saddle point of quasi-tetragonal symmetry. This progressive switching between orthorhombic and tetragonal symmetries, allows to estimate a coercive field and a remnant polarization in far better agreement with experimental values than previous studies of bulk HfO₂. Energy dependency of the saddle point, as a function of thickness and Si concentration is also assessed, providing useful data for ferroelectricity engineering.
[1] T.S. Böscke et al., App. Phys. Lett., 99, 2011, p102903.
[2] J. Müller et al., in Proc. VLSI Technol., 2012, p25.
[3] S. Salahuddin et al., Nanoletters, 8, 2008, p405.
[4] T. François et al., SSDM (2018) to appear in JJAP (2019).
[5] M. Stengel et al. Nature Physics, 5, pp304–308 (2009)

The dynamic electrical behaviors of an MFS capacitor was simulated mainly using Landau–Khalatnikov (LK) equation to understand the origin of the NC and its developing process at the ferroelectric/semiconductor hetero-junction. In an MFS capacitor, depolarization voltage due to the existence of remanent polarization is additionally applied to the gate voltage and it decreases as approaches zero during polarization switching from the full-polarized state. Therefore, the voltage applied to the ferroelectric layer decreases during polarization switching. The same situation also occurs decreases when the depletion layer forms. The physical picture of such a NC process will be given using the time-resolved simulation results and compare the differences from the proposed mechanisms such as steady-state and transient NC processes.

Promising technology boosters for future scaled CMOS can be regarded as 3D nano-sheet (NS)/nano-wire (NW) structures, new channel materials and the combination. Thus, MOSFETs with alternative channels such as Ge and III-Vs on the Si platform have been strongly expected over recent 15 years for high performance and low power logic devices, where the reduction in V_dd is the most critical requirement. CMOS using these channels can reduce the gate overdrive (V_g-V_th) and resulting low V_dd at a given Ion, because of the high injection velocity due to the low effective mass. These high mobility channels can be more important for NS/NW CMOS than FinFETs, because of limited rooms to increase the channel width, different from FinFETs. In spite of the strong efforts to introduce such alternative channels, however, the implementation into the advanced CMOS platform has not been visible yet, because of wide aspects of difficulties in the device integration.
In the more-Moore approach, Ge/III-V 3D stacked CMOS is one of the promising device structures. This is because 3D integration by using low temperature process is much easier for Ge and III-V than Si. In addition, the ultralow contact resistance of Ge and In(Ga)As with metals can be expected through utilizing Fermi-level pinning of the interfaces with meals under low thermal budget. In the beyond-CMOS approach, on the other hand, steep slope devices have stirred a strong interest from the viewpoint of ultralow power applications. One of the most promising steep slope devices is tunneling-FETs (TFETs). Here, Ge/III-V channels are also expected to enhance the TFET performance, because of the increased tunneling probability due to the small and direct bandgap. In particular, the source/channel junctions composed of the type-II hetero-structure are quite effective in improving the TFET characteristics, because the effective bandgap (DE_g) between the valence band top of the source and the conduction band bottom of the channel is reduced, resulting in the increase in Ion with maintaining low Ioff.
In this paper, we briefly address the current status of MOSFETs and TFETs using alternative materials such as Ge, III-V and oxide semiconductors for future low power scaled devices and review the recent progress in device and process technologies on a basis of our research activities. Among these devices, Ge pFETs can be the closest to the real applications. Although InGaAs-based nFETs are also promising, stringent controls of material quality and super-smooth device geometry are strongly needed. Since Ge nFETs and III-V pFETs are still in an immature stage, the combination of In(Ga)As nFETs and Ge pFETs and, in particular, the combined 3D stacked CMOS seem promising. We presented highly-strained GOI and InGaAs-OI formation technologies and ultra-thin body InGaAs QW channel design as viable solutions for advanced CMOS.
Also, the introduction of alternative channels is more essential for improvement of TFET performance. The possibilities of Ge complementary TFETs and InGaAs QW nTFETs were addressed. Here, the suppression of defect-related currents is a key issue. Finally, we proposed and demonstrated the novel bi-layer TFETs using the type-II hetero-structures composed of oxide semiconductors such as ZnO and ZnSnO, and column-IV semiconductors such as Si, SiGe and Ge. We have experimentally demonstrated the operation of Si/ZnO and Ge/ZnO TFET operation with remarkably high I_on/I_off of ~10⁸, low I_off and minimum SS of 71 mV/dec. As a result, the oxide semiconductors/column-IV semiconductor bi-layer TFETs are expected to be one of the potential options of TFETs overcoming CMOS in terms of the ultra-low power operation.

Strain engineering for pFETs has been conventionally achieved by embedded SiGe source/drain to boost the transistor current drive and transconductance [1]. Historically, transconductance was monotonically improved by advancing the CMOS technology generations. However, this trend was no longer observed when FinFETs were introduced to the mainstream CMOS [2]. The deviation from the historical trend of transconductance is attributed to ineffectiveness of the embedded SiGe stressors (in spite of higher mobility near-(110) surfaces) and/or increased contribution of the S/D resistance as the contacted gate pitch size aggressively scales down. Strained SiGe (s-SiGe) channel, with built-in uniaxial compression, is a strong option to overcome this issue. In fact, SiGe channel has been utilized in CMOS industry as a knob to control the threshold voltage (Vth) and in part to boost the pFET reliability and transport [3]. Moreover, introduction of SiGe channel for planar pFET has improved reliability, resulting in further Equivalent-Oxide-Thickness (EOT) scaling over Si. For s-Si1-xGex FinFETs, choice of Ge content (x) has multipronged effects and it is not trivial. Adding more Ge can ideally build in more channel stress resulting increased hole mobility. On the other hand, fin height control due to the critical thickness constraints, process thermal budget, bandgap reduction and gate-induced drain leakage (GIDL) control remain challenging. From the view point of carrier transport, High-Ge-Content (HGC) s-SiGe FinFETs are of great interest for two reasons: (1) very high level of strain (~ 3GPa) can be achieved when lattice matched to Si [4]. (2) if strain-relaxed buffer (SRB) SiGe with moderate Ge % is used to tensily strain Si nFET, higher Ge is required to compressively strain the pFET [5]. The GIDL issue can be mitigated by operating the device at a lower VDD, i.e. below 0.6V, in accordance with logic roadmap [4]. Controlling the fin height, to be competitive with the state-of-the-art Si FinFETs, remains challenging. Above all, a major challenge is formation of gate stack and interface trap control which is more pronounced in HGC SiGe compared to Si and pure Ge. In this talk, materials and process innovations to enable relatively tall fins and optimized replacement high-k metal gate (RMG) stacks on high-Ge-content SiGe channels will be discussed and their impact on key device characteristics will be presented. In particular, we review our recent progress in interfacial layer formation and passivation [6], high hole mobility and record performing short channel pMOS FinFETs. In addition, aggressive gate length scaling down to 15nm via an ultra-thin replacement metal-gate is demonstrated.

[1] T. Ghani et al., IEDM, 2003, p. 197.
[2] P. Hashemi, et al., IEDM, 2017, p. 824.
[3] S. Krishnan et al., IEDM, 2011, p. 634.
[4] P. Hashemi et al., IEDM, 2014, p. 402.
[5] R. Xie et al., IEDM, 2016, p. 47.
[6] P. Hashemi et al., VLSI Tech. Symp., 2017, p. 120.

Si and SiGe quantum dots (QDs) have exciting potential in microelectronics and quantum computing as well as in on-chip optical sources. These QDs could enable single electron devices, spin qubits, and on-chip light sources for integrated Si(Ge) based photonics and electronics. However, scalable methods for creating size-controlled and on-chip position-controlled Si/SiGe QDs at dimensions less than 5 nm do not currently exist. To address this challenge, we explore the use of a unique, enhanced Ge diffusion process during the thermal oxidation of Si/SiGe heterostructures as a potential route to create Si/SiGe QDs. Initial oxidation work using Si/SiGe multilayer fins resulted in the formation of vertically stacked, horizontal Si nanowires with diameters down to 2 nm encapsulated. After oxidation, these Si nanowires were encapsulated in defect-free epitaxial strained SiGe. High angle annular dark field scanning transmission electron microscopy (HAADF-STEM) analysis revealed that Ge rapidly diffused along the Si/SiO₂ interface during oxidation, effectively encapsulating the Si layers in SiGe as the oxidation continued. We extend this approach to the oxidation of vertical Si/SiGe axially heterostructured pillars, rather than fins, defined via electron beam lithography and reactive ion etching, as a route to create stacked Si QDs instead of lateral Si nanowires. Results on the formation of QDs within the pillars after oxidation will be presented. Further, the unique Ge diffusion along the sidewalls of the oxidizing Si/SiGe heterostructure material is affected by the circumference of the initial unoxidized nanostructure, with Ge diffusion being observed in pillars with initial diameters greater than 50 nm and not observed for initial diameters less than 50 nm. A detailed picture of the effects of curvature as well as crystal orientation of the oxidizing surface on Ge diffusion will be presented. In total, these findings could lead the way to scalable manufacturing of Si/SiGe QDs for single electron devices as well as on-chip light emission and sensing. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

Thermal and mechanical stress often causes plastic deformation(slip) of the silicon (Si) wafers during high temperature electrical device fabrication. Interstitial oxygen atoms (Oi) can diffuse to the dislocation cores and be trapped there to impede the dislocation by locking. The Oi in the silicon becomes highly supersaturated as the crystal cools and can nucleate and grow into SiO₂ precipitates (oxide precipitates, OPs) under certain high temperature treatments. Small OPs can pin dislocations and slow slip propagation. Large OPs, however, can soften the wafers both by consuming the dissolved Oi, reducing dislocation locking, and by acting as dislocation sources. It is well known that oxygen forms thermal donors at low annealing temperature (300 – 450 °C), which can result in deleterious resistivity shift, as the same temperature range is often used for post-metallization annealing. In RF devices, where high resistivity of the substrates is critical, ultra-low oxygen concentration ([Oi]) wafers are widely used to reduce thermal donor generation. Due to the lack of Oi to lock and pin the dislocations, low [Oi] wafers are weaker and more prone to slip and plastic deformation. Nitrogen doping is known to be effective in locking dislocations and can be added to the crystal to increase strength, but in combination with oxygen generates new donors, which are stable at higher temperature (〉1000°C), exacerbating resistivity shift issues.

Germanium (Ge) seems to be a good candidate for strengthening Si, as it is electrically neutral and forms a solid solution with Si at all concentrations. Ge may impede dislocation motion directly by means of its larger atomic size comparing to Si, or indirectly through changing the behavior of Oi diffusion and/or precipitation. Little data is available on the effect of Ge doping on the dislocation motion in silicon wafers with ultra-low [Oi] (1.5 – 3 × 10¹⁷ atoms/cm³). Previous work on Ge at high [Oi] (5 – 12 × 10¹⁷ atoms/cm³) reported improved slip resistance, due to Ge enhancing Oi precipitation to pin the dislocation motion. It is unclear whether Ge, as a substitutional impurity, can diffuse to the dislocation cores to prevent the dislocation motion by locking, or retard slip propagation by solid solution strengthening.

In this work, we study the dislocation unlocking stress of ultra-low [Oi] Si wafers (1.5 – 2 × 10¹⁷ atoms/cm³) with Ge doping (5 – 6 × 10¹⁹ atoms/cm³). Samples with similar [Oi] but without Ge were used as control. Both types were annealed for various times (0.25 – 16 hours) and temperatures (600 – 750 °C) before mechanical testing, to allow the impurities to diffuse and bind to the dislocations. The samples were then loaded in a three-point bending configuration, and the stress required to unlock dislocations was evaluated. The pinning effect of OPs was negligible at such low [Oi], where precipitation was suppressed, which allowed us to investigate the role of Ge on dislocation motion. The average dislocation velocities as a function of shear stress were found to be comparable for Ge and control groups, and independent of the annealing condition prior to mechanical loading. At all annealing temperatures tested, the unlocking stress as a function of annealing time initially rises linearly before taking a constant value. The saturated unlocking stress is lower at higher temperature, indicating the impurities have a higher tendency to “boil off” from dislocations. The rate of the initial rise is found to be strongly dependent on annealing temperature, with an activation energy of 1.52 eV and 1.68 eV for Ge doped and control samples, respectively. The preliminary results showed that Ge by itself does not have a significant impact on the dislocation unlocking stress for the annealing conditions tested.

Silicon-germanium (SiGe) alloys are promising for advanced FinFET channels due to their electronic properties and ease of integration into existing Si CMOS processes. However, Ge-O bonds at the channel/insulator interface introduce defect energy states. Previous investigations into suppressing Ge-O bond formation have involved liquid sulfur treatments or ammonia plasma pre-deposition, or post-deposition N₂ plasma nitridation. Sulfur treatment presents reliability concerns, while post-deposition nitridation lacks control over oxide nucleation. In this work, an in-situ downstream RF plasma containing a mixture of N and H species on Si_0.7Ge_0.3(001) surfaces prior to deposition of high-k oxides Al₂O₃ and HfO₂ by atomic layer deposition (ALD) has been investigated using metal-oxide-semiconductor capacitor (MOSCAP) structures. C-V and I-V characterization was performed, demonstrating improved interface state density (Dit) and leakage current for plasma-cleaned devices. X-ray photoelectron spectroscopy (XPS) was used to investigate the chemical environment at the SiGe/high-k interface.
Al₂O₃ and HfO₂ MOSCAPs were fabricated to compare the in-situ N₂/H₂ plasma clean with an HF(aq) only preclean. 40 Al₂O₃ cycles were grown with TMA and H₂O precursors at 250 C, and 50 HfO₂ cycles were grown with TDMAH and H₂O precursors at 250 C. Prior to deposition, SiGe substrates were treated with 2.5 cycles of 2% HF(aq) followed by deionized water, with plasma cleaned devices receiving an exposure to 20s downstream RF plasma at 20 W with 500 mTorr N₂, 25 mTorr H₂, and 475 mTorr Ar. A significant improvement to D_it was observed for the plasma cleaned devices; HF + plasma Al₂O₃ MOSCAPs had an EOT of 3.14 nm and peak D_it of 7.2 x 10¹¹ cm^-2eV^-1, compared with 3.39 nm EOT and 3.6 x 10¹² cm^-2eV^-1 for the HF only device, illustrating Dit improvement without a decrease in EOT. On HfO₂ devices, HF + plasma and HF only MOSCAPs had EOT values of 1.61 and 1.77 nm and peak D_it values of 2.9 x 10¹² and 4.8 x 10¹² cm^-2eV^-1. Leakage currents at -2 V bias were 100x lower for HF + plasma Al₂O₃ and HfO₂ MOSCAPs, consistent with a more uniform oxide layer after plasma clean.
Using capacitance- and conductance-voltage measurements, a full interface state model across the band-gap was used to find the integrated Dit, demonstrating a 5x improvement in integrated Dit on Al₂O₃ HF + plasma MOSCAPs compared with HF only, and a 30% improvement compared with sulfur-passivated devices. With HfO₂ MOSCAPs, integrated D_it value was decreased 2x for HF + plasma devices compared with only HF.
To investigate the chemical structure at the interface, a thin Al₂O₃ layer was deposited using 5 ALD cycles on both HF only and HF + N₂/H₂ plasma cleaned surfaces, and XPS spectra were recorded. Plasma-treated SiGe exhibited lower intensity Si and Ge peaks, consistent with improved Al₂O₃ nucleation. Si and Ge nitride peaks appear after plasma treatment, consistent with a nitride layer suppressing Ge-O bond formation.

Nowadays, germanium (Ge) is a potential replacement for Si owing to its higher electron and hole mobility [1]. For scaling equivalent oxide thickness (EOT) of gate dielectric for high-performance Ge MOSFETs, different kinds of high-k materials have been extensively studied [2-3]. The dielectric constant values of HfO₂ and ZrO₂ are 23and 30, respectively [4-5], so that ZrO₂ possess greater potential in scaling EOT due to its higher dielectric constants. However, GeO vaporization and diffusion into the high-k layer would induce more interfacial defects at the interface [6]. Recently, several studies had focused on improving the quality of the interfacial layer by doping metal into GeO_x interfacial layer (IL) [7-9]. In this paper, we, thus, doped metal Yttrium (Y) into GeO_x IL and using ZrO₂ instead of HfO₂ for the gate stack to investigate the impact of the Y addition on the electrical properties of the MOSCAPs on Ge.
First, the native oxide on p-type Ge (100) was removed by diluted fluoric acid (DHF). Second, an YGeO_x IL was formed by sputtering a 0.6-nm-metal Yttrium (Y) followed by remote plasma oxidation in an ALD reactor. A ZrO₂ layer as high-k layer was deposited by ALD using tetrakis(dimethylamino)zirconium as the precursor. TiN gate electrode was formed by sputtering and lift-off lithography. Finally, post metal annealing (PMA) was performed at 400–600 °C for 1 min in N₂ atmosphere.
According to the results of electrical measurements, including C-V and I-V, the lowest D_it value of ~ 4.1×10¹¹ eV^-1cm^-2 for the sample with YGeO IL was achieved through PMA at 500 °C and the gate leakage current level was of ~8.8×10^-8 A/cm² @V_FB-1V, which was more than 4 orders of magnitude lower than that of the one with GeO_x IL. However, the EOT value of the gate stack with YGeO_x IL was significantly increased as compared to the control one. For more deeply studying the interfacial quality, we used angle resolved X-ray photoelectron spectroscopy (ARXPS) to observe the phenomenon of Ge diffusion into the overlaying ZrO₂ layer. The results in ARXPS indicated that the photoelectron intensity of Ge 3d core-level for the YGeO_x case was much lower than the GeO_x case, implying more severe GeO diffusion occurred in the GeO_x case. To better understand what had happened, we integrated the areas of Ge and Zr signals in XPS plot to have the atomic ratio of Ge to Zr. The result showed that in the GeO_x case higher ratio of Ge to Zr near the interface between IL and high-k layer, especially as the X-ray incident angle was small. According to the thermodynamic theorem, Y₂O₃ (△G_f⁰= -1905.31 kJ/mol) has lower Gibbs free energy than GeO₂ (△G_f⁰= -497.06 kJ/mol). Hence, it is believed that doping Y in the GeO_x IL can lead to better thermal stability and suppress the GeO vaporization during high-temperature annealing. In summary, incorporation of Y in GeO_x could enhance the stability of the IL and significantly improve the interface quality of the gate stack on Ge in terms of lower interface state density. However, the EOT value became worse as the addition of Y.


References:
[1]K. Saraswat, IEDM Tech.Dig., 659 (2006)
[2] S. G. Lim, S. Kriventsov, T. N. Jackson, J. H. Haeni, D. G. Schlom, A. M. Balbashov, R. Uecker, P. Reiche, J. L. Freeouf and G. Lucovsky ,Journal of Applied Physics 91, 4500 (2002)
[3] G. D. Wilk, R. M. Wallace and J. M. Anthony, Journal of Applied Physics 89, 5243 (2001)
[4] Y.-S. Lin, R. Puthenkovilakam and J. P. Chang, Appl. Phys. Lett. 81, 2041 (2002)
[5] C. H. Chou, H. H. Chang, C. C. Hsu, W. K. Yeh and C. H. Chien, IEEE ELECTRON DEVICE LETTERS, 37,2(2016)
[6] Y. Abe, N. Miyata, and N. Miyata, J. Electrochem. Soc., 16, 375 (2008)
[7] C. Lu, C. H. Lee,W. Zhang, T. Nishimura, K. Nagashio and A. Toriumi, Appl. Phys.Lett., 104, 092909 (2014)
[8] Y. H. Tsai, C. H. Chou, A. S. Shih and C. H. Chien, IEEE Elec. Dev. Lett., 37, 1379 (2016)
[9] C.H. Chou, Y.H. Lu, and C.H. Chien, ECS Journal of Solid State Science and Technology, 7 (2) N15-N19 (2018)

As FinFET scaling continues for advanced CMOS nodes (10/7nm), contact resistance remains a dominant component affecting device performance. The FinFET S/D contact area has become smaller with scaling (narrower fins due to reduced fin pitch), resulting in drastically increased contact resistance. To achieve higher drive currents and fully realize the performance gain from FinFET architectural changes such as narrower and taller fins, it is critical to achieve contact resistivity ρ_c <1.0x10^-9 Ω.cm² for both PMOS and NMOS.
In this paper, we first review the requirements and recent trends for contact resistance reduction for advanced CMOS devices. Then, we discuss the various approaches that have recently demonstrated reduction in ρ_c, such as the use of in-situ heavily doped epitaxial films for S/D, and advanced implant and anneal techniques. The implant techniques leverage damage engineering concepts and include (i) pre-silicide amorphization, (ii) cryogenic (-100^οC) implantation and (iii) plasma doping (PLAD) for conformal doping. With such high levels of doping from epi and implant approaches, this paper will also discuss the integration of advanced laser anneal techniques for improved dopant activation while minimizing diffusion, such as millisecond laser anneal, and nanosecond laser anneal (for super-activation), that are imperative for contact resistance reduction. Finally, we will discuss an alternative contact approach, which implements wrap-around contacts that cover the entire S/D fin surface in order to increase the effective contact area while maintaining the same contact size, potentially providing a pathway to further reduce the contact resistance for advanced CMOS nodes.

Cu is the preferred interconnect metal in modern CMOS nodes due to its low bulk resistivity. However, two major challenges exist with deeply-scaled Cu interconnect vias. First, at via widths under 10 nm, physical vapor deposited Ta-rich TaN diffusion barriers cannot deposit uniformly on high-aspect ratio vias where a uniform sub-2nm nanometer diffusion barrier is required. Second, the long mean free path of electrons in Cu causes an increase in resistivity in thin layers, motivating the use of metals such as Co or Ru with shorter mean free paths. Atomic layer deposition (ALD) processes for high-aspect ratio patterns exist for Co and Ru, but the need for longer grains requires highly-selective ALD processes proceeding from the bottom-up. Ideal processes nucleate well only Si or metal surfaces, but surface defects on SiO₂ and low-k dielectrics can cause unwanted nucleation. In this work, the effectiveness of a self-assembled organic monolayer as both a diffusion barrier and as a passivation agent to enhance selective ALD is investigated.

Previous studies on alternative diffusion barriers have involved amorphous Co-Ti alloys deposited via RF sputtering. Alternatively, sub-2nm thick SAMs containing bulky groups with N or P atoms have also proven to be effective as Cu diffusion barriers on Si and SiCOH. To enhance selectivity of ALD processes, SAMs composed of hexamethyl-disilazane (HMDS) and octadecyl-trichlorosilane (ODTS) have been used to block hydroxyl sites, preventing deposition of HfO₂ on SiO₂ without blocking deposition on Si. However, these SAMs require extended treatment periods of 24-48 hours. This work demonstrates the use of the molecule 2-diphenylphosphino-ethyl-triethoxysilane (DPPETS), known to be a Cu diffusion barrier, and in the present work, as a rapidly-acting ALD passivant for middle-of-line and back-end-of-line.

SiO₂ and SiCOH substrates are first treated by an organic degrease of hexane, acetone, methanol, and DI water followed by HF clean. Liquid-phase DPPETS is applied as a 1% solution in toluene for 1 hour at 70 C, followed by hexane sonication to remove particle contamination, 10 cycles of a selective MoSi_x ALD process using MoF₆ and Si₂H₆ are employed to investigate nucleation density on dielectric by AFM. Contact angle measurements are used to probe the presence of active hydroxyl sites, which decrease hydrophobicity. X-ray photoelectron spectroscopy (XPS) is used to investigate the chemical state of the passivated and unpassivated dielectric surfaces after ALD. On SiO₂, passivation of surface defects is observed, with an increase of contact angle from 40° to 82°. However, on SiCOH, the contact angle is not significantly affected by DPPETS passivation.

AFM of the SiO₂ after HF pre-clean, after DPPETS passivation at 1 hr, and after 10 cycles of MoSi_x ALD on both passivated and unpassivated SiO₂ over a 2x2 µm region confirms a uniform passivation layer prior to deposition with a roughness of 2.9 Å. After 10 ALD cycles of MoSi_x on passivated SiO₂, the number of particles taller than 1 nm are reduced by a factor of 4 compared with unpassivated SiO₂. Nuclei on unpassivated SiO₂ are roughly 8 nm in height, corresponding with the expected thickness of MoSi_x deposited on Si, whereas on the passivated sample are ~4-8x shorter, consistent with delayed nucleation due to the protection of SiO₂ defect sites by the DPPETS monolayer. As shown in XPS studies on Si, deposition readily proceeds as metallic MoSi_x, whereas on unpassivated SiO₂, only 5.6% residual Mo is present at the surface. However, on DPPETS passivated SiO₂, Mo content is reduced to 1.4%. On the unpassivated SiO₂, a metallic Mo component is observed, consistent with partial MoSi_x deposition. However, on the passivated SiO₂, no metallic Mo component is observed, consistent with nucleation of Mo on -OH sites forming MoO_x. The Mo present being an oxidized state is consistent with MoO_x nuclei on remaining defect sites blocking further Mo deposition.

In this paper, a research of HfO₂-based gate stack with Ti-doped interfacial GeO_x layer on p-type Ge bulk are fabricated. The result shows that Ti-GeO_x interfacial layer (IL) had better interface quality (D_it) and better thermal stability than GeO_x IL.
In the continuous scaling down of the device for logic circuits, Germanium has became the most attractive materiel because of its high electron and hole-mobility compares to Si. However, the poor interface quality between Ge bulk and high-k material is one of the issue to be solve. The GeO will volatilize from the interfacial layer (IL) over 400 °C, which is the main reason of the poor interface quality. In recent studies, metal doped into GeO_x IL can significantly improve the thermal stability. In this paper, incorporating Ti into common HfO₂-based (TiN/HfO₂/Ti-GeO_x/Ge) gate stack were demonstrated. The electrical performance and TEM images will be discussed.
First of all, native oxide removal of p-type Ge (100) wafer was carried out by diluted fluoric acid (DHF). A 300 nm SiO₂ was deposited by Plasma enhanced CVD (PECVD), followed by using pattering and etching to defining capacitance area. Subsequently, In-situ GeO₂ was grown by O₂ plasma oxidation followed by 2.1 nm HfO₂ as high-k dielectric deposited in ALD chamber. A thin film of Ti metal was sputtered before GeO_x growth to achieve the Ti doped into GeO_x IL. Finally, the top gate electrode consisted of a plasma-enhanced atomic layer deposited TiN layer and a sputtered TiN layer was patterned by photolithography and dry-etching process. Before the dry-etching process, post metal annealing (PMA) was conducted at temperature varied between 400 °C and 500 °C for 1 minute in an N₂ ambient.
According to the results, the D_it for Ti-GeO_x can achieve a 2 × 10¹¹ eV^-1 cm^-2 value. By contrast, normal GeO_x was up to nearly 1 × 10¹² eV^-1 cm^-2. In addition, constant voltage stress under 8 MV/cm stress field was conducted. The results show the ΔD_it for GeO_x case was approximately 6 × 10¹¹ eV^-1 cm^-2. On the other hand, that of Ti-GeO_x was less than 2 × 10¹¹ eV^-1 cm^-2. The TEM image shows that the Ti-GeO_x still remains after a PMA of 500°C. However, the GeO_x was already vaporized, which indicate that Ti-GeO_x has better thermal stability. The missing IL for the standard sample also can explain the degradation of the D_it. GeO vaporization induce a lot of dangling bonds or oxygen vacancies, which result in worse IL quality. Therefore, Ti-GeO_x can remain stable and a better interfacial quality after a PMA of 500°C.
In summary, incorporating Ti into GeO_x can suppress the GeO vaporization which leading to better interface quality. In addition, the constant voltage stress tolerance can be improved. Therefore, Ti-GeO_x is a candidate as an effective IL for Ge gate stack, which could be a promotion on high performance Ge MOSFET.
References:
[1] S. K. Wang et al., “Desorption kinetics of GeO from GeO₂/Ge structure,” Journal of Applied Physics, vol. 108, no. 5, p. 054104, 2010.
[2] C. Lu, C. Lee, T. Nishimura, and A. Toriumi, “Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT,” in VLSI Circuits (VLSI Circuits), 2015 Symposium on, 2015, pp. T18-T19: IEEE.
[3] M. Houssa, G. Pourtois, M. Caymax, M. Heyns, “First-principles study of the structural and electronic properties of (100) Ge/Ge(M)O₂ interfaces (M= Al, La, or Hf),” Applied Physics Letters, vol. 92, no. 24, p. 242101, 2008.
[4] A. P. Huang, Z. C. Yang and Paul K. Chu, “Hafnium-based High-k Gate Dielectrics,” Advances in Solid State Circuits Technology.
[5] Y. H. Tsai et al., “Improving Thermal Stability and Interface State Density of High-k Stacks by Incorporating Hf into an Interfacial Layer on p-Germanium,” IEEE Electron Device Letters, vol. 37, no. 11, pp. 1379-1382, 2016.

Abstract pending

For high-performance nanoscale transistors and extension of CMOS roadmap, there are still many difficulties that need to be overcome. A low-grade interfacial layer (IL) between high-K gate dielectrics and semiconductors, which results in current degradation, low gate capacitance, and severe short channel effect, is one of the most important issues. However, it is difficult to prevent the formation of the thermodynamically unstable low-K IL such as SiO_x and GeO_x. Hence we come up with a concept of introducing a non-oxygen buffer layer between high-K gate dielectrics and semiconductors. In this study, aluminum nitride (AlN) of good chemical stability and electrical characteristics is used as the buffer layer between the crystalline zirconium oxide (ZrO₂) high-K gate dielectric and the semiconductor to restrain the formation of the low-K, unstable IL. A suppression of IL is confirmed by the X-ray photoelectron spectroscopy and the high-resolution transmission electron microscopy. A reduction in the equivalent oxide thickness and the leakage current density (J_g) are achieved by the AlN buffer layer. In addition, a decrease of interface trap density (D_it) is accomplished because of the hydrogen passivation from the remote hydrogen plasma during the AlN deposition. All the results indicate that the AlN buffer layer is effective in providing a high-quality interface to improve the performance of advanced metal-oxide-semiconductor field-effect-transistors.

A novel material structured in thin film form, Sub-Nanometer Periodic Stack Dielectrics (SN-PSD) has been developed for applications to a new generation of logic analog and memory semiconductor micro/nano-devices. Compared with conventional single layer dielectric films, SN-PSD exhibits substantial improvement in dielectric breakdown voltage (~2.4V, or 35% improvement), and reduced leakage current by about one order of magnitude. High-density capacitor structures utilizing SN-PSD layer would enable on-chip decoupling capacitors in digital and analog integrated circuits (ICs), data storage elements in IR image sensors, energy storage in transmitters, and DRAM and other semiconductor memories to improve the performance and reduce the silicon footprint. The SN-PSD would also be suitable for use as a gate dielectric in silicon carbide (SiC) CMOS FETs for its low leakage current and high breakdown voltage. Existing single-layer-dielectric capacitors often have a large footprint, and have issues with high leakage current and early dielectric breakdown, making their use in developing devices problematic. The time dependent dielectric breakdown lifetime extrapolation for SN-PSD indicates that the dielectric breakdown lifetime will exceed 10 years under equivalent electric field of 16.5MV/cm for HfO₂/TiO₂ SN-PSD-based capacitors, versus 9.1MV/cm for single layer HfO₂-based capacitors. Compared to single layer HfO₂ capacitors, the breakdown mechanism of the newly developed HfO₂/TiO₂ SN-PSD capacitors has been changed from hard breakdown to soft breakdown. The capacitance voltage (C-V) characteristics have been analyzed. The charge and discharge cycle has been studied for 10,000 cycles without degradation. The frequency response of capacitor has been characterized for frequencies of 10Hz, 100KHz, and 1MHz. Underlying mechanisms for the SN-PSD functionalities will be discussed.

Gallium nitride (GaN) power devices have become one of the most promising candidates for applications in power electronic systems, offering remarkable improvements in energy conversion efficiency, switching frequency, and system volume. As one of the most important fundamental building blocks of semiconductor electronic devices, p-n junctions, created by doping methods using ion implantation, diffusion of dopants, or epitaxy, are also of great importance in fabricating GaN power devices. However, they are still difficult to implement for GaN, especially regarding p-type doping. It was found that GaN was not very resistant to ion beam disordering and this problem became more severe at higher dose ion implantation. For diffusion of dopants, the understanding of this process in GaN is also in its infancy. Epitaxy on GaN substrates may partly solve these issues due to the reduced dislocation density in the materials and doping during growth is still the most effective way to get well-controlled doping. Moreover, to fabricate high-performance GaN power devices and integrated-circuits, selective-area doping is indispensable. However, some physical mechanisms are still not clear, especially on regrown p-GaN. In this work, to mimic selective-area doping, p-GaN was regrown on an etched GaN surface on GaN substrates by metalorganic chemical vapor deposition. Vertical GaN-on-GaN p-n diodes were fabricated to investigate the effects of the etch-then-regrowth process on device performance. The crystal quality of the sample after each epitaxial step was characterized by X-ray diffraction, where the etch-then-regrowth process led to a very slight increase in edge dislocations. A regrowth interfacial layer was clearly shown by transmission electron microscopy. Strong electroluminescence was observed with three emission peaks at 2.2 eV, 2.8 eV and 3.0 eV, respectively. The 2.2 eV peak was related to the well-known yellow luminescence in GaN, which is due to capture of conduction band electrons by a deep acceptor level centered at 2.2 eV below the conduction band edge (CBE). The 2.8 eV peak originated from the donor-acceptor pair (DAP) luminescence, i.e., the transition from a deep donor level (~ 0.4 eV below the CBE) to the Mg acceptor level which is ~ 0.2 eV above valence band edge (VBE). The forward current density increased slightly with the increasing temperature, while the reverse current density was almost temperature independent indicating tunneling as the reverse transport mechanism. This result is very similar to the reported Zener tunnel diode comprising a high doping profile at the junction interface. High levels of silicon and oxygen concentrations were observed at the regrowth interface with a distribution width of ~100 nm. This work provides valuable information of p-GaN regrowth and regrown GaN p-n diodes, which can serve as an important reference for developing selective doping for advanced GaN power electronics for high voltage and high power applications.

Gallium oxide, one of the promising ultrawide-bandgap material, has recently attracted considerable interest because of its potential for high power application and cost-effective growth. Its large bandgap (4.8 eV) and high breakdown electric field (8 MV/cm) result in superior energy density capabilities. The critical field strength of gallium oxide is more than 20 times that of silicon and more than twice that of silicon carbide and gallium nitride. The BFOM of gallium oxide is at least four times larger than those of SiC and GaN, indicating its great potential for high power application. Another advantage of gallium oxide is the availability of cost-effective single-crystal substrates. The edge-defined film-fed growth (EFG) method, described by Labelle and Mlavsky, is one of the main methods to grow large-sized β-Ga₂O₃ substrates, as its relatively low cost and scalability make it aptly suited for use in mass production. Electronic devices such as field effect transistors (FETs) and Schottky barrier diodes (SBDs) and optoelectronic devices such as solar-blind photodetectors fabricated on the β-Ga₂O₃ substrates have been reported. However, the mechanism of the temperature-dependent performance of these devices is still not very clear. The non-ideal properties including (i) temperature-dependent Schottky barrier height and (ii) ideality factor and (iii) unreasonably small extracted Richardson constant cannot be easily explained by traditional thermionic emission theory with a homogeneous barrier. Similar behavior has been observed for a-IGZO, nanocrystalline ZnO, and ZTO. As a result, in this paper, a modified thermionic emission model over an inhomogeneous barrier having a voltage-dependent barrier height has been investigated and used to explain these non-ideal phenomena.

While current magnetic RAM devices have demonstrated impressive speed, endurance, and retention, the power requirements for this technology still represent a key challenge for its widespread adoption. The ability of a spin Hall material to switch the spin orientation of a neighboring magnetic layer could serve as a key element in future low-power spin-orbit torque (SOT) MRAM devices. The spin Hall angle is given by the ratio between the induced transverse spin Hall conductivity due to spin-orbit interactions and the longitudinal electrical conductivity. While a high spin Hall angle is important, it is also critical to ensure low electrical resistance in order to develop energy efficient memory. In this work, we use first principle approaches to calculate the spin Hall conductivity in leading spin Hall materials: β-W (A15), β-Ta, and Pt-based alloys. We first calculate and confirm the fully relativistic Fermi surfaces and band structures for these materials using multiple ab-initio approaches, including plane wave formalisms (VASP, Quantum Espresso [1, 2]) and a relativistic Korringa-Kohn-Rostoker (KKR) approach [3]. The intrinsic spin Hall conductivity is calculated using two independent implementations of the Kubo formula based on the Berry curvature [4,5,6]. For β-W, we predict intrinsic spin Hall angles ranging from 0.24 (bulk) to 0.45 (film) in excellent agreement with experiments [7,8]. The spin Hall conductivity in β-W is sharply peaked just below the Fermi energy and the origin of this peak can be traced to closely spaced spin-orbit split bands near the Fermi energy. We will discuss how symmetry breaking in the A15 crystal phase leads to enhanced spin Hall conductivity and how this could potentially be leveraged in other materials. Calculations for Ta doped β-W show that the spin Hall conductivity peak can be shifted to the Fermi energy, boosting the spin Hall conductivity and angle by ~20%. This finding agrees with results from a recent study based on plane wave projection to maximally localized Wannier functions [9]. Since oxygen and nitrogen are often used to stabilize the metastable β-W, we also examine the potential impact of these dopants on the electronic structure and spin Hall conductivity. Predicting the spin Hall conductivity in the β-Ta is particularly challenging computationally due to the large tetragonal unit cell with 30 atoms. Our spin Hall conductivity predictions for β-Ta are in good agreement with experiments and our results indicate that the local β-Ta atomic environment could be similar to that found in the A15 phase. Finally, using a virtual crystal approximation, we examine the intrinsic spin Hall conductivity in Pt based binary alloys. We find good agreement with measured spin Hall conductivity for most of the composition range and the deviations from the predicted values can be traced to skew scattering contributions. Taken together, these three different material systems provide important insight on how the crystal structure and doping in a material can be tailored to boost spin Hall conductivity.


[1] G. Kresse and J. Hafner: Phys. Rev. B 47, 558 (1993).
[2] P. Gianozzi et al, J. Phys. Condens. Matter 29, 465901 (2017).
[3] M. Gradhand et al: Phys. Rev. B 80, 224413 (2009).
[4] M. Gradhand et al: Phys. Rev. B 84, 075113 (2011).
[5] P. D’Amico et al: Phys. Rev. B 94, 165116 (2016).
[6] M. B. Nardelli et al: Comp. Mat. Sci., 143, 462 (2018).
[7] C. F. Pai et al: Appl. Phys. Lett. 101, 122404 (2012).
[8] K. U. Demansius et al., Nat. Comms., 7, 10644 (2016).
[9] X. Sui et al: Phys. Rev. B, 96, 241105 (2017).

Perpendicular magnetic materials with low damping constant and high thermal stability have great potential for realizing high-density, non-volatile, and low-power consumption spintronic devices, which can sustain operation reliability for high processing temperatures. In this work, we study the Gilbert damping constant (α) of perpendicularly magnetized W/CoFeB/MgO films with a high perpendicular magnetic anisotropy (PMA) and superb thermal stability. The α of these PMA films annealed at different temperatures (T_ann) is determined via an all-optical Time-Resolved Magneto-Optical Kerr Effect (TR-MOKE) method. We find that α of these W/CoFeB/MgO PMA films decreases with increasing T_ann, reaches a minimum of α = 0.015 at T_ann = 350 °C, and then increases to 0.020 after post-annealing at 400 °C. The minimum α observed at 350 °C is rationalized by two competing effects as T_ann becomes higher: the enhanced crystallization of CoFeB and dead-layer growth occurring at the two interfaces of the CoFeB layer. We further demonstrate that α of the 400 °C-annealed W/CoFeB/MgO film is comparable to that of a reference Ta/CoFeB/MgO PMA film annealed at 300 °C, justifying the enhanced thermal stability of the W-seeded CoFeB films. Further, we discuss the dependence of the TR-MOKE signal on the magnitude and angle of the applied field, by utilizing a numerical algorithm based on the Landau-Lifshitz-Gilbert equation. The optimized operational conditions that produce the largest TR-MOKE signals are predicted and confirmed.

Thin film transistors (TFTs) with high electrical performances (mobility > 10 cm² /Vs, V_th < 1 V, SS < 1 V/decade, on/off ratio ~ 10⁶) obtained from the silicon and oxide-based single-crystalline semiconductor materials require high processing temperature and hence not suitable for flexible electronics. Amorphous oxide based transparent electronic devices are attractive to meet emerging technological demands where crystalline oxide/silicon-based architectures cannot provide a solution. Here, we tackle this problem by using a novel amorphous oxide semiconducting material—namely indium tungsten oxide (IWO)—as the active channel in flexible thin film transistors (FTFTs). Post-annealing temperature at as low as 270^oC for a-IWO thin films deposited by RF sputtering at room temperature could result in smooth morphology (R_rms ∼ 0.42 nm), good adhesion and high carrier density (n ∼7.19 × 10¹⁸ cm⁻³). Excellent TFT characteristics of flexible devices could be achieved with linear field effect mobility µ_FE ~ 25.86 cm²/Vs, sub-threshold swing SS ~ 0.30 V/decade, threshold voltage V_th ~ -1.5 V, on/off ratio I_on/I_off ~ 5.6×10⁵ at 3V and stable operation during bending of the FTFT. Additionally, IWO TFTs were implemented as synapses, the building block for neuromorphic computing. Paired-pulse facilitation (PPF) up to 138% was observed and showed an exponential decay resembling chemical synapses. Utilizing this characteristic, high-pass dynamic temporal filter was devised providing increased gain from 1.55 to 21 when frequency was raised from 22 to 62 Hz. The high performance and stability of flexible TFTs obtained with IWO films demonstrate their promise for low voltage electronic applications.