Call for Papers

Please contact the symposium organizers with questions.

Even as conventional Cu/ULK interconnect technology has slowed in recent years due to challenges in both ultra-low k integration and metal barrier scaling, a plethora of options are being investigated for technology nodes below 10 nm, including new conductors, dielectrics, barrier layers, and process integration methods. In parallel, emerging packaging technology such as 2.5D/3D ICs integration are demonstrating means to improve circuit density and performance. Technologies including Through Silicon Vias are increasingly utilizing recent interconnect material and process advances to further packaging innovations. Finally, using interconnects as a backbone, the introduction of additional functionality in the BEOL has constituted new areas of research and opportunity. This session will focus on both continued advances in conventional interconnect technology and new emerging areas. Topics will include advances in ILD materials and integration, novel etch stop and hard-mask materials, advanced metallization materials and processes, area selective deposition and supervia scaling boosters, alternatives to conventional interconnect technology (3D, optical interconnects) and the introduction of additional functionalities in the BEOL.

Topics will include:

• ILD Materials ULK synthesis, spin-on, sol-gel, fillable, flowable, PECVD precursors, MOF/COF, POC, PMO, photo-patternable low-k
• Novel etch stop and hardmask materials
• Selective Depositions–Metal on Metal (MoM), Metal on Dielectric (MoD), Dielectric on Dielectric (DoD), Dielectric on Metal (DoM)
• Alternative to Cu/ULK interconnects 3D integration through silicon vias, bonding, thinning
• Introduction of additional functionality in the BEOL BEOL interconnect novel materials research
• Reliability, failure analysis methods and techniques electromigration
• Applications of interest, Advanced interconnects–optical, wireless, C-based, beyond Cu, based on 1D or 2D materials
• Metallization for advanced interconnects CVD, PVD, ALD, ECD, ELD advances in liner, Cu seed, and fill
• Metal resistivity modeling, alternative metallization approaches for the tightest pitch
• Barrier-free metallization and self-forming barriers, bottom-up metallization schemes
• RIE, plasma processing, planarization, and cleaning technologies
• Directed assembly technology and molecular self-assembling technologies
• Surface modification for ALD/CVD/ELD and self-assembled monolayer (SAM)/polymer deposition
• TDDB Mechanical stability during integration (LER, LWR, line wiggling and pattern collapse) and CPI
• BEOL capacitors, transistors, resistive RAM and sensors device design, electrical testing and reliability
• Advanced process characterization design-technology co-optimization modeling techniques

Invited Speakers:

• Griselda Bonilla (IBM T.J. Watson Research Center, USA)
• Jasmeet Chawla (Intel, USA)
• Remi Dussart (Université d'Orléans, France)
• Jacques Faguet (Tokyo Electron Limited, USA)
• Daniel Gall (Rensselaer Polytechnic Institute, USA)
• Mikhail Krishtab (imec, Belgium)
• Vincent Larrey (CEA-LETI, France)
• Murugesan Mariappan (Tohoku University, Japan)
• Naoya Okada (National Institute of Advanced Industrial Science and Technology, Japan)
• Suketu Parikh (Applied Materials, Inc., USA)
• Rikka Puurunen (Aalto University, Finland)
• Kavita Sha (Nova Measuring Instruments Ltd., USA)
• Mayumi Takeyama (Kitami Institute of Technology, Japan)
• Rudy Wojtecki (IBM T.J. Watson Research Center, USA)

Symposium Organizers