Resistive switching RAM (RRAM) represents one of the most promising future emerging technologies for post-Flash high density memories [1] due to their low power, high speed and great scalability. However, many issues still remain to be solved, in particular in the low current regime, where variability of relevant parameters, such as high and low resistance states [2-4], and random telegraph noise (RTN) [4-8] constitute serious obstacles to the reliability of the technology.
In this paper we address variability with a novel Monte Carlo model. Based on a Poisson statistic [2-4], set and reset transitions are seen as an injection of ions, or defects, each of them facing different Coulomb barriers which facilitate or, instead, block their motion inside the oxide layer. In this way, high current compliances lead to low variability due to the fact that many defects are injected, thus the effect of the random barriers is averaged. On the contrary, low current compliances bring elevated variability due to the reduced number of injected defects, hence no average effect is present. The model allows for a description of the switching statistics of high-low resistance, reset current and voltage, thus providing an extensive physical vision of the phenomenon.
Another issue is RTN noise that affects the resistance states at low voltages. The origin resides in the random fluctuation of a trap between two states, e. g. neutral and negative charge. Two dependences can be found. One is the size-dependence of the fluctuation [5,9,10], in fact the relative resistance change is related to the conductive filament diameter. In fact, the trap partially or totally depletes from electrons the conductive filament, obtaining lower or higher RTN fluctuations. To capture this effect, a 3D finite element model has been implemented, which solves the carrier transport equations and gives a detailed vision of the RTN transition. The second dependence is instead related to the bias [3], namely, switching times from one resistance state to the other are thermally activated through the Joule heating produced by the flowing current, hence the transition rates increase at higher voltage, leading to an average between the two resistance states. To model the RTN kinetics, the model also solves the Fourier equation, giving the temperature in the trap's position and, thus, the transition rates.
[1] K. Prall, et al., Proc. IEEE IMW 1 (2012).
[2] S. Balatti, et al., IEEE Electron Device Lett. 34, 861 (2013).
[3] S. Ambrogio, et al., IEDM Tech. Dig., 31.5, (2013).
[4] A. Fantini, et al., Proc. IEEE IMW 30 (2013).
[5] D. Ielmini, et al., Appl. Phys. Lett. 96, 053503 (2010).
[6] Y.-W. Lian, et al., IEEE Electron Device Lett. 33, 973 (2012).
[7] F. M. Puglisi, et al., Solid-State Electronics 84, 160 (2013).
[8] P. Huang, et al., IEDM Tech. Dig. 2661 (2012).
[9] K. S. Ralls and R. A. Buhrman, Phys. Rev. B 44, 5800 (1991).
[10] R. Soni, et al., J. Appl. Phys. 107, 024517 (2010).

A Resistive RAM is a resistor with memory functionality: Its resistance can be electrically tuned and “stored” in a nonvolatile way. It can be very simply fabricated from a metal-insulator-metal structure. Despite large research efforts, resistive device applications are only at the emerging stage, and basic research is still needed. Though it is now accepted that resistance variation proceeds through defects creation in OxRAM, several hypothesis have been put forward to explain defects origin, such as redox reactions at electrodes or field-induced defect generation in the bulk.
We have previously discussed on a global model for the understanding and optimization of mechanisms at the origin of Set and Reset processes in HfO2 OxRAM [1]. We have shown that oxygen vacancies are mainly created by hot electron injection, with preferential injections through grain boundaries as proposed by Bersuker et al[2]. The bottom electrode work function as well as the built in potential of the device control the injection mechanisms and so the “filament” strength and the reset capability. Top electrode morphology and its affinity to oxygen impact the reset of the device (an oxygen reservoir effect with back-diffusion of oxygen ions). Most of these results were obtained thanks to the complementary study of MIM devices through I-V cycles and CVS (constant voltage stress measurements) [3-4].
We propose here to show how, by combining I-V cycles, CVS and CCS (constant current stress), one can obtain information on the nature of the conductive “filament”. This is illustrated by using several different metals as top and bottom electrodes. As an example, with silver as top electrode, the HfO2 MIM device behaves as a CBRAM while it is OxRAM with gold. For these two examples, absorption current following by SILC (stress induced leakage current) is observed in the CVS mode with gold while only the absorption current is observed with silver. With copper the memory presents a reduced forming voltage, also observed with Ti, which can help to decrease the high overshoot current and so improve the reliability of devices. Therefore impact of copper and the metallic ions diffusion or not through the oxide is discussed. Depending on the metallic electrode nature, I(t) curves obtained in the CVS mode may show a parabolic behaviour: the current is found to increase, to reach a maximum and then to decrease as a function of time. This effect is more pronounced for electrode with high thermal conductivity such as tungsten. Based on this result, impact of the thermal conductivity on reset is discussed. In the same manner, the constant current stress shows several different behaviours as a function of the metallic electrode.
[1] C. Mannequin et al, MRS Spring Meeting 2013
[2] G. Bersucker et al, J. Appl. Phys.110 (2011) 124518
[3] C. Mannequin et al, J. Appl. Phys.112 (2012) 074103
[4] P. Gonon et al, J. Appl. Phys.107 (2010) 074507

One of the major issues in RRAM technology, which may jeopardize its introduction as a viable non-volatile option for NAND replacement, is variability of device characteristics, both device-to-device and cycle-to-cycle in the same device. In order to mitigate excessive variability, we need to identify its sources, which may have both as-fabricated (initial structure) and operation-induced (associated with forming and set-reset processes) components. Variations in the conductivity of high and low resistive states are intrinsically linked to a physical mechanism governing RRAM transitions between these states. In this presentation, we discuss the RRAM dielectric structural features, which determine device operation processes and contribute to RRAM variability.

There is presently an extensive effort to develop non-volatile resistive random access memories (RRAM) based on metal oxides, particularly those made of high K oxides such as HfO2. The general storage processes have been described by Waser et al [1], DeGraeve [2], Bersuker [3], Shiraishi [4] and others. The experimental performance of the different oxides has been compared [5]. It is interesting to understand the detailed atomistic processes in order to understand the best material. The general mechanism is that a conductive filament of oxygen vacancies is formed across the film in a forming step; oxygen vacancies then migrate towards the tip of a partly formed filament, or disperse away from this tip into the oxide, in the SET and RESET processes. The filament in the ON state has a metallic conductivity with small positive temperature coefficient of resistance, but is strongly semiconducting in the OFF state. The partly formed filament acts as a metallic tip, with a high electric field at its tip. Charged oxygen vacancies migrate towards this tip. Inside the tip is metallic, with no electric field, so further increases in vacancy concentration are not needed. The high current density in the filament also creates O vacancy/ O interstitial Frenkel pairs.
The energy parameters of these various processes are calculated at the M/MOx oxygen chemical potential (O poor limit). The migration barriers in the different charge states, and the various 0/n+ transition levels with respect to the work functions of the metal electrodes are calculated, for the popular oxides, HfO2, TiO2, Ta2O5, Al2O3. Al2O3 has the largest migration barriers and defect formation energies. Ta2O5 the smallest migration barriers.
1. R Waser, et al, Adv Mats 21 2632 (2009)
2. R DeGraeve, et al, Tech Digest VLSI (2013)p8.1; Tech Digest VLSI (2012); S Clima et al, APL 100 133102 (2012); L Roux, et al, VLSI (2013) T12-1, S Clima, Microelec Eng (2013)
3. G Bersuker, et al, JAP 110 124518 (2011)
4. K Shiraishi et al, SSDM (2014) A7-1; K Kamiya et al, APL 100 073502 (2012); PRB 87 155201 (2013)
5. J J Yang et al, Nature Nanotechnol 3 429 (2008)

Oxygen vacancy motion and agglomeration into Magnéli phases are regularly associated with resistive switching in TiO2. However, correlations between resistivity states and defect distributions are poorly linked and require direct analysis. This study reports in situ electrical biasing of TiO2-based resistive switching devices inside the transmission electron microscope (TEM). Metal-Insulator-Metal (MIM) devices consist of W/TiO2/TiN layers fabricated by sputtering TiN on single-crystal rutile TiO2 substrates, extracting ~1.5 x 3 µm specimens and electron-beam depositing W inside a focused ion beam (FIB) system. The devices are extracted, thinned to electron transparency, and mounted to W probes inside the FIB. The in situ TEM experiments were performed using a nanomanipulated W probe to contact the device and apply electrical bias. TEM analysis coordinated with electrical biasing shows that electroformation induces Magnéli phase formation at the W/TiO2 interface that eventually leads to an abrupt resistivity drop. Further biasing extends the Magnéli phase region across the entire TiO2 layer towards the TiN interface. Selected area diffraction pattern analysis observed satellite reflections along <011> directions consistent with {011} shear structures and satellite reflection spacings consistent with oxygen deficient Magnéli phases that have metallic conductivity. Resistive switching behavior was observed in the current-voltage measurements during successive voltage sweeps. Resistivity states could also be associated with an observed ~50nm Magnéli phase free zone at the TiO2/TiN interface. Wadsley defects associated with oxygen vacancy accumulation were observed in this zone when the device was at a low resistance state and disappeared when the device was switched to the high resistance state. Further interpretation of these results is corroborated by finite element modeling of electric field and temperature distributions within the device during electrical biasing. Implications for device design and interpretation of defect influences on the acting resistive switching mechanism is discussed.

Thin film metal-insulator-metal (MIM) tunnel devices have experienced a renewal in interest for high speed applications such as optical rectennas for IR energy harvesting, IR detectors, hot electron transistors, and macroelectronics. For many of these applications, figures of merit include high asymmetry, strong nonlinearity, and fast responsivity of current vs. voltage (I-V) behavior at low voltages. The standard approach to achieving high speed rectification in an MIM device is based on Fowler-Nordheim tunneling (FNT) conduction, in conjunction with the use of asymmetric work function metal electrodes (where Phi;_M1 ne; Phi;_M2) to produce an asymmetric, polarity dependent electron tunneling barrier. The properties of single layer MIM diodes are dominated by the choice of insulator. We first report the conduction mechanism and performance of a variety of MIM devices fabricated on ultra-smooth amorphous metal bottom electrodes (ZrCuAlNi or TaN) using a variety of insulators deposited via atomic layer deposition (ALD Al₂O₃, Nb₂O₅, Ta₂O₅, HfO₂, SiO₂, and ZrO₂) and Al top electrodes. Al₂O₃, HfO₂, and SiO₂, were found to be dominated by Fowler-Nordheim conduction. In contrast, Ta₂O₅, Nb₂O₅, and ZrO₂ were found to be dominated by Schottky emission at low fields and Poole-Frenkel emission (PFE) at higher fields. The energy depth of the traps that dominate PFE in each material are estimated and are found to correspond with the energy depth of sputter induced oxygen-vacancies measured via reflection electron energy loss spectroscopy (REELS).¹ Narrow bandgap dielectrics such as Ta₂O₅ and Nb₂O₅ are attractive for MIM diodes because the small barrier heights allow for low turn-on voltages. However, because conduction is based on emission, rather than tunneling, these materials may not be suitable for high speed rectification. Recently, we showed that a nanolaminate pair of insulators (Al₂O₃/HfO₂) can be used to form MIIM diodes with enhanced performance over single layer MIM diodes and demonstrated that observed enhancements in low voltage asymmetry are due to "step tunneling," a situation in which an electron may tunnel through only the larger bandgap insulator instead of both.² Because MIIM diodes based on step tunneling require only one of the dielectrics to be dominated by tunneling, narrow bandgap dielectrics dominated by thermal emission may be combined with wider bandgap dielectrics dominated by tunneling to enable low turn-on voltage high asymmetry MIIM diodes. In this presentation, we will discuss the performance of a variety of bilayer MIIM diodes (Al₂O₃/Ta₂O₅, HfO₂/Ta₂O₅, ZrO₂/Ta₂O₅, Al₂O₃/ZrO₂, and HfO₂/ZrO₂). These results represent an additional way to engineer MIM diode operation and advance the understanding needed to manufacture high quality thin film tunnel devices for microelectronics applications.
1. S.W. King, B. French, and E. Mays, J. Appl. Phys. 113, 044109 (2013).
2. N. Alimardani and J.F. Conley, Jr., Appl. Phys. Lett. 102, 143501 (2013).

Electronic memory relying on charge trapping always faces a voltage-time dilemma: it requires a high-energy barrier for data retention (>10 years) under zero/low electrical stimuli, yet it incompatibly demands a low-energy barrier for fast programming (<100 ns) under a modest programming voltage. The dilemma may be avoided by using a high-temperature programming step, but such solution causes excessive power or damage. The dilemma thus poses a serious road block to stable yet ultrafast charge-trapping devices, such as resistive switching random access memory (RRAM).
Using a localized electron-phonon interaction as an atomic-level lever to readjust the barrier height, we have engineered a reconfigurable barrier and resolved the dilemma. We implemented this solution in nanometallic RRAM, which employs “flexible” amorphous materials with strong-electron-phonon-interaction sites where trapped electrons see a reconfigurable barrier— higher during storage and lower during programming. The interaction first converts a trapped-electron state from an unstable positive-U state to a stable negative-U state; later, its unraveling during re-programming leads to the demise of the trapped-electron state.
We present the first real-time evidence for such action using a single 10^-13 s mechanical impulse, which originates from the Lorentz force induced by an ~10^-13 s electron burst in SLAC National Accelerator Laboratory. It triggers bond distortion, reverses the stabilizing electron-phonon interaction, and causes switching from the trapped-electron state (high-resistance state) to the free-electron state (low-resistance state), without any voltage. The nanometallic RRAM can retain long-term memory and reprogram at a sub-picosecond speed, making it suitable for universal memory and possibly other applications.
References:
1. Nature Nanotechnology, 6, 237 (2011)
2. Advanced Materials, 23, 3847 (2011).
3. Advance Functional Materials, 22, 546 (2012).
4. Scientific Reports 2, 744 (2012)
5. ACS Nano 7, 2302 (2013)

Memristive devices (also known as RRAM when used for memory) are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage or current, which can be used to store and process information for computing systems beyond CMOS technologies. These devices have shown great scalability, switching speed, non-volatility, analogue resistance change, non-destructive reading, 3D stack-ability, CMOS compatibility and manufacturability. However, there are still a number of challenges facing memristive devices for real applications, including device variability and isolation in a crossbar array. This talk will discuss and address these challenges from the materials perspective.

Resistively switching devices have attracted great attention for potential use in future nonvolatile information storage. Their resistance can be changed by applying appropriate voltages. This resistive switching effect has been observed in a variety of oxide materials, e.g. SrTiO3, TiOx or TaOx. Prior to actual resistive switching of valence change memory cells an electroforming step is typically required. This initial electroforming step impacts device performance and switching variability. Thus, a thorough understanding of the physical processes involved in the electroforming process is fundamental for device optimization.
In this study, the electroforming process in strontium titanate (STO) single crystals is made visible. Transparent samples of Fe doped STO single crystal were put under temperature and longitudinal electrical stress and observed by means of high resolution transmission optical microcopy, whereby the voltage and current were being logged with time and the sample was continuously captured with a camera. For the experiment a custom sample enclosure was constructed.
In the electrocoloration process, color changes within the sample are caused by a valence change of the Fe ions, and accordingly by drift of oxygen vacancies. The colorful regions are growing and propagating towards the electrodes. At the anode Fe atoms are reduced and thus form a dark brown region, while at the cathode they are oxidized and the color turns to bright yellow. The redox reaction is therefore an indirect proof of the oxygen vacancy drift-diffusion in the bulk.
Time development and behavior of the color areas within the sample are influenced by multiple factors (voltage, current, temperature, dopant and defect concentration, ambient atmosphere, time, etc.). We study the influence of the particular parameters by capturing the progression of electrocoloration at several samples. The measurements show current and resistance change over time along with sample visual mapping.
The behavior is to some extend similar to previous published findings [1], [2], but also new phenomena are observed, i.e. the formation of lines and impermanent spots in the bulk. These are analyzed by different ex-situ characterization techniques (EDX, mösbauer spectroscopy, AFM, etc.). Furthermore, 1D drift-diffusion simulations of the temporal evolution of the oxygen vacancy distribution are performed, which represent well the initial progress of the virtual cathode region.
[1] J. Blanc, Physical Review B, 4, 3548-3557, 1971
[2] R. Waser, Journal of the American Ceramic Society, 6, 1654-1662, 1990

Nanoelectromechanical systems (NEMS) switches are a candidate "beyond CMOS" technology, with a key benefit being massively reduced power consumption. However, the reliability of the contact interface is a principal challenge for the commercialization of NEMS switches, as the electrically conducting contacting surfaces need to be able to open and close up to a quadrillion times without suffering from excessive adhesion, wear, or contamination. These failure mechanisms are not well understood, and materials that can exhibit the needed performance have not yet been demonstrated.
To develop a better understanding of the failure mechanisms, we developed a nanoscale electrical contact testing method based on atomic force microscopy (AFM) that enables billions of contact cycles in laboratory timeframes. Single asperity Pt-Pt contacts were cycled using forces and environments representative of NEMS switch operation. Contact resistance increased by up to six decades due to cycling-induced growth of insulating tribopolymer at rates that were enhanced when cycled in humid air or under the presence of a voltage. Sliding of the contact led to recovery of conductivity through displacement of the tribopolymer, suggesting a route for ameliorating contamination-induced failure.
Second, to achieve desirable switch performance, we have canvassed compatible material sets to identify those that are highly conductive, minimally adhesive, chemically inert, mechanically robust, and amenable to CMOS fabrication processes. One promising candidate is platinum silicide (Pt_xSi). Successful integration of Pt_xSi contacts into many NEMS switch architectures requires the use of amorphous silicon (a-Si), a relatively unexplored approach compared to the use of single crystal Si. We have performed the first direct characterization of the mechanical and electrical contact properties of Pt_xSi of multiple stoichiometries, formed through controlled diffusion of a-Si and platinum (Pt), in comparison with pure Pt. The silicides were produced from bilayer a-Si/Pt film stacks inside a X-ray photoelectron spectroscopy (XPS) system for in situ quantification of stoichiometry as a function of temperature and annealing time. PtSi, Pt₂Si and Pt₃Si phases could be identified and distinguished, and layers of Pt and a-Si of approximately equal thickness were shown to favor Pt-rich silicides (Pt₂Si and Pt₃Si) instead of the PtSi phase commonly observed in Pt/sc-Si silicidation. The silicides demonstrated only modest increases in contact resistance and significantly improved mechanical properties. We also demonstrate that Pt_xSi can be used to release NEMS switches with a self-formed gap caused by interfacial separation driven by shrinkage-induced tensile stress. This indicates that a-Si thickness has a direct impact on stoichiometry, which can thus be easily tuned to obtain desired properties.

In0.53Ga0.47As and atomic layer deposited (ALD) Al2O3 are among the candidates channel and dielectric materials, respectively, for future high performance III-V n-channel MOS devices. In particular, the ability to achieve large band offsets and a thermally stable interface with Al2O3 makes it an interesting choice for an interlayer dielectric between an InGaAs channel and higher-k materials. Achieving a low density of electrically active defects at the interface has been a long-standing challenge for all deposited dielectrics on III-V arsenide channels. Moreover, traps in the oxide layer may also reduce the charge in the channel and thus degrade the on-state performance of InGaAs MOSFET devices. In this presentation, we describe approaches to passivate the interface and bulk oxide defects with various treatments, like large-dose exposure of the InGaAs surface to trimethyl-aluminum (TMA) prior to ALD, atomic hydrogen dosing, and either post-ALD or post-gate metal forming gas (5% H2/95% N2) anneals (FGA).
Experimental methods employed include quantitative interface trap and oxide trap modeling[1, 2] of MOS capacitor data obtained over a range of frequencies and temperatures. We also perform x-ray photoelectron spectroscopy to characterize possible film stoichiometry changes during annealing and the oxidation state of In, Ga and As at the dielectric/channel interface. These ex-situ data will be compared with the results of in-situ scanning tunneling microscopy/spectroscopy for certain passivation schemes[3, 4]. The effects of pre- and post-dielectric defect passivation schemes will be examined for ALD-Al2O3 samples prepared on both initially-clean and well-ordered As2-decapped In0.53Ga0.47As substrates and on initially air-exposed substrates. Relevant comparisons to low-temperature ALD-grown HfO2 films on InGaAs substrates will also be reported.
References
1. H. Chen, Y. Yuan, B. Yu, J. Ahn, P.C. Mcintyre, P.M. Asbeck, M.J.W. Rodwell, and Y. Taur, IEEE Transactions on Electron Devices 59, 2383 (2012).
2. Y. Yuan, B. Yu, J. Ahn, P.C. Mcintyre, P.M. Asbeck, M.J.W. Rodwell, and Y. Taur, IEEE Transactions on Electron Devices 59, 2100 (2012).
3. W. Melitz, T. Kent, A.C. Kummel, R. Droopad, M. Holland, and I. Thayne, The Journal of Chemical Physics 136, 154706 (2012).
4. W. Melitz, J. Shen, T. Kent, R. Droopad, P. Hurley and A. C. Kummel, ESCS Transactions, 35(4) 175-189 (2011)

Two of the leading materials considered for use in post silicon n-channel regions of planar-FETs and finFETs are SiGe and InGaAs, as both of these alternatives contain high intrinsic electron mobilities. A broader range of channel materials allowing better carrier confinement and mobility could be employed if a universal control monolayer (UCM) could be ALD or self-limiting CVD deposited on multiple materials and crystallographic faces. Si-OH is a leading candidate for use as the UCM, as silicon uniquely bonds strongly to all crystallographic faces of InGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge enabling transfer of substrate dangling bonds to silicon, which is then readily passivated by atomic hydrogen or molecular H2 (g). The surface may subsequently be functionalized by dosing with an oxidant such as HOOH(g) in order to create the UCM terminating Si-OH layer which would react with nearly any ALD precursor. This process serves in eliminating the need for metal precursor nucleation, decreasing EOT, and lowering border trap density and fixed charged associated with interfacial layers or even direct bonding of oxide to non-silicon semiconductors. This study focuses on depositing a saturated Si-H seed layer via self-limiting and saturating CVD on InGaAs(001)-(2x4) at a low substrate temperature of 250°C. XPS in combination with STS and STM were employed to study and characterize the electrical and surface properties of the saturated silicon seed layer on InGaAs(001)-(2x4).
The self-limiting and saturating CVD procedure includes a decapped In0.53Ga0.47As(001)-(2x4) surface dosed with13 MegaLangmuir of Si3H8 at a sample temperature of 250°C. The XPS spectra was recorded following the self-limiting and saturating Si3H8 CVD and shows the increase of the silicon 2p3/2 peak and the decrease in the gallium 3p3/2 peak, indicative of saturating surface coverage as compared to spectra of the clean decapped surface. Additional dosing with Si3H8 does not further increase in the silicon 2p3/2 peak nor further decrease in the gallium 3p3/2 peak areas consistent with self-limiting CVD. STM images are acquired of the In0.53Ga0.47As(001)-(2x4) surface following self-limiting and saturating CVD of Si3H8 at 250°C and post annealing, and high atomic surface order is observed.

Replacing silicon with high-mobility channel materials such as InGaAs will be surely the next evolution of MOSFET devices. Alternative materials such as High-k dielectrics and metal gates have already been successfully introduced. InGaAs based channels hold the promise of circuits operating at lower Vdd and hence consuming low power as the dynamic power roughly scales as V2dd. Two different strategies for integrating As based compounds as MOSFET channels are actually foreseen: fully depleted III-V/On Insulator or FinFET. This integration still faces many challenges like direct III-V epitaxy on Si, channel/high k interface control, and contact resistance.
We focus on the direct growth of As compounds on Si(100) 300 mm substrates. GaAs and InGaAs layers are grown by an AMAT MOCVD tool. TMIn, TMGa and TMAl are used as group III elemental precursors whereas TBAs is used as group V elemental precursor. Typical growth temperature ranges between 300 and 700°C and pressure ranges between 1 and several hundred Torr. We have studied the structural and the physical properties of GaAs, InGaAs, AlGaAs layers grown either on blanket or patterned Si(100) wafers by AFM, FIBSTEM, TEM, SIMS, µPL, cathodoluminescence, XRD. We showed an improvement of the material quality as they are elaborated in SiO2 cavity even with an aspect ratio less than 2. Antiphase boundary and dislocation densities are strongly decreased as the width of the cavity goes bellow 100 nm. By adjusting properly the growth conditions and the stack in the quantum well structure, we were able to observe room temperature micro-photoluminescence of single InGaAs QW, with In composition ranging between 10 and 53% and a total stack thickness well below 1 µm.

The scaling of logic CMOS devices requires the use of high mobility semiconductor channel materials such as InGaAs. However, the interfaces of III-V and high K oxides such as Al2O3 and HfO2 can still possess a high interface state density, D_it. Various methods have been used to lower this density, such as choice of oxide, and recently the use of nitrogen treatment of the interface. We have calculated that the replacement of the last layer of the III-V by an Al-N layer greatly reduces the interface defect state density, because N-N dimers do not form, N dangling bond states are deep in the valence band and Al dangling bond states lies higher in the conduction band [1]. This result was recently confirmed experimentally [2,3]. Here, we extend these calculations to other III-Vs such as InGaSb and GaSb where a similar behavior is found.
1. Y Guo, L Lin, J Robertson, App Phys Lett 102 091 606 (2013)
2. T Aoki et al, Tech Digest SSDM (2013) J-8-3
3. V Chobpattana... S Stemmer, App Phys Lett 102 022907 (2013)

Since the fundamental material properties of Si start to limit the ultimate scaling of nanoelectronics, new materials will have to be introduced to continue the performance scaling. Germanium, various III/V compounds, nanowires and 2D materials, such as graphene or MoS2 are potential candidates to become the next generation high mobility channel material in highly scaled devices. Direct growth of both Ge and III/V in Si STI trenches is a very attractive option for co-integration of these materials on bulk Si substrates. Gate stack optimization on Ge and III/V is a major challenge but at present various solutions are available and it can be expected that Ge and III/V will find their way into advanced technologies in the near future, either in FinFET structures or in nanowires grown directly on Si. Ultimately power consumption rather than speed is limiting the scaling roadmap. Tunnel-FETs, based on III/V or graphene, can provide good performance at lower power consumption by virtue of their improved subthreshold behavior. The combination of new materials and devices generates exciting possibilities for future technologies and will allow to continue the scaling of nano-electronics beyond the Si roadmap.

We demonstrate, for the first time, high-performance GaAs devices (nMOSFETs and pMOSFETs) that are integrated into CMOS circuits (inverters, NAND and NOR logic gates, and five-stage ring oscillators). These devices were enabled by the high-quality interface of single-crystalline La2O3 grown on GaAs(111)A by atomic layer epitaxy.

A tunnel field-effect transistor (TFET) is expected to have the feasibility of apply voltage scaling because the carrier injection by the band-to-band tunneling in TFET allows us to yield steep subthreshold swing (SS) below 60 mV/dec, which is the lower limit of conventional MOSFETs. Therefore, TFETs have attracted much attention as a strong candidate for low power device applications. However, the reported results of Si TFETs show low drain current due to the large band gap. One of the feasible solutions for mitigating this problem is to employ a Ge/Si hetero-junction source structure. A Ge/Si hetero-structure with staggered type-II band alignment can effectively reduce tunneling width in the source junction, which can simultaneously satisfy the high on/off current ratio and steep SS in the TFET operation.
In the Ge/Si hetero TFETs, tunneling currents are generated near the Ge/Si junction and, therefore, a formation of high quality Ge with abrupt doping profile and high doping concentration in Ge is important. Ion implantation for doping in Ge layers can cause generation of many defects in the Ge layers. Moreover, the formation of abrupt Ge/Si hetero-structure is very difficult because the Ge atoms can diffuse into Si during annealing.
Therefore, we grow Ge layers with in-situ boron doping by molecular beam epitaxy at extremely low temperature of 200 °C. In this study, the effects of Ge layers with different boron concentrations in the Ge layers on the performance of the nTFET are examined. The Ge layer as the p⁺-source is grown on SOI substrates. It is found that the device performance improvement including 4-times-higher drain current is obtained by increasing the boron-doping concentration from ~10¹⁶ cm^-3 to ~10²⁰ cm^-3. The large drain on/off current ratio over 6 orders of magnitude and steep subthreshold swing of 58 mV/dec are obtained.

Ge has been extensively investigated as a potential channel material for post-silicon CMOS because of its higher carrier motilities. However, smaller bandgap and higher permittivity of Ge causes severe junction leakage current and short channel effects (SCEs). Recently, silicon-on-insulator (SOI) structure has been widely investigated due to better electrostatic integrity. Therefore, germanium on insulator (GeOI) is a solution with same concept of SOI to suppress junction leakage and SCEs. Hence it is highly desirable to create a high quality Ge layer on Si substrates.
In this work, we fabricated GeOI structure on Si substrate utilizing ELO technique with wafer scale and then demonstrated high performance tensile-strained GeOI nMOSFETs.
Ge has nearly the identical lattice constant to GaAs, and AlAs in which epitaxial lift-off (ELO) processes have been demonstrated by sacrificially etching an AlAs layer. Therefore, with the proper epitaxy and ELO technique for Ge layer, Ge layer transfer onto disparate materials systems can be realized. First of all, a crystal Ge layer is epitaxially grown on GaAs substrate with an AlAs splitting layer. Then, the epitaxial Ge/AlAs/GaAs heterostructure bonds with Si substrates. By splitting at AlAs layer with HCl solvent, epitaxial Ge layer transfers on Si substrates.
Using this ELO-GeOI substrate, we fabricated the tensile strained accumulation-type GeOI nMOSFETs with in-situ phosphorus doped epitaxial SiGe stressors. After GeOI layer was thinned by wet etching process, SiO2 dummy gates were formed on the GeOI substrates. n+ SiGe (x = 0.7) layer was epitaxially grown by LP-CVD to induce the tensile stress to GeOI channel. After removing the SiO2 dummy gates, GeOI active areas were defined by mesa-isolation. Al2O3 as a gate dielectric was deposited by ALD process with O3 passivation and TaN metal gate was sputtered, followed by patterning using electron-beam lithography and RIE process. Finally, BEOL process was performed at the maximum temperature of 300 °C. An enhancement of 70% in the maximum of transconductance was observed in tensile-strained device with Lg = 60 nm compared to the unstrained device. A record-high drive current of 457 mu;A/mu;m at Vd = 1V and Vg-Vth = 1.5V among Ge nMOSFETs was observed due to the strain and low-parasitic resistance.
These results indicate that ELO-GeOI substrate has a high potential to realize Ge based CMOS as well as to integrate Ge devices with Si CMOS.
Acknowledgement
This work was supported by a grant from JSPS through the FIRST Program initiated by CSTP.

We have already demonstrated superior properties of GeO2/Ge gate stacks formed by high-pressure O2 [1]. An obvious disadvantage of this process, however, is that relatively thick GeO2 is necessarily formed. We have very recently found that the retarded oxidation rate of Ge in high-pressure O2 by slightly decreasing the oxidation temperature [2]. This is quite promising because we can achieve ultra-thin and high quality GeO2/Ge gate stacks. Furthermore, the layer-by-layer oxidation is observed [3] by oxidizing the atomically flat Ge surface [4]. Both properties are quite beneficial for Ge n-FETs with very thin GeO2 together with very high mobility at high electron density region [5].
[1] A. Toriumi et al., IEDM (2011).
[2] C. H. Lee et al., APEX (2012).
[3] C. H. Lee et al., SSDM (2013).
[4] T. Nishimura et al., APEX (2012).
[5] C. H. Lee et al., IEDM (2013).

The high hole mobility in germanium has motivated a renewed interest in this semiconductor for future electronic devices. In particular its integration as channel material in Complementary Metal Oxide Semiconductor (CMOS) architectures would improve operation speed. However, many issues still need to be addressed before Ge can be efficiently integrated in high performance MOSFETs. Among them a critical problem is to provide a high-quality interfacial layer. The recent observation by electrically detected electron spin resonance spectroscopy (EDMR) of Pb-like centers at the Ge/GeO2 interface [1-3] allowed a more systematic investigation of the passivation of this technologically relevant interface considering both the Ge(001) and the increasingly attractive Ge(111) orientations. In this work we will report on the characterization of different interfaces produced on both Ge(100) and Ge(111) substrates by Al2O3 direct growth using atomic layer deposition (ALD), and GeO2 and sulfur passivation. We will report EDMR results correlated with admittance spectroscopy of the interface traps, and deep level transient spectroscopy (DLTS) measurements.
[1] S. Baldovino, A. Molle, and M. Fanciulli, Appl. Phys. Lett. 93, 242105 (2008)
[2] S. Baldovino, A. Molle, and M. Fanciulli, Appl. Phys. Lett. 96, 222110 (2010)
[3] S. Paleari, S. Baldovino, A. Molle, M. Fanciulli, Phys Rev. Lett. 110, 206101 (2013)

The next Ultra Thin Box and Buried Silicon-On-Isolator (UTBB SOI) p- Metal-Oxide-Semiconductor generations for the 14 nm and 10 nm nodes requires very low pitch patterns and the use of Si1-xGex sources and drains (S/D) to compressively strain the channel and improve hole mobility [1]. The silicidation process consists in sequential metal/semiconductor reactions under thermal budget to reduce access resistance between active areas and interconnexions [2]. Thus, growth mechanisms must be understood in terms of texture in order to optimize the silicidation process and thermal stability [3-5]. The texture is usually extracted from blanket wafers. Because of the extrem narrow S/D area, this study is proposed to evaluate the confinement impact on Si1-xGex metallization in terms of phase texture, phase formation and thermal stability for different Ni1-yPty alloys.
As reference, the texture evolution is studied on blanket wafers by varing Pt content. Then, the Ni-rich germanosilicide texture is explored in the bottom of regular arrays of aggressive trenches, by X-ray diffraction on the D2AM synchrotron beamline (ESRF). On a 20 nm thick Si0.7Ge0.3 epitaxial layer, SiO2 trenches are patterned by e-beam lithography inside 600*600 µm2 dies. The most aggressive trench pitchs / widths / depths are 64 nm / 32 nm / 100 nm respectively which matches with targeted dimensions of the next 10 nm node. Ultrathin Ni1-yPty films are deposited in the bottom of trenches by RF-PVD followed by the Ni rich germanosilicide phase growth using a RTA annealing system at 280 °C during 30 sec. In order to extract a trend of the texture as a function of Pt content and pitch, Pt content varies from 0 at. % up to 15 at. % and the pitch from 1 µm down to 64 nm. TEM analysis are also performed to observed the bottom germanosilicide morphology (interface, grains sizeshellip;)
A significant change in texture and phase is highlighted as a function of Pt content on blanket wafers. An epitaxial theta;-Ni2Si seems to grow preferentially compared to δ-Ni2Si in presence of Pt [6]. This impacts the mono-germanosilicide texture and consequently the morphological stability. When the salicidation process is carried out in the largest trenches, this phase change is still observed as on blanket wafer. However, with the pitch size decrease, the Ni1-yPty rich germanosilicide film switches from an epitaxial texture in the largest pitch to another texture in the narrowest pitch. The Pt content promotes the epitaxial texture in small patterns, but the effect seems to be lost with pitch size reduction. The texture transition seems to occur around 100 nm pitch which corresponds to the germanosilicide grain size.
[1] M. Vinet, 2012VLSI-TSA (2012).
[2] S. Kim, IEEE Transactions on Electron Devices 49 (2002) 467.
[3] C. Detavernier, Nature 426 (2003) 641.
[4] H. Kimura, Microelectr. Eng. 88 (2011) 557.
[5] S. Gaudet, JAP 107 (2010) 093515.
[6] F. Panciera, Microelectr. Eng. 107 (2013) 167.

Frequency dispersion is a commonly observed feature in the experimental capacitance-voltage characteristics of III-V MOS devices. This characteristic has been reported on a wide variety of III-V substrates in conjunction with many different dielectrics. The conventional interface state capacitance model, which works extremely well for Si devices, does not accurately model the frequency dispersion observed in III-V systems. Different physical models have been developed to explain the origin of this frequency dispersion. One model, disorder induced gap states (DIGS), attributes this dispersion to the tunneling of carriers into a disordered region caused by oxidation of the III-V substrate. A separate model attributes this dispersion to border traps located inside and associated with the high-k dielectric. In this talk, electrical characterization, modeling and physical characterization is used to demonstrate that the observed frequency dispersion must be due to the disruption of the crystalline III-V semiconductor during oxide deposition and not due to border traps located in the high-k dielectric.
Acknowledgments: The author acknowledges the SRC Global Research Collaboration, NSF ECCS-0925844, NSF ECCS-1039988, the SRC FCRP Center for Materials, Structures, and Devices, SEMATECH, and NIST for present and past support of this work. The work to be presented here was performed with numerous people including: C. L. Hinkle, R. M. Wallace, R. V. Galatage, A. Sonnet, B. Brennan, H. Dong, D. M. Zhernokletov, M. Milojevic, F. S. Aguirre-Tostado, S. Anwar and G. Bersuker

We report recent results with InAs/InGaAs MOSFETs with self-aligned MOCVD-regrown InGaAs source and drain. On-state transconductance as large as 2.7 mS/micron have been observed in 55nm Lg devices. We will describe the role of back barrier design, vertical spacers in the high-field region, and channel quantized bandgap on off-state characteristics. We will also describe recent results with ALE-defined InGaAs finFETs, a technology with the potential for few-nm body thickness and high height/pitch aspect ratios, and discuss its potential application in low-voltage logic

InGaAs MOSFET with Gate-all-around (GAA) structure is a promising candidate for CMOS logic circuit beyond the 10nm technology node because of its high electron injection velocity and excellent immunity to short channel effects. In order to further dramatically improve the on-current and meanwhile keep the off-state under control, vertically stacked nanowire structure, we call it as 4D transistor, is introduced. In this work, InGaAs 4D GAA MOSFETs with multiple stacks of ultrathin nanowires are demonstrated. On-current over 2uA/um normalized by device width are obtained and good electrostatic control are achieved for the first time for 4D transistor due to the ultrathin nanowire structure. Junctionless MOSFET structure is used to reduce the series resistance. Meanwhile, we also report on the exploratory experiments on the vertically stacked double-gate structure first time on InGaAs MOSFETs to achieve high on-current and good electrostatic control at the same time.

Measurements of the reflectivity of low-energy electrons, typically 0 - 10 eV above the vacuum level, are known to provide a sensitive means of characterizing 2-dimensional (2D) materials such as graphene or hexagonal boron nitride (h-BN). Phenomenologically, it was found that one can determine the number of 2D layers on a substrate, and also obtain information concerning the interface between the 2D layers and the substrate [1]. However, up to now there has not been a fundamental understanding of how the measured reflectivity is determined by these quantities. A first-principles description of low-energy electron reflectivity spectra has recently been developed, yielding results that compare well with experimental data for both graphene and hexagonal boron nitride (h-BN) on various substrates [2]. Results comparing experiment and theory will be presented, from which the interface structure between the 2D material and the substrate is determined.
2D materials enable the development of a range of novel electronic devices. This presentation will focus on one such device, a SymFET (Symmetric Field-Effect Transistor) that relies on the symmetry between the valence and conduction bands in opposite graphene electrodes of a graphene-insulator-graphene (GIG) junction [3,4]. The state-of-the art in GIG and SymFET fabrication will be described, focusing on recent experimental results [5] in which negative differential resistance was observed in SymFET type devices employing h-BN for the insulator layer. The theory describing SymFET device operation will be discussed, including the aspects of energy and momentum conservation as well as the possible roles of (i) relative orientation of the two graphene electrodes, and (ii) scattering within the insulator layer.
*Work performed in collaboration with N. Srivastava, P. Mende, Q. Gao, M. Widom (Carnegie Mellon University), T. Roy, E. Vogel (Georgia Inst. Technology), A. Ismaj, R. Ruoff (Univ. Texas - Austin).
References
[1] H. Hibino et al., Phys. Rev. B 77, 075413 (2008).
[2] N. Srivastava et al., Phys. Rev. B 87, 245414 (2013).
[3] R. M. Feenstra, D. Jena, and G. Gu, J. Appl. Phys. 111, 043711 (2012).
[4] P. Zhao, R. M. Feenstra, G. Gu, and D. Jena, IEEE Trans. Electron Devices 60, 951 (2013).
[5] L. Britnell et al., Nature Comm. 4, 1794 (2013).

We demonstrate a new paradigm of electronic switches without using semiconducting channels. Metallic nanoparticles deposited on one dimensional (1D) insulators has led to the creation of room-temperature tunnel field effect transistors (TFETs).
Our TFETs are based on quantum tunneling between gold quantum dots (QDs) deposited on the insulating boron nitride nanotubes (QDs-BNNTs) [1]. We show that QDs-BNNTs are insulating at low bias voltages, but allow electron tunneling at room-temperature when sufficient potential is applied. Since the switching behaviors are based on quantum tunneling, these FETs have suppressed leakage current and contact resistance. In addition, the performances of our FETs are enhanced at shorter tunneling channel, in contrast to the short channel effects in Si devices. Thus QDs-BNNTs are advanced materials for FETs that could by-pass some of the fundamental limitations in semiconducting channels.
High-quality BNNTs were grown by the growth-vapor-trapping (GVT) approach [1]. The as-grown BNNTs are insulators with diameters of ~15-50 nm. These BNNTs are used as 1D substrates for the deposition of gold QDs by pulsed-laser deposition [2]. BNNTs are almost ideal as the substrates for the deposition of these QDs due to their uniform and controllable diameters. Furthermore, their defect-free sp² BN network makes them chemically inert to the deposited QDs, and remains electrically insulating. Scanning transmission electron microscopy (STEM) [3] suggests that the gold QDs are crystalline, and are preferentially deposited on one side of the BNNTs. These QDs form a 1D array of particles with estimated diameters ranging from about 3-10 nm and inter-dot spacing of about 1-5 nm. The transport properties of these QDs-BNNTs were characterized by a four-probe scanning tunneling microscopy (4-probe STM) [4]. We show that the turn-on voltages of this QDs-BNNT decrease from ~30V to < 0.1V as the transport length decreased [5]. These switching behaviors can be modulated by a gate potential and are fully simulated by a theoretical model. The on-off ratio of these devices is estimated to be on the order of 10⁴. Details of these results will be discussed in the meeting.
Y. K. Yap acknowledges the support from the U.S. Department of Energy, the Office of Basic Energy Sciences (Grant DE-FG02-06ER46294), the Center for Nanophase Materials Sciences at Oak Ridge National Laboratory (CNMS at ORNL) (Projects CNMS2009-213 and CNMS2012-083), and the ORNL&’s Shared Research Equipment (ShaRE) User Program (JCI).
References:
[1]. (a) Wang et al, Nanoscale2, 2028 (2010); (b) Wang et al, in Chapter 2 of B-C-N Nanotubes and Related Nanostructures (Springer, 2009); (c) Lee et al, Nanotechnology19, 455605 (2008); (d) Lee et al, Chem. Mater.22, 1782 (2010).
[2]. Wang et al, Nano Letters5, 2528 (2005).
[3]. Zhou et al, Nature Nanotech.7, 161 (2002).
[4]. Kim et al, Nano Letters10, 3096 (2010).
[5]. Lee et al, Adv. Mater.25, 4544 (2013).

In 2008, we theoretically predicted that it could be possible to stabilize a ferroelectric material at a state of negative differential capacitance, which when used as a gate insulator in a MOSFET, could reduce the subthreshold swing below the otherwise fundamental 60 mV/decade. Reducing the swing below 60mV/decade means that the overall supply voltage and power dissipation could be reduced significantly. The difference of this concept with other existing proposals to reduce the subtheshold swing in MOSFETs is that the mechanism of electron transport remains unchanged and therefore the speed of operation does not need to be traded off for lower energy dissipation. In the recent years, multiple experimental demonstration have established this concept from both fundamental and technological point of view. In this talk, I shall discuss the conceptual background and recent experimental studies regarding this concept. I shall also discuss challenges and open questions as we currently see them.