Operational lifetime is a crucial performance feature for many electronic devices such as organic light emitting diodes (OLEDs). One of the many failure mechanisms which limit OLED lifetime is the electromigration of metallic components of the electrode materials, forming short circuits through the device architecture. Metals such as silver, copper or aluminium are e. g. used in the highly conductive shunting lines which are necessary to reduce resistive losses in the transparent electrodes of large area OLED panels. A direct study of the effects of metal electromigration in devices, however, is complicated by the interference with other failure mechanisms, as well as by the very localised formation of short circuits, which renders the application of imaging techniques highly challenging.
In this contribution, we present a study of silver and copper electromigration through PEDOT:PSS films, a conductive polymer which is frequently used as replacement for indium tin oxide as transparent electrode material in OLEDs. Due to the experimental setup, electromigration can be studied isolated from other phenomena, and in addition, the formation of short circuits by metal dendrite growth can be easily monitored using electrical current monitoring and optical microscopy. We have studied both experimentally and theoretically the influence of various parameters such as the electric field strength, electrode material and intrinsic electrical conductivity of the PEDOT:PSS on the speed of short circuit formation and on the appearance of the formed metal dendrites. Silver was found to migrate at a much higher rate than copper, and a high current density through the PEDOT:PSS was found to increase the migration rate, which is consistent with the assumption of metal migration being induced by the force exerted on the metal atoms by the moving charge carriers. The results from our study have been correlated with lifetime studies in functional OLED devices. Currently, our experimental setup is used to develop strategies to suppress or slow down metal electromigration and thus improve OLED lifetime.

The generally short lifetimes of organic light-emitting diodes (OLEDs) presents a challenge to their widespread acceptance for use in large-area displays and solid-state lighting. A greater understanding of the degradation mechanisms would help to further improve the reliability of OLEDs particularly at high brightness levels by optimizing the material selection and structural design, and pave the way for their broader applications as lighting sources. In this work, we studied the stability of green phosphorescent OLEDs with different structures under constant-current (20-50 mA/cm²) stressing. Through the modifications of the ITO anode by different plasma treatments and the hole transport layer (HTL) by incorporating inorganic component or dopants, we proved that energy level misalignment at the ITO/HTL interface leads to localized joule heating, accelerating defect generation and luminescence decay. Pulsed current stressing was then employed to suppress the joule-heating effect so as to differentiate the thermal and nonthermal factors governing the device degradation. The luminance evolution comprised an initial rapid decay regime and a subsequent slow decay regime, and only the latter was governed predominantly by electrical excitation. In OLEDs with an appropriate energy level alignment at the ITO/HTL interface, pulsed stressing with 10% duty cycle only improved the effective half life by ~15% as compared to continuous-wave stressing, indicating a minor role played by joule heating.

The intrinsic mechanisms of OLED degradation are investigated in this work. An increase of voltage and a decrease of luminance and efficiency of OLED under accelerated degradation conditions (i.e. constant high current) were observed in the experimental analysis. Degradation of OLED can be due to the decrease of charge carrier mobility, the change of electrode contact, or the formation of more traps.
In this work an increase in the luminance ideality factor of OLED in diffusion regime has been observed from pristine to degraded device. Such increase of this value can either be interpreted as the deterioration of contact, which will change the current into injection limited. Or it can due to the formation of more traps, which brings the trap-assisted recombination more dominant.
Further experiments have been carried out where the dependence of corresponding open-circuit voltage (V_oc) on the incident light intensity (I) was investigated. From the 2.0kT/q enhancement of the V_oc dependence on the logarithmic incident light intensity in the aged devices we could eliminate the influence of electrode contact change. Furthermore the formation of more traps during degradation is being investigated.

Organic light-emitting diodes (OLEDs) for lighting and display, and organic photovoltaic (OPV) devices are all extremely sensitive to ambient moisture, and therefore have to be encapsulated. Large-area organic light-emitting diodes (OLEDs) for general lighting are the most sensitive to ambient degradation. Water ingress into the OLED stack leads to a local oxidation of the cathode, resulting in the formation non-emissive regions called black spots. A single black spot of sup3; 100 µm in diameter is visible by the naked eye, and the OLED is considered to be a reject.
Black spots have been observed and recognized to be caused by degradation in air for more than 2 decades. The water ingress occurs at pinhole locations in the cathode. A general consensus is that the pinholes are caused by particles, which has been confirmed for large pinholes caused by large particles (larger than a few µm in diameter). By improving the processing conditions and environment, these large particles can be avoided, with only smaller pinholes remaining. Although the remaining pinholes are the main moisture pathway leading to OLED degradation, the pinhole locations in the cathode have never been studied for the smaller pinholes. The reason for this missing knowledge is trivial: it is the equivalent of looking for a needle in a haystack. On average we observe 1-10 pinholes/mm² in a 100 nm thick Al cathode. These pinholes are expected to be below several 100 nm in diameter. Logically, the sparsely distributed small pinholes makes detection very difficult, which is even more obscured by the presence of particles and morphological features present on or underneath the cathode, that do not lead to a pinhole. Furthermore, the resulting black spot around a pinhole can only be observed at the bottom (emissive) side of the device through the substrate, although a possible analysis of the pinhole should be performed on the other side of the device, on top of the cathode.
Here, we will present our studies into black spots, black spot growth, black spot growth rate, and the defects causing the pinholes. To study the smaller pinholes, a new method has been developed by which we can determine the pinhole location with great accuracy. Subsequently, the pinhole can then be studied with focussed ion beam scanning electron microscopy (FIB-SEM) to determine the cause of the pinhole. We can use the same technique to study the cathode pinhole/particle coverage of an inorganic thin film barrier, which is the basis of all multi-layer thin film barrier encapsulations.

Transition metal dichalcogenides (TMDCs), which are MoS₂ and WS₂ in this experiment, were used as hole injection layers (HIL) in organic light-emitting diodes (OLEDs) and hole extraction layer (HEL) in organic photovoltaic (OPVs) cells in order to enhance the stability in air condition. TMDCs were synthesized by chemical vapor deposition method with spin-coated (NH₄)₂MS₄ (M = Mo, W) precursor and small amounts of sulfur power. To modulate the low work function of synthesized TMDCs, the UV/ozone (UV/O₃) surface treatment was performed. The properties of synthesize TMDCs were evaluated by transmission and field emission scanning electron microscopy, Raman spectroscopy, and synchrotron radiation photoemission spectroscopy. Green OLED and OPV devices were fabricated with raw and UV/O₃ treated TMDC on indium-tin oxide electrode. TMDC-HIL OLEDs and TMDC-HEL OPVs show higher properties in view point of air stability. Even after air exposure with pulsed operation for 38 hours, the green OLED devices are still working, in contrast to poly(3,4-ethylenedioxythiophene):poly(styrene-sulfonate)(PEDOT:PSS) OLED devices which failed after 10 hours. The turn-on voltages of OLED with UV/O₃ treated TMDCs were 4.4 V (MoS₂) and 4.1 V (WS₂), which decreased from 5.2 V (pristine MoS₂) and 5.1 V (pristine WS₂). The best luminance efficiency of OLED based on UV/O₃ treated TMDCs was 11 cd/A, which was similar to the efficiency of PEDOT:PSS OLEDs. In TMDC-HEL OPVs, the air stability is longer about 2~3 times comparing with OPV based on PEDOT:PSS. The power conversion efficiencies of OPVs using UV/O₃ treated TMDCs as HEL were equivalent to 95 % efficiency of PEDOT:PSS based ones. These results suggest that the UV/O₃ surface treated TMDCs could be a promising candidate in application to optoelectronic devices as a HILs and HELs.

Many Ge and III-V-based MOSFETs as well as GaN-based HEMTs and MOS-HEMTs are significantly compromised in performance and reliability by their high densities of interface, border, and bulk oxide traps. Problems may also arise when characterizing traps in FETs made on modern high mobility channels, due to their device structures and material properties that are different from their conventional counterparts. In this talk, we present the results of our study of these traps as obtained by the use of several electrical characterization techniques. In particular, we will review the novel ac transconductance technique that we recently introduced, which enables us to probe interface traps in the band gap as well as border and bulk traps in the gate dielectrics even without a body contact. We will also show that the Inelastic Electron Tunneling Spectroscopy (IETS) offers the unique capability to provide spatial and energy information about traps, as well as to distinguish between two types of traps: those that give rise to trap-assisted conduction and those that simply trap carriers. Ionizing radiation-induced trapping of charges in MOS-FETs and MOS-HEMTs made on III-V semiconductors are also reported and discussed.

Because of the high critical fields associated with their wide band gaps, their high spontaneous polarization, their high carrier mobilities and saturation velocities, AlGaN and GaN are ideal materials for high electron mobility transistors for high-power and high-frequency applications. However, the reliability of AlGaN/GaN HEMTs for these applications remains a concern. Permanent degradation of the drain current, increased off-state gate leakage, and drain current collapse have all been associated with the high electric fields across the AlGaN layer, especially at gate edges, and have been found to be accelerated at high temperatures. Permanent degradation of electrical properties has been found to correlate with physical damage in the form of surface pits that form near gate edges. The rate of pit formation and growth and the corresponding rate of electrical degradation are accelerated by the presence of water, even when devices are passivated with silicon nitride layers. Pits are also often found to be associated with particles containing oxygen and gallium. It has been argued that pit formation is the result of field-enhanced electrochemical oxidation of gallium. This requires field-induced transport of oxygen (probably in the form of OH^-) through the nitride, and may also be associated with degradation of the nitride itself. Recent work has shown that pits tend to form on threading dislocations that are near the gate edge, rather than exactly at the gate edge where the electric field is highest. Links between electrical degradation, physical degradation, and the physical properties of the device materials will be reviewed and discussed.

Current collapse in AlGa(In)N/GaN heterostructure field effect transistors (HFETs) persists as a major reliability constraint in the pathways of widespread realization of III-nitride electronic devices. The phenomenon is marked by the significant decrease in microwave output power in RF PAs and prominent increase in dynamic resistance of power switches. Electrically active states are held responsible for this trap related event, whose capture/emission time governs the corresponding trapping/detrapping mechanisms though the exact origin of the concerned deep levels along with the involved dynamics remains a vastly debated topic.
In our earlier studies, transient measurements combined with pulse drive responses of nitride HFETs were analyzed to explore the possibilities of dislocations affecting the current dispersion characteristics. The investigations confirmed that dispersion is strongly correlated with the threading dislocation density (TDD) in the epilayers. However, it was not possible to pinpoint a single mechanism responsible for the trapping during OFF-state quiescent bias though either tunnelling or trap-assisted Frenkel-Poole emission or hopping conduction were the plausible transport mechanisms.
Based on previous understandings, in the present study, the analysis was further extended for AlGaN/GaN HFETs fabricated on epistructures with TDDs ~2x10⁸/cm²,~ 7x10⁹/cm², and ~5x10¹⁰/cm². To replicate practical modes of operations, the quiescent bias point was chosen as V_GS in soft-pinch off (~V_Th), moderate pinch-off(~V_Th-3), or deep pinch-off state(~V_Th-6) and V_DS varied upto 18 V. Among devices in different wafers, both the current dispersion and the OFF-state gate leakage for identical bias values were found to correspond to the respective TDDs. Also, for devices in the same wafer, the dispersion was dependent upon the reverse bias in a particular pattern. Temperature and field-dependent OFF-state terminal current measurements were assessed for each of these quiescent biases to identify the spatial leakage mechanism at any of the bias states.
Next, these devices with TDDs spanning three orders were subjected to step stress bias (without the application of storage thermal stress) upto permanent device degradation featuring large irreversible increase in both R_ON and current compression as well as OFF-state leakage. Moreover, same bias dependent compression and qualitative leakage current measurements were carried out for the stressed devices.
Heteroepitaxial growth being the only commercially feasible option for fabrication of nitride devices, significant TDD generation and propagation throughout the active layers is a given owing to the large epilayer-substrate (SiC,Al₂O₃,Si) lattice and thermal mismatch. In this regard, this study elucidating the correlation among TDDs, OFF-state leakage and current dispersion in fresh devices, and their evolution in degraded devices provides detailed insights into the reliability barriers of III-N HFETs.

High voltage AlGaN/GaN HEMTs have seen widespread application in power and RF electronics. Low on-state resistance due to high channel mobility at the AlGaN/GaN heterointerface coupled with high critical field for breakdown in the III-N system (E_Casymp;3 MV/cm for GaN) has led to significant progress in developing the AlGaN/GaN HEMT as a high-voltage device for next-generation switching power electronics. Many issues related to AlGaN/GaN HEMT reliability remain unresolved and are poorly understood. In particular, properties and locations of defects in the AlGaN/GaN material system and how these defects impact performance at the device- and circuit-level are important factors in developing power devices with both improved performance and reliability.
In this work, we investigated the trapping properties of AlGaN/GaN HEMTs with recessed gates and SiO₂ gate dielectrics with devices featuring thicker AlGaN barrier layers and no SiO₂ present. Drain current transients were analyzed following blocking-state stress (V_gs<V_th, V_ds=100 V), and these transients, believed to be due to electron emission, exhibited strong stress-time-dependent behavior. A modified current transient analysis method with regularization techniques was used to characterize the recovery transients. The recovery transient is analyzed by fitting to a sum of exponentials of the form
ΔI_d = sum;α_i(1 - e^-t/tau;_i)
where α_iis the coefficient of a process associated with time constant tau;_i. The modified current transient method used here imposes parsimony and can be described by
y_fit = min(|y - Aα|² + lambda; |d²/dt² Aα|²)
where y is the recovery transient and Aα is the estimation of y. This treatment allows imposing curvature and prior knowledge on solutions while penalizing over-fitting and providing greater resolution of spectral features. Extracted time constant spectra demonstrate that a temperature-independent component becomes progressively slower as stress time is increased and is present in both types of devices. Recessed-gate devices with SiO₂ gate dielectrics exhibit negative and positive transient components representative of simultaneous trapping and emission processes, where carrier trapping dominates at short recovery times and emission is prominent at longer recovery times. The observed device behavior is explained by trapping of electrons in the AlGaN barrier during stress and annihilation of positively charged traps in the SiO₂ at short times during recovery.
Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy&’s National Nuclear Security Administration under contract DE-AC0494AL85000. The work at Sandia work was performed under funding from SNL&’s Laboratory Directed Research and Development Program. The MIT work was partially funded by the DARPA DAHI program, monitored by Dr. Daniel Green, and the ONR DEFINE MURI, monitored by Dr. Paul Maki.

Gallium nitride (GaN) and related alloys and heterostructures are now the foundation for numerous device applications ranging from advanced electronics to solid state lighting due to their advantageous bandgaps and transport properties. GaN materials also possess superior radiation hardness making them of great promise for applications in space systems. To date, research efforts on the radiation-induced degradation and defects in GaN have been primarily focused on n-type GaN. However, there is great interest in p-type GaN due to a variety of device structures for which p-GaN is a necessary component, but to date there is a comparative paucity of information regarding radiation effects in p-GaN. Hence, this work focuses specifically on the creation and properties of electronic defects in p-GaN that result from exposure to high energy proton irradiation. Here, a combination of high resolution deep level transient/optical spectroscopy (DLTS/DLOS) measurements applied to systematic sample sets of proton-irradiated p-GaN layers grown by ammonia-based molecular beam epitaxy (NH₃ MBE) is used to comprehensively reveal and characterize irradiation-induced trap states in these materials. Several new bandgap states are revealed, with very different sensitivities and introduction rates due to proton exposure.
A unique p⁺/p^-/n⁺ device structure was designed, grown by NH₃MBE and processed to facilitate DLTS and DLOS measurements, which enables both low contact resistance and 1 MHz capacitance measurements for ideal trap characterization. The samples were exposed to 1.8 MeV protons with total fluences of 1×10¹³ cm^-2 and 3×10¹³ cm^-2.
Prior to irradiation, hole traps were observed at E_V+1.50 eV, E_V+2.42 eV, E_V+3.00 eV and E_V+3.28 eV, all with concentrations around 1×10¹⁵ cm^-3. Subsequent proton irradiation brings significant changes to both DLTS and DLOS spectra, introducing several new traps and also affecting the concentration of as-grown defects. Specifically, at a proton fluence of 3×10¹³ cm^-2, the concentrations for pre-existing traps at E_V+2.42 eV, E_V+3.00 eV and E_V+3.28 eV increase by 3.0×10¹⁵, 1.2×10¹⁵, and 1.6×10¹⁵ cm^-3, respectively. Two new deep states are detected at E_V+0.48 eV and E_V+1.02 eV, with concentrations of 6.4×10¹⁴ and 3.0×10¹⁴ cm^-3, respectively. Introduction rates are being calculated using other irradiation fluence values but it is already clear that the introduction rates are not equivalent for each defect, with the as-grown trap at Ev+2.42 eV being most sensitive to irradiation, the trap at Ev+1.50 eV showing no change in its concentration and the new traps being of intermediate introduction sensitivity. By comparing these results with theoretical calculations, we will discuss possible origins for the irradiation-induced traps in p-GaN. We will also discuss and compare overall irradiation resistance of p-GaN with our prior work on n-GaN in an attempt to create a comprehensive treatment of both n and p type GaN.

VCSELs are increasingly being employed for data links within computer servers and switches. They offer high bandwidth density (>300Gbps/cm^2) and low power consumption (<10pJ/bit) at high speeds. They are particularly attractive at high speeds, such as 25Gbps. At such speeds, electrical signals can only propagate inches unless exotic laminates are used along with power hungry signal conditioners and repeaters. The latest VCSEL based multi-channel transceivers are small enough to be placed directly adjacent to the logic chips (ASIC or CPU) and signal at high speed without integrity loss . Once converted to light, the signals can travel 50 to 100 meters without additional conditioning or boosting. In engineered computer systems and switches, optical transceivers are used in large numbers, the internal temperatures within these systems are high, and these systems require extremely high reliability. This raises multiple challenges for VCSELs to meet the necessary reliability and performance. Various design trade-offs are made to try to optimize reliability and performance but trade-offs are constrained by several factors. For example, VCSEL speed increases always involve higher current densities which decrease reliability in an exponential manner. Most VCSELs used in the past in optical transceivers were based on GaAs/AlGaAs. Many VCSEL manufacturers are converting to GaAs/InGaAs for the potential higher speed and reliability. In this presentation we will review the emerging applications for optical transceivers, the associated reliability requirements, our experiences covering more than a decade with VCSEL based parallel transceivers, and the future applications and reliability and bandwidth needs for these devices.

Over the last few years, the research in the field of InGaN-based laser diodes has shown impressive advancements: these devices can currently cover the wavelength range between 375 nm and 530 nm, and are expected to find wide application in the next generation projectors, optical data storage systems, and biomedical devices. Moreover, it has been recently demonstrated that blue InGaN lasers can be used for the fabrication of high-intensity white lamps, for application in the automotive field.
Most of these applications require high optical power levels (>0.25-1 W for the single laser diode): as a result, the devices are driven under extreme conditions; typical current densities can be in excess of 10 kA/cm², corresponding to high levels of power dissipation (~50 kW/cm²) and self heating (Tj>100-150 °C). These factors may lead to the early degradation of the laser diodes, since temperature and current act as driving forces for the gradual degradation.
This presentation describes the physical mechanisms responsible for the degradation of InGaN-based laser diodes submitted to high current/temperature stress; more specifically, we will discuss the following relevant topics: (i) the degradation of the efficiency of the quantum well region due to the generation of non-radiative centers, and the properties of the related defects; (ii) the changes of the electrical characteristics of the devices induced by the exposure to high temperatures; (iii) the sudden degradation of the laser diodes, due to catastrophic-optical damage and to electrostatic discharges. In addition, we will discuss the role of the various driving forces (temperature, current, optical power) in accelerating the degradation kinetics, and the relation between time-to-failure and material quality.
The results described within the presentation will be critically compared to recent papers, to give an exhaustive description of the topic.

The degradation of laser diodes constitutes a challenge for laser manufacturers and end users. The catastrophic optical damage (COD) of laser diodes consists of the sudden drop off of the optical power. COD is generally associated with a thermal runaway mechanism in which the active zone of the laser is molten in a positive feedback process. Degraded devices present dark line defects (DLDs) along the laser cavity produced during the laser operation; these DLDs are regions of the active zone of the laser with very low or null light emission as revealed by cathodoluminescence (CL) studies of the degraded regions of the laser. These dark lines are locally generated, either at the front facet, or inside the cavity, propagating along the cavity driven by the optical field. The physical sequence leading to the formation of such lines and the associated loss of output optical power is described in the literature; however, there is a lack of consensus about the connection between the successive steps leading to COD. Understanding this is crucial to improve the technological factors that can strengthen the laser diodes. The full sequence of the degradation consists of different phases, in the first phase a weak zone of the laser is incubated, and the local temperature is increased in such a zone; when a critical temperature is reached the thermal runaway process takes place. Usually, the positive feedback leading to COD is circumscribed to the sequential enhancement of the optical absorption by the increase of the temperature. However, the meaning of the critical temperature has not been unambiguously established. Herein, we will discuss about the critical temperature, and the physical mechanisms involved in this phase; in particular, we will describe the defect morphology and the conditions under which such critical temperature can be reached, both in the front mirror face and the inner cavity. For this, we will analyze the meaning of the critical temperature and the influence of the progressive decrease of the thermal conductivity of the laser structure on the degradation during the laser operation. We will compare the critical temperature estimated by a thermomechanical model with the values usually reported, which range between 1300C and 2000C.

Reliability and degradation processes in broad-area InGaAs-AlGaAs strained quantum well (QW) lasers are under intensive investigation because these lasers are the key components for fiber lasers and amplifiers that have found both industrial and military applications in recent years. Unlike single-mode lasers that were developed for high reliability telecom applications, broad-area lasers were mainly targeted for applications that require less stringent reliability of the lasers until recently. Especially, the lack of field reliability data is a concern for satellite communication systems where high reliability is required of lasers for long-term duration. For our present study, we addressed this concern by performing long-term lifetests of broad-area InGaAs-AlGaAs strained QW lasers and also by studying mechanisms that are responsible for catastrophic degradation of the lasers.
We performed long-term lifetests on industry standard broad-area lasers under automatic current control (ACC) mode for low-stress failure mechanism investigation. Our lifetests accumulated over 35,000 test hours and failure mode analysis was performed on failures using our technique developed to observe dark line defects nondestructively. We also performed a series of shorter-term lifetests on window lasers under ACC mode for our physics of failure investigation to understand the root causes of degradation mechanisms. Window lasers have an opening introduced in backside n-metal contacts during device fabrication, and this configuration allowed us to perform time-resolved electroluminescence (TR-EL) and time-resolved photoluminescence (TR-PL) measurements. We employed both destructive and nondestructive techniques. Our nondestructive techniques included TR-EL, TR-PL, and deep level transient spectroscopy (DLTS) techniques to study precursor signatures of failures - traps and non-radiative recombination centers (NRCs) in pre- and post-stressed lasers. Our destructive techniques included focused ion beam (FIB), electron beam induced current (EBIC), and high-resolution TEM (HR-TEM) techniques to study dark line defects and crystalline defects including dislocations in post-stressed lasers. Our long-term lifetest results and physics of failure investigation results will be presented.

Recent innovations on quality-improved GaN free-standing substrate have provided us widely-spread Blu-ray lasers, ultra-high brightness LEDs. They also brought us inspiration of supreme vertical-structure power devices which require large fatal-defect-free areas in GaN epitaxial wafers grown on the GaN substrates.
Evaluation of GaN epitaxial layers by electrical properties of p-n junction diodes is a suitable method for evaluating the presence of fatal defects because the p-n junction diodes do not contain uncertainties of surface features such as Schottky diodes. We fabricated p-n junction diodes using MOVPE-grown epitaxial layers on free-standing GaN substrates and evaluated reverse and forward diode characteristics for the existence of fatal defects. The substrates were from Hitachi Metals made by VAS-method. The substrate has a feature that its threading dislocations are almost uniformly distributed with a density of 1-3e6 cm^-2. Also, these dislocations consist of edge and mixed ones. Any pure screw dislocation was not found in their wafers and substrates. The fabricated diode with n-GaN drift-layer whose thickness was 20 µm and its circular electrode with 60 µm in diameter showed low specific on-resistance of 0.9 m#8486;cm² and a high breakdown voltage over 3 kV. The high break down voltage was maintained in larger diode with an electrode of 400 µm in diameter although the diode contains more than a thousand threading dislocations under the electrode. In another diode with a much larger circular electrode of 3 mm in diameter showed a high breakdown voltage comparable with those of smaller diodes. Therefore the edge and the mixed dislocations are thought to be not the fatal defect for the diodes with high breakdown voltages. For the next step, we examined an effect of so-called “core” with Nitrogen-faced inversion domain. Some suppliers of GaN substrate use wide-period (<1 mm) coalescent growth methods to reduce the dislocation density at a region among the intentionally placed cores. Because Hitachi&’s GaN substrate did not contain any core, we specially obtained a wafer with high core density for the experiment. A diode with a core extended to epitaxial layers showed large leakage current and low breakdown voltages, however, those with a core terminated within the substrate showed normal breakdown behavior. So, we can conclude the threading core should be a fatal killer defect for the power diodes. A large area device should be fabricated to escape the threading core.
High quality GaN epitaxial layers with low dislocation density enabled us to form p-n diodes by Mg-ion implantation to n-GaN, which has been difficult because of preferential decomposition of the surface at the defect regions during a high-temperature annealing. A clear rectifying I-V characteristics and UV-blue light emissions were observed. The high quality GaN opens a door to a wide variety of device processing leading to highly efficient power devices.

To improve reliability of large area light emitting devices, we have developed a low temperature epitaxial growth technique for inorganic materials named pulsed sputtering deposition (PSD) and demonstrated fabrication of RGB InGaN LEDs on amorphous SiO₂ substrates.
Large area light emitting devices are usually based on organic materials. However, organic devices suffer from poor reliability because they are vulnerable to water, oxygen, and heat. If we fabricate large area light emitting devices with inorganic crystals such as group III nitrides, this weakness is largely alleviated. Group III nitride semiconductors have, indeed, been widely used for high performance optical devices, but the applications are limited in small size devices because of their high fabrication cost. This limitation stems mainly from two problems: the use of expensive MOCVD process and the use of small single crystalline substrates.
To solve the former, we have to develop a new low cost epitaxial growth technique named PSD. PSD should attract much attention of industry engineers because its productivity is much higher than that of conventional MOCVD. In this technique, surface migration of the film precursors is enhanced due to the pulsed supply of high energy atoms and, therefore, the temperature for epitaxial growth is dramatically reduced. We have confirmed that PSD allows us to obtain device quality III nitride films even at room temperature and to fabricate a 632 nm LED at a maximum process temperature of as low as 480°C.[1] The long wavelength of this LED can be ascribed to the suppression of phase separation during the growth of the high In content InGaN due to the reduced growth temperature.
To solve the latter, we have utilized various large area low cost substrates such as metal foils and graphite sheets that have never been used for growth of semiconductors due to their chemical vulnerability. It should be noted that successful growth of epitaxial nitride materials on these substrates can be ascribed to the dramatic reduction in growth temperature by the use of PSD. In this presentation, we will show successful operation of InGaN multi-quantum-well RGB full colar LEDs on low-cost substrates by the use of PSD. [3]
[1] E.Nakamura et al., Appl. Phys. Lett. 104, 051121 (2014)
[2] T.Watanabe et al., Appl. Phys. Lett. 104, 182111 (2014).
[3] J.-W. Shon et al., Scientific Reports, SREP-14-02636A (2014).

UVC LEDs have many applications in disinfection of air, water, and surfaces as well as for many absorption and fluorescence spectroscopy applications. The performance of these devices has increased rapidly in the last several years and we are beginning to see market adoption in these applications. Pseudomorphic UVC LEDs on AlN have demonstrated reliability and lifetimes suitable for introduction into a commercially available product. While the commercial product is rated for an L50 value of 1000 hours, testing has been performed in excess of 4,000 hours, with the results showing much longer predicted L50 values on the order of 7000 hours when operated at the rated current of 100 mA and a case temperature of 25 ^oC. This long lifetime has necessitated the investigation of acceleration parameters to allow for faster identification of potential reliability issues as the performance of the device is improved continuously.
Accelerated lifetime testing has been carried out as a function of temperature and current, the two most common acceleration factors for LEDs. High current testing has been carried out at 200 and 300 mA with a case temperature of 25 ^oC, while 100 mA testing was performed over a case temperature range of -40 ^oC to 85 ^oC. The degradation versus temperature is constant at -40 ^oC and 25 ^oC and begins accelerating at temperatures higher than 25 ^oC. A similar trend shows a reduction in the predicted L50 at higher currents.
Two primary degradation mechanisms were identified from these tests. The first is an exponential degradation commonly seen in LEDs. At higher temperatures the rate of degradation is higher in the early stages of operation but then slows as time increases, suggesting possible changes in the degradation mechanism as a function of temperature. In addition to the exponential degradation, sudden sharp changes in output power were seen. This was accompanied by a dramatic increase in the reverse leakage current of the diode. Infrared emission microscopy was used to identify the areas of increased leakage current. Scanning Electron Microscopy was used in these locations to gain insight into the cause of the increased leakage current. This analysis showed areas that were completely destroyed due to a localized, extremely high current density. An area which had not seen the catastrophic degradation, but showed a response in emission microscopy was analyzed with Transmission Electron Microscopy. A defect beginning in the AlN substrate and a high defect density in the epitaxial layers were observed in this location. Details on the acceleration factors and effect of defects on the lifetime and reliability will be discussed.

Free-standing GaN substrate is used for nitride-based optoelectronic devices because of its high thermal conductivity and low dislocation density. Recently, high-performance green laser diodes grown on semi-polar free-standing GaN substrate have been reported. Moreover, it becomes more important as a substrate for GaN power devices. From the viewpoint of epitaxial growth, surface morphology of substrate is also crucial. However, there are only few reports about surface pretreatment of GaN. In this study, we investigated the effects of thermal cleaning on surface of (0001) c-plane and semi-polar planes free-standing GaN substrates.
MOVPE system was used to perform thermal cleaning of free-standing GaN substrates. Thermal cleaning pressure was fixed at 500 Torr, and the ambient was H₂ + NH₃ or N₂ + NH₃. The temperature was varied from 800 to 1100 ^oC.
Substrates from A-corporation without thermal cleaning exhibit smooth surfaces. In contrast, substrates from B- and C-corporation had damaged surface with polishing scratches. In the case of substrates from A-corporation, smooth surface with atomic steps were observed after cleaning at 1000 ^oC, and surface morphology became rough with large islands at 1100 ^oC. On the other hand, atomic steps were formed on substrates from B-corporation for 950 ^oC whereas pits formed on the surface at 1100 ^oC. For substrates from C-corporation, polishing scratches were disappeared and atomic steps were formed with increasing cleaning temperature, and an optimized surface morphology was obtained at 1100 ^oC. Etching rates increased with increasing cleaning temperatures for all substrates, and etching rates of H₂ + NH₃ ambient was larger than those of N₂ + NH₃ ambient. Furthermore, surface polarity of substrates also influences the GaN etching rates, especially, etching rate of (20-2-1) GaN substrate was larger than those of the other substrates. The surface became slightly N-rich for the samples annealed over 1050 ^oC by XPS analysis, which suggested desorption rate of Ga atom is higher than that of N atom.

Ultraviolet (UV) light emitting diodes (LEDs) emitting radiation in the UV-B spectral region (280 - 320 nm) are promising candidates for applications, such as UV curing, phototherapy, and plant-growth lighting. However, currently two factors limit the use of (InAlGa)N-based UV LEDs: Firstly, the optical output power is low due to a low external quantum efficiency. Secondly, the optical power under constant current operation decreases rapidly over some hundred hours.
In this paper we present a detailed study on the degradation of electro-optical parameters of (InAlGa)N multiple quantum well LEDs emitting around 310 nm under different stress conditions. All samples were grown by metal organic vapor phase epitaxy on sapphire substrates and then processed to bottom emitting LEDs. The devices were flip-chip mounted on AlN ceramic submounts using AuSn soldering for efficient heat dissipation.
One set of LEDs with different emission areas was stressed at constant current density of 75 A/cm² (I = 30 mA and 50 mA). A second set was stressed at 225 A/cm² (90 mA and 150 mA). For both sets the ambient temperature was kept constant at room temperature. A third set of samples was stressed at a current of 100 mA (65 A/cm²) but different temperatures between 15°C and 80°C.
We observed two main optical power degradation modes, dominating at different times of operation. First a strong degradation is observed between 0 h to 100 h, showing an exponential decay. The maximum drop in optical power exponentially depends on the temperature with an activation energy of 160 meV. The reduction of optical power was between 10 % for 15°C and 28 % for 80°C. The drop in optical power was accompanied by an increase of the operation voltage of 0.4 V, e.g. for LEDs stressed at 80°C and 100 mA. The second degradation mode is a long term degradation for operation times >100 h, which can be reasonably described by a square root time dependence. Here, the degradation rate depends on the current-density, rather than the current. No measurable degradation can be observed at 75 A/cm². At 225 A/cm² a degradation rate of 0.6 %/h^0.5 can be calculated. Furthermore, these degradation rates changed with temperature at 100 mA, e.g. 0.3 %/h^0.5 at 15°C to 1.0 %/h^0.5 at 80°C. Again, the corresponding activation energy is 160 meV. The reverse-bias leakage current at -2 V shows an inverse trend in comparison to the optical power, e.g. it increases from 0.6 mu;A to 3.3 mu;A at 225 A/cm² and room temperature.
None of the samples showed measurable changes in the peak wavelength. Therefore, changes of the material composition in the active region can be excluded. The increase of voltage during the first hours of operation could indicate the degradation of the LED contact layers. Furthermore, the reverse-bias leakage current is known to be dominated by the defect density in nitride-based LEDs. This leads to the assumption that both degradation modes could be driven by point defect motion or formation.

Owing to its high reflectance in the visible region, Ag reflector has been widely applied in LED device and package. However, peoples have found that the Ag reflector would suffer sulfuration. As a result, the reflectance of the Ag reflector film will decrease and the lighting performance of the entire LED device would drop significantly.
In this study, we first studied the sulfuration resistance of the Ag reflector. The sulfuration resistance test was done with an immersion
process in the 0.01M Na₂S solution for 10 minutes. The reflectance was measured by PerkinElmer Lambda35 UV/VIS Spectrometer.
We found that the Ag reflector would be tarnished seriously by sulfuration and the reflectance of the tarnished Ag reflector drops below 40%. An Ag-Pd alloy reflector was produced by the electroless plating process. Then, the Ag-Pd alloy reflector was also tested with the sulfuration resistance. The preliminary results show that the Ag-Pd alloy reflector only drops about 15% after the sulfuration test. Its reflectance is still above 70% Compared to the pure Ag reflector, the Ag-Pd alloy reflector layer shows a good sulfuration resistance in this work. In this talk, we will also present the XPS and XRD study on the Ag and Ag-Pd reflectors after the sulfuration resistance tests. Also, both the Ag and Ag-Pd reflectors would be processed as the reflector layer in GaN light-emitting diodes (LEDs). The light output power of LEDs with the Ag and Ag-Pd reflectors would be analyzed after the sulfuration resistance tests.

During the last two decades, light-emitting diodes (LEDs) based on InGaN material systems have been successfully developed heuristically rather than analytically by changing various experimental parameters including epitaxial layer structures, epitaxial growth conditions such as temperature, pressure, and growth speed, and annealing conditions of the p-layer, with a final goal of achieving a higher light output power. Nowadays, however, their optoelectronic performances are hardly improved by utilizing such methods so that in-depth characterization methods assessing the interrelations of experimental parameters independently and quantitatively are absolutely necessary. For this purpose, we have developed systematic characterization techniques such as the current-voltage (I-V), the current-light power (I-P), the capacitance-voltage (C-V) under forward and reverse biases, the photocurrent (PC) and electroreflectance (ER) spectroscopies, the temperature-dependent electroluminescence (TDEL), and the internal quantum efficiency (IQE) measurements.
In this work, by comprehensively applying these techniques, we systematically investigate how the growth temperature (T_g) of the p-(Al)GaN layer in the InGaN/GaN multiple-quantum-well (MQW) blue LEDs grown on a sapphire substrate affect the external quantum efficiency (EQE), the light extraction efficiency (LEE), and the internal quantum efficiency (IQE). While there doesn&’t exist any difference in current-voltage characteristics under forward and reverse biases among the samples, it has been found that the EQE increases, the IQE decreases, and the LEE increases with increasing T_g of the p-(Al)GaN layer. It has been suggested that the increased LEE at higher T_g results from the improved crystal quality in the p-layer and subsequently little optical absorption band tail there. The decreased IQE at higher T_g is due to the increased Mg diffusion into the QW nearest to the p-layer during the p-layer growth and subsequently higher nonradiative recombination rate there. Moreover, a method estimating the Mg diffusion length is demonstrated by analyzing both the C-V curve and the ER spectra under reverse biases for the first time.

III-nitrides are promising material for the light emitting diodes (LEDs), laser diodes(LDs) or power devices. It has been grown on sapphire substrate and high quality devices were realized. On the other hand, the LEDs based on III-nitride showed the efficiency decreasing at high current region due to the poor thermal conductivity of sapphire substrate. So, the removal of substrate or another substrate is necessary to get brighter LED such as domestic lighting. Silicon substrate has high thermal conductivity, therefore, it is suitable to realize the high current region devices. In this paper, we focused on the silicon substrate and tried to get semi-polar GaN or make LD structure.
At first we deposited an SiO₂ film on (001)Si substrate and made mask and window (1-10mm) pattern by using conventional photolithography. The prepared substrate was followed by immersing into the KOH solution. The KOH solution showed anisotropic etching of Si surface. We could get {111}Si facet with (0001) bottom face on (001)Si substrate. It is well-known that the (0001)GaN axis can align the (111)Si axis. We adapted the selective are growth(SAG) of GaN on this substrate by MOVPE, as a result, the declined (0001)GaN was obtained. The angle difference between (001) and (111)Si surface is 54.7^o, on the other hand, that of (1-101) and (0001) GaN is 62 ^o. So that, the 7degree off Si substrate is proper to get (1-101)GaN on (001)Si substrate. We tested SAG of GaN on the 7degree off (001)Si etched by KOH and successfully got the semi-polar (1-101) GaN. We also obtained flat (1-101)GaN surface by making the stripe GaN structure coalesced. The obtained semi-polar crystal was observed by SEM/CL system. There are many dark spot at the edge of the structure, on the other hand, few numbers of dark spot were observed from center to top area. This is because the nucleation occurred at top of {111}Si facet and most of dislocation was bent at initial stage of GaN crystal growth. So, the dislocation did not propagate toward the top area. We could confirm that the crystal quality was good by adapting this method. So, we grew LD structure on (1-101)GaN/(001)Si substrate and formed micro cavity by cleaving. The photoluminescence(PL) excited by N₂ laser was performed at room temperature. The luminescence was corrected from the crystal edge. We could confirm the strong non-linear luminescence intensity as excitation power, narrowing of emission and the longitudinal mode of cavity structure. We could achieve the lasing of these structures from 420nm to 480nm.

Al_xGa_1-xN-based III-nitride compound materials are promising for fabricating long-life-time and high-power-conversation of light emitting diodes (LEDs) or laser diodes (LDs) in deep-ultraviolet (DUV) region, which is also expected for flame detectors, medical sterilizers, and nano-imprint lithography equipment etc. Nevertheless, the performances of Al_xGa_1-xN-based devices still need to be improved for shorter wavelength in DUV region, because the crystal quality of Al_xGa_1-xN deteriorates as increasing Al mole-fraction. At the same time, the optical polarization direction also switch from Eperp;[0001] to E#8741;[0001] as increasing Al mole-fraction and, therefore, a higher intensity of DUV luminescence is expected from non-polar plane Al_xGa_1-xN, (e.g. m- and a-plane) rather than c-plane one. A high crystal quality of a-plane AlN grown on r-plane sapphire is considered a solution to achieve high efficiency of Al_xGa_1-xN-based DUV region light sources with high Al mole-fraction. Unfortunately, a-plane AlN grown on r-plane sapphire, even nowadays, still suffer inverted twin problem, which roughen the growth surface. It is considered high crystal uniformity of AlN growth can be achieved by using ammonia (NH₃) pre-flow, and our group has also obtained high crystal quality of c-plane AlN ((e.g. the full wave half maximum of X-ray rocking curve at (002) and (102): 16 and 154 arcsec, respectively) with NH₃ pre-flow. In this study, we investigated the influence of different NH₃ pre-flow conditions on crystal quality and surface morphologies of a-plane AlN.
a-plane AlN grown on r-plane sapphire substrates were prepared by using a metalorganic vapor phase epitaxy (MOVPE) reactor. All substrates were first cleaned at 960-1260 ^oC for 10 min. Then, NH₃ was supplied at 1200 ^oC for different times (30, 300 and 600 s) just before supplying trimethylaluminum (TMA) for a-plane AlN growth. Growth temperature, background pressure, and epi-layer thickness of a-plane AlN were all maintained at 1200 ^oC, 30 torr, and 300 nm, respectively. Surface morphologies and roughness of all samples were estimated by using an atomic force microscope (AFM). All samples show 3-dimentional (3D) growth of a-plane AlN. Root mean squares of surface morphologies for NH₃ pre-flow time at 30, 300 and 600 s are 6.85, 12.99, and 14.35 nm, respectively. Sizes of 3D islands shrink, and the heights of 3D islands increase as increasing NH₃ pre-flow time. This result demonstrates that lateral growth of a-plane AlN is promoted by reducing NH₃ pre-flow time, and smoother surface morphologies can be obtained with NH₃ pre-flow time at 30 s.

AlN is one of the most promising materials for optoelectronic applications in the deep UV region. However, single crystal wafer of AlN is too expensive, and high-density threading dislocations exist in AlN epitaxial films on sapphire substrate due to the large lattice and thermal mismatches. The control of AlN growth near the interface between AlN and sapphire substrate is one of the key issues for obtaining high-efficiency UV devices. In this work, we studied the control of the AlN buffer layer by annealing in a carbon-saturated N₂-CO ambient. The effects of annealing were investigated as a function of AlN buffer layer thickness, growth temperature, and annealing temperature.
AlN epilayers were grown on c-plane sapphire substrates by metal-organic vapor phase epitaxy (MOVPE). AlN buffer layers with thicknesses of 100-1000 nm were grown at 800-1250 ^oC under a pressure of 30 Torr. Subsequently, the AlN buffer layers were thermally annealed in a carbon-saturated N₂-CO ambient at 1500-1750 ^oC for 2 h. Finally, high-temperature AlN layers with a thickness of 2 mu;m were grown on the AlN buffer layers in a H₂-N₂ mixture at 1450 ^oC under 30 Torr.
By annealing in a carbon-saturated N₂-CO ambient, the surface morphology of all AlN buffer layer was dramatically changed, and the RMS values were improved. Additionally, the FWHMs of the XRCs of AlN buffer layers were significantly and linearly decreased with increasing annealing temperature up to 1700 ^oC. The FWHMs of (0002) and plane (10-12) XRCs for the AlN on AlN buffer layer with the thermally annealing are 16 and 154 arcsec, respectively. It indicates that most of dislocations in the AlN on the annealed AlN buffer layer are edge type, and are markedly reduced.

The use of AlN as a nucleation layer has been critical to the development of III-nitride on silicon devices. AlN acts as a barrier, preventing gallium precursors from etching the substrate. It also induces compressive strain in overgrown GaN layers which compensates the tensile stress that arises during cooling. Many studies have investigated the influence of AlN growth parameters on the crystal quality and morphology of subsequent GaN layers; however there is a limited understanding of the growth mechanisms of single AlN films in the literature. This work investigates the morphology and structure of AlN grown on silicon (111) with the use of an aluminum interlayer. Atomic force microscopy (AFM) and transmission electron microscopy are utilized to understand the thermodynamics and kinetics of AlN grown below the melting point of aluminum, at 800^OC and near 1100^OC. The morphological evolution of a two temperature (low temperature to high temperature) nucleation layer is studied with AFM. Finally, molecular dynamics simulations are employed to better understand interdiffusion between the substrate and the initial Al and AlN layers.

To improve higher emission efficiency in GaN based III-V optoelectronic devices having GaInN emission layers with higher Indium concentrations, three-dimensional information of Indium distribution near the crystal defects and phase separation are inevitable.
First, we describe details analysis of Indium distributions of multiple quantum wells (MQWs) near the inverted pyramidal shaped defects (so called V-shaped pits) initiating from the treading dislocations by laser assisted three dimensional atom probe (3DAP).
Next, we show the spatial fluctuations of Indium distribution observed in normal (non- defective) regions of MQWs. Although the frequency distributions of Indium concentration of QW layers derived from 3DAP analyses are well fitted by a normal distribution, two-dimensional mole fraction maps of each QW layers are exhibited uneven periodic patterns. These patterns were considered to be associated with the compositionally modulated structures and the domain sizes of them were evaluated by auto-correlogram. We will discuss the formation mechanism of the compositional modulations in MQWs.

GaN device reliability has become a major factor in technology acceptance for various electronics applications. At the heart of reliability are the degradation modes of devices subjected to a variety of harsh environments, including high energy particle radiation, high power RF biasing, very high voltage biasing for power switching, and simultaneous combinations of these stressors. While there are clear connections between dislocation density and the degradation of AlGaN/GaN material and HEMT characteristics, how the electron trapping behavior of all physical defect structures involved with device reliability remains complex and increasingly important. This work explores different modes of GaN HEMT degradation when subjected to proton irradiation and electrical stressing. Specific trap states associated with different stress conditions are revealed using standard and HEMT-based deep level optical spectroscopy (DLOS) and deep level transient spectroscopy (DLTS) methods. These trap characterization techniques provide quantitative information about degradation-limiting traps that can exist anywhere within the device bandgap profile and can be distributed within specific regions of the device structure.
Multiple types of AlGaN/GaN HEMTs were characterized in a systematic fashion using DLOS and DLTS before and after the application of RF switching, high voltage switching and proton irradiation. At a high level, we have identified a clear distinction between device degradation modes due to proton bombardment where threshold voltage (V_T) instability is the major issue, and electrical stressing where large changes in the drain resistance (R_D) are observed. Proton irradiation is found to increase the concentration of several traps at E_C-1.3 eV and 3.28 eV in the GaN buffer, which appear to be responsible for large and persistent V_T shifts in GaN HEMTs, and a state at E_C-0.72 eV in the GaN buffer that separately correlates with an increase in V_T dispersion. An entirely different set of stress-sensitive traps is observed after electrical stressing (i.e., RF and high voltage switching). As is now well-known, RF biasing increases the concentration of a buffer trap with an activation energy of E_C-0.57 eV in the drain access region that causes knee-walkout, drain-lag and output power loss through its trapping/detrapping activity. However, high drain voltage switching of GaN-on-Si power HEMTs creates a different and much deeper buffer trap (E_C-2.0 eV), which, through extensive DLOS studies, is shown to be responsible for total current collapse. The different traps and degradation modes created by different stress conditions will be compared in detail. The use of DLOS and DLTS to track the activation of these defects will be shown as essential to accurately determine critical defect properties needed to establish accurate predictive reliability models, and guidelines for improved end of life material and device designs.

Thermal oxidation is the key process to achieve high quality interfaces on Si and SiC devices. On c-plane GaN no suitable gate dielectric for normally-off operation has been found for deposited layers, showing large drifts caused by very high density of interface states lying above 1E13 cm^-2 [1]; hence native oxidation could be the key for comparable interface qualities as on other materials. Epitaxially grown GaN (0001) on Si (111) occur in high densities of threading dislocations (TDs) up to 1E10 cm^-2. Though GaN represents a very inert material, these TDs serve as preferred sites for chemical reactions, as is observed after defect etching. Their influence on the oxidation mechanism of GaN has not been understood yet, despite their importance especially in the presence of high dislocation density.
In this work we propose a new perspective on the dry thermal oxidation mechanism of GaN studied with AFM, TEM and EDX. Our results reveal (1) enhanced vertical oxidation at threading dislocations (TDs) and (2) enhanced decomposition at these TDs. Both observations will explain the commonly observed increase of interface roughness during thermal oxidation of GaN [3, 4]. The transformation of GaN to Ga₂O₃ is significantly slower at defect free surface sites compared to TD areas. Our investigations suggest that at higher temperatures (T>900°C), the Ga₂O₃ formation is solely controlled by the decomposition of GaN and subsequent oxidation of the metallic gallium. Owing to the exothermic formation enthalpy of Ga₂O₃ from GaN and O₂ above 750°C [5] the actual local temperature of the sample is higher than the apparent one. This means that adding oxygen to the system supports the decomposition; hence the oxidation mechanism is promoted by the amount of oxygen added due to both, the excess offer of oxygen and the availability of metallic gallium. This mechanism is preferred at TDs and grain boundaries and is true for oxidation temperatures above 850°C. Oxidation promoted decomposition can additionally be seen to play a role at defect free interfaces at T=1100°C as it will be demonstrated by TEM investigations. The resulting surface roughness after oxidation is therefore explained by an inhomogeneous Ga supply at the defect free interface compared to grain boundaries and TDs. The results are relevant for process improvements of thermal oxidation and explain why interface roughness is an intrinsic feature of such processes.
[1] P. Lagger et al., Appl. Phys. Lett. 105, 033512 (2014). [3] T. Hossain et al., Phys. Status Solidi C 3-4, 565 (2014). [4] H.S. Oon and K.Y. Cheong, J. Mater. Eng. Perform. 22, 1341 (2013). [5] M.R. Ranade et al. J. Phys. Chem. B 104, 4060 (2000).

The generation of non-classical states of light is of fundamental scientific interest in quantum optics and an important technological challenge in quantum information processing. Semiconductor quantum dots (QD) are potential candidates using them as single-photon emitting devices because of their atomic-like energy structure and capability for electrically triggered operation. In particular, III-nitride QDs are promising room-temperature quantum emitters due to their large exciton binding energy and confinement potential.
Unfortunately, III-nitride based heteroepitaxially grown layers generally contain a high number of threading dislocations (TD). Despite the high density of TD, Rouvière et al.¹ reported preferential nucleation of GaN/AlN quantum dots near threading dislocations in AlN. From integral photoluminescence, persistent QD emission despite the close proximity to dislocations was concluded, but microscopic evidence was not provided.
Using cathodoluminescence spectroscopy performed in a scanning transmission electron microscope (STEM-CL) we give direct evidence of quantum dot like emission from nanometer-sized GaN islands nucleated in close proximity of TD. The islands result from GaN quantum well layer growth by metal-organic vapor phase epitaxy on AlN/sapphire templates. After deposition of few monolayers of GaN forming the QW layer a growth interruption without ammonia supply was applied prior to cap layer growth of 40 nm thick AlN.
The cross-section STEM image clearly shows the AlN/sapphire template and the GaN quantum well (QW) layer. Originating from the AlN/sapphire interface vertically running TDs show up in the STEM images. In dislocation free domains, the GaN QW layer with 1-2 monolayer thickness can be observed. In the presence of TDs islands of GaN with twice the QW thickness across a lateral extent of about 100 nm are formed. By comparison of the STEM images with the simultaneously recorded panchromatic CL mappings at 16 K the highest intensity is unambiguously asserted to the GaN islands. Very sharp emission lines with line widths below 500 µeV between 220 nm and 300 nm are measured which confirms QD-like electronic properties within these islands. In defect free regions, the blue shifted emission from the GaN quantum well at 210 nm wavelength with a FWHM of 220 meV can be seen.
In conclusion, the thickness fluctuations of GaN monolayers preferentially occuring at threading dislocations act as confinement potential for generated excitons in all three dimensions. The TDs do not inhibit the quantum-dot like emission with state-of-art GaN/AlN QD line widths^2-4.
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[1] J. L. Rouvière et al., APL 75, 2632 (1999)
[2] S. Sergent et al., APL 103, 151109 (2013)
[3] M. J. Holmes et al., Nano Lett. 14, 982 (2014)
[4] F. Demangeot et al., pss C 6, S598 (2009)

GaN-based high electron mobility transistors (HEMTs) offer excellent high-power and high-frequency performance, allowing them to amplify high power signals at microwave frequencies very efficiently. The current in GaN HEMTs flows in a two-dimensional electron gas at the interface between GaN and AlGaN layers, which offers excellent electrical properties (high carrier density and mobility). Understanding the physics of failure in these devices remains an important issue, with both abrupt failures and gradual parametric degradation having been observed. These devices may show sudden and permanent damage when subjected to very high reverse bias-stress. This failure mechanism has been addressed by improvements in processing technology. However, the parametric degradation that occurs in the “semi-ON” state at moderate drain biases remains an issue. In this condition, the device is biased close to pinch-off, but the relatively small numbers of electrons that are flowing are accelerated by a high electric field. The resulting energetic carriers can activate, by dehydrogenation, or reconfigure defects near the interface. The defect generation is greatest at the end of the gate on the gate-drain side, where the lateral electric field is at its maximum. This may lead to significant reductions in drain current and transconductance, as well as shifts in threshold voltage, resulting in poor DC, RF and large-signal performance.
GaN/AlGaN HEMTs grown under various conditions (i.e., gallium-rich, nitrogen-rich, and ammonia-rich) have been analyzed and the defects responsible for degradation in each device type have been identified. The atomic-scale nature of the traps that produce changes in threshold voltage, leakage current, and drain current have been related to changes in transconductance and turn-off voltage using a combination of electrical measurements, quantum mechanical calculations, Monte-Carlo device simulations, and accelerated degradation tests. A relatively simple formulation has been developed under the assumption that the hot-electron scattering cross-section is independent of the electron energy. In this case one can relate the change in defect concentration to the operational characteristics of a device, such as the spatial and energy distribution of electrons (electron temperature), electric field distribution and electron energy loss to the lattice. The number of electrons with energy (obtained from device-level Monte Carlo simulations) in excess of that required to activate a defect (obtained from density functional theory) is used to predict the degradation rate.
The results of quantum mechanical calculations of candidate defect formation energies as functions of growth conditions and Fermi level position were used to identify the primary defects responsible for the degradation as hydrogenated Ga vacancies or hydrogenated N antisite defects. In each case, degradation occurs by the hot electrons providing the energy needed to release a hydrogen atom. The calculations also yield the activation energy for hydrogen release.

Potentiometric solid state chemical sensors can be operated on the differential mode using a pair of sensing films. The first one corresponds to the principal sensing element, whose output voltage is affected by the noise and the signal from the target analyte. The second film corresponds to a contrast sensing element with output voltage affected by the noise only, in theory. However, the contrast film also possesses an undesired output voltage due to the signal from the target analyte. Here, pairs of films possessing a large difference between their analyte sensitivity and almost equal sensitivity to the noise are studied. Noise is here interpreted as any systematic variation of an undesired parameter, and not 1/f. Temperature, buffer concentration and time variation were studied. Differential measurements were performed in a differential Instrumental Amplifier Extended Gate Field-Effect Transistor (D-IA-EGFET) device. Three materials in 4 single films were used as the sensing element of the device: i) non-protonated polyaniline (PANI-EB), ii) protonated polyaniline (PANI-ES), iii) fluorine-doped tin oxide (FTO) and iv) titanium dioxide (TiO₂). The pairs were composed of: i) PANI-EB x PANI-ES; ii) PANI-EB x FTO and iii) FTO x TiO₂. Measurements were performed in buffer solution with pH from 2 to 8. This allowed the determination of pH sensitivity for each film. Using D-IA-EGFET the above pairs were characterized for the same pH range. For solutions with fixed pH 6, results were obtained as a function of temperature in the range 30° C to 50° C and buffer concentration from 1 mM to 400 mM. Time evolution was also monitored up to 60 seconds. PANI-EB x PANI-ES pair presented the best results with a sensitivity of 42 mV/pH, linearity of 97 %, and stable response against the variation of the above parameters. PANI-EB x FTO pair presented sensitivity of 35 mV/pH, linearity of 97 % and stable response only for time variation. The last pair, FTO x TiO₂ presented sensitivity of 25 mV/pH, linearity of 98 % and stable response for buffer concentration and time variation. PANI films are conductive polymers, FTO is a conductor and TiO₂ a semiconductor material. When used to detected ionic species, PANI films are characterized by the ion exchange mechanism, while the site binding ion-sensing mechanism occurs for FTO and TiO₂. The properties of the single films determine their effectiveness in the differential mode. Thus, the sensing films must have similar properties according to the noise to be canceled. The electrical characteristics of the single films dictated the differential sensor effectiveness against temperature variation, while the properties of potential determination by ion-sensing mechanism determined the behavior according to the buffer concentration variation. In summary, the PANI-EB x PANI-ES pair will correct cancel the undesired variations. This work was supported by CAPES, CNPq and FAPESP Brazilian agencies.

In manufacturing semiconductor devices, drying after chemical treatment is important since many particles and defects are generated during drying step. Among defects caused during drying step, leaning and collapse of pattern due to high surface tension of rinse liquid become more important since aspect of ratio of pattern increases as device shrinks. To prevent leaning of pattern, hot Isopropyl Alcohol (IPA) which has lower surface tension than water was used for drying liquid. However, there is limit of temperature due to bubbling and lower surface tension of hot IPA is not enough to prevent leaning of pattern as device shrink since surface tension of IPA become saturated as temperature increases. Therefore, we tried to prevent leaning through controlling other parameters which effect on stress of pattern. In general, max stress to pattern during drying process is expressed as bellows ;
σ_max=6γbull;costheta;bull;(A/R)² / D
Which refers to γ: Surface Tension, A/R : Height / Width, D : Distance between pattern, theta; : Contact Angle.
To decrease stress to pattern, surface tension and A/R have to decrease and distance between patterns have to increase. Also, stress to pattern is proportional to costheta; and increase of contact angle of liquid to substrate reduces applied pattern stress during drying process. Based on equation, stress to pattern can be near zero when contact angle of liquid to substrate becomes near 90 degrees. To increase contact angle, we selected water for drying liquid instead of IPA since it is easy to increase contact angle through hydrophobic or water repellent coating of surface. Among many water repellent coating chemicals, contact angle near 90 degrees to substrate was obtained and we applied this chemical to ISO pattern in coupon test. In top view SEM images, pattern leaning occurred after drying using water and IPA. Also, partial leanings of pattern occurred even using hot IPA. However, in our coupon test, there was no leaning after drying using water repellent coating chemical. Based on coupon evaluation results, we tried to apply this chemical to ISO pattern of 300mm full wafer using LAM DV-P single spin cleaning equipment. After treatment of water repellent coating chemical to ISO pattern wafer, there was no leaning observed with top view CD-SEM. To detect pattern leaning of full wafer more precisely, wafer inspection was done. In wafer inspection result, there are leaning in edge of wafer due to non-uniformity of etching depth in ISO pattern of aspect ratio of near 11 in case of hot IPA. Also, there are too many leaning to scan full wafer and scan stop in beginning of scanning at the pattern of aspect ratio of 12. However, we obtained near leaning free after water repellent chemical treatment to ISO pattern of 300mm full wafer in pattern of aspect ratio of 11 and there was little leaning in pattern of aspect ratio of 12.

Zn-IV-N₂ semiconductors, where IV refers to Si, Ge or Sn, consist solely of earth abundant, non-toxic and inexpensive elements. They point the way to next generation nitride semiconductors for optoelectronic devices such as full-solar spectrum photovoltaics, three-color LED displays and high-performance laser diodes. However, there is a lack of researches on the valence band structure of Zn-IV-N₂ semiconductors, especially about ZnSnN₂ due to the difficulty of preparing materials surfaces for photoemission studies.
In this study, the valence band structure of ZnSnN₂ was investigated by x-ray photoelectron spectroscopy (XPS). 400nm thick polycrystalline ZnSnN₂ thin films were prepared, using reactive RF-sputtering deposition on a c-plane sapphire substrate. The X-ray diffraction (XRD) measurement of films indicated that ZnSnN₂ has an orthorhombic crystal structure in a Pna2 space group. This is proved by the a, b, c lattice parameters of 5.86 Å, 5.51 Å and 6.77 Å. These values are consistent with theoretical calculations, based on density functional theory (DFT) (which calculated a, b, c lattice parameters are 5.91 Å, 5.54 Å and 6.81 Å). The direct band gap of films was estimated to be 1.8eV, based on the linear extrapolation from the square of the absorption coefficient (α²) versus photon energy (hnu;). The Hall measurement has shown that ZnSnN₂ is a kind of n-type materials with electron concentration ranging from 8.4×10¹⁹ cm^-3 to 2.2×10²⁰ cm^-3.
The XPS investigation was conducted in an ultra high vacuum (UHV) chamber with the pressure of 10^-8 Torr. The instrument was calibrated, using the Fermi edge of a gold reference sample. The experimental results have demonstrated that the Fermi level of ZnSnN₂ is above the valence band maximum (VBM) 2eV, which results in a filled conduction band and can be explained by the Burstein-Moss effect. Theoretical calculations based on the DFT method have revealed that the electrons from N 2p orbital as well as Zn 3d orbital contribute to the main electronic structure of the valence band. Agreement between the theoretical valence band density of states (VB-DOS) and the XPS valence band spectrum has been achieved by considering the instrumental broadening and the shift in VBM.

NAND Flash memory device has been aggressively scaled down for higher density and cost reduction for several years. Especially, tunnel oxide (Tox) has become thinner to obtain better gate controllabitity and narrower threshold voltage (Vth) distribution of NAND cells. However, the extremely down-scaled Tox leads to a degradation of reliability originated from traps in Tox and interfacial traps between the Si substrate and Tox. In order to suppress those trap sites on sub 20-nm technology, we investigate the chlorine incorporation during tunnel oxidation process.
The Chlorine concentration profiles between the Si substrate and Tox are observed by secondary ion mass spectroscopy. To evaluate Chlorine incorporation effects in Tox, we measure reliability and electrical characteristics such as charge-pumping (CP), charge-to-breakdown (Qbd), stress-induced leakage current (SILC) and random telegraph noise (RTN). These results show that Chlorine incorporation makes lower trap density in Tox and at the interfacial layer as well as better reliability characteristics, compared with the conventional NAND cells.

Process-induced defects in electroplated Au interconnect metallization on GaAs devices were detected during the course of reliability testing. Abnormally high lognormal sigmas (σ > 0.7) indicated the existence of a bi-modal failure mechanism. A distinct early lifetime failure mode was observed along with the intrinsic electromigration metallization wear-out failure mode. Increased temperature stress showed only a slight acceleration on the early failure mechanism but selection of a higher resistance degradation failure percentage criterion reduced the extent of these early failures. Physical characterization of the electroplated Au film revealed as-deposited nanoscale voids. Elimination of these voids through process improvement as well as suggested mechanisms for the early failures is discussed.

We study the influence of interfacial polymer morphology on charge accumulation and transport in organic field-effect transistors (OFETs) by combining transport measurements, infrared charge modulation and vibrational spectroscopy, and DFT calculations. n-type poly{[N,Nprime;-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5&’-(2,2&’-bithiophene)} (Polyera ActivInk N2200) OFETs were fabricated treating the gate dielectric with different self-assembled monolayers. The resulting molecular inter-layers have a two-fold effect: they reduce trap state density at the dielectric interface and affect interfacial morphology of the polymer film by modifying the surface energy. OFET transport characteristics show excellent n-type transistor behavior, with significant improvement of electron mobility and on-off ratio in devices treated with self-assembled layers and with the most hydrophobic gate dielectric surface. This is in good correlation with results from infrared charge modulation spectroscopy (IR-CMS), a unique electro-optical technique to selectively probe polaronic and vibrational transitions of the conjugated polymer at the nanometer-thick charge accumulation layer. Density functional theory (DFT), Raman and linear vibrational spectroscopy are also used to isolate the effects of self-assembled monolayers on the interfacial morphology of the active material and its influence on transport properties.

With charge carrier mobility of organic materials far exceeding that of amorphous silicon, making them real candidates for commercial applications, the next challenging issue lies in realizing their potential in developing stretchable electronics. The promises of wearable and biocompatible device have made stretchable organic semiconductors highly desirable and a class of its own. Here we prepared a series of DPPTT-based polymer semiconductors with varying density of an 18-carbon linear alkyl side chain. The objective is to investigate chemical moieties that encourage elasticity by modifying the molecular structure of the polymer. Ideally stretchability could be introduced without compensating high charge mobility. The 10% and 20% linear alkyl side chain polymers showed an improvement in hole mobility but a decrease in mechanical properties. From dichroic ratio experiments the 20% polymer is stable up to 50% strain while the 10% polymer is stable up to 100% strain. UV-Vis of individual polymer films suggest an increase in linear alkyl side chains induces a more planar structure as well as an increase in H-aggregation, hence an improvement in mobility but a compromise in stretchability.

1. Introduction
#12288;Reduction of thermal conductivity using impurity, point defects, nano-precipitates, nano-grains, interfaces and etc. is one of the key strategies to improve the dimensionless figure of merit ZT for thermoelectric materials [1]. Magnesium half silicide Mg₂Si is promising n-type thermoelectric material used in a middle temperature range (400K - 800K) [2,3]. A number of donor impurities such as Bi, Sb, As, P and Al are investigated to optimize the electron concentration for obtaining the optimal ZT and thermoelectric properties in Mg₂Si [2-4]. Effects of donor impurity on thermal conductivity in Mg₂Si, however, have not been investigated systematically. In this paper, we investigate the effect of Bi and Sb dopant impurity on the lattice thermal conductivity in single crystalline like Mg₂Si grown from the melt.
2. Experimental
#12288;Bulk Mg₂Si crystals with well-developed crystalline domains were grown by the vertical Bridgman method using a BN coated alumina crucible [2,4]. Source materials of Si (99.999%) and Mg (99.98%) were weighed at stoichiometric composition and charged in the crucible with Bi (99.999%) or Sb (99.9999%) dopant element. The amount of Bi and Sb dopant in the charged source was varied between 0 and 3 at%. Characterization of the grown crystals was carried out by optical microscopic, SEM and TEM observations and XRD analysis. Thermal conductivity and thermoelectric property were measured using Nano Flash (Netzsch LFA447) and ZEM-III (ULVAC-RIKO), respectively. Carrier concentration and practical dopant concentration in the grown crystals were determined by Hall effect and XRF measurements. Lattice constant depended on the dopant concentration was also evaluated at 25°C by the precise powder XRD measurement using Si-internal standard. Lattice thermal conductivity was also calculated using the first-principle technique based on anharmonic lattice dynamics (ALD) method.
3. Results and Discussion
#12288;Average concentrations of Bi and Sb dopant in the grown crystals were approximately 20 % and 50 % of the added dopant in the source, respectively. This result is acceptable for the conventional melt grown crystal, and the practical dopant concentrations were well accorded with the electron concentration of the measured Mg₂Si specimens. The lattice thermal conductivity at 300K reduced significantly with increasing the dopant concentration even if the very small practical dopant concentrations. The lattice thermal conductivity of Sb and Bi doped sample decreased to 3.3 W/mK and 2.9 W/mK at practical dopant concentration of 1.2 at% and 0.5 at%, respectively, which is approximately 30 % of the non-doped samples. This result agreed well with theoretical calculation based on the ALD method.
References
[1] Y. Lan et al., Adv. Funct. Mater., 20(2010)357-376.
[2] H.Udono et al., ICT, C.a.5(2008)Oregon, USA.
[3] J. Tani et al., Intermetallics, 15(2007)1202-1207.
[4] T.Takahashi et al., TSJ, PS-13(2011)Japan.

As continuously scaling down the devices for logic circuit, higher mobility channel materials have been considered to boost driving current such as Ge or SiGe. However, most high mobility materials have a significantly smaller bandgap as compared to Si, which will result in higher Band-To-Band-Tunneling leakage. As a result, S/D and channel engineering must play leading role for boosting the device performance. We, therefore, propose a NiSiGe/n-Si Schottky Junction formed microwave-annealing for the Si capped SiGe quantum well devices (Si/Si_xGe_1-x/Si,x=0~1).
The multi-layer structure of Si/Si_0.57Ge_0.43/Si was grown by ultra-high vacuum chemical vapor deposition system. The channel composed of a 5nm-thick SiGe with biaxial compressive strain and Si cap was grown at 420~500 and 550 °C, respectively. Isolation film SiO₂ was deposited on multi-layer architecture after series surface cleaning. Then, the definition of junction active area was accomplished with lithography and wet-etching. Because of bulk annealing characteristic of microwave, the technique was utilized to form NiSiGe as low leakage Schottky junction ranging from 370 to 470 °C for 150 s in N₂ ambient. The un-reacted Ni film was removed, followed by Al deposition as the back contact. The characteristics of microwave-annealed-NiSiGe Schottky junction was investigated with AFM, SEM, TEM, XRD, and electrical analyzer.
The AFM images demonstrated the surface morphologies of NiSiGe layer with various annealing temperatures. NiSiGe agglomeration emerged as forming temperature up to 600 °C by rapid thermal annealing (RTA) which will lead to unstable junction current. Relatively, microwave annealing can suppress the formation of junction defects and prevent the agglomeration due to lower forming temperature. For the purpose of distinguishing the pros and cons between the microwave annealing and rapid thermal annealing (RTA), I-V characteristics were evaluated to check the electrical performance of Schottky junction. Microwave-annealed Schottky junction exhibited better I_ON/I_OFF ratio about 3×10⁵ formed at 350 °C and more stable off-current characteristic as compared to the one with rapid thermal annealing (RTA). In addition, barrier height and ideality factor of the microwave-annealed Schottky was 0.62 eV and 1.07, respectively. High resolution TEM images showed the polycrystalline structure, good uniformity of the NiSiGe and a distinct interface between NiSiGe and Si.
Microwave annealing is beneficial in integrating quantum well p-channel MOSFETs with Schottky S/D because of its low temperature feature. We believe our microwave-cooperated quantum well architecture is promising for the high performance logic circuits and enable SiGe or Ge channel devices to be integrated on the Si substrate for the future applications.

Polymeric semiconducting materials possessing effective π-π intermolecular interactions coupled with good solution processability have been highly investigated. Structure-property relationships associated with side-chain structure, π-π intermolecular interactions, polymer solubility, thin film crystallinity, and charge carrier transport are reported for a donor-acceptor(1)-donor-acceptor(2) polymer: 5-decylheptadecyl (5-DH), 2-tetradecyl (2-DT), and linear n-octadecyl (OD) side-chains are substituted onto a polymer backbone consisting of terthiophene units (T) between two different acceptor moieties, benzothiadiazole (B), and diketopyrrolopyrrole (D), pTBTD, to afford pTBTD-5DH, pTBTD-2DT, and pTBTD-OD, respectively. In the 5-DH side-chain, the branching point position is distant from the polymer backbone, whereas it is proximal in 2-DT. This study demonstrates that incorporation of branched side-chains with the remote branching position merges the advantages of improved solubility with effective π-π intermolecular interactions normally associated with linear chain substitution on conjugated polymers. The pTBTD-5DH material exhibits superior qualities with respect to the degree of polymerization, solution processability, π-π interchain stacking, and charge carrier transport relative to the other analogs. The polymer exhibits a field-effect hole mobility of as high as 2.95 cm² V^-1 s^-1, a 3-7 fold increase compared with that achieved with pTBTD-2DT and pTBTD-OD. [1]
Furthermore, 2,2&’-bithiazole was copolymerized with dithienyldiketopyrrolopyrrole to afford a novel n-channel poly(dithienyl-diketopyrrolopyrrole-bithiazole), PDBTz. PDBTz exhibited pure n-channel behavior with excellent ambient stability and an electron mobility reaching 0.3 cm²Vshy;^-1s^-1 based on organic field-effect transistors (OFET) characterization, in contrast to a recently discussed isosteric conjugated polymer, a copolymer of the electron rich bithiophene with dithienyldiketopyrrolopyrrole possessing pure hole transport (p-channel) characteristics. This inversion of charge carrier transport characteristics suggests a significant potential for bithiazole in developing robust n-channel semiconducting materials. Significantly, 5-DH side-chain was incorporated into PDBTz to enhance polymer solubility in non-halogenated solvents, and hence the system may have desirable characteristics for large-scale fabrication of devices. PDBTz cast from non-halogenated solvents exhibited excellent electron transport performance based on OFET results and film morphologies commensurate with high mobility. [2]
[1] Fu, B., Baltazar, J., Sankar, A. R., Chu, P.-H., Zhang, S., Collard, D. M. and Reichmanis, E. (2014). Adv. Funct. Mater., 24: 3734-3744. doi: 10.1002/adfm.201304231
[2] Fu, B. et. al.(2014), Molecular Engineering of Bithiazole Based Soluble n-Channel Polymer Semiconductors. To be submitted.

Pm-Si:H PIN and NIP solar cells structures grown using plasma enhanced chemical vapor deposition (PECVD) technique were analyzed during 400 hrs of light-soaking exposition. The evolution of the structural and optical properties was observed and characterized by Raman spectroscopy, spectroscopic ellipsometry and exodiffusion experiments. The effect observed is related to defects creation due to induced hydrogen diffusion, break of Si-H bonds and the generation of dangling bonds that causes less passivated films. The film microstructure, hydrogen stability, configuration and therefore the optical properties varied with the exposition time. The crystalline fraction of these structures is between 12 to 18% and increase with the exposition time. The optical gap decreases from 1.76 to 1.6 eV for the PIN structure while for the NIP decreases from 1.62 to 1.54 eV. The hydrogen stability and its amount bonded in these films are dependent of the device architecture. Hydrogen diffusion induces structural crystallization and generates a decrease on the absorption properties of the films which in turn is expected to reduce the device efficiency during operation. In this work we show that long range motion of hydrogen during light soaking causes a hydrogen rearrangement on the film and microstructure changes along with a shift on the exodiffusion peaks. Hydrogen diffusion is very different during light-soaking for both structures. We determined that the total hydrogen that effuses from PIN structure is lower than for the NIP, which is expected to cause less degradation of its optoelectronic properties under illumination, and a more stable device during operation.

The hetero-junction photodiodes based on silicon and III-V compound semiconductors provide significant advantages in the high speed operation and the utilization of wide wavelength range of light due to the high carrier mobility of III-V semiconductors and various combination of different band gap semiconductors. Furthermore, standard silicon processes can be employed in the fabrication of III-V/Si hetero-junction photodiodes. However, hetero-integrations of III-V compound semiconductors on silicon substrates by the traditional methods such as wafer bonding and direct growth suffer from the lattice and thermal mismatches between the two dissimilar materials, resulting in the generation of defects and the degradation of electrical/optical properties. In this study, we introduce room-temperature epitaxial layer transfer printing technique for the hetero-integration of III-V semiconductors on Si substrates with high interface quality and electric/optical performances. Although the hetero-junction photodiodes are fabricated at room temperature, our device shows high rectification ratio of 7.7 x 10⁴ at ±3 V and very low leakage current of 7.4 x 10^-5 A/cm² at -3 V in dark state. Under the light power of 48 mu;W at wavelength of 750 nm, we achieved the photo-responsivities of 7.5 and 1.9 AW^-1 at reverse bias of -3 V and near zero bias condition respectively. The epitaxial transfer printing introduced in this study can be potentially employed for the fabrication of various combination of hetero-junction semiconductors for diverse optoelectronic applications.

Over the last decade, InAs quantum dots (QDs) on GaAs substrate grown by Stranski-Krastanov (S-K) mode represent one of the most promising technologies for applications in quantum photonics. The issues of broad linewidth in the Photoluminescence (PL) spectrum can be overcome by the thinning the GaAs barrier layer gap between seed and active layer QDs for enhancing the efficiency of QDs devices. This paper will revealed the benefit of using ultrathin barrier layer on a QD heterostructure to advancement in optoelectronics application.
This abstract deal with the detailed investigation of coupled bilayer InAs Quantum dots (CBQDs) by using ultra thin GaAs barrier layer (scale down upto 4 nm) and impact of rapid thermal annealing (RTA) on their optical properties. With fixed seed layer QD coverage of 2.5 ML, bilayer dots were overgrown with varying GaAs barrier layer of 4.5 nm (sample A), 4 nm (sample B) and the details study is carried out by photoluminescence (PL) spectra, atomic force microscopy (AFM) and transmission electron microscopy (TEM). From the PL spectrum at 18k, we observed sample A gives long emission peak of 1191 nm. Comparing the above two samples, we have also grown another sample C with 3.2ML QD coverage and 4.5nm GaAs spacer. With decreasing the barrier thickness, the position of dots between the seed and active layer exhibit a vertical align transition interrelationship. For ultra-thin GaAs spacer layer, maximum electron carrier tunneling was observed which can be very compact and is also capable of high-speed operation at terahertz frequencies. From the Room temperature PL spectrum, we have observed the emission peaks of sample A,B and C at 1247 nm, 1231 nm and 1271 nm respectively. Therefore, by using 4.5 nm GaAs barrier layer with 3.2ML QD coverage, we have observed long wave emission peak. The calculated activation energy from temperature dependent PL spectrum for sample A, B and C are 330.46 meV, 292.74 meV and 332.29 meV respectively which suggested sample C has better confinement. From the AFM results, sample C shows homogeneous in dot size array (dot density 1.6×10¹⁰/cm² ) compared to sample A and B. The QDs height and width for sample C are 4 ± 1 and 14-17 nm which are calculated from TEM images by using ImageJ software. To remove the as-grown defects from the heterostructure and also to check the stability in PL peak, we have done RTA for all the samples at different temperature ranging for 650°C to 800°C. The minimum blue-shift in PL peak is observed from sample C (~15.5 nm) from as-grown to 800°C). The percentage variation in activation energy of each sample namely sample A, B, C along with annealing temperature was found to be 37.5, 62.77 and 22.17 respectively. Also from TEM micrograph, we have observed the QDs in sample C maintain uniform size and shape till 800°C annealing temperature. Riber, France and DST, India is acknowledged.

A new donorminus;acceptor organic semiconducting co-polymer (PDPP-TAT) containing acetylene linkages based on dithienyl-diketopyrrolopyrrole (tDPP) has been synthesized and compared with a tDPP-based co-polymer (PDPPTVT) containing vinylene linkages. The sp-hybridized carbons in the acetylene linkages result in favorable overlap of the electron wave functions of the tDPP units along the main chain. Further, the π-conjugation of PDPP-TAT was found to be highly insensitive to the chain conformation, in contrast to that of PDPP-TVT. As a result, PDPP-TAT provides favorable charge transport for electrons as well as holes, and enables facile charge transport in amorphous and tie-molecular regions connecting its crystalline domains. PDPP-TAT exhibits ambipolar characteristics with a high electron/hole mobility ratio (mu;_e/mu;_h) of sim;0.3 in field-effect transistors, whereas PDPP-TVT exhibits unipolar characteristics with a mu;_e/mu;_h value that is a factor of 30 lower. Our results demonstrate that the conformation sensitivity of charge transport is a vital factor in the electrical performances of actual organic transistor devices.

In a manufacturing semiconductor device, drying technique after using chemical becomes more important since particles and defects caused during drying make large yield loss of devices. Among defects caused after dry of chemical, pattern leaning due to high surface tension of rinsing water causes difficulty of patterning and cleaning as aspect ratio of pattern increases. In DRAM device, the height of capacitor pattern becomes higher to obtain enough capacitance since surface area of capacitor decreases as device size decreases, and this causes more patterns leaning after removing oxide using chemical. To prevent pattern leaning, hot Isopropyl Alcohol (IPA) which has lower surface tension than water is used for drying. However, low surface tension of hot IPA becomes insufficient to prevent pattern leaning of high aspect ratio pattern. To solve this problem, we searched another method to prevent pattern leaning. In general, max stress to pattern during drying process is expressed as σmax=6γmiddot;costheta;middot;(A/R)² / D ; (γ: Surface Tension, A/R : Height / Width, D : Distance between pattern, theta; : Contact Angle). To prevent pattern leaning, we have to decrease surface tension, A/R and increase distance and contact angle to substrate. As device shrinks, decrease of A/R and increase of distance is undesirable for device manufacturing. Therefore, we tried to increase contact angle of liquid to substrate. Also, in capacitor patterning process, we use silicon oxide layer for mold for capacitor structure and after etching this oxide layer, TiN layer is deposited inside etched hole type structure. After this process, buffered oxide etchant (BOE) is used to remove mold oxide layer and this removing step of oxide causes leaning of pattern since height of capacitor pattern is over 1000nm. Therefore, we tried to increase contact angle of water to TiN substrate. To increase contact angle of water to TiN substrate, we used water repellent chemical coating on TiN substrate. After water repellent chemical treatment, contact angle of water on TiN substrate increased to 90 degrees, which is higher than no treated TiN substrate of 10~20 degrees. We applied this chemical to pattern by coupon test and leaning of pattern was decreased in capacitor pattern of A/R 20 without supporter structure. For the full wafer test, we used single spin type equipment (LAM DV-P) and process sequence was as below; BOE treatment → DIW rinse → water repellent chemical coating → DIW rinse → dry
We discovered that temperature and viscosity of chemical have important effect on leaning of pattern in full wafer test. Also, pre treatment and post treatment of IPA in water repellent chemical step decreased residue and leaning of pattern. Using these results, we applied this chemical to full wafer capacitor pattern of A/R 20 without supporter structure and we obtained the result of few leaning in cell center. However, there are still leanings in edge of cell and improve evaluation is under progress.

The molecular design of high-performance conjugated polymers is based on molecular-orbital energetics and crystal-engineering concepts that are capable of efficiently controlling the frontier orbital energy levels and the p-orbital overlap, because these factors are closely related to charge injection and transport. The conventional notion that the energy levels and the band gaps are primarily governed by conjugated building blocks in the backbones has driven rapid progress in the molecular design of conjugated backbones.
In recent years, studies have shown that side-chain engineering can significantly affect molecular packing and the p-planar distance, in addition to its conventional role as a solubilizer
Herein, we present the results of our study in side chain engineering based on poly(diketopyrrolopyrrole) to optimize the side-chain length for maximum charge-transport capabilities, as well as to study the molecular structural-electrical property relationships.

Cadmium Zinc Telluride (CZT), considered as a viable material for use in room temperature radiation detectors, has an undesired presence of tellurium inclusions in the bulk. Thermal treatment, in the form of annealing, has been utilized to test the viability of refining CZT into better detector material, either by the elimination of the Te inclusions or by the migration of the inclusions under a temperature gradient, but usually with a deterioration of electrical properties. We took infrared micrographs and current voltage (IV) characteristics of CZT samples prior to thermal treatment. We carried out 24-hour thermal treatments with a range of temperature from 100^oC to 700^oC to determine an optimal annealing temperature and to verify change in the sizes, morphologies, and locations of the tellurium inclusions on the surfaces and within the crystal bulk of the CZT. The IV curves and resistivities prior to and after thermal treatments were compared, as were the infrared micrographs before and after annealing. Also, the changes in electrical properties of the samples with annealing conditions were compared against structural changes monitored at the same steps during the annealing process, in order to understand the effects of the thermal annealing to the radiation detector properties of the material. Correlations between the shape, size and position of inclusions and electrical properties of the material were attempted.

Spacecrafts are required to be less size, weight and cost. These requirements are available to apply thin film solar cells for solar paddle. Particularly, flexible solar cells are needed for new type of satellites, for example, a space solar sail. A copper indium gallium di-selenide (CIGS) thin-film solar cell is suitable for these types of satellites.
CIGS solar cells are promising candidate for future thin-film space solar cells since it has demonstrated high conversion efficiencies exceeding 20%. This is significantly higher than other thin-film solar cells such as a-Si. Excellent radiation tolerance of CIGS thin-film cells has also been reported. The cells have potential to be low-cost, lightweight and flexible since they can be formed on polyimide or metal sheet substrates. Therefore, we can develop flexible solar paddles with utilizing the CIGS cells.
Radiation damage studies for CIGS thin-film solar cells had reported that electrical properties of the cells do not degrade by high-energy electrons. We monitored the electrical performance of CIGS cells under electron irradiation. This experiment revealed that the performance degrades under irradiation, and it rapidly recovers at room temperature after the irradiation. This result confirmed that CIGS cells have high radiation tolerance for electrons.
We have demonstrated on-orbit performance of CIGS solar cells by using Japanese small satellites since 2002. CIGS solar cells on the MDS-1 satellite were exposed in GTO environment for about 600 days. The short-circuit current of the CIGS cells did not degrade, and the open-circuit voltage of the cells degraded only about 1 %. Theses results prove high radiation tolerance of CIGS solar cells. The results enabled us to expect that any shielding materials such as a coverglass are not necessary for CIGS solar cells to suppress radiation degradation in space.
We have been operating the Cubesat XI-V satellite for more than five years since October, 2005. A CIGS cell module without a coverglass is mounted on one of the surface planes. The generation current of the module has been monitored since then. The result so far shows that the generation current trend of the CIGS module exhibits constant values for over eight years in orbit. The flight data is proving that the performance of CIGS cells does not degrade even without a coverglass.
These results from space demonstrations must prove for space using of CIGS solar cells.

GaN reliability has been studied by examining the effects of radiation and threading dislocation density (TDD) on GaN and AlGaN/GaN HEMTs. GaN and its alloys are radiation-hard materials compared to more conventional semiconductors, making them very promising for space applications. Current GaN HEMT research has mostly focused on device degradation without identifying the defects causing this degradation or the defects&’ formation mechanism. This work investigates the identification of these defects. The effect of line defects, specifically dislocations, is also studied. Mobility as well as device degradation is shown to be highly correlated to TDD.
The formation and properties of defects created from high energy proton irradiation was systematically studied by high-resolution deep-level transient/optical spectroscopy (DLTS/DLOS) measurements. Through this process new bandgap states have been identified. Formation energies of electrically active point defects are a function of Fermi Level position. Studies of n-type versus p-type GaN have been done to understand the effects of Fermi level position on radiation-induced trap states. Different trap levels with different introduction rates have been found for p-type vs n-type GaN, showing the effects of Fermi level position on electrically active point defect formation. We have also been able to understand the mechanism behind the widely reported positive threshold voltage shift after irradiation in HEMTs. The shift is due to the creation of traps in the GaN buffer. The buffer traps reduce the 2DEG density. Careful comparisons of heterostructures to fully processed HEMTs and Si-doping studies of the buffer layer have all pointed to buffer traps. By Si-doping the buffer, the threshold voltage shift is pushed to higher irradiation fluences. All the work on bulk GaN layers, AlGaN/GaN heterostructures and HEMTs are consistent with GaN traps at energies E_C-3.25 eV and E_C-1.25 eV causing threshold voltage shifts in the HEMTs.
The effects of TDD on mobility for bulk n-type GaN layers and AlGaN/AlN(2 nm)/GaN HEMTs has been studied. Peak low temperature mobility for bulk layers increased from 348 cm²/Vs to 3327 cm²/Vs when the TDD was reduced from 2 x 10¹⁰ to 2 x 10⁶ cm^#8209;2. Room temperature mobility increased from 317 cm²/Vs to 1265 cm²/Vs for the same samples. Low temperature (77 K) mobility for AlGaN/AlN(2 nm)/GaN HEMTs increased from 2330 cm²/Vs to 10640 cm²/Vs when the TDD was reduced from ~10¹⁰ to ~ 10⁷ cm^#8209;2. Room temperature mobility increased from 1240 cm²/Vs to 2020 cm²/Vs for the same samples. Device performance was also assessed by studying the effects of TDD on device degradation, including maximum drain current, gate-lag, and trap generation evaluated from drain current. AlGaN/GaN HEMTs with low TDD (~10⁷ cm^#8209;2) show no degradation during off-state stressing while high TDD (~10¹⁰ cm^#8209;2) HEMTs showed significant degradation.

[Introduction] The bandgap of In_xGa_1-xN can be tunable from near infrared (InN at 0.65 eV) to ultraviolet (GaN at 3.42 eV) by changing In composition, which provides an almost perfect match to the solar spectrum. However, even if many efforts have been made by many groups, the present conversion efficiency of InGaN solar cell is quite far from their theoretical one. In the InGaN solar cell structure, to obtain the excess absorption, the thickness of InGaN film higher than 300 nm is necessary. Therefore, to understand the nature of the photovoltaic properties and further improve the performance of InGaN solar cells, it is important to investigate the behaviors of solar cell with a thick InGaN active layer. In this study, the current transport mechanism at different temperatures of a InGaN p-i-n homojunction are investigated. It is found that the traps inside the p-InGaN region are considered to be the dominant reason that degrades the photovoltaic properties.
[Experiment] Sample used in this study is the InGaN p-i-n homojunction solar cell which was grown on GaN/sapphire templates using a metal organic chemical vapor deposition system. It contains a 150 nm-thick n-In_0.15Ga_0.85N epilayer, 240 nm-thick i-In_0.15Ga_0.85N active region, and 90 nm-thick p-In_0.15Ga_0.85N layer. A 15 nm-thick p-GaN was further deposited for ohmic contact. The devices were
fabricated using a standard semiconductor processing technique.
[Results] The dark I-V characteristics dependent on the temperature was performed from room temperature to 373 K. It is noted that the electrical behaviors at the forward region display a large variation with temperature. From 0 to 1.5 V, the slopes of lnI-V plots show a strong dependence on temperatures, which can be described by the thermionic emission transport. However, at the higher voltage, the tunneling becomes the dominant transport of carriers, which are less dependent on temperatures. The great variation of the I-V curves in the forward region brings forward a great degradation of the photovoltaic properties. The open-circuit voltage degrades rapidly with increasing temperature, while short-circuit current density first increases and then decreases. From analysis, the traps inside the p-i-n junction are the dominant reason that degrades the photovoltaic performance of the solar cell at high temperatures. These traps are mainly located inside the p-type region, and thermally sensitive. Possible sources of traps states include dislocations, impurities, or Ga or N vacancies.

Continuous demand for improved device technology has made insulated-gate and surface-passivation structures inevitable for AlGaN/GaN power switching transistors. In particular, the deposition of insulator films on the access region surface of the transistor controls surface traps, leading to operation stability and reliability improvement. From the viewpoint of the HEMT application, it is desirable to evaluate interface state properties using an actual AlGaN/GaN structure with a very thin AlGaN layer (15-25 nm). Accordingly, this paper presents characterization of electronic states at insulators/(Al)GaN interfaces, particularly focusing on insulator/AlGaN/GaN structures.
The undoped AlGaN/GaN heterostructure grown on a sapphire substrate by MOCVD was used in this work. We prepared Al₂O₃/AlGaN/GaN (HEMT-MOS) samples with and without the etching of the AlGaN surface. For the etching of AlGaN, we used a Cl₂-based ICP process at RT. An Al₂O₃ film with a nominal thickness of 20 nm was deposited on the AlGaN surface by ALD at 350 0C for 170 cycles, using precursors of water vapor and TMA.
The HEMT-MOS samples showed characteristic capacitance-voltage (C-V) curves with two steps. The constant capacitance at the forward bias corresponds to the Al₂O₃ capacitance, whereas that at the reverse bias is determined by the total capacitance of the Al₂O₃ and AlGaN layers. To understand interface properties of the HEMT-MOS structure, we have developed a C-V calculation method taking into account charges in electronic states at the Al₂O₃/AlGaN interface. A comparison between experimental and simulation results showed that only a limited energy region of interface states is detectable using the standard C-V analysis at RT.
To evaluate near-midgap electronic states at insulator/AlGaN interfaces at RT, we have developed photo-assisted C-V method. First, under dark condition, a forward gate voltage high enough to observe the insulator capacitance is applied. At this state, almost all of interface traps are filled with electrons under a nearly flat band condition. After reaching a sufficiently negative gate bias, a monochromatic light with photon energy less than the bandgap of AlGaN is illuminated to the sample surface. After switching the light off, we restarted the voltage sweep toward 0 V under dark condition. Then, we can observe the C-V curve shift toward the reverse bias direction, corresponding to the photo-assisted change in the interface state charge.
For the first time, we have estimated the state density distributions of the Al₂O₃/AlGaN interfaces using the combination of the numerical fitting of C-V curves and the photo-assisted C-V method. The sample processed with the ICP etching included electronic states with densities higher than 2 x10¹² cm^-2eV^-1. The TEM image predicted disorder of the chemical bonds at the AlGaN surface, resulting in poor C-V characteristics due to high-density states at the Al₂O₃/ICP-etched AGaN interface.

GaInN/GaN superlattice structures are used as active layers in commercially available visible-light emitting devices. There are many interesting features that render these GaInN/GaN superlattice structures particularly useful as efficient light emitters. In addition, these GaInN/GaN superlattice structure are also useful in high conversion efficiency solar cells. Most devices employing GaInN superlattice are fabricated on GaN, because the growth of thick GaInN films with high crystallinity on substrates other than GaN is very difficult. Several studies have been previously conducted to elucidate the mechanism by which defects form via strain relaxation in GaInN/GaN superlattice structures, because it is necessary to minimize defect formation in order to improve device performance. However, current understanding of the critical layer thickness at which misfit dislocations are introduced in GaInN/GaN superlattice structures is insufficient. In this study, we observed the growth of the GaInN/GaN superlattice structure by in situ X-ray diffraction monitoring.
The samples were grown on c-plane sapphire substrates using metalorganic vapor phase epitaxy apparatus with a horizontal face down 2” × 3” reactor. After the growth of a 3-mu;m-thick GaN template at 1,050 °C on c-plane sapphire covered with a low-temperature GaN buffer layer using H₂ carrier gas at 933 hPa, it was cooled to 750 °C and the carrier gas was changed to N₂. Then, GaInN/GaN supperlattice structure was grown on the GaN template. The threading dislocation density of the GaN template was ~3 × 10⁸ cm^-2. We evaluated the GaInN films with symmetric (0002) Bragg diffraction using an in situ XRD system. As the results, the satellite peaks from the -1^st to the +1^st order can be obtained from these in situ X-ray diffraction spectrums. From the full width at half maximums (FWHMs) of the 0^th and -1^st satellite peaks as a function of the superlattice periods, we observed a clear trend in each FWHM. It was found that by analyzing this trend along with florescence microscopic and transmission electron microscopic analysis, an analysis of the In segregation and misfit dislocation are possible. Accordingly, if we employ in situ X-ray diffraction under various growth conditions, the optimization of the growth conditions will become easier because it would be possible to determine the number of periods at which In segregation and misfit dislocation increases by only one growth procedure.

As solid-state optoelectronics device manufacturing has continued to mature, so too have the characterization techniques and methods necessary for understanding the increasingly subtle defects responsible for device performance and reliability issues. Advances in scanning microscopies such as Focused Ion Beam (FIB), Scanning Electron Microscopy (SEM), and Scanning Transmission Electron Microscopy have allowed for identification and inspection of these smaller and more subtle defects. Although we have the tools that can resolve atomic scale defects, the main issues become how to find the defects in a reasonable amount of time and effort and how to make sure that what is being analyzed isn't an artifact of the analysis. Fortunately, we can progressively hone in on specific defect location by using a combination of lower spatial resolution techniques such as Electroluminescence (EL), Emission Microscopy (EMMI), Electron Beam Induced Current (EBIC), and Cathodoluminescence (CL) with higher resolution techniques such as FIB, SEM, and STEM through the use of imaging software overlays. In this review I will provide a variety of examples showing how this methodology of using complimentary techniques works to locate and identify highly localized defects helping to better understand the root cause failure mechanisms.

High spatial resolution spectroscopic information may be acquired by using an electron beam in a modern scanning electron microscope (SEM), exploiting a phenomenon called cathodoluminescence (CL) where electrons are promoted from the conduction band to the valence band upon impingement of the high energy electron beam onto a semiconductor. This approach offers several advantages over usual optical spectroscopy techniques. The multimode imaging capabilities of the SEM enable the correlation of optical properties (via CL) with surface morphology (secondary electron mode) at the nanometer scale [1] and the large energy of the electrons allows the excitation of wide-bandgap materials. In addition, CL sensitivity to material composition, as well as the presence of defects, makes it a technique of choice for device characterization.
Quantitative CL has extensively been used to study ageing effects and reliability issues in advanced III-V semi-conductor devices such as nitride-based power devices, light emitting diodes (LEDs) or vertical surface emitting laser (VCSEL) devices. Here, we will show an overview on the latest study on a selection of those devices.

The AlN/GaN/AlN quantum well (QW) structure has shown attractive properties such as a tunable 2DEG whose charge can be varied by the QW thickness as well as the barrier thickness. The 2DEG in the QWs provide the largest carrier confinement possible in Al(Ga)N/GaN material systems. Taking these advantages, HEMTs based on the AlN/GaN/AlN double heterostructures have been demonstrated. In these ultra-thin AlN/GaN/AlN structures, GaN is present in the very thin QW layer. Thus using QW structures and isotope ¹⁵N as dual optical marker can provide methods for the accurate study of the dependence of strain on thickness, and phonon relation to isotope effects. In this work, we start by calibrating the Raman spectra of quasi-relaxed GaN layers on SiC and Sapphire substrates, as well as completely strain-free bulk single-crystal GaN. We did the same for AlN on sapphire and bulk single-crystal AlN. Then we used these accurate calibrations for measurement of strain in thin GaN QW HEMT channels embedded in AlN. A larger frequency upshift of the E₂^H phonon is observed in GaN with decreasing well thickness, and is correlated to the compressive biaxial strain. All QW samples have shifts of E₂^H with ΔE₂^H > 25 cm^-1, indicating much higher strain levels than the modest shifts from calibration measurements of thick GaN-on-sapphire and GaN-on-SiC templates. To explore the effects of isotopes, Ga¹⁴N_0.46¹⁵N_0.54 QW and Ga¹⁴N QW with the same thickness of 28 nm were grown and measured. From the Raman measurements, frequency shifts and width broadening are clearly observed for E₂^H and A₁ phonons in 28 nm Ga¹⁴N_0.46¹⁵N_0.54 QW. The effects of Nitrogen isotopes could be explained from a simple harmonic oscillator model, and the broadening is an accurate measure of the isotopic alloy disorder. The strain distribution in GaN-channel field effect transistors (FET) was also explored by Raman spectroscopy. The multiple marker techniques demonstrated here for the first time can be applied in several other III-V heterostructures, particularly vertical devices for power electronics, and optoelectronic devices such as LEDs and LASERs, where the active regions are buried far away from the surface.

Bulk crystals of AlN and SiC have been grown mainly by high-temperature (>2000 0C) sublimation technique. The Al and Si vapors in the sublimed gas are highly reactive and gradually corrode most of conventional crucible materials during the growth process. These corrosive effects deteriorate quality of bulk crystals and epitaxial films, and raise material and process costs. Among the potential corrosion-resistant materials for the bulk and epitaxial growth, TaC is the most promising material because of its excellent chemical stability. The material and machining cost of TaC bulk materials, however, is very high because the Ta is an expensive rare metal and the metal carbide is a typical brittle material. To reduce both the material and forming costs of TaC components, a TaC-coated graphite substrate can be a suitable option. Here we demonstrate the fabrication of very thick TaC protective coatings on graphite crucibles (with the film thickness about 100 um) using a novel low-cost process, that is, wet ceramic process. The newly-developed TaC-coated crucibles were applied to the AlN sublimation growth process, and have proved its reliability and durability under the harsh growth conditions.
The TaC coatings were formed on graphite crucibles for AlN powder source containers and top lids. The TaC slurry, which is consists of TaC powder, solvent mixture, organic binder, and sintering agent, was applied on the crucible with a paintbrush or spray gun. The TaC powder compact films on the graphite crucibles were sintered in a reduced-pressure Ar atmosphere at a temperature over 2000 °C. The thickness of resultant sintered TaC films was controlled to be in the range of 50 to 150 um. The as-formed TaC films showed metallic-luster surfaces with the color of yellow gold, and no crack or pinhole was observed through visual inspection.
To verify the reliability of the TaC-coated graphite crucibles under the AlN sublimation growth conditions, the crucibles filled with AlN source powder were heated up to 2000-2350 0C for 20-100 hours in N2 atmosphere. The optimized TaC-coated crucibles as AlN source containers after the test run (e.g. seedless growth) showed no visible damage (such as peeling off of the TaC film and/or substrate corrosion through pinhole) on the TaC film and graphite substrates. Then, the bulk AlN single crystal growth was performed with the crucible setup and growth conditions almost same as the test run except presence of a seed crystal. The resultant AlN single crystal with the thickness about 7 mm was separately grown on the specially-designed top lid from surrounding polycrystals. This indicates that the high degree of freedom for the shape forming, which is an inherent strength of the coated crucible, is also crucial factor to reproducibly obtain AlN single crystals. Thus, it is concluded that the newly-developed TaC-coated graphite material is the best candidate for the production of AlN bulk crystals.

This study revealed for the first time the lattice distortion of low-temperature-grown (LTG) In_0.45Ga_0.55As on an InP substrate. X-ray reciprocal space mapping (RSM) of LTG In_0.45Ga_0.55As grown at 220 °C showed that the LTG-In_0.45Ga_0.55As layer was compressively strained, although its lattice constant parallel to the substrate surface was smaller than that of the InP substrate. Moreover, there was no distinct transformation of this lattice distortion after annealing the sample to 550 °C.
LTG-GaAs-based compound semiconductors have attracted much attention because they can realize photoconductive antennas (PCAs) activated by femtosecond fiber lasers with wavelengths of 1.5 mu;m for terahertz (THz) wave emission and detection. Because fiber lasers are less expensive and more compact than conventional optical sources, THz time-domain spectroscopy systems with these PCAs will become more practical. In order to achieve efficient THz-wave emission and detection by using PCAs with LTG-GaAs-based semiconductors, it is essential to obtain materials that have high carrier mobility, an ultrashort carrier lifetime, and high resistivity. However, it is difficult to obtain these characteristics, especially high resistivity, in narrow-bandgap semiconductors. In this study, we investigated the crystal structure and lattice distortion of the LTG In_xGa_1-xAs on an InP substrate by comparing the results of X-ray RSM and Rutherford backscattering spectrometry (RBS) as the first step in obtaining the characteristics mentioned previously in achieving efficient PCAs with LTG-GaAs-based semiconductors for THz-wave emission and detection.
LTG In_0.45Ga_0.55As, with a thickness of 2.0 mu;m, was grown on an (100) InP substrate by molecular beam epitaxy at a temperature in the range of 200 °C-240 °C. After the growth of the LTG In_0.45Ga_0.55As, we annealed the samples at 400 °C and 550 °C for 1h in an H₂ atmosphere. We investigated the crystal structure of the LTG In_0.45Ga_0.55As by high-resolution X-ray diffraction (XRD) on a Bruker AXS D8 Discover Diffractometer.
The (400) reflection XRD peaks were observed for the LTG-In_0.45Ga_0.55As samples grown at 220 °C and 240 °C. The sample grown at 200 °C did not show an XRD peak, suggesting that crystalline quality deteriorates drastically at a growth temperature between 200 and 220 °C. X-ray RSM around the asymmetric (115) reflection of the LTG-In_0.45Ga_0.55As sample grown at 220 °C showed that the LTG-In_0.45Ga_0.55As layer was compressively strained, although its lattice constant parallel to the surface of the substrate was smaller than that of the InP substrate. This lattice distortion did not change after annealing the samples to 550 °C. Because the RBS angular scans in our previous study suggested that both of the same as-grown and annealed LTG-In_0.45Ga_0.55As layers include 40% interstitial In atoms in their crystals, the result of this study suggests the possibility that periodic defect structures are present in the LTG In_0.45Ga_0.55As.

A heterojunction phototransistor (HPT) is very attractive compared with photodiodes because of its good compatibility with a heterojunction bipolar transistor (HBT), high photoresponse even at low bias voltage and immunity from avalanche noise [1]. Since InGaP has an advantage over AlGaAs in the material properties and fabrication process, the InGaP emitter has been actively employed to replace the AlGaAs in the AlGaAs/GaAs HPT. Although there have been many reports on the study of electrically-stressed InGaP/GaAs HBTs [2], there is a little or none on the electrically-stressed InGaP/GaAs HPTs. In this paper, we report the effects of electrical stress on the characteristics of InGaP/GaAs HPTs in detail. We gave an electrical stress, which was much smaller than that usually given to the HBTs, at room temperature and an elevated temperature to the InGaP/GaAs HPTs with and without the emitter-ledge passivation, which has demonstrated the improved performance of HBTs.
The HPT epilayers were grown on S.I. GaAs (100) substrate by metal-organic chemical vapor deposition (MOCVD). Although the structure and design are similar to the HBTs, the emitter area is 160,800 mu;m², much larger than those of typical HBTs in order to increase the collector photocurrent. The electrical stress was given to the phototransistors by keeping a collector current of 60 mA (corresponding to a current density of 37 A/cm²) for 1 hour at room temperature. The electrical stress was found to be too small to affect the common-emitter current gain and photocurrent of both HPTs without and with the InGaP emitter-ledge passivation at room temperature. However, both current gain and photoresponse at 420 K decreased significantly in the electrically-stressed HPTs, but those of the HPT with the emitter-ledge passivation were still higher than those of the HPT without the emitter-ledge passivation. The effect of the electrical stress was more significant if it was given at 420 K even for the period reduced to 15 min. There was a significant decrease in the current gain and photoresponse even at room temperature in the HPT without the emitter-ledge passivation, while a little decrease was observed in the HPT with the emitter-ledge passivation. The effect of the electrical stress on the photoresponse was also much more significant than that on the current gain, and the emitter-ledge passivation was more effective in suppressing the degradation of the HPTs.
Furthermore, for a potential application of the InGaP/GaAs HPTs in space, we will irradiate the HPTs with high-energy electrons at the Japan Atomic Energy Agency and characterize their degradation as a function of the energy and fluence.
References
[1] S. Chandrasekhar et al., IEEE Photon. Technol. Lett 5, 1316 (1993).
[2] W. Liu et al., IEEE Electron Device Lett 14, 301 (1993).

Amorphous Se (a-Se) based photosensors have a high photoconversion efficiency because of the avalanche multiplication in a-Se at a relatively low electric field. However, the photosensors suffer from thermal and electrical instabilities as a result of the low glass transition temperature (T_g) of a-Se. To mitigate the instabilities, a-Se is generally alloyed with a small amount of arsenic to increase T_g. In this study, we use multilayered a-Se/As_xSe_1-x thin films instead of single-layered As-doped a-Se thin films to fabricate a-Se based photosensors. Multilayer thin films of 1 mu;m in thickness were prepared by alternating thermal evaporation deposition of a-Se and As₂Se₃ on a ZnO/ITO support, of which the ZnO layer is used as the hole blocking layer. The atomic concentration of As in the amorphous As_xSe_1-x layer and the thickness of each layer of a-Se and As_xSe_1-x depend on the evaporation temperature and the rotation speed of the sample holder, which was at room temperature. The thermal stability of the multilayer thin film was studied by aging the film at 60^oC for various periods of time followed by x-ray diffractometry and Raman spectroscopy analyses. The multilayer structure has a much better thermal stability than the single a-Se layer; this may be ascribed to As incorporation in the a-Se layer during the As₂Se₃ evaporation process, leading to the increase in T_g of the a-Se layer. A higher evaporation temperature of As₂Se₃ and a thinner a-Se layer result in a better thermal stability of the multilayer thin film. Because of the high thermal stability, the a-Se/As_xSe_1-x photosensor withstands a higher breakdown field (>40 V/mu;m) than the a-Se photosensor (~20 V/mu;m). Moreover, the multilayer photosensor has a photosensitivity comparable to the single-layered a-Se structure under the blue light exposure while it greatly lowers the dark current density by two orders of magnitude. The dark current suppression can be ascribed to the hole barrier developed at the p-p isotype heterojunction between the a-Se and As_xSe_1-x layers. Although the multiple As_xSe_1-x interfaces may slightly impair the photoconductivity of the photosensor due to photogenerated carrier recombination, the high breakdown field and the low dark current density allow the As_xSe_1-x multilayer structure for the use as a sensitive photosensor with a high contrast.

Germanium-tin (Ge_1-xSn_x) alloys have recently garnered much attention towards the development of a silicon-compatible Group IV light source for optical interconnects and other integrated applications. Although Ge has an indirect band gap, it is predicted that the addition of 6-8% of Sn can transform Ge into a direct band gap material. However, the epitaxial growth of Ge_1-xSn_x is a challenge due to the significant accumulation of strain from the 14.7% lattice mismatch between α-Sn and Ge. In the case of Ge_1-xSn_x grown on Si or Ge-buffered Si, a buildup of compressive strain energy limits the ultimate coherent film thickness. When this critical thickness is exceeded, strain relaxation of the lattice occurs via the creation of dislocations, which can have detrimental effects on the performance of Ge_1-xSn_x photonic devices. Determining the critical thickness for Ge_1-xSn_x materials and developing methods of exceeding the critical thickness are important for developing practical, high-performance devices.
We theoretically and experimentally investigate the critical thickness of Ge_0.92Sn_0.08 grown by Reduced-Pressure Chemical Vapor Deposition (RPCVD). Using X-Ray Diffraction (XRD) Reciprocal Space Mapping (RSM), we show that 30 nm of Ge_0.92Sn_0.08 remains fully commensurate while 60 nm and 100 nm exceed the critical thickness, resulting in partial relaxation. Furthermore, we demonstrate that a Ge_0.92Sn_0.08/Ge multiple quantum well design can minimize the relaxable strain energy of the system and be leveraged to overcome this critical thickness constraint. This approach makes it possible to grow more pseudomorphic layers that in total exceed the single layer critical thickness. Reciprocal space mapping indicates that our multiple quantum well design remains over 99% strained with reduced defect density when compared to the equivalent single layer thickness. This enables the potential of achieving thicker, unrelaxed Ge_1-xSn_x films with improved material quality for integration into Ge_1-xSn_x-based devices.

The 2-dimensional electron gas (2DEG) in passivated AlGaN/GaN structures is known to be caused by donor-type interface defects. Experimental and theoretical studies show an influence of oxygen-involving surface structures on the 2DEG [1, 2]. Additionally, interfacial oxygen is suggested to correlate with dynamic device drifts [3], though the exact role of oxygen is still not completely clear. In order to correlate electrical interface characterisation with the existing interface oxygen species, we will present a sample preparation method for XPS analysis to investigate the interface as apparent surface, through a thin uniform dielectric layer. This approach offers the advantage of both, the possibility of chemical interface analysis and the comparison to electrical measurements of the exactly same interface.
We use LPCVD deposited Si₃N₄ and compare high- to low-oxygen AlGaN surfaces in order to examine changes in the species and the device behaviour. The removal of surface oxygen applying ammonia-based treatments is known to reduce the amounts of oxygen [4], though it has not been shown yet, if an oxygen-free interface can be achieved for deposited Si₃N₄ layers.
For sufficient information depth during XPS analysis, the ideal Si₃N₄ thickness is found to be 1.6 +/- 0.2 nm. The Al2p peak serves as a measure; though its electrons possess a greater inelastic mean free path, its concentration is only one quarter of the Ga-at%. The elemental investigations are based on Ga3d photoelectrons, due to their higher kinetic energy over the Ga2p ones. Comparison to AES and TEM-EELS data allows the conclusion that the top 1 nm of the layer is re-oxidised (SiO₂). To exclude diffusion of oxygen to the interface, thicker passivation layers are additionally investigated by TEM-EELS, XPS and AES. Gradually removing layer-by-layer, either by selective etching of SiO₂ over Si₃N₄ with aq. HF solutions or by 1 keV Ar sputtering at 67.5° during XPS measurements, shows a shift of the O1s peak to lower energies from 532.3 eV > 531.7 eV > 530.8 eV, as the standard bond enthalpies decrease from O-Si > O-Al > O-Ga. We find no indication that interfacial oxygen is bonded to any other element than the group-III metal. In agreement with the HSAB principle > 60% of the interfacial oxygen is bonded to Al rather than to Ga. However, an oxygen free surface could not be obtained, as additionally confirmed by ToF-SIMS data. The low-oxygen sample still shows about 6 at% of oxygen at the interface.
The interfacial differences after surface treatments and analysis by XPS through thin films suggests that the polarisation charge present in the material inhibits the removal of oxygen, thus we believe that the metal-oxygen bond plays an important role for polarisation charge-compensation at the interface. [1] M.S. Miao et al., JAP 107, 123713 (2010). [2] B. Bakeroot et al., APL 116, 134506 (2014). [3] M. Fagerlind et al., JAP 108, 014508 (2010). [4] K. Tracy et al., JAP 94, 3163 (2003).

NAND flash memory technology has been scaled down continuously for more productivity, but at the same time reliability properties have become worse due to increase in trap generation in tunnel oxide and inter-poly dielectrics as well as cell-to-cell interference and disturbance. For the reliability enhancement, n-type poly Si floating gate (FG) has been replaced with p-type poly-Si. By adopting p-type poly-Si FG, the virgin threshold voltage increases and charge loss of programed cells in NAND flash memory devices decreases. Because p-type poly-Si FG may increase charge gain of erased cells, however, cautious approach is needed. Also, diffusion of boron atoms in the p-type poly-Si FG into tunnel oxide (Tox) makes Tox quality worse, leading to degradation of reliability properties. To simultaneously reduce the virgin Vth of cells and boron diffusion into Tox, a thin layer of un-doped poly-Si is inserted at the bottom of p-type poly-Si FG. We profile boron concentration using secondary ion mass spectroscopy(SIMS) and achieve the decreased boron concentration in Tox. To evaluate the improvement on reliability properties, electrical characteristics such as time dependent dielectric breakdown(TDDB), stress-induced leakage current(SILC), random telegraph noise(RTN), endurance and data retention have also been measured. The results indicate that inserting un-doped poly-Si produces lower trap density in Tox and better reliability as compared to the conventional process.

As the device shrinks to sub-20nm technology nodes, small particles (< 26nm) and metal contamination (2) which is hard to detect by current analytical techniques may cause unwanted costly wafer scraps and yield loss. Undetectable metal contamination (08 atoms/cm²) on the wafer surface can cause unacceptable surface roughness and pitting on an EPI wafer. This pitting defect is only detected at post pad oxide deposition inspection.
One micron deep and ~20A wide pits are observed as randomly distributed over the silicon wafers after pre-cleaning and Pad Oxide deposition inspection. The root cause of these pitting defects is determined to be the incoming metallic contamination.
Previous studies [1] have shown that a spontaneous chain reaction is initiated when a heavy metallic contamination such as Cu and Fe come in contact with silicon in presence of oxidizing agents (H₂O₂, O₂ dissolved water, O₃). Prior to the chain reaction, metallic contaminants and silicon are with zero charges. The metallic contaminants act as catalyst and react with oxidizing agent. This oxidation reaction oxidizes both metal and silicon from zero to “+1” oxidation state. This oxidation reaction occurs until silicon is fully oxidized to its +4 oxidation state and dissolves in solution. Remaining heavy metal, although very low in concentration, continues to catalyze this chain reaction and creates the local pitting defects until the heavy metals&’ concentration falls below critical level. Effects of various chemistry time and sequence for surface cleaning prior to Pad Oxide Deposition have been evaluated. This paper will provide a possible solution to eliminate the source of the defects by altering the chemical sequence in the existing recipe.
[1] Sheng-Hsiung Chen; Shen-Li Chen; Long-Yeu Chung; Wen-Kuan Yeh. Tiny Pitts are the Yield Major Killer Caused by Metal Contamination in Wet Bench Cleaning. Proceedings of the 13th International Symposium on the Physical & Failure Analysis of Integrated Circuits, pp 129-132, 2006 (DOI: 10.1109/IPFA.2006.251013).

We have successfully fabricated metal-ferroelectric-insulator-silicon (MFIS)-type memory thin-film transistors (TFTs) with a large single-grained Pb(Zr,Ti)O₃ (PZT) on glass substrate. The single-grain of (PZT) was obtained by separating the temperature of nucleation and growth. An artificially controlled nucleation seeds were formed in a 40 mu;m row and the location of polycrystalline-silicon (poly-Si) channel were 10 mu;m offset from the nucleation seeds. The growth of the PZT seeds was carried out by post-annealing until the single-grained covers the poly-Si channel. The device exhibits a good performance in terms of large memory window (3.5 V), ultra-fast programming and erasing (P/E) switching, long data retention, and an excellent P/E fatigue cycles. Comparing with the poly-grained MFIS-type memory (TFTs), the single-grained MFIS-type TFTs showed a high reliability performance due to its non-grain boundary effect. As a result, achieving a single-grained PZT is a important factor for high performance of ferroelectric memory transistors and useful for the display applications.

An important trend in organic electronics is currently mechanical flexibility. The ultimate goal is to develop electronic systems that cannot only be flexed into a bending radius of a few millimeters but can also be tightly rolled, bent around sharp edges or repeatedly creased without degradation of their electronic functionality. With no additional mechanical stress-release layers, the most flexible organic field-effect transistors based on a polycrystalline organic semiconducting layer could be bent without any degradation of their electrical performance to a radius as low as 260 µm. Although degradation of these devices based on bis-(triisopropylsilylethynyl) pentacene or bis-triethylsilylethynyl anthradithiophene thin films, was observed below a critical bending radius of about 200 µm, these results provided evidence that crystalline solution-processable organic semiconducting materials could be intrinsically more flexible than initially thought.
High performance non-volatile memory that can operate under various mechanical deformations such as bending, folding and stretching is another kind of electronic devices required for the next generation of smart wearable and foldable electronic applications. Up to now, only a few organic non-volatile memories with mechanical flexibility have been demonstrated with sufficiently reliable data retention and endurance. In fact, most of the previous non-volatile memories are categorized as bendable devices with their bending radii much greater than 1 mm. Memories with further severe bending have rarely been demonstrated. Furthermore, no memory device has been properly operated with extreme mechanical deformation, i.e. folding that resulted in permanent, plastic deformation of a device with an infinite radius of curvature at the folded line.
Here, we have successfully demonstrated an extremely flexible, high performance air-stable non-volatile ferroelectric field-effect transistor (Fe-FET) memory with p- and n-type dual mode operation. In both non-destructive carrier type modes, the device with solution-processed multiple polycrystalline layers exhibited excellent data retention and endurance of more than 6000 s and 100 cycles, respectively. Our Fe-FETs were found to be highly robust towards severe mechanical stimuli such as bending and sharp folding, even without the use of an additional device protection treatment. As mentioned above, no significant performance degradation was observed at repetitive extreme bending events with the bending radii as low as 500 µm or even after 1000 sharp folding cycles involving inelastic deformation of the device. Mechanical characterization using nanoindentation and delamination tests revealed that the stable performance at large strains may be attributed to the unique material properties of QQT(CN)4 and strong adhesion between the polycrystalline PVDF-TrFE and QQT(CN)4 layers.

Recently, flexible and stretchable display is being considered as a next generation display and its various emerging applications are growing very rapidly ranging from wearable display, to biomedicine and robotics industries. Pioneering studies on flexible and stretchable displays based on organic materials have tried to exploit the advantages of their excellent intrinsic mechanical properties. However, critical weaknesses of organic materials are it shows poor electrical properties and reliability. Also the requirement of special encapsulation layers is the key challenge to overcome vulnerability from environment like moisture and oxygen.
Here, we demonstrate all inorganic-based active-matrix light emitting diodes (LEDs) display consist of single-crystal Si thin film transistors (TFTs) and AlInGaP LEDs which shows outstanding electrical property and good reliability. Back-plane TFT which was transfer printed from mother silicon on insulator (SOI) wafer on plastic/rubber substrates shows mobility of 950 cm²/V.s and on/off current ratios exceeding 10⁶.Transfer printed ultrathin and highly efficient AlInGaP LED arrays were well integrated with back-plane TFTs and the active matrix LED structures were formed. During the dynamic operation, the displays were rapidly driven by high speed TFT arrays and shows fast response time with low cross-talk level which is necessary to realize high resolution display system. Moreover, our active-matrix LED arrays showed robust operation in bending states and even high stretching level by use of serpentine structures. We also confirmed that, this structure enabled systematical change in the separation between the unit pixels throughout the test.
In conclusion, the all inorganic based active matrix display embedding on flexible and stretchable substrates have been presented. Furthermore, we show that the proposed display structure is favorable not only for its high flexibility, but also for a high stretchability that is potentially applicable to large sizes.

Recent intensive research into the development of high mobility polymer semiconductors has achieved field effect mobilities higher than 10 cm²/Vs, when fabricated as a polymer thin film transistor. However, most of this work has been aimed at achieving a high mobility/reliability in polymer semiconductors, with very few reports regarding the use of non-chlorinated solvents in the processing of polymer semiconductors. From an industrial point of view, the chlorinated solvent that is currently the most widely used in the processing of polymer semiconductors should be excluded owing to its high environmental cost. Here, we show that controlling the random copolymerization between two different diketopyrrolopyrole-based conducting units by varying the relative quantity of each represents a suitable synthetic strategy to increase the solubility of polymer semiconductors in a non-chlorinated solvent, without compromising high charge carrier mobility. Highly performing and reliable polymer thin film transistors processed from environmentally benign solvents such as tetralin are demonstrated for the first time, resulting in a mobility of greater than 5 cm²/Vs.

SiC wafers have recently started being applied in power devices. There are also several applications that take advantage of the material properties of SiC such as its excellent thermal conductivity. For example, practical high frequency GaN devices and GaN LEDs on SiC wafers have been achieved. In addition, we have prepared an experimental prototype of a Si-on-SiC substrate by directly bonding a thin Si layer and a SiC substrate. Efficient reduction of the self-heating effect was demonstrated in Si devices fabricated on this Si-on-SiC substrate. In order to expand the application of single crystalline SiC, however, reduction of the cost of SiC substrates is an important issue. Moreover, in some SiC applications, microscopic crystalline defects such as dislocations and stacking faults are not a significant problem. In contrast, reduction of these defects is critical for the application of 4H-SiC in power devices.
In this study, a faster crystal growth rate for SiC that enables the reduction of SiC wafer production costs is demonstrated. The correlation between the growth rate (R_g) of crystalline SiC crystal and the presence of macroscopic defects, such as macro-pipes, hexagonal plate defects, inclusions, and sub-grain boundaries, is also discussed.
High growth of SiC substrates was achieved using the sublimation method. SiC powder as a raw material was loaded into a graphite crucible and then sublimed and deposited on an SiC substrate located on the inner upper surface of the crucible as a seed crystal. The selected seed crystal was 6H-SiC, because 6H-SiC can be grown at a temperature higher than the growth temperature of 4H-SiC. The high growth temperature is suitable for high-speed growth.
In general, the R_g of the sublimation method is reported to be 0.2-0.4 mm/h. In the present study, R_g was controlled in the range 0.2-1.4 mm/h by changing the growth parameters, including the growth temperature and pressure, the temperature difference, and the distance between the seed crystal and the raw material. When R_g > 0.4 mm/h, an increase in the macroscopic defects in the 6H-SiC is observed. These macroscopic defects cause undulations in the 6H-SiC substrate surface, which is a problem even for applications other than SiC power devices.
Based on a detailed comparison of the growth conditions and macroscopic defects, it was revealed that these defects were not generated during growth; furthermore, most of these defects were generated on the seed crystal surface. The growth conditions required for a fast growth rate resulted in damage to the surface of the seed crystal, and the damaged surface then caused the formation of the problematic macroscopic defects. By controlling the initial stage of crystal growth, however, a reduction of the macroscopic defects in the 6H-SiC with R_g of 0.9 mm/h is achieved. Consequently, it was possible to realize 6H-SiC growth with a growth rate above 1 mm/h without the formation of macroscopic defects.

Diamond has an attractive interest as one of next-generation power electronics materials. Recently, development of thermally-stable, high-current diamond field effect transistors (FETs) with Al2O3 gate and passivation dielectrics deposited by an atomic layer deposition (ALD) technique were reported to be as large as 1 A/mm by Waseda Univ. and NTT groups. In addition, since the sheet hole density in the hydrogenated-diamond surface was reported to be as high as 1E14 cm-2 which was one or two orders larger than other semiconductors. Therefore, we should use such the big advantage and then have to develop the high-k gate dielectric for diamond in order to control the high-density hole carrier. Since the high-k dielectric provides the large capacitance at a given gate voltage, the controllable carrier density is predicted to be increased with increasing the dielectric constant. For this purpose, as a first step to search the best high-k insulator material to the diamond, we have demonstrated the diamond FETs with high-k HfO2/HfO2, LaAlO3/Al2O3 Ta2O5/Al2O3, and ZrO2/Al2O3 stack gates prepared by a combination of sputter-deposition (SD) and ALD techniques. Since the FET property is sensitive to the interfacial states between the diamond and dielectric and the border traps in the dielectrics, it is essential to obtain the guideline for developing the excellent gate dielectric for diamond.
In this paper, we will show why the high-k dielectric insulator is required for diamond and demonstrate the LaAlO3, HfO2, Ta2O5, and ZrO2 as the gate insulator of the FETs using the hydrogenated diamond (H-diamond) p-type channel. In addition, to understand the interface property between the diamond and dielectric, we will investigate the electric properties of interface between the H-diamond and insulator.

Due to its excellent properties, diamond is one of the best candidates for electronic applications [1]. Nevertheless, up to now, only monocrystalline material exhibits sufficient properties even if defects such as dislocations still hamper its development. Synthesis of single crystalline diamond layer is limited in size because there is no available substrate with dimensions higher then typically 3x3 mm² at reasonable cost. Heteroepitaxial diamond grown on iridium substrates by CVD technique is a promising material for the next generation of electronic and radiation detection devices [2, 3]. The up-scaling possibilities of the growth process are particularly interesting for producing larger diamond surfaces, compatible with microelectronic technologies. However, the performances of devices are limited by the residual mosaicity and the presence of high density of dislocations in the range of 10⁷-10⁹ cm^-2 and one key point for improving this technology is to have a better understanding and control of the first growth steps[4-7].
In this work, High Resolution Transmission Electron Microscopy (HRTEM) analysis of the interface between heteroepitaxial diamond on monocrystalline iridium buffer layer will be presented. The sample underwent a Bias Enhanced Nucleation step followed by a short CVD growth step. Dual beam Focus Ion Beam (FIB) has been used for preparation of HRTEM lamella. The studied interface results from Bias Enhanced Nucleation and CVD growth steps.: between monocrystalline iridium films and Bias-enhanced nucleation of diamond and between BEN diamond and CVD diamond layer. These lamella have been observed using a TEM JEM-ARM200F, with an atomic resolution and defects such as stacking faults, micro twins and dislocations have been observed. Ultra high resolution images allowed identifying highly oriented diamond grains related to BEN step and diamond grown during CVD step.
References
[1] Bucciolini, et al., 8.15 - Diamond Detectors for Dosimetry, in Comprehensive Biomedical Physics, A. Brahme, Editor 2014, Elsevier: Oxford. p. 229-248.
[2] Schreck, M., et al., MRS Bulletin, 2014. 39(06): p. 504-510.
[3] Stolz, A., et al., DRM, 2006. 15(4-8): p. 807-810.
[4] Bauer, T., et al.,DRM, 2004. 13(2): p. 335-341.
[5] Chavanne, A., et al.,DRM, 2012. 22(0): p. 52-58.
[6] Hessmer, R., et al.,DRM, 1994. 3(4-6): p. 951-956.
[7] Vaissiere, N., et al.,DRM, 2013. 36(0): p. 16-25.

Boron nitride (BN) is a missing piece of group-III nitride semiconductors. BN possesses sp²-bonding as well as sp³-bonding phases. Cubic BN (c-BN), one of the sp³-bonding phases, has a large bandgap energy of 6.25 eV and a high breakdown field of 8 MV/cm, which may further expand the possibilities of nitride-based semiconductor devices. c-BN is a thermodynamically metastable phase, which can be stabilized only by high-pressure synthesis. Recently, we have successfully grown single-crystal c-BN films on diamond substrates by means of ion-beam-assisted MBE [1]. Here, we show influence of the diamond surface on the BN phase formation and the growth temperature on the in-plane epitaxial relationship between c-BN and diamond.
The c-BN films were grown on single-crystal diamond (111) substrates by electron-beam evaporation of B in a flux of N₂⁺ and Ar⁺ ions. In-situ thermal cleaning of the diamond surface was carried out at T_c prior to the BN growth at T_g.
First, influence of the thermal cleaning temperature was investigated. We grew two c-BN films at the same T_g of 620 °C after the diamond surface cleaning at different T_c (620 °C for sample A and 910 °C for sample B). RHEED images indicated that the diamond surface cleaned at T_c = 620 °C is an oxygen-terminated one (1×1) whereas that cleaned at T_c = 910 °C is a reconstructed diamond surface (2×1). In the FT-IR spectra of the BN films, only an absorption peak originating from sp³-bonding was observed for sample B while weak absorption peaks originating from sp²-bonding were also discernible for sample A. TEM observation of sample A revealed that the sp²-bonded BN phase is formed at part of the c-BN/diamond interface, which may have a harmful effect on sp³-bond formation. Note that, in both samples A and B grown at T_g = 620 °C, the c-BN (111) films are composed of two rotated domains whose in-plane epitaxial relationships are diamond[-12-1]//c-BN[-12-1] or diamond[-12-1]//c-BN[1-21].
Next, we focus on influence of the growth temperature. We prepared the third c-BN film at high T_g of 910 °C. The diamond surface was cleaned at T_c of 910 °C (sample C). In the FT-IR spectrum, only a strong absorption peak originating from sp³-bonding was observed. Moreover, the FWHM of the peak decreased with increasing T_g, indicating an improved crystal quality of the c-BN film. We confirmed the formation of single domain c-BN (111) film by RHEED and TEM, where the in-plane epitaxial relationship is diamond[-12-1]//c-BN[-12-1]. Growth at a higher temperature (T_g = 910 °C) is preferential for the formation of single-domain c-BN films.
In summary, surface of the diamond substrate and growth temperature are key parameters in the growth of phase-pure and high crystallinity c-BN (111) films.
[1] K. Hirama, Y. Taniyasu, S. Karimoto, Y. Krockenberger, and H. Yamamoto, Appl. Phys. Lett. 104 092113 (2014).

Gallium oxide (Ga₂O₃) semiconductors are gaining interests as being applied to power electronic devices and ultraviolet optical devices. There are two major crystal structures for Ga₂O₃, that is #65370;corundum-structured a-Ga₂O₃ and orthorhombic b-Ga₂O₃. The latter is the thermodynamically stable phase and the successful highly crystalline b-Ga₂O₃ substrates has been the motive force for their device applications. On the other hand, the former can lead formation of a-(Al,Ga,In)₂O₃ alloy semiconductors with the entire compositional range for band gap engineering, and in addition they can be alloyed with transition-metal oxides such as Fe₂O₃, Cr₂O₃, and V₂O₃ for function engineering. However, the metastable phase of a-Ga₂O₃ can cause thermal instability and electrical defects leading to degraded device properties. In this presentation, we report the stability and defect issues of a-Ga₂O₃-based semiconductors for their future bloom.
We used the mist CVD technology for the crystal growth on c-plane sapphire substrates. One of the serious problems for a-Ga₂O₃ is the thermal stability, that is, it turns to subject inclusion of the b-phase at high temperature. The slight doping of Al, however, was effective to stabilize the samples so that it was stable until the growth and the successive annealing temperatures to 650 and 750^oC, which were marked high compared to the regular undoped films, that is, 500 and 650^oC, respectively. The phenomena was similar to solution hardening of GaAs due to slight addition of In.
Electrical defects have been the serious problem for device applications. Misfit dislocations at the interface to sapphire were the fatal problem for the electrical properties, and the elimination of them clearly contributed to enhance the mobility. Further, it was found that doped donor impurities and oxygen vacancies were not simply the donor centers but their complex, as well as hydrogen impurities acted as donor centers.
In oxide semiconductors, the role of defects seems to be characteristic to these materials, and the understanding of their physics is important for their development to devices.

Ga₂O₃ is appealing for the next-generation high-voltage power devices due to its wide-bandgap of 4.8 eV and the availability of low-cost melt-grown native substrates. The rising interests in semi-insulating Fe-doped Ga₂O₃ substrates for low-leakage Ga₂O₃ field-effect transistors (FETs) call for systematic studies into the thermal behavior of Fe as a compensating acceptor in Ga₂O₃. Of particular importance is the effect of ion damage on Fe redistribution as Si ion (Si⁺) implantation is a key technique for doping the source/drain and channel of Ga₂O₃ FETs [1]. In this work, we demonstrate for the first time that Fe diffusion in Si⁺-implanted Ga₂O₃ is enhanced as a result of an athermal mechanism mediated by implant-generated defects, the adverse effects of which can be overcome by inserting a highly-resistive Ga₂O₃ buffer layer between the implanted layer and the Fe-doped substrate.
Homoepitaxial unintentionally-doped (UID) Ga₂O₃ deposited on edge-defined film-fed grown Fe-doped β-Ga₂O₃(010) substrates by molecular beam epitaxy were used to examine the extent of Fe redistribution as a result of growth at 560 °C, high temperature annealing of the as-grown epilayer, and high temperature annealing after the epilayer was uniformly implanted with Si⁺ at 3×10¹⁷ cm^-3. The annealing was performed at 950 °C for 30 min in N₂, which were typical conditions for efficient Si⁺ implant activation in Ga₂O₃ [2]. Secondary ion mass spectroscopy revealed that Fe was thermally stable in the UID Ga₂O₃ but redistributed significantly in the implanted material beyond the extent of intrinsic thermal diffusion. This anomalous phenomenon, which shared common features with transient enhanced diffusion of implanted dopants in Si, was attributed to Fe interacting and forming mobile complexes with defects injected by implant damage. Si⁺ penetrating into the substrate due to implant straggle could have caused unintentional lattice damage beyond the designated implantation depth. It was also possible that the responsible defect species traversed large distances from the implanted region to the substrate.
The Fe outdiffusion was effectively suppressed by isolating the substrate from the implanted layer with an undoped Ga₂O₃ buffer layer thicker than 0.7 mu;m that protected the substrate from unintentional ion damage and prevented remote diffusivity-enhancing defect species from reaching the substrate. Temperature-dependent current-voltage measurements indicated that the undoped Ga₂O₃ buffer was highly resistive with inter-device leakage consistent with 2D variable-range-hopping conduction presumably along the surface. The buffer scheme, together with proper surface passivation, will constitute an integral process module for Ga₂O₃ FETs and can be adopted for planar inter-device isolation to improve process yield and uniformity.
[1] M. Higashiwaki et al., Tech. Dig. - IEEE Int. Electron Devices Meeting, p. 707 (2013).
[2] K. Sasaki et al., Appl. Phys. Express 6, 086502 (2013).

Low dielectric constant thin films represent a special subclass of porous materials where the electrical and mechanical properties are tuned by controlling porosity. [1] The accurate determination of mechanical properties is a critical requirement in understanding structure-property relationships and enabling their implementation into technologically relevant devices. As of today, nanoindentation is the technique of choice but it is widely accepted that materials densification and substrate effects are two inevitable drawbacks of this method when applied to low dielectric constant thin-films. The substrates&’ true influence onto the measurement has remained a key unanswered question for the last 25 years. As a result, to minimize the substrate contribution, it has been empirically established that no more than the top 10% of the film should be probed, preventing the direct determination of porous thin film mechanical properties at dimensions used in real technological applications. In this presentation, we prove that this generally accepted belief is wrong and comes from the inability of scientists to decouple the substrate contribution from sample densification occurring during nanoindentation. We demonstrate using low-k porous organosilicates [2] and porous metal organic frameworks [3] that densification follows known mathematical scaling and can be separated from the substrate effect.
[1] W. Volksen, R. D. Miller, G. Dubois, Chem. Rev. 2010, 110, 56-110.
[2] W. Volksen, K. Lionti, T. Magbitang, G. Dubois, Scripta Mater. 2014, 74, 19-24.
[3] D. F. Bahr, J. A. Reid, W. M. Mook, C. A. Bauer, R. Stumpf, A. J. Skulan, N. R. Moody, B. A. Simmons, M. M. Shindel, and M. D. Allendorf, Physical Rev. B., 2007, 76, 184106-13

Zinc oxide (ZnO) is an excellent optical material which has a wide band gap (~ Eg= 3.37 eV) and a large exciton binding energy (=60 meV). This large binding energy makes it interesting for realization of laser diode and light emitting diodes at room temperature. Novelties in microwave assisted growth method are; it produces rapidly in a minutes, high device quality material and conformal growth on the substrates. We have synthesized single crystal ZnO nanostructures (nanorods, nanoflower and millimeter long single crystal fibres) by novel microwave-assisted growth method in aqueous and non-aqueous medium in a few minutes. Micron size (2-6 µm long and 80-150 nm diameter) ZnO nanostructures are synthesised by using zinc salt (acetate or acetylacetonate) however water, ethanol, ethylene glycol are used as solvents in appropriate molar proportions to produce tuneable optoelectronic materials. Millimeter long single crystalline ZnO fibres are synthesized in non-aqueous medium ethanol and ethylene glycol in appropriate proportion (3:5) using zinc acetylacetonate salt (mM). Long single crystals are characterised by fluorescence microscope, excited with ultraviolet (UV) source and micro photoluminescence (PL) using 325 nm laser source, emission results at 364 nm in UV range whereas smaller nanostructures gives in broadband peak in visible range (at ~555 nm) due to defects either by native or deliberately doped with foreign elements and band edge emission in UV range (at ~380 nm) due to band to band electronic transitions. Optical tunability controlled by two ways in these ZnO structures, firstly, by controlling process parameters and secondly, by appropriate doping with very low concentrations such as Antimony (Sb), Nickel (Ni), and Nitrogen (N₂). TEM results show that doping with Antimony (Sb) to ZnO nanostructures not only develops tailorable optical properties but also acts as growth enhancer moreover ZnO expel out Sb and stays over tips of the nanorods. ZnO nanostructures are not only grown and collected as powder but also on various substrates (Si, ITO and Ti/Pt on SiO₂) which is immersed during the microwave exposure. Various structural, morphological and optical characterizations such as XRD, FESEM, TEM, and micro photoluminescence (PL) have been done in order to control the tuneable optical properties. This optical tunability in these ZnO nanostructures is ideal candidate to be utilized in designing and fabricating the novel nanoscale optoelectronic devices.

CZT is a semiconductor material that promises to be a good candidate for uncooled gamma radiation detectors. However, to date, technological difficulties in production of large size defect-free CZT crystals are yet to be overcome. The most common problem is accumulation of Tellurium precipitates as microscopic inclusions. These inclusions influence the charge collection through charge trapping and electric field distortion. The common work-around solutions are to fabricate pixelated detectors by either grouping together many small volume CZT crystals to act as individual detectors, or to deposit a pixelated grid of electrical contacts on a larger, but defective, crystal, and selectively collect charge. These solutions are satisfactory in an R&D environment, but are unsuitable for mass production and commercial development. Our modeling effort is aimed at quantifying the various contributions of Tellurium (Te) inclusions in CZT crystals to the charge generation, transport, and collection, as a function of inclusions size, position, and concentration. We model the energy deposition of gamma photons in the sensitive volume of the detector using LANL&’s MCNP code. The electron-hole pairs produced at the energy deposition sites are then transported through the defective crystal and collected as integral charge at the electrical contact sites using CERN&’s Garfield software package. The size and position distribution of Tellurium inclusions is modeled by sampling experimentally measured distributions of such inclusions on a variety of commercially-grown CZT crystals using IR microscopy and image processing software packages.