Symposium EP11 : Novel Materials for End-of-Roadmap Devices in Logic, Power and Memory

Graphene’s high thermal and electrical conductivity makes it a promising material for next generation electronic devices, however a lack of a band gap leads to poor on-off ratios hindering its use in logic applications. Atomically precise graphene nanoribbons (GNRs) with uniform widths and armchair edges are fabricated via a scalable solution synthesis method to create a material with a well-controlled bandgap. [1] The bandgap of chevron graphene nanoribbons has been estimated to be 1.3 eV with photoelectron spectroscopy [1], 1.6-1.8 eV with UV-vis-NIR and photoluminescence spectroscopy [2,3], 2.8 eV with high resolution electron energy loss spectroscopy [4], and 1.57 eV with computational modeling [1]. Electronic characterization of solution-synthesized graphene nanoribbons has not performed with scanning tunneling spectroscopy due to problems caused by solvent residue. Scanning tunneling spectroscopy (STS) of nanoribbons directly assembled on noble metal surfaces is complicated by image charge screening which prevents measurement of the intrinsic nanoribbon bandgap. [5] Our work addresses these challenges through a dry contact transfer method that cleanly transfers solution-synthesized graphene nanoribbons onto H:Si(100) under ultra-high vacuum. The placement of nanoribbons onto a non-metallic substrate enables measurement of the intrinsic nanoribbon bandgap and offers a potential route towards graphene nanoribbon device fabrication. We deposit GNRs onto H:Si(100) under ultra-high vacuum using a fiberglass applicator, characterize the nanoribbons using scanning tunneling microscopy (STM), scanning tunneling spectroscopy (STS), and current imaging tunneling spectroscopy (CITS). STS indicates a 1.6 eV bandgap, in agreement with computational modeling. Using hydrogen depassivation lithography dangling bonds are formed underneath the graphene nanoribbons to examine silicon-graphene interactions. The GNRs are found to show metallic behavior when in contact with clean Si(100). CITS shows spatial variation in the electronic structure of the chevron graphene nanoribbons, providing direct evidence of charge localization. In contrast to straight armchair graphene nanoribbons which have been experimentally shown to have an increased local density of states at the edges [5], charge localization occurs at the center of chevron graphene nanoribbons. In conclusion, we have developed a protocol for detailed imaging and electronic characterization of solution-synthesized graphene nanoribbons on arbitrary substrates with high spatial resolution. The ability to visualize the local density of states provides further insights into how atomically precise engineering of graphene nanostructures changes their electronic properties.

[1] T. Vo, et al., Nat Commun 3189 (2014)
[2] T. Vo, et al., Farady Discussions 173 (2014)
[3] T. Vo, et al., Nano Lett. 15 (2015)
[4] C. Bronner, et al., Angew Chem Int Ed Engl 52 (2013)
[5] Y. Chen, et al., ACS Nano 7 (2013)

Chemical vapor deposition (CVD) using transition metal is the most promising way to produce large-size monolayer graphene. However, the graphene from the CVD method has usually numerous structural defects which cause to degrade its outstanding physical properties. Thus, it would be a great challenge to prepare high-quality graphene sheet without such structural defects, for promising applications. Recently, there have been many studies on the preparation of single crystal graphene to improve the quality, but most of them are far away from the practical way. Here we show large-area, single crystal graphene sheet on modified copper film with the most preferred lattice orientation by using a thermal annealing method. In this study, we show the way to convert polycrystalline copper film into single crystalline one, derived from unexpected abnormal grain growth (AGG) followed by recrystallization. By using (111) oriented copper film, large-area, high-quality graphene has been successfully prepared with time efficiency, particularly with no significant grain boundaries (GBs), confirmed by Raman, optical microscopy after UV/ozone treatment, and scanning tunneling microscope (STM). The absence of such GBs in the graphene sheet led to a high carrier mobility of ~12,000 cm²/Vs on SiO₂/Si wafer.

In field-effect transistors, the inherent randomness of dopants and other charges is a major cause of device-to-device variability. For a quasi-one dimensional device such as carbon nanotube transistors, even a single charge can drastically change the performance, making this a critical issue for their adoption as a practical technology. Here we calculate the effect of the random charges at the gate-oxide surface in ballistic carbon nanotube transistors, finding good agreement with the variability statistics in recent experiments. A combination of experimental and simulation results further reveals that these random charges are also a major factor limiting the subthreshold swing for nanotube transistors fabricated on thin gate dielectrics. We then establish that the scaling of nanotube device uniformity with gate dielectric, fixed charge density, and device dimension is qualitatively different than conventional silicon transistors, reflecting the very different device physics of a ballistic transistor with a quasi-one-dimensional channel. The combination of gate oxide scaling and improved control of fixed-charge density should provide the uniformity needed for large-scale integration of such novel one-dimensional transistors even at extremely scaled device dimensions.

A focused electron beam induced process (FEBIP) is a “direct-write”, additive nanolithographic process, using high-energy electrons. A possibility to tightly focus electrons accelerated to high (tens of keV) energy provides a superior lithographic capability (atom-by-atom lithography) to controllably manipulate material structure and properties on nanoscale, through either deposition or etching. The FEBIP is particularly useful when applied to monolayer graphene whose electronic properties can be changed by nano-scale modification of its geometry to nanoribbons and quantum dots or controllable doping (i.e., p-n junction formation).
In this work, we report on development of new methods for nano-scale modification of high-quality monolayer graphene grown by chemical vapor deposition (CVD) with an assist of the FEBIP. First, we demonstrate a utility of a focused electron beam induced deposition (FEBID) technique for dynamic modulation of carrier transport in a graphene field-effect transistor via controllable carbon doping of the graphene conduction channel. This unique capability of the FEBID technique is substantiated by electrical measurements in conjunction with the detailed AFM imaging of the channels. Next, we present the use of supersonic oxygen micro-jet for focused electron beam induced etching (FEBIE) to achieve high-resolution, fast and ‘clean’ patterning of graphene, minimizing parasitic carbon deposition at the etch boundaries. We demonstrate this new mode of FEBIE via experimental observations and supporting theoretical analysis of the physical mechanisms underlying the supersonic oxygen micro-jet assisted FEBIE.

Acknowledgement: This work was primarily supported by the U.S. Department of Energy (DOE), Office of Science, Basic Energy Sciences (BES), under Award #DE-SC0010729 (FEBID/E experiments, test structure fabrication and electrical measurements, and data analysis). AFOSR BIONIC Center Award No. FA9550-09-1-0162 provided support for synthesis of graphene samples and Raman/AFM characterization. The authors would like to thank Dr. Marius Chyasnavichyus for his technical assistance with AFM measurements and data analysis.

Moving beyond the limits of silicon transistors requires both a high-performance channel and high-quality electrical contacts. Carbon nanotubes provide high-performance channels below 10 nanometers, but as with silicon, the increase in contact resistance with decreasing size becomes a major performance roadblock. We report a single-walled carbon nanotube (SWNT) transistor technology with an end-bonded contact scheme that leads to size-independent contact resistance to overcome the scaling limits of conventional side-bonded or planar contact schemes. A high-performance SWNT transistor was fabricated with a sub-10 nanometer contact length, showing a device resistance below 36 kilohms and on-current above 15 microampere per tube. The p-type end-bonded contact, formed through the reaction of molybdenum with the SWNT to form carbide, also exhibited no Schottky barrier. This strategy promises high-performance SWNT transistors enabling future ultimately-scaled device technologies.

Ion doping with an electrolyte offers an effective way to reconfigurably dope two-dimensional (2D) materials p- or n-type. An electrostatic double layer (EDL) is formed by the ions in the electrolyte and their image charges in the channel, with sheet carrier densities that can exceed 10¹³ cm^-2 for both p- and n-type doping. To obtain a static doping profile without a constantly applied bias, the ions must be drifted to the surface of the 2D crystal and immobilized by decreasing the temperature of the device below the glass transition temperature (T_g) of the electrolyte. For electrolytes such as polyethylene oxide (PEO) and LiClO₄, the device requires cooling below -40 °C, precluding this approach from practical use in 2D electronic devices. In this work, an electrolyte with a T_g greater than room temperature, polyvinyl alcohol and LiClO₄, (PVA:LiClO₄, T_g = 80°C) is used to electrostatically gate graphene FETs. Because the T_g of the polymer is greater than room temperature, the EDL can be “programmed” at T > T_g and then “locked” in place by cooling to room temperature, providing a static doping profile. Hall bar measurements verify that sheet carrier densities of 10¹³ cm^-2 can be achieved at room temperature, with time-dependent current measurements on a graphene FET indicating that 80% of the EDL is retained after 8 hours at room temperature. This represents an improvement in EDL retention of 10⁸x over PEO-based electrolytes at the same temperature. In addition, unlike PEO-based electrolytes, PVA:LiClO₄ is compatible with the chemicals used in standard photolithographic processes, enabling metal contacts to be patterned directly on the electrolyte, as well as patterning of the electrolyte itself. This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of six SRC STARnet Centers, sponsored by MARCO and DARPA.

With continued scaling, selective deposition is likely to become an enabling process to achieve device features at the ~10 nm length scale. Both planar geometries and 3-D structures such as FinFETs will benefit from selective deposition processes, with the bottom-up, self-aligned growth enabled by this method helping to mitigate overlay challenges in lithography. In this presentation, we will describe area selective deposition using a variety of strategies based on atomic layer deposition (ALD). ALD is a good choice for selective deposition because its chemical specificity provides a means to achieve selectivity on a spatially patterned substrate. Typically self-assembled monolayers (SAMs) are used to passivate the surface, using SAMs in the regions where deposition is not desired. However, a major challenge is that after a finite amount of material is deposited, the ALD process also nucleates on the part of the surface covered with the SAM. We will describe several strategies to overcome the growth on the SAM and achieve significantly higher selectivity in area selective ALD of metal oxides. In one approach, to improve the blocking properties of the SAM on copper surfaces, SAM molecules are re-dosed between ALD cycles with the purpose of recovering the SAM. Results show that selectivity can be retained for much thicker metal oxide films. In a second strategy, area selective ALD is combined with selective removal of any residual dielectric film with a mild etchant, again greatly improving the final selectivity. In both cases, selective ALD of more than 60 nm of metal oxide dielectric material has been achieved. These strategies open up the possibility for new applications in next generation electronic devices.

Recently in semiconductor memories such as working memories (SRAM, DRAM) and storage memories (NAND memory), it is becoming difficult to meet the target performance only by scaling technologies. Especially for 1X nm high speed working memories and beyond, the large power consumption brings more serious issues due to rapidly increase memory capacity, operation speed and leakage current of scaled CMOS. Moreover, the speed gap between each memory levels in addition to the speed gap between the operation speed of MPUs and that of working memories have expanded year by year.
In this invited talk, it is discussed about the directionality of the semiconductor memory hierarchy structure in the future from the background mentioned above, as shown in Fig.1. It is introduced that with using 3D stacked memories based on Vertical MOSFETs (see Fig.2) and STT-MRAMs (see Fig.3), the current issues of cell density, speed gap and power consumption will be simultaneously overcome, and novel memory hierarchy structure will be achieved. In addition, from the viewpoint of future high-end memory system, the impact of memory technologies hybridized with Vertical MOSFETs and spintronics devices such as MTJs is discussed. Finally, nonvolatile logic (see Fig.4) as one of application of STT-MRAM is shown.
Acknowledgment: This work was supported in part by CIES’s Industrial Affiliation on the STT MRAM program, an R&D Subsidiary Program for Promotion of Academia–Industry Cooperation of METI, ImPACT Program of CSTI and ACCEL Program under JST.

References
T. Endoh, K. Kinoshita, T. Tanigami, Y. Wada, K. Sato, K. Yamada, T. Yokoyama, N. Takeuchi, K. Tanaka, N. Awaya, K. Sakiyama, and F. Masuoka, "Novel Ultra High Density Flash Memory with A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEEE 2001 IEDM, pp. 2.3.1-2.3.4, 2001

T.Endoh, S.Togashi, F.Iga, Y.Yoshida, T.Ohsawa, H.Koike, S.Fukami, S.Ikeda, N.Kasai, N.Sakimura, T.Hanyu and H.Ohno, “A 600MHz MTJ-based nonvolatile latch making use of incubation time in MTJ switching,” 2011 IEDM, pp.75-78, 2011.

T.Endoh, T.Ohsawa, H.Koike, T.Hanyu, and H.Ohno, "Restructuring of Memory Hierarchy in Computing System with Spintronics-Based Technologies", Symposia on VLSI Circuits, pp89-90, 2012, (Invited)

T.Endoh," Spintronics Based NV-Memory/Logic for High Performance & Low Power", 2013 VLSI Technology Short Course of 2013 Symposium on VLSI, June 2013 (Invited)

T.Endoh "STT-MRAM Technology and Its NV-Logic Applications for Ultimate Power”, CMOS Emerging Technologies Research, MINATEC, 2014 (Invited)

H.Koike, T.Ohsawa, S.Miura, H.Honjo, S.Ikeda, T.Hanyu, H.Ohno, and T.Endoh,“A power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation”, Jpn. J. Appl. Phys. 54, 04DE08, March 2015.

T.Imamoto, Y.Ma, M.Muraguchi, and T.Endoh, “Low -Frequency Noise Reduction in Vertical MOSFETs Having Tunable Threshold Voltage Fabricated with 60 nm CMOS Technology on 300 mm Wafer Process”,Jpn. J. Appl. Phys. 54, 04DC11, March 2015.

Utilizing monolayers of compressive organic materials we have developed and demonstrated nanoelectromechanical (NEM) switches operating through a tunneling switching mechanism. With abrupt switching behavior and near-zero leakage currents, NEM switches are promising competing technology to the complementary metal-oxide-semiconductor transistors. However, conventional NEM switches suffer from relatively large actuation voltages and premature failure due to permanent adhesion of device components, referred to as stiction. Our proposed tunneling NEM switches overcome these challenges, providing a promising platform for the development of low-voltage and stiction-free devices. In these switches, the switching gap is composed of a sub-5 nm compressive organic layer formed through a self-assembly process and sandwiched between conductive contacts. Application of a voltage between the contacts provides a force to mechanically compress the molecular film, decreasing the tunneling gap. As the tunneling gap is reduced, an exponential increase in the tunneling current is obtained to switch on the device. Once the applied voltage is removed, the elastic force restored in the compressed molecules overcomes the surface adhesive forces to recover the top electrode to the off-state position. Presence of the molecular film facilitates formation of a few-nanometer-thin switching gap which promotes lowering of the actuation voltage. Concurrently, the molecular layer which avoids direct contact between the electrodes enables nanoscale control of the surface adhesive forces to promote stiction-free operation. Precise engineering of the molecular film mechanical properties through chemical synthesis and thin-film assembly techniques can tune the switching performance. Utilizing metal-molecule-metal and metal-molecule-graphene tunneling junctions we have demonstrated such tunneling NEM switches. With sub-2 V operation and over 5 orders of magnitude current conduction modulation, these devices can enable a multitude of low power electronics applications.

The performance of GaN devices is degraded by a high concentration of defects at the dielectric/GaN interface, which results in reliability issues, i.e. gate leakage and current collapse. The defects responsible for these failure mechanisms are likely related to the surface and interface charge that compensate the strong spontaneous polarization of GaN (~1.81x10¹³ charges/cm²); but research indicates these failure mechanisms can be at least partially mitigated with appropriate cleaning processes and gate dielectric. Plasma-enhanced ALD (PEALD) for dielectric deposition uses oxygen plasma as the oxidant, which offers significant advantages over other ALD techniques as well as non-ALD techniques, including lower impurity content, improved stoichiometry, lower deposition temperature, and versatility. Some of the most promising PEALD dielectrics include Al₂O₃ and SiO₂. Al₂O₃ will likely be the high-k dielectric of choice for these III-N devices, where these films variability make it the ideal candidates for PEALD studies. The variability of Al₂O₃ is related to the varied crystal structures, which provide a range of dielectric constants, densities, and band gaps. For example, research has shown that crystalline Al₂O₃ has required growth conditions >600 °C dependent on the precursor and substrate, even for plasma-enhanced ALD. However, Al₂O₃ films are also characterized by positive charge near or at the interface, which may interfere with desired electrical behavior. SiO₂, on the other hand, is a very consistent material with a large band gap (8.9 eV). Therefore, for applications where band offsets are more crucial than dielectric constant, e.g. vertical CAVETs, SiO₂ may prove instrumental. Research has thus worked to investigate ALD-dielectric/GaN interfaces with particular attention to the influence of surface preparation, gate dielectric and dielectric passivation growth conditions, as well as post deposition annealing on interface states. In our specific work, in-situ photoelectron spectroscopy in conjunction with ex-situ electrical characterization has been used to examine the relevant interface for high-powered applications.
This research is supported by the ONR DEFINE MURI and ARPA-E Switches Programs.

Enhancement mode (E-mode) GaN based devices are the focus of research and development fuelled by power switching and high frequency applications. E-mode devices make simpler power amplifier circuits possible by using a single polarity voltage supply, and this will also lead to lower cost and an improvement of system reliability. For high power switching applications in particular, increased safety can be achieved by using a normally-off device. Due to high polarization effect of GaN/AlGaN structures, the GaN based devices are not naturally off. Several approaches have been reported in the past to realize the normally-off operation GaN transistors including thermally oxidized gate insulator [1], fluorine/hydrogen plasma treatment [2], recessed gate structures [3], p-type gate injection [4], and surface channel GaN [5]. In this report, we investigate the incorporation of nitrogen species into Al₂O₃ using N₂ plasma exposure during ALD film growth as an approach to realize the E-mode operation of GaN devices. As reported in Ref. [6], nitrogen may incorporate on cation or anion sites or interstitial sites and become the source of negative fixed charges within Al₂O₃. The shift of flat band voltage (V_fb) of GaN MOSCAP to the right with △V_fb = 3 V have been achieved for 17 nm of oxide thickness (T_ox) after using 10 second N₂ plasma exposure following each ALD cycles with ΔV_fb = 4.6 V following post deposition annealing (PDA) at 1000 C for 30 minutes under N₂ ambient. A uniform distribution of N content across the oxide was detected using XPS measurement before PDA. But after the PDA treatment, a higher N content within the bulk oxide was detected suggesting a higher bulk oxide charges located within the oxide leading to a larger V_fb shift of GaN MOSCAP. The effectiveness of this approach for oxide charge modification of ALD-grown Al₂O₃ will be presented in detail. The positive shift of V_fb observed in this work brings us a step closer in the direction of preparing E-mode GaN-based FETs with both low trap densities and sufficient threshold voltage shift.
References:
[1] K. Inoue et al., Elect. Dev. Meet., IEDM Technical Digest. International, pp. 25.2.1 (2001).
[2] Zhang et al., Appl. Phys. Lett. 103, 033524 (2013).
[3] W. B. Lanford, et al., Electron. Lett. 41, no. 7, 449 (2005).
[4] Y. Uemoto, et al., IEEE Trans. Elect. Dev. 54, no. 12, 3393 (2007).
[5] W. Huang, et al., IEEE Elect. Dev. Lett. 27, no. 10, 796 (2006).
[6] Choi et al., Appl. Phys. Lett. 102, 142902 (2013).

Electrically active defects that trap carriers are critically important in MOS devices. Their effects are particularly pronounced for arsenide-based (e.g. InGaAs) semiconductors intended for NMOS devices because of 1) the relative ease of forming surface defects on these crystals, 2) the lack of an insulating native oxide (such a SiO₂) to inhibit tunneling of electrons from the substrate into near-interface defects in deposited gate dielectrics, and 3) the low density of states in the conduction band of the semiconductor that enhances the effect of charge traps on the measured capacitance compared to materials such as Si or Ge. The relative contributions of interface defects and traps in the oxide (border traps) to the frequency-dependent capacitance- and conductance-voltage behavior of high-k/InGaAs gate stacks can be most effectively resolved if suitably abrupt interfaces are prepared.

Border traps in the oxide reduce the charge in the channel and thus degrade the on-state performance of InGaAs MOSFETs. In this presentation, results are reported on the effects of various approaches to reduce the density of border traps (N_bt) in ALD-Al₂O₃ dielectrics, such as variation of the ALD temperature, and of forming gas (5% H₂/95% N₂) anneal (FGA) conditions. Dielectric deposition was performed immediately after in situ thermal desorption of a protective As₂ layer that prevents oxidation and contamination of the InGaAs(100) surface during prior air exposure. Quantitative border trap modeling of MOS capacitor data obtained over a range of frequencies and measurement temperatures indicate that Al₂O₃ MOS capacitors fabricated using a standard TMA/H₂O ALD chemistry at 120°C have a 2X-3X lower border trap density (N_bt), without increasing the interface trap density (D_it), compared to samples prepared at a more standard 270°C Al₂O₃ ALD temperature. The reduction of N_bt with decreasing ALD process temperature is consistent with time-of-flight secondary ion mass spectrometry depth profiles that show more effective hydrogen incorporation in the low-temperature ALD-grown Al₂O₃ films during post-gate FGA. Bias-temperature-stress testing of these Al₂O₃/InGaAs gate stacks results in interface trap generation, but had no detectable impact on N_bt, for the stress conditions investigated.

The nature of border trap response in low-temperature ALD-HfO₂ films is also reported, and compared to ALD-Al₂O₃. Pre-ALD InGaAs surface preparation conditions are found to strongly influence D_it for low-T ALD-HfO₂ MOS capacitors, but have no effect N_bt.

III-V compound semiconductors have superior electron and hole mobilities compared to silicon, which makes them alternative materials to fabricate transistors that are faster and use less energy. Since the oxides of III-Vs contain many defects and have undesirable electrical properties, aqueous passivation chemistries are needed to incorporate III-V materials into existing semiconductor processing lines. This study seeks to determine whether a thin (~2-3 nm) layer of a sulfur-containing molecule can chemically passivate clean III-V surfaces to prevent oxide regrowth upon ambient exposure. Alkanethiols with chain lengths from 3-20 carbon atoms were deposited from the liquid phase on GaAs (100) (RMS=0.20 nm by AFM) after oxide removal with HF and HCl. Their effectiveness in preventing oxidation in ambient conditions was characterized using ellipsometry, X-ray photoelectron spectroscopy (XPS), and Fourier-transform infrared spectroscopy (FTIR). The ellipsometry thickness of self-assembled monolayers (SAMs) formed with thiols with chains of 18 and 20 C atoms was 21.6±0.5 and 25.5±0.5 Å, respectively (the calculated molecular length of the ET molecule is 27 Å). The C 1s XPS peak showed that thiols with longer carbon chains exhibited higher surface coverages, as well as reduced surface oxidation after ambient exposure. Transmission FTIR peaks at 2918±1 and 2850±1 cm^-1, corresponding to asymmetric and symmetric stretches of CH₂ moieties, demonstrated the formation of a well ordered monolayer for chains with 18 (1-octadecanethiol, OT) and 20 (1-eicosanethiol, ET) carbon atoms. SAMs formed by 20 min immersions in ET solutions were able to protect the GaAs surface from oxidation for up to 30 min based on XPS. Based on these results, the (100) crystal plane of the small-band gap semiconductors In_0.53Ga_0.47As (RMS=0.18 nm) and InSb (RMS=2.3 nm) was modified with ET SAMs. The deposition process consisted of 20 min and 20 hour immersions in dilute solutions of ET immediately after the acid cleaning. The surface reoxidation was slowed down with the ET treatment (only a 20 h immersion in ET yielded oxygen concentrations below detectable levels in the O 1s XPS state after exposing to air for 4 min). From the XPS analysis, the passivation layer bonds to the surface as a sulfide. The thickness of the overlayer (ET and InGaAs or InSb oxides) after immersing for 20 h in the ET solution was 26.3±0.1 Å on InGaAs and of 41.6 ±2.8 Å on InSb. Transmission FTIR showed that ET forms an ordered layer on InGaAs as evidenced by the presence of the asymmetric methylene stretch at 2919 cm^-1, but a partially ordered layer is formed on InSb at the same conditions (the asymmetric methylene stretch by ATR was shifted to 2925 cm^-1). These results show that the sulfur-based chemistries are bonding to InGaAs and InSb but the resulting layer is not dense enough to prevent oxygen or water vapor from diffusing and reacting at the surface.

Indium nitride (InN) is of interest in tunnel field effect transistors (TFETs) due to its small effective electron mass and its large band offsets with other nitrides which enables formation of staggered- or broken-gap alignments between TEFT sources and drains. However, a surface electron accumulation layer in InN has been a hindrance for fabrication of TFETS. This electron accumulation at the surface results from occupied surface states of In-In bonds. Scanning tunneling microscopy (STM), x-ray photoelectron spectroscopy (XPS), scanning tunneling spectroscopy (STS) and atomic force microscopy (AFM) have been used to investigate the atomic and electronic structure of InN (0001) surfaces after wet-chemical cleaning, atomic hydrogen cleaning, O₂ passivation and atomic layer deposition (ALD) of Al₂O₃. Ex-situ wet cleaning using HCl, NH₄OH, and (NH₄)₂S solutions formed a smooth and uniform surface and XPS measurements confirmed that carbon and oxygen were below 10%. STS measurement showed n-type conductivity with a band gap of 0.70 eV. The n-type conductivity indicates the accumulation of electrons resides on the InN surface. STM and STS measurements verified that the surface of InN is terminated with In-In double layer with no band gap consistent with the metallic characteristics of the surface. O₂ passivation of InN surface was performed to remove the In-In double layer. STM line traces revealed that domains were formed with step height of 3.5 angstrom which belongs to two monolayers of InO_x. The band gap of O₂ passivated InN surface was ~0.8 eV and Fermi level was at the mid-gap. This data is consistent with formation of an O-In-O layer that might remove the electron accumulation on the InN surface. MOS capacitors were fabricated on InN substrates with and without O₂ passivation by 60 cycles of Al₂O₃ ALD followed by Ni gate metal and front side contact deposition. The MOSCAPs on In-rich surfaces showed strong Fermi level pinning and approximately no capacitance variation as a function of gate bias. Cyclic oxidation and oxide removal has been tested to increase the Fermi level modulation in InN MOSCAPs.

I will present details of an exciting joint research effort investigating the potential for realizing polarization-induced interband tunneling transistors with III-Nitride heterostructures, and the materials challenges and requirements in reaching that goal.

A broader range of channel materials allowing better carrier confinement and mobility could be employed if a universal control monolayer (UCM) could be ALD or self-limiting CVD deposited on multiple materials and crystallographic faces. Si-OH is a leading candidate for use as the UCM, as silicon uniquely bonds strongly to all crystallographic faces of InGa_1-xAs, In_xGa_1-xSb, In_xGa_1-xN, SiGe, and Ge enabling transfer of substrate dangling bonds to silicon, which may then be functionalized with HOOH(g) in order to create the UCM terminating Si-OH layer. This study focuses on depositing a saturated Si-OH seed layer on InGaAs(001)-(2x4) at a substrate temperature of 350°C. XPS in combination with STS/STM were employed to characterize the electrical and surface properties of the saturated Si-OH seed layer on InGaAs(001)-(2x4).
The 350°C self-limiting CVD procedure employs a decapped In_0.53Ga_0.47As(001)-(2x4) surface dosed with total 87.6 MegaLangmuir Si₂Cl₆ followed by 210.55 MegaLangmuir total anhydrous HOOH(g). Complete saturation of silicon coverage is determined to occur once further dosing with Si₂Cl₆ leads to no further increase in the silicon 2p peak or further decrease in the substrate gallium 3p peak areas. Complete surface saturation of Si-O_x on InGaAs(001)-(2x4) was determined to occur once no further increase in the O 1s peak was seen with additional anhydrous HOOH(g) doses. Following Si-O_x surface saturation, 300,000 Langmuir TMA was dosed at 250°C, and XPS shows the emergence of the Al 2p and C 1s peaks indicative of TMA surface nucleation. The surface was subsequently dosed with 500 Langmuir atomic H at 250°C to remove the methyl groups on the surface aluminum, and replace with -H termination as well as remove any residual chlorine from the surface. The surface was then exposed to air for 30 minutes, dosed with an additional 500 Langmuir atomic H at 250°C, and then STS was performed. STM measurements of the Si-O_x surface show uniform surface coverage . STS measurements show the surface Fermi level (F_L) position moves towards midgap due to a surface dipole formation from –OH groups and oxygen bonding to the surface. TMA dosed on the Si-O_x surface shifts the F_L back towards the conduction band, consistent with unpinning and the -OH induced surface dipole being lessened through surface bonding with dimethylaluminum groups. Following the hydrogen dosing and air exposure, the F_L remains near the conduction band edge consistent with the surface being stable and unreactive in air. Initial MOSCAP fabrication results show the deposition of an Si-H_x layer on InGaAs(001) seeds Al₂O₃ gate oxide nucleation, and improves device performance by decreasing frequency dispersion, increasing C_max, and lowering the false inversion bump compared with InGaAs(001) MOSCAPs with no Si-H_x passivating layer, indicating the Si-O_x control layer should also serve as an electrically passivating layer for InGaAs(001) MOSCAPs and elevate device performance.

As transistor sizes decrease well into the sub-10 nanometer scale, Silicon (Si), the most widely used material in current transistor technologies will rapidly approach its fundamental scaling limits. In_0.53Ga_0.47As (InGaAs), with an electron mobility at least eight times that of Silicon, is considered a strong candidate for higher performing and more energy-efficient electronic devices. Integrating InGaAs in future mainstream transistors would help deliver more computing power and continue with Moore’s Law. However, one of the main challenges that still remains to be solved with InGaAs is how to achieve the highest possible level of dopant activation both in terms of percentage and total activation. In order to solve this problem a fundamental understanding of dopant behavior in the InGaAs crystal lattice is needed. In this talk, the energetics and dynamics of Si diffusion in InGaAs are presented. Si is a promising dopant for n-type transistor channel materials. Previous experimental results have suggested that Si has a concentration-dependent, and relatively low, diffusivity in InGaAs. Using a combination of ab initio and Kinetic Monte Carlo techniques, as well as experiments, we predict the limits of dopant activation and describe the relative prominence of dominant diffusion mechanisms at different temperatures. We also predict the effects of local environments, in terms of ordering of cations, say, and defect-induced strains on overall diffusion.

Recent progress with silyl halide elimination ALD reactions has opened up novel thermal ALD materials possibilities with applications in logic and memory [1],[2]. The antimony ALD process is an example, which uses antimony chloride and alkylsilyl antimony precursors to deposit elemental Sb [1]. By using an alternate metal halide precursor along with alkylsilyl antimony, one can deposit mixed metal-antimonide films by ALD. In this work we demonstrate the deposition of crystalline, intermetallic hafnium antimonide (HfSb) and aluminum antimonide (AlSb) by ALD. We present here the effect of process conditions on the antimonide film growth rate, composition, crystallinity, morphology, and electrical properties such as resistivity and work function.

Deposition of HfSb was performed between 200-250 °C using hafnium chloride and trimethylsilyl antimony precursors in a Pulsar® 3000 crossflow ALD reactor. The growth rate in this temperature range was 0.23-0.31 Å/cycle. Deposition of AlSb was performed between 125-250 °C using aluminum chloride and trimethylsilyl antimony precursors in a Pulsar® 3000 crossflow ALD reactor and an EmerALD 3000 showerhead ALD reactor. The growth rate in this temperature range was 0.45-0.58 Å/cycle.

Several unique features of the HfSb and AlSb films were observed. XRD analysis of a HfSb film deposited at 250 °C shows a crystalline diffraction pattern matching a recently discovered phase, Hf₅Sb₉ [3]. Hf5Sb9 is an interesting phase in crystallography, as it is the only example of an inorganic compound with a pure T-net, a planar layer of three-bonded Sb atoms [3],[4]. Previous synthesis of this phase was only achieved above 1000 °C, while our deposition was at 250 °C. Literature indicates that this phase is metallic with ~350 Ω^-1cm^-1 conductivity and low Seebeck coefficient of 3 µV/K. SEM analysis shows elongated nanocrystals or nanowires formed from the ALD process. The films of AlSb were highly reactive to air. Capping with a-Si was performed to allow for XRD analysis. XRD of the capped AlSb deposited at 250 °C shows a crystalline diffraction pattern matching one-to-one AlSb. AlSb is a semiconductor with a lattice constant of 6.1 Å, a band gap of 1.61 eV and a high conduction band energy useful for heterojunction device engineering [5].

[1] V. Pore, et al., Chem. Mater., 2011, 23 (2), pp 247–254
[2] C. H. Winter, et al., AVS 14th Int. Conference on Atomic Layer Deposition, 2014, Kyoto, Japan
[3] A. Assoud, et al., Angew. Chem. Int. Ed. 2004, 43, 5260
[4] J. Xu, et al., Z. Anorg. Allg. Chem. 2008, 2367_2372
[5] I. Vurgaftman, et al., J. Appl. Phys., 2001, 89, 5815-5875

Recently 3D Dirac semimetals, that are 3 D analogues of graphene, have gained significant attention in the physics community. In these materials linear dispersed bands give rise to mass-less electrons that behave like photons rather than usual electrons. Due to this exotic electronic structure 3D Dirac semimetals have been shown to have extremely high carrier mobility and magnetoresistance which makes them of high potential interest for applications in computer technology. Current materials however all have major disadvantages for future applications. Many of them are toxic (Cd3As2) or highly air sensitive (Na3Bi). An additional problem is that the energy range of the linear dispersed bands is usually very small such that a small amount of defects can destroy the desired properties. This is problematic for thin film growth which would be needed for potential applications. It is therefore of interest for a materials scientists to search for better suited 3D Dirac materials.

Here I will introduce a new material, ZrSiS, which is not only stable in air and water but also non-toxic and shows linear dispersed bands in an energy range larger than 4 eV, much larger than anything known before. This properties, as well as the ease with which large single crystals can be grown make ZrSiS of high interest for potential applications. I will explain how we used simple materials science and chemistry logic to predict this material to have an electronic structure that hosts mass less electrons and then proceeded to grow this material and confirmed the electronic structure. I will furthermore show initial results on electrical transport measurements and thin film growth.

In this work, we compare the performance of black phosphorous (BP) and the transition metal dichalcogenides (TMDs) MoS₂, MoSe₂, MoTe₂ and WS₂ for FET applications at the end of ITRS roadmap. Benchmarking results are compared against the equivalent Si FETs.

Device parameters are adopted from the 2019 and 2028 columns of 2013 ITRS. Quantum mechanical simulations show that while BP produces the best current at 2019 node, it is severely affected by scaling due to large tunneling at 2028 node and is most adversely affected by scaling among all of the vdW materials. The low transport mass of 0.15 which benefits BP for longer channels, is detrimental for shorter channels because of the increased direct tunneling. Si produces the least current at both nodes. Double gate (DG) TMD FETs give approximately twice the current compared to their single gate (SG) counterparts even for monolayer films.

Our devices have a high-k oxide under the gate and a low-k oxide in the source-drain extensions. The high-k/low-k spacer combination maintains improved gate control and reduces gate capacitance by reducing fringing (a factor of 2.5 for a BP FET). Also, DG FETs result in nearly twice the capacitance of the SG FETs which is reflected in their higher energy consumption albeit shorter delay.

For a 32 bit adder, at the 2019 node, Si provides the slowest circuit and BP is the fastest (63% faster than Si). Among the vdW materials, MoSe₂ is the slowest (57% compared to BP). Switching from SG to DG improves speed but at the cost of a higher energy (1.7 times in case of MoS₂ and Si FETs).

At the 2028 node, Si is still the slowest (even slower than 2019 node by 77%). However, WS₂ is the fastest (82% faster than Si) and BP is the slowest (37% slower compared to WS₂) among the vdW FETs. DG FETs are accompanied by faster switching for the price of energy (63% higher energy consumption for a 31.5% improvement in speed for the MoS₂ FET).

WS₂ has a smaller effective mass (compared to the other TMDs), although not small enough to enhance tunneling with extreme channel length scaling. Its large spin splitting in the K-valley along with the small effective mass jointly act to keep the quantum capacitance (and hence the total capacitance) at a minimum.

In summary, although BP is largely known for its extremely high low field mobility and large transverse density of modes, and even though it is the best choice at the 2019 node, the WS₂ FET beats the BP FET at the end of roadmap. For ultra-short channels, WS₂ has the optimum effective mass of 0.35, large enough to prevent direct tunneling but smaller than any of the other TMD materials considered. DG FETs can produce a large current, but they are usually accompanied with large capacitance, which adversely affects the energy consumption. The high-k/low-k gate dielectric combination keeps the capacitances at a minimum without sacrificing gate control.

Supported by FAME, one of six centers of STARnet, a SRC program sponsored by MARCO and DARPA.

Over the last years, two-dimensional (2D) materials are attracting an increasing amount of interest for various electronic applications owing in particular to the ideal electrostatics conditions that can be enabled in a three-terminal field-effect transistor (FET) geometry. Transition metal dichalcogenides (TMDs) as MoS₂, WSe₂, or WS₂, to just name a few, or black phosphorus (BP) offer sizable bandgaps at mobilities that cannot be achieved in three-dimensional, bulk type materials that are scaled down to similar dimensions. The key is the absence of dangling bonds at the 2D semiconductor to substrate or gate dielectric interface that allows for highly conductive channels with sub-nm body thicknesses. In my presentation I will discuss the benefits of an ultra-thin body structure for scaled device applications. I will also elucidate the critical impact of Schottky barrier (SB) contacts in the context of TMD and BP devices and will present an analytical approach that allows extracting materials and device information as the SB height and bandgap of single- and multi-layer FET structures. Moreover, I will also present an analysis on the impact of layer thickness on the current flow in multi-layer TMDFETs and scaling aspects that make ultra-thin body structures behave distinctly different from doped conventional devices.

Advances in 2D materials such as transition metal dichalcogenides (TMDs) and graphene have enabled a host of advanced device concepts. We will discuss analog rf circuits that can be made in mechanically flexible TMD circuits which be used for the Internet of Things (IoT). We will also describe beyond-CMOS ideas such as tunnel FETs that can be used in novel logic and memory circuits that are enabled by the unique properties of graphene and TMDs.

The transition metal dichalcogenides (TMDs) are two-dimensional layer solids with van der Waals bonding between layers. In this work, we will try to explain the strong Fermi level pinning at the TMD interfaces. Three important aspects will be discussed including the metal contract for TMDs, the band offsets between different TMDs, and the intrinsic defect induced Fermi level pinning.
We first investigated how the layered structure and the van der Waals interaction affects the metal contact. We calculate their Schottky barrier heights (SBHs) of a wide range of metal contacts on TMDs using super-cell models and density functional theory. It is found that the SBHs without defects are quite strongly pinned, with a pinning factor S of about S=0.3 for all TMDs, a similar value for both top and edge contact geometries. This arises because there is direct bonding between the contact metal atoms and the TMD chalcogen atoms, for both top and edge contact geometries, despite the weak interlayer bonding in the isolated materials. The Schottky barriers largely follow the metal induced gap state (MIGS) model, like those of three-dimensional semiconductors, despite the bonding in the TMDs being largely two-dimensional and within the layers. The pinning energies are found to be lower in the gap for edge contact geometries than for top contact geometries, which might be used to obtain p-type contacts on MoS₂. It is found that MoO₃ is a good p-type contact. The strong dipole in MoO₃ could further help to lower the SBH.
We further calculated the band offsets between different TMDs and compare them with bulk cases. In the Schottky barriers of 3D semiconductors, the metal’s travelling wave states decay as evanescent waves in the semiconductor gap, and these ‘MIGS’ pin the Fermi energy of the metal to the semiconductor CNL. The pinning factor S is quite low. At a 3D semiconductor heterjunction, the MIGS-like states only occur where there are band states on one side of the heterojunction, and not where there is a complete gap. These states pin the bands of each smeiconductor together with the same S value as at the Schottky barrier. We previously showed that in the 2D TMDs, their Schottky barriers are actually 3D-like because of strong metal to TMD bonding. Thus in TMDs, the SBs are 3D-like, but the heteorjunctions are 2D-like, in complete contrast to the 3D case.
Finally we identify some intrinsic defect could further pin the Fermi level near the conduction band. The S/Se vacancy has much lower formation energy than the Mo/W vacancy. The S/Se vacancies are all found to introduce 0/+1 and +1/+2 transition states in the band gap. The transition levels are deep in the mid-gap region in MoSe₂, WS₂, and WSe₂ while close to CBM in MoS_2. The formation energy of anion vacancies is much larger than that in MoS₂. The Fermi level pinning near the conduction band edge due to reactive metal electrode should be suppressed in MX2 other than MoS₂.

In the last decade there has been a renewed interest in layered materials that can be stable in their monolayer form. Demonstration of the remarkable electronic properties of graphene led to exciting research on the potential nanoelectronic applications of this material. Research focused on graphene analogs such as MoS₂ and other transition metal dichalcogenides (TMD) has gained momentum in the last five years due to their similar mechanical properties to graphene coupled with their semiconducting nature that provides the potential for integration in traditional nanoelectronic device architectures. One of the predicted benefits of using 2D materials for nanoelectrics is the potential for atomically abrupt, low defect density interfaces due to the absence of dangling bonds on the surface. This absence of dangling bonds can hinder thin film depositions onto these materials and thereby present a significant challenge to the integration of 2D materials into current nanoelectronic device fabrication processes.

Presented will be a summary of our work studying the nucleation of atomic layer deposition (ALD) precursors on 2D materials including graphene and MoS₂. These studies have investigated the thin film morphology and also the interface chemistry using a range of microscopy and spectroscopy techniques. We will discuss the differences and similarities between graphene and the TMD family of materials and also survey the range of functionalization methods that have been employed to enhance the ALD nucleation.

This work was supported in part by the Southwest Academy on Nanoelectronics sponsored by the Nanoelectronics Research Initiative, by the center for Low Energy Systems Technology (LEAST), one of the six centers supported by the STARnet phase of the Focus Center Research Program (FCRP), a Semiconductor Research Corporation program sponsored by MARCO and DARPA, and by the US/Ireland R&D Partnership (UNITE) under the NSF award ECCS-1407765.

The wide range of transition-metal dichalcogenides (TMDs) (eg MoS₂, WSe₂) allows for band structure engineering to provide type 2 or type 3 band alignments for use in tunnel FETs (TFET). Stacked layer TMD heterojunctions would allow the desired band engineering while the van der Waals inter-layer bonding removes the lattice matching condition needed for the analagous III-V semiconductor heterojunction. The choice of which TMDs to use depends on their band offsets.
We have directly calculated these band offsets for the monolayer (ML) or bulk cases using 1 ML supercells or 5 ML supercells of the two component semiconductors and derive the band offsets from the local density of states in each part. We use a hybrid functional to correct the band gap error, and include the van der Waals correction to DFT. Of particular interest are the heterojunctions between MoS₂, MoSe₂, WS₂ and WSe₂ against SnS₂, HfS₂ or ZrS₂. Of these compounds, SnS₂, HfS₂ and ZrS₂ have deeper valence band maxima (VBMs), being d⁰ compounds, while MoX₂ and WX₂ have higher VBMs due to the extra band filling as d² compounds. Also, the VBNs rise towards to the vacuum level along the series MS₂, MSe₂, MTe₂. We find that MoS₂ or WS₂ on SnS₂ gives a type 2 band offset. SnS₂ on MoSe₂ or WSe₂ gives a type 3 offset, for both the ML and bulk cases (especially bulk). The calculated VBM energies of bulk SnS₂, SnSe₂, HfS₂, MoS₂ and WSe₂ are close to their measured XPS values [1]. The calculated band offsets of bulk HfS₂:WSe₂ (1.9 eV) is very close to its XPS value (1.88 eV)[2], and that of MoS₂ on WSe₂ is close to its experimental value (0.88 eV)[3]. The band offsets follow close to the electron affinity rule.
[1] R Schlaf, et al, JAP 85 2732 (1999)
[2] C Kreis, et al, App Surf Sci 166 17 (2000)
[3] M H Chiu, et al, Nature Comms 6 7666 (2015)

III-V compound semiconductors are considered to extend the logic device roadmap as conventional silicon (Si) field-effect transistor (FET) scaling is fast approaching its limits. As alternative channel material, they are well positioned to deliver performance increase for logic switching devices due to their higher electron mobility and saturation velocities compared to Si. A challenge is to further reduce the supply voltage to decrease the power consumption. This can be addressed by Tunnel FETs (TFETs) which make use of band-to-band tunneling to inject charge carriers into the channel and thus enable sub-kBT/q switching and low-voltage operation.
In this presentation we will discuss our recent progress to monolithically integrate III-V nanostructures on Si using template-assisted selective epitaxy (TASE). This method allows the epitaxial growth of vertical as well as lateral nanowires and more complex nanostructures monolithically integrated on Si. Based on InAs nanowires grown by lateral TASE on Si multiple-gate FETs were fabricated and performance parameters extracted. The TASE approach has been also applied to fabricate vertical InAs-Si p-type nanowire TFETs on Si. A process flow to fabricate vertical TFETs was developed and significantly improved by (1) optimizing the InAs NW growth process (growth temperature, V/III ratio and precursor flow) for high yield and material quality, (2) using inorganic TEOS spacer layers, (3) using ALD for depositing the metal gate, and (4) scaling the EOT from 2.7 to 1.5 nm.

Continued scaling of silicon FETS will require new device structures as well as the introduction of non-traditional semiconductor materials, with high mobility III-V compound semiconductors one promising route. Low dopant activation is a fundamental issue, however, limiting the lowest resistivities that can be achieved. In this work, we explore the use of sub-millisecond laser spike annealing (LSA) to reach high annealing temperatures for short times to achieve high metastable activated concentrations. For silicon-doped InGaAs, we demonstrate improve dopant activation relative to techniques like rapid thermal and furnace annealing.

In_0.53Ga_0.47As on lattice-matched InP films were doped with Si either through ion-implantation (5x10¹⁴ cm^-2, 10 keV, 80^°C) or by in-situ doping to metastable carrier concentrations of ~3x10¹⁹ cm^-3 by molecular beam epitaxy. Samples were annealed by scanning a diode laser (980 nm) across the sample with a 5 ms dwell using single (non-overlapped) sweeps. The spatial variation across this single laser stripe was analyzed with high spatial resolution to understand annealing as a function of peak temperature in a combinatorial approach. Peak annealing temperatures were determined using Pt thin film thermistors (spatial variation) with absolute temperatures established by decomposition of block-co-polymer films. Micro-Raman spectroscopy was used to characterize active carrier concentrations using shifts of the longitudinal optical phonon-plasmon coupling mode.

Compared to furnace and RTA anneals, the short timescales of LSA allowed samples to reach higher temperature prior to thermal damage. These higher temperatures allowed activation of high-dose implants to a peak concentration of 1.4x10¹⁹ cm^-3, the limit established previously by RTA and furnace anneals. However, higher metastable concentrations were observed for two stage annealing, combining an RTA at 750°C with LSA to achieve concentration of 1.8x10¹⁹ cm^-3. In contrast to longer timescale anneals, metastable activated concentrations are stable during LSA annealing with no observable deactivation. The high 3x10¹⁹ cm^-3 concentrations achieved by MBE growth remained fully active up to the damage threshold. Other dopants studied, including Te-doped InGaAs and S-doped InAs, show similar trends during LSA processing.

Oxide-based resistive switching memory (RRAM) is considered as a valuable non-volatile storage technology, because it offers fast switching, high endurance and good scalability [1,2]. RRAM operation relies on the resistance modulation of a conductive filament (CF). The CF is considered as a reversible local valence-change in the oxide (insulator) of a metal-insulator-metal structure [1-3]. While the usage of CMOS-friendly materials have paved the way to the sub-1X node integration for RRAM [4], the filament observation is still a challenge, and assessing the ultimate scaling-capability of resistive switching (RS) is hampered by lithography. In this work we experimentally observe in three-dimension (3D) the CF in bipolar oxide-based RRAM. This is enabled by scalpel C-AFM, which collects C-AFM images of the conductive filament at different depths leading to a full 3D-characterization of the conductive volumes.[5] Due to the role of the oxygen vacancies (V_o) in defining the composition of the CF and its conductive properties, scalpel C-AFM is carried out in high vacuum (10^-5 mbar) in order to minimize the interaction of the CF with the oxygen in the ambient. Next, by exploiting the modulation of the contact area of an AFM-tip we demonstrate resistive switching in a device as small as 3 x 3 nm. Finally, by statistical analysis of RS in 3 x 3 nm devices together with the shape of CFs, we demonstrate that the modes of operation observed, can be related to the number of defects contained in the CF and modelled through a low-defects assisted quantum-point-contact (QPC). Our observations physically explain the sub-10nm operation of RRAMs and provide strong evidences that the CF behaves as a defect modulated quantum point contact. Our results indicate possible scalability for the RS mechanism in the ~ 10 nm² regime.

Ref.
[1] R. Waser, M. Aono, Nat. Mater., 6 (2007) 833–40.
[2] H.-S.P. Wong, S. Salahuddin, Nat. Nanotechnol., 10 (2015) 191–194.
[3] G.-S. Park, et al., Nat. Commun., 4 (2013) 2382.
[4] B. Govoreanu, et al., IEDM Tech. Dig., 2011, pp. 31.6.1 – 31.6.4.
[4] U. Celano et al., Nano Lett. 2014, 14, 2401–2406.

Redox-based switching effects encountered in metal oxide cells offer a huge perspective for future nanoelectronics - with respect to highly scalable non-volatile memories and logic devices, exhibiting extremely fast switching and excellent energy efficiency. A range of material systems exist in which ionic transport and redox reactions on the nanoscale provide the essential mechanisms for memristive switching. It will be emphasized that the switching kinetics must show an ultra-nonlinear characteristics, in order to facilitate fast switching (ns range) and high data retention (10 years range). The microscopic physics of the processes involved such as temperature and field accelerated ion transport, nucleation and growth of phases on the nanoscale will be reviewed and their contributions to the device performance will be discussed.

Two-terminal resistive switches are one of the most promising candidates for future low-power non-volatile memory and logic applications [1]. Here, logic states are encoded by conductive filaments which are manipulated by the drift of cations or oxygen vacancies depending on the electrode and switching materials used. The filament growth and dissolution mechanisms and the dynamics involved are, however, still open questions, restricting significant device optimization [2]. We present a novel spectroscopic technique to optically characterize in situ the resistive switching effect [3]. We exploit the high optical sensitivity to the filament growth and rupture in the tightly confined plasmonic hotspot which is present in the switching material. Plasmon-enhanced spectroscopy allows probing resistive switches with realistic cell geometries under easily tuneable ambient conditions without the need of sophisticated sample preparation or electron beams perturbing the drift of ions. The presented technique is not restricted to cation based resistive switches only but can be also used for oxygen vacancy devices where in situ characterization of the filament formation using electron microscopy is even more challenging. The optical signatures we detect over many cycles indicate incomplete removal of particles from the filament upon RESET and suggest that the filament can nucleate from different positions from cycle to cycle. These results are complemented by electron microscopy [4] and characterization of redox reactions during the switching. We discuss the implication of these findings on the device endurance and stability.

[1] R. Waser and M. Aono, Nature Materials, vol. 6, pp. 833 - 840, 2007.
[2] S. Tappertzhofen, E. Linn, U. Böttger, R. Waser and I. Valov, IEEE Electron Device Letters, vol. 35, pp. 208-210, 2014.
[3] G. D. Martino, S. Tappertzhofen, S. Hofmann and J. Baumberg, submitted, 2015.
[4] Y. Yang, G. Gao, L. Li, X. Pan, S. Tappertzhofen, S. Choi, R. Waser, I. Valov and W. Lu, Nature Communication, vol. 5, p. 4232, 2014.

A new approach to memory will be presented that relies on the electrostatic gating of 2D crystals using lithium ions. Specifically, the development of a 2D electrolyte based on cobalt crown ether phthalocyanine (CoCrPc) will be emphasized, and the first device results will be presented. The proposed design for the memory device consists of two, 2D crystal layers, such as graphene or MoS₂, separated by a 2D electrolyte. Source and drain contacts, deposited on the top 2D crystal layer, are used to detect the resistance of the channel, which is modulated by the presence or absence of Li⁺ at the surface. When Li⁺ is near the channel, image charge is induced in the channel resulting in a low resistance (1) state, and when the Li⁺ is moved away from the channel via a gate, the channel is switched to the high resistance (0) state. Li⁺ will be toggled back and forth between energetically favorable sites within the crown ethers of the CoCrPc molecule to create the two states. Density functional theory calculations indicate that induced charge on one or the other of the electrodes will modulate the energy barrier encountered by the ions, making fast switching (~ 1 ns) and long retention (> 1 year) possible. Unlike resistive random access memory (RRAM), where conductive filaments are formed and broken to create the 0 and 1 states, this memory concept relies on the physisorption of ions to the 2D crystal and there is no charge exchange. We have demonstrated the solution-phase deposition of an ordered monolayer of CoCrPc on graphene. Li⁺ is introduced to the crowns of the CoCrPc by exposure to a solution of LiClO₄ and solvent, followed by annealing. To explore the electronic properties of this 2D electrolyte, a simplified device has been fabricated: a backgated graphene field-effect transistor covered with a monolayer of CoCrPc:LiClO₄. Initial current-voltage measurements indicate that the backgate can be used to pull Li⁺ to the channel surface, inducing n-type doping with sheet carrier densities of ~ 4 x10¹² cm^-2. While this state can be retained for the duration of the measurement (~ minutes), the ion response to the backgate is slower than predicted, and may include both a fast and a slow contribution. Efforts are currently underway to understand the materials properties that are limiting the switching speed, and longer retention measurements are planned.

This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of six SRC STARnet Centers, sponsored by MARCO and DARPA, and NSF grant #ECCS-GOALI-1408425.

Resistive random access memory (ReRAM) made of transition metal oxides sandwiched by two metallic electrodes has received great attention recently, due to the possibility of switching memory elements between high resistance states and low resistance states by varying the applied electrical bias across the oxide layer.¹ The most widely accepted explanation for this phenomenon is that filamentary regions of oxide with higher conductivity can be formed and broken depending on the applied bias, causing the transition between the “set” and “reset” states of the ReRAM device.² Nevertheless, the mechanism of the conductive filament formation is still not yet well understood, mainly due to the difficulty of detecting such filaments in a typical metal-oxide-metal device geometry. In this report, for the first time we replaced the top electrode by an ionic liquid gating to form and characterize the conductive filaments in TiO₂. Because ionic liquid can be readily rinsed off from the programmed oxide surface, this configuration saves the trouble of removing the top metal electrode,³ which strongly complicates subsequent characterization of the conductive filaments after formation. In addition, current flow is significantly limited due to the high resistivity of the ionic liquid, enabling us to test the effects of local electromigration of defects in the oxide distinct from those of local Joule heating.

Thin TiO₂ layers (~10 nm thickness) were grown by atomic layer deposition on a Pd bottom electrode structure. The TiO₂/Pd stack was coated with insulating photoresist, and small circular windows (with diameters ranging from 10 um to 150 um) were opened to expose the surface of the TiO₂. On the photoresist and near to the window edge, a top Pd electrode was patterned. The TiO₂ surface was electrically connected to the top Pd electrode using a drop of ionic liquid, and the conductive filaments were formed by applying a constant positive bias between the top and bottom Pd electrodes. After ionic liquid biasing, an increase of the oxide layer conductivity was detected depending on the amplitude and duration of the applied gate bias. Conductive atomic force microscopy (C-AFM) was then used to map the the TiO₂ surface, and surface features showing local regions of high current were detected in C-AFM maps, allowing a systematic study of the distribution and size of these regions on the employed biasing conditions. Finally, to reliably test the hypothesis that local coalescence of oxygen vacancies form the conductive filaments, we filled and stabilized the testing enclosure with ¹⁸O₂ tracer gas for extended hours after biasing the devices, and used Nano-SIMS measurements to characterize the local oxygen elemental exchange on the biased TiO₂ surface, to correlate it with the C-AFM data.

1. J. J. Yang et al., Nature Nanotechnology, 3, 429 (2008).
2. D-H. Kwon et al., Nature Nanotechnology, 5, 148 (2010).
3. U. Celano et al., Applied Physics Letters, 102, 121602 (2013)

Emerging memory devices such as ReRAM and STTRAM, as well as traditional NAND and DRAM are starting to explore complex materials to enable high performance devices. Chalcogenide based solid state electrolytes to enable ion motion in ReRAM, chalcogenide based phase change materials and complex High-K oxides in DRAM and NAND are examples of increasing complexity in the memory landscape. The material and electrical properties required to enable these different technologies are widely different. Several critical parameters such as dielectric constant, band offset, trap density, modulus, crystallinity and texture have to be simultaneously optimized for each technology. This talk highlights the performance requirements of advanced memory devices and materials engineering required to enable these devices

First principles calculations are employed to identify atomistic pathways for the generation of vacancy-interstitial pair defects in TiO2. We find that the formation of both oxygen and titanium defects induces a net dipole moment indicating that their formation can be assisted by an electric field. We also show that the activation barrier to formation of an oxygen vacancy defect can be reduced by trapping of holes which may be injected by the electrode. The calculated activation energies suggest that generation of titanium defects is more favorable than generation oxygen defects although activation energies in both cases are relatively high (>3.3 eV). These results provide much needed insight into an issue that has been widely debated but for which little definitive experimental information is available.

[1] S. Abdelouahed and K P. McKenna, J. Appl. Phys. 118, 134103 (2015)

Resistive Random Access Memory (RRAM) is a novel form of non-volatile memory that is expected to play a major role in future computing and memory solutions. It has been shown that the resistance of RRAM devices can be precisely tuned by modulating switching voltages by limiting peak current, and by adjusting the switching pulse duration. This enables the realization of novel applications such as memristive neuromorphic computing and neural network computing. We have developed memristive RRAM devices and integrated logic devices on a 300mm wafer platform with the IBM 65nm 10LPe process technology. This technology was customized with custom-developed tungsten metal 1 (M1) and dual tungsten/copper via 1 (V1) structures, within which the RRAM stack is embedded. The RRAM itself consists of an inert tungsten bottom electrode, hafnium oxide based active switching layer, a titanium oxygen exchange layer, and an inert titanium nitride top electrode. The test platform includes RRAM device sizes ranging from 100 x 100 nm² to 10 x 10 μm² in a vertically-integrated crossbar configuration, as well as high density memory arrays and on-chip 1T1R (1 transistor 1 RRAM) structures based on 100 x 100nm² devices. Linear sweep and controlled pulse (down to 10 ns) based electrical characterization of RRAM elements was performed to determine key endurance, reliability, retention and threshold voltage parameters. Our results demonstrate that the set operation (which shifts the RRAM device from the high to the low resistance state) is only dependent on the voltage of the switching pulse and the peak current limit. The reset operation, however, occurs in an analog fashion and appears to be dependent on the total energy of the applied switching pulse. Pulse energy was modulated by varying the peak voltage and pulse duration. Using these switching data we are able to create a model of the set characteristics as a function of peak current and pulsing voltage, and the reset characteristics as a function of pulse voltage and duration. This model enables simulation of complex circuits, such as memristive neuromorphic and neural network systems.

Resistive Random Access Memory (RRAM) has emerged as a leading candidate for non-volatile storage class memory. RRAM devices typically consist of a metal/insulator/metal (MIM) structure and exhibit switching of the device resistivity state (low to high, high to low) by application of electrical bias. It is now widely accepted that shunting and rupturing of local conductive paths (filaments) directly determines the resistance state. In oxide-based devices the filament is usually attributed to agglomeration of oxygen vacancies. We lack however the quantitative estimates of the filament size and composition. Since the non-volatile nature and device reliability issues (i.e. retention and endurance) are directly related to the irreversible structural transformations in the device, microstructural evidence is essential for eventual commercialization of RRAM. In this study, we aim to quantify the size, location, and chemical nature of the conductive filaments in programmed RRAM devices by a variety of device and materials characterization methods: high-resolution transmission electron microscopy (HRTEM), Scanning TEM (STEM)-electron energy loss spectroscopy (EELS), rapid thermal annealing (RTA), transient thermometry, and electro-thermal simulation.

The RRAM devices analyzed in this study are cross-bar type with a 85 nm MIM stack consisting of TiN/a-HfAlO_x/Hf/TiN. The small size of the device allows for examination of the entire active region of the device by TEM and imaging the filament irrespectively of its location. The HfAlO_x, as imaged with a C_s-corrected FEI Titan, is completely amorphous, while the Hf and TiN layers are nanocrystalline. In each of the switched devices, however, we have found a single crystallite ~ 8-16 nm in size embedded in an amorphous HfAlO_x matrix. The crystallite was tetragonal HfAlO_x with a lattice parameter of d₁₀₁=~0.30 nm. The HfAlO_x crystallization temperature (T_c) of 850 K was determined by combining RTA and HRTEM imaging. In parallel, we have determined the filament size by transient thermometry. The temperature profile extracted from these measurements suggests that the peak filament temperature is > 1500 K at the center, with the heat affected zone (T > T_c = 850 K) extending to a radius of 8 nm around the filament. These results are consistent with our HRTEM observations of the crystallite size. The potential filament location (crystallite) in the switching and endurance failure devices was analyzed by STEM-EELS and its chemical nature has been identified and correlated with the various switching and failure mechanisms.

Nickel Oxide (NiO_x), with its p-type behavior and nickel-vacancy controlled conductivity, is a promising electronic material for non-volatile memory, logic and photovoltaic device applications. In ReRAM devices, it has shown low voltage operation and fast programming. In solar cells, its low valence band offset and high conduction band offset with Si make it a good candidate for hole-selective, electron-blocking contacts.
Recently Ni amidinate (Bis(N,N’-di-t-butylacetamidinato) nickel(II)) has been shown to be a stable metal-organic compound suitable for ALD deposition of different Ni compounds such as metallic Ni, NiN_x, NiO_x etc. In this work, we present a detailed recipe optimization of ALD NiO_x. We present stoichiometry control by changing the deposition temperature. We observe that very close-to-stoichiometric films can be deposited using the optimized recipe. However, the films show some over-stoichiometry (x>1), which is the main source of p type conduction in NiO.
NiO_x was deposited using alternating pulses of Ni amidinate precursor and ozone in an Intermolecular Tempus A-30 ALD system. The precursor temperature was varied from 80 °C to 120 °C and the substrate temperature was varied from 150 °C to 280 °C. The deposition rates, film crystallinity, and film stoichiometry were determined using X-ray reflectivity (XRR), X-ray diffraction (XRD) and X-ray photoemission spectroscopy (XPS) respectively. Strong ALD behavior is observed from 150 °C – 200 °C. In this ALD temperature window the growth rate as a function of precursor pulse time saturated quickly, and the film non-uniformity across a 300 mm wafer was