9:30 AM - *EP2.3.01
Breakthrough Performance, Reliability and Robustness of SiC Junction Transistors
Siddarth Sundaresan 1,Stoyan Jeliazkov 1,Brian Grummel 1,Ranbir Singh 1
1 GeneSiC Semiconductor Dulles United States,
Show AbstractDespite having an npn epitaxial structure resembling a Si BJT, the switching performance of the SiC Junction Transistor or SJT is purely controlled by its terminal capacitances, similar to a SiC MOSFET or JFET. Further, the absence of a “high-resistance” SiC MOS channel in the SJT enables the SJT’s RON,sp to be almost exclusively limited by the resistance of the n- drift region. In contrast, the MOS channel resistance is a major component of the total RON,sp in present day, 900-1700 V rated SiC MOSFETs. Recently released SJTs feature RON,sp as low as 2 mΩ-cm2 for a breakdown voltage (BV) of 1450 V, and a RON,sp of 2.4 mΩ-cm2, for a breakdown voltage of 2000 V. Current gains > 100 are achieved, even on the highest current SJTs. Unlike Si BJTs, SJTs do not suffer from second breakdown, and can perform under unclamped inductive switching (UIS) conditions, even at full rated collector currents. Near-∞ Early voltage and a negative temperature co-efficient of current gain in a SJT ensure low collector currents under short-circuited load conditions, resulting in short-circuit withstand time as high as 14 µs, even at > 80% of the maximum rated BV. Recent technological developments at GeneSiC have significantly improved the stability of the SJT current gain (β) under high-current stress conditions. A 1000-hour long, 200 A/cm2 DC current stress results in only 10% reduction of the current gain (β) during the early stages of the stress test, while the β is perfectly stable for the remainder (>90%) of the stress duration. Interestingly, a smaller β compression is observed, when the collector current stress is applied not as DC, but at a high switching frequency ≥ 200 kHz. A comprehensive survey of the recent technological developments made at GeneSiC on SiC Junction Transistors will be presented in this paper.
10:00 AM - EP2.3.02
Al+ Implanted Vertical 4H-SiC p-i-n Diodes: Experimental and Simulated Forward Current-Voltage Characteristics
Roberta Nipoti 1,Giovanna Sozzi 2,Maurizio Puzzanghera 2,Roberto Menozzi 2
1 CNR-IMM Bologna Italy,2 UniPR-DII Parma Italy
Show AbstractThis study is a step forward towards the capability of simulating the electrical characteristics of SiC devices with identical geometry but different areas without the use of adjusting factors.
The material parameters featuring the static forward current transport in Al+ implanted vertical 4H-SiC p-i-n diodes have been obtained by studying the measured temperature dependence of the periphery and the area current densities of vertical diodes with circular emitters of diameters in the range 150-1000 mm. More precisely, vertical 4H-SiC p+-i-n diodes with Al+ ion implanted p+ emitter have been fabricated and the forward and reverse current-voltage characteristics have been measured in the temperature range 300-560 K. The periphery and area current density have been obtained by the procedure described in [1]. The traps responsible for the generation and the recombination currents in the space charge region of the ion implanted bipolar junction have been identified by the Arrhenius plots of the forward and reverse area saturation currents, as shown in [2-3]. Carrier life time in the space charge region, average diffusion velocity in the neutral region, and surface quality factor have been obtained as described in [3].
The static forward characteristics at room temperature of vertical p-i-n diodes with circular emitter of different diameters has been simulated by Synopsys-Sentaurus TCAD suite [4] where the 4H-SiC transport properties at room temperature has been fixed taking into account the results of the analysis of the measured I-V characteristics.
For every diode dimension, simulated and measured forward characteristics fit ones to the others with none need of adjusting factors.
[1] A. Nath, Mulpuri V. Rao, F. Moscatelli, M. Puzzanghera, F. Mancarella, and R. Nipoti, IEEE proceedings "Ion Implantation Technology (IIT), 2014 20th International Conference on", Portland, OR, USA, pp. 1-4.
[2] U. Grossner, F. Moscatelli, and R. Nipoti, Mater. Sc. Forum, vol. 778-780, pp. 657-660, Feb. 2014.
[3] M. Puzzanghera, and R. Nipoti, submitted for the proceedings of ICSCRM2015, Giardini Naxos, October 4-9, 2015
[4] http://www.synopsys.com/Tools/TCAD
10:15 AM - EP2.3.03
Optimization of Ion Implantation Processes for 4H-SiC DIMOSFET
Nicolo Piluso 1,Stefania Privitera 2,Enzo Fontana 1,Alfio Russo 1,Simona Lorenti 1,Salvatore Coffa 1,Francesco La Via 2
1 STMicroelectronics Catania Italy,2 IMM-CNR Catania Italy
Show AbstractIon implantation processes are believed to be fundamental for the success of 4H-SiC DIMOSFET devices, since determine the on resistance value and may affect the defect density and the channel mobility.
The implantation dose and the activation temperature are therefore two crucial parameters that need to be studied in detail. Indeed, ion implantation at high dose generates a detrimental disorder in the lattice crystal that cannot be easily restored by the following annealing process and, on the other hand, a low dose may affect the performance, by increasing the resistivity of the device.
In this work the ion implantation doses as well as the activation temperatures have been fine tuned in order to optimize the electrical characteristics of MOSFET devices.
Epitaxial layers with thickness 6 µm, and carrier concentration of 1016 at/cm3 have been used.
An optical characterization of the whole epitaxial wafers has been performed by Candela CS-920. This allows us to determine the surface defects distribution (comet, pit, carrot) and the crystallographic defects concentration (stacking faults density) as well, before ion implantation.
After the implantation step the samples have been analyzed by means of photoluminescence (PL) in order to determine the defect density introduced by the process. A typical 4H-SiC spectrum shows a peak related to the band edge centered at 388nm. A wide additional PL peak, located at 500 nm, is observed, due to the agglomeration of defects (points and extended) generated by the implantation. The monitoring of this PL signal (amplitude, shift, and width) provides the quality of the process carried out and gives the opportunity to optimize the DIMOSFET processes.
Complete MOSFET devices have been then manufactured and characterized.
A strong relationship between implanted dose, activation temperature (ranging between 1600 and 1700 °C) and electrical results has been observed. Improvement of the subthreshold leakage current as well as of the mobility has been achieved in optimized devices.
11:30 AM - *EP2.3.05
Investigation of Co-Sputtered Pt-Ti for Simultaneous Ohmic Contacts to N- and P-Type 4H-SiC
Robert Okojie 1,Dorothy Lukco 2
1 NASA Glenn Research Ctr Cleveland United States,2 Vantage Partners, LLC, NASA Glenn Research Center Cleveland United States
Show AbstractThe building block of bi-polar semiconductor integrated circuits is the p-n junction diode, which conventionally, requires successive fabrication steps to form ohmic contacts on the n-type and p-type contact surfaces. Conventional fabrication processes are time consuming, costly, and result in reduced yields with increasing successive fabrication steps and complexity. These problems are further compounded in silicon carbide (SiC) p-n-junction based devices by the non-planar topography resulting from reactive ion etching that is generally not friendly to multiple fabrication processes. It leads to lower device yields, non-uniform device-to-device performance characteristics, and overall below par device performance.
To address these challenges, the use of a single process step to simultaneously realize ohmic contacts on the two conductivities in 4H-SiC has been investigated. Another goal is to ensure that the specific contact resistances on the two conductivities are nearly identical and low in comparison to conventional values. We had previously reported the application of Tungsten-Nickel alloy to achieve simultaneous ohmic contacts to n- and p-type 4H-SiC having low specific contact resistance comparable to conventional values. As an extension of that work, selected ratio compositions of co-sputtered Pt-Ti thin films were investigated.
Three p-type epilayers with acceptor concentrations, Na = 2x1019, 7x1019, and 2.5x1020 cm-3, respectively, and one n-type epilayer with donor concentration, Nd = 7x1018 cm-3 were used in this study. The ratios of the co-sputtered Pt-Ti were 80:20, 50:50, and 20:80 atomic percent. After annealing at temperatures ranging between 800 and 1200 oC in argon ambient, specific contact resistances were extracted by the transmission line method (TLM) of measurement. Epilayers of thicknesses between 0.5 and 3 µm were homoepitaxially grown on semi-insulating 4H-SiC substrates. The TLM structures in the epilayers were obtained by conventional contact mask deposition and mesa patterning, followed by reactive ion etching to form the mesa. The metallization was deposited and etched to create the traditional TLM test structures. The samples were separated into groups, with each group comprising of four samples (3 p-types and 1 n-type). Each group was then rapid thermal annealed in argon ambient at different temperatures between 800 oC and 1200 oC for 5 seconds.
Results show that simultaneous ohmic contacts with specific contact resistances as low as 6.5 x10-5 Ω-cm2 and 7.34 x 10-4 Ω-cm2 were obtained for the 80:20 Pt:Ti ratio on the p-type sample with doping concentration of 2.5x1020 cm-3 and the n-type samples after annealing at 1000 oC, respectively. Thus, this composition is a potential candidate for use as simultaneous ohmic contacts for bi-polar junction based 4H-SiC devices. The comprehensive results from this investigation, the subsequent work done, and a comparative analysis with previously published results will be presented.
12:00 PM - EP2.3.06
Effect of Surface Counter-Doping with Antimony on Channel Transport in Lateral 4H-SiC MOSFETs
Yongju Zheng 1,Tamara Isaac-Smith 1,Ayayi Ahyi 1,Sarit Dhar 1
1 Auburn University Auburn United States,
Show Abstract4H-SiC MOSFETs exhibit low channel mobility and poor sub-threshold slope due to the existence of different types of charge traps, at or near the SiO2-SiC interface [1]. With Antimony (Sb) implantation in the channel region of lateral 4H-SiC MOSFETs, an improvement of channel mobility and sub-threshold slope has been observed. A ~10nm deep counter-doped layer on the surface of MOSFET channel region can be formed by Sb implantation and subsequent oxidation with NO annealing. This improves the channel field-effect mobility of 4H-SiC MOSFETs with lightly doped p-bodies to ~110cm2V-1s-1 by providing higher electron density in the channel, as well as lower carrier scattering [2]. For high voltage power electronics applications, a large Vth of about ~5 V is desired in order to have a large noise margin for normally off operation. This is achieved by employing moderately high p-body in the range of ~1-5E17/cm3. Therefore, in this work we investigated the effect of Sb surface counter-doping on MOSFETs with p-body doping of 1E17/cm3 and 5E17/cm3. Our results indicate that the Sb counter-doping process results in significant improvement of channel mobility (33cm2V-1s-1) and sub-threshold slope characteristics compared to reference devices without the surface counter-doping (22cm2V-1s-1). This, in conjunction with a large positive Vth makes this process extremely promising for SiC power MOSFET fabrication. While the results were impressive, SIMS revealed that a significant amount of Sb atoms is lost during the fabrication process which limits the improvement. We attribute this to the higher activation anneal temperature (1650°C) compared to our earlier experiments (1550°C). In order to optimize the process further, we are currently investigating the effect of different activation anneal temperatures and different Sb implantation energies on the Sb distribution profile in both SiO2 and SiC. In this talk, we will discuss the Sb counter-doping process in detail in context of these new experiments.
References
[1]G. Liu, B. R. Tuttle, and S. Dhar, “Silicon carbide: A unique platform for metal-oxide-semiconductor physics,” Appl. Phys. Rev. 2, 021307(2015).
[2]Modic, G. Liu, A. C. Ahyi, Y. Zhou, P. Xu, M. C. Hamilton, J. R. Williams, L. C. Feldman, and S. Dhar, “High channel mobility 4H-SiC MOSFETs by antimony counter-doping,” IEEE Electron Device Lett., vol. 35, no. 9, September 2014.
12:15 PM - EP2.3.07
Transmission of Signals Using White LEDs for VLC Application
Paula Louro Antunes 2,Vitor Silva 2,Manuel Vieira 2,Manuela Vieira 3
1 ISEL Lisbon Portugal,2 CTS-UNINOVA Caparica Portugal,1 ISEL Lisbon Portugal,2 CTS-UNINOVA Caparica Portugal,3 DEE-FCT Caparica Portugal
Show AbstractRecent developments in LEDs allowed them to be used in environmental lighting and have revealed many advantages over incandescent light sources including lower energy consumption, longer lifetime, improved physical robustness, smaller size, and faster switching. Besides this general lighting application, LEDs are now used in other specific fields such as automotive headlamps, traffic signals, advertising, and camera flashes. However another emerging field of application is in advanced communications technology due to its high switching rates. Thus, the visible light spectrum is currently being used in the Visible Light Communication (VLC) technology, taking advantage of the lighting infrastructure based on white LEDs, enabled by the invention of efficient blue LEDs.
In this paper we propose the use of a multilayered pinpin device based on a-SiC:H to work as a photodetector operating in the pertinent range of operation for VLC (375 nm – 780 nm) using as optical sources white LEDs based on phosphor and on a tri-chromatic RGB chip. The photodetector device consists of a p-i'(a-SiC:H)-n/p-i(a-Si:H)-n heterostructure with low conductivity doped layers, sandwiched between two transparent contacts. It works as an optical filter in the visible range with tunable spectral sensitivity dependent on both applied bias and type of steady state optical bias (wavelength, intensity and direction of incidence on the device).
Optoelectronic characterization of the device is presented and includes spectral response, transmittance and I-V characteristics, with and without background illumination. Results show that when the device is biased with front optical steady state light of short visible wavelength (400 nm) superimposed with the pulsed light emitted from the optical transmission sources, it exhibits an increased output current in the long range of the spectrum (550-650 nm), and a reduction of the same photocurrent for the short wavelengths (400-500 nm). Additionally, the background illumination from the back side also influences the photocurrent signal that is enhanced in the short wavelength range and strongly reduced for the long wavelengths.
Thus the device works as a visible optical filter with controlled wavelength sensitivity through the use of adequate optical biasing light, which enables the possibility of detecting different wavelengths. This feature allows the recognition of the individual components of the tri-chromatic white LED, which enlarges the amount of information transmitted by this type of white LED, when compared to the phosphor based LED.
A decoding algorithm for the detection of different optical signals is presented and discussed with an error detection procedure. A capacitive optoelectronic model supports the experimental results and explains the device operation. A numerical simulation will be presented.
2:30 PM - *EP2.4.01
Advances in Fast Crystal Growth of 4H-SiC
Hidekazu Tsuchida 1
1 Central Research Institute of Electric Power Industry (CRIEPI) 2-6-1 Nagasaka, Yokosuka Japan,
Show AbstractThis paper reports our recent achievements in fast 4H-SiC epitaxial growth and high-speed crystal growth by high-temperature gas source method, aiming to produce high-quality 4H-SiC epilayers at a high-throughput and boules with a low production cost.
Toward a high-throughput production of high-quality 4H-SiC epilayers, we developed a new single-wafer vertical reactor [1]. The reactor comprises lower and upper resistive heaters, a cylindrical wall inside the upper heater and a disc-shaped suscepter. A single 150 mm-diameter 4H-SiC wafer is placed on the susceptor and rotated up to 1000 rpm. The carrier and source gases are introduced from the top of the reactor. The total time for heating and cooling the wafer between the transfer and growth (1600-1650°C) temperatures is less than 15 min, which allows production of a 10 μm-thick epilayer within 30 min when the growth rate is ~50 μm/h. By controlling the gas-reaction in the hot zone and the thickness of the boundary layer above the wafer, we obtain a 11.3 μm-thick, 150 mm-diameter 4H-SiC epilayer at a 54 μm/h, achieving the thickness uniformity of ±2.3% and the doping uniformity of ±6.5% (average doping concentration: 6.1×1015 cm-3). Defect densities of
3:00 PM - EP2.4.02
Growth and Characterization of 200mm Silicon Carbide
Xueping Xu 1,Ping Wu 1,Avinash Gupta 1,Varatharajan Rengarajan 1,Mark Ramm 1,Ilya Zwieback 1,Gary Ruland 1
1 II-VI Incorporated Pine Brook United States,
Show AbstractSilicon carbide (SiC) is a wide bandgap semiconductor with high thermal conductivity, which is ideal for high-power, high-temperature, and high-frequency electronics. Higher quality and larger diameter SiC substrate is required in order to improve the performance and reduce the manufacturing cost of SiC-based electronic and optoelectronic devices. In this paper, we report the growth and characteristics of 200mm SiC substrates. SiC crystals were grown using advanced axial gradient physical vapor transport technique. Crystals with diameter larger than 200mm were first achieved by multiple generations of successive crystal growth where the single crystal area was expanded within each growth. The SiC substrates were characterized by resistivity mapping, x-ray rocking curve scanning for crystal quality, and cross-polarizer imaging for overall stress. Crystal defects were further analyzed by etching in molten hydroxide. Threading screw dislocations, basal plane dislocations, and threading edge dislocations were differentiated based on the shape and size of etching pits, and mapped with a microscope imaging system. The overall quality of 200mm SiC substrates is comparable to our commercial grade 150mm substrates.
3:15 PM - EP2.4.03
Conversion of BPDs in 4H-SiC Epilayers Grown on 2° Offcut Substrates
Rachael Myers-Ward 1,Paul Klein 1,Kevin Daniels 1,Anthony Boyd 1,Virginia Wheeler 1,Nadeem Mahadik 1,Robert Stahlbush 1,D. Kurt Gaskill 1
1 Naval Research Laboratory Washington United States,
Show AbstractSilicon carbide is a material of interest for high-voltage and high-power switching device applications. Basal plane dislocations (BPDs) are a major concern for SiC bipolar devices as they source Shockley-type stacking faults in the presence of an electron-hole plasma and reduce minority carrier lifetimes [1, 2]. Many researchers have investigated methods to reduce the BPD density by experimenting with pre-growth treatments [3-5], substrate orientation [6], growth parameters [6, 7] and growth interrupts [8]. This work investigates extended defects, morphology and lifetime in 4H-SiC epilayers grown on substrates offcut 2° toward the [11-20].
Epilayers were grown on 2° offcut substrates in a horizontal hot-wall reactor using the standard chemistry of silane (2% in H2) and propane. Epilayers were grown at various growth rates, C/Si ratios, and growth temperatures. The pressure was maintained at 100 mbar for all growths. Some samples were grown with a 5 µm highly doped n+ buffer layer using ultra high purity nitrogen prior to the low doped epilayers. Ultraviolet photoluminescence (UVPL) imaging was used to identify BPDs in the low doped epilayers. Time resolved photoluminescence measurements were performed to determine the minority carrier lifetime of the layers and Raman spectroscopy was used to analyze polytype inclusions. Electron trap concentrations were determined using deep level transient spectroscopy (DLTS). Surface roughness was measured by atomic force microscopy and the morphology was also characterized using Nomarski microscopy.
When a 15 µm epilayer was grown without a buffer layer, step bunching was observed and the surface roughness was 6.0 nm RMS. For comparison, a standard 4° offcut sample typically has 3.0 nm RMS for a 20 µm epilayer. Using UVPL, it was found that after 4 µm of epi, 90% of the BPDs had converted in the low doped layer as compared to 70% in a 4° offcut sample, indicating the conversion is faster in the lower offcut material. 3C-SiC inclusions were present in the epilayers as verified using Raman spectroscopy. The inclusions were reduced by increasing the growth temperature and lowering the C/Si ratio. Changing these growth parameters resulted in specular film morphology, however, the minority carrier lifetime shortened. The lifetime ranged from 0.5 – 4 µs depending upon growth conditions. DLTS results will be presented for samples exhibiting short carrier lifetimes.
[1] J.P. Bergman, et al. Mater. Sci. Forum Vol. 353-356, 299 (2001).
[2] R.E. Stahlbush, et al., J. Electron. Mater. 31, 370 (2002).
[3] Z. Zhang, et al., Appl. Phys. Lett. 89, 081910 (2006).
[4] J.J. Sumakeris, et al., Mater. Sci. Forum 527-529, 529 (2006).
[5] H. Tsuchida, et al., Mater. Sci. Forum 483-485, 97 (2005).
[6] W. Chen and M.A. Capano J. Appl. Phys. 98, 114907 (2005).
[7] T. Ohno, et al., J. Cryst. Growth 271, 1 (2004).
[8] R. E. Stahlbush, et al., Jr., Appl. Phys. Lett. 94, 041916 (2009).
3:30 PM - EP2.4.04
Characterise Defects, Stress and Dopants in SiC Wafers with Fast Raman Mapping
Tim Batten 1,Andrew King 2
1 Renishaw plc Wotton-Under-Edge United Kingdom,2 Renishaw Inc. Chicago United States
Show AbstractWe illustrate the effectiveness of Raman mapping as a method for characterising and quantifying the stress and free carrier concentration distribution associated with defects in SiC. These defects include polytype inclusions and micropipes, in small SiC research samples as well as in whole wafers. Here, we show 2D and 3D Raman images of wafers and defects, consisting of millions of spectra, collected in timescales that would have seemed impossible a decade ago.
SiC devices have the potential to replace Si devices for some high power, high voltage applications. Initial market areas include electric cars, electric trains and transformers in electrical grids. Over the last decade, continual improvements in material quality have enabled the realisation of working devices with suitable yields for early mass production. Additional work is still required to scale up production and improve yields to reduce the cost of devices. To meet these demands a better understanding of defect formation and prevention is required, along with improved quality control in production.
Raman spectroscopy is a non-destructive technique that provides sub-micrometre information on the vibrational, crystalline and electronic structure of materials. Raman is a tried and tested tool for analysing SiC[1], but in the past measurements have been slow, with a single spectrum taking anywhere from 10 seconds to a minute to acquire. These times have been drastically reduced to the order of milliseconds, thanks to fundamental advances in hardware and software. This vastly extends the challenges to which Rama spectroscopy can be applied. For example, a detailed Raman map of a SiC wafer, which in the past would have taken 115 days to acquire, can be completed in 2 hours[2], making Raman spectroscopy an option for industrial quality control. One of the key strengths of Raman is that by focusing the light at a range of depths it is possible to generate not only 2D, but also 3D maps. This allows discrimination between device structure layers such as the substrate and the epilayer and as a result defects and their origins can be characterised more comprehensively.
[1] Nakashima, S-I., and H. Harima, Raman investigation of SiC polytypes, physica status solidi (a), 162.1, (1997), 39-64.
[2] T. Batten and O. Milikofu, Silicon Carbide and Related Materials 2014 p.229
3:45 PM - EP2.4.05
Assessment of Factors Controlling the X-Ray Penetration Depth in Studies of 4H-SiC Using Monochromatic and White Beam Synchrotron X-Ray Topography in Reflection Geometry
Yu Yang 1,Jianqiu Guo 1,Ouloide Goue 1,Balaji Raghothamachar 1,Michael Dudley 1
1 Stony Brook Univ Stony Brook United States,
Show AbstractSynchrotron X-ray Topography has been shown to be a vital tool for the nondestructive characterization of defects in 4H-SiC crystals [1-2]. Techniques utilizing reflection geometry are particularly useful for discerning defects at different depths below the crystal surface. For example, in studying defects in SiC pin diode structures, which typically comprise a buffer layer homoepitaxially grown on a substrate, with the drift layer grown on top of the buffer layer, it is important to be able to discriminate the depth at which particular defect configurations reside. This is particularly important for the characterization of defects resulting from relaxation processes such as interfacial dislocations and half loop arrays [3]. Accurate discernment of the depth of a defect requires precise measurement of the effective penetration depth of the X-ray beam in the diffraction geometry in question. This paper provides an assessment of the factors controlling that penetration depth in grazing incidence, reflection and back reflection geometries. There are generally two approaches adopted depending of the level of perfection of the crystal. In deformed regions (such as around dislocation cores) the penetration depth is simply determined by photoelectric absorption. In perfect regions it is determined by extinction. We will present a comparison between measured penetration depths in various diffraction geometries with those calculated using these two approaches and develop an optimized model to explain our observations.
4:30 PM - *EP2.4.06
Wide Bandgap Materials for High Power and High Frequency Applications
Olof Kordina 1,Orjan Danielsson 1,Jawad ul Hassan 1,Jr-Tai Chen 1,Erik Janzen 1
1 Department of Physics, Chemistry and Biology Linköping University Linköping Sweden,
Show AbstractThe road to develop SiC into a mature power semiconductor has been long and very crocked. It was not until some very decisive innovations took place that SiC could rise and begin it real success story. These very important technological innovations are: the development of the seeded sublimation growth by Tairov and Tsvetkov enabling large, round wafers to be produced; the development of the carbonization layer for the growth of SiC on Si substrates by Nishino et al. which raised the interest in SiC; and the development of the step-flow growth process on off-axis substrates by Kuroda et al. which allowed very high quality epitaxial layers to be grown on SiC substrates at reasonably low temperatures. Since then many new innovations and development has taken place. This paper will focus on the development work done at Linköping University with emphasis on the hot-wall CVD reactor and the high temperature CVD reactor. An important application for semi insulating (SI) SiC is for the growth AlGaN/GaN structures for HEMT of high power, high frequency devices. The high thermal conductivity of the substrate and the fact that the lattice mismatch and mismatch in coefficient of thermal expansion is relatively small between particularly AlN and SiC makes it ideal for this application. High quality SI SiC substrates are therefore essential. At Linköping University very high quality AlGaN/GaN material has been developed in a hot-wall reactor which also will be presented in this paper.
5:00 PM - EP2.4.07
Reduction in Background Carrier Concentration for 4H-SiC C-Face Epitaxial Growth
Johji Nishio 2,Hirokuni Asamizu 3,Mitsuhiro Kushibe 1,Hidenori Kitai 2,Kazutoshi Kojima 2
1 Corporate Ramp;D Center, Toshiba Corp. Kawasaki Japan,2 Advanced Power Electronics Research Center National Institute of Advanced Industrial Science and Technology (AIST) Tsukuba Japan,2 Advanced Power Electronics Research Center National Institute of Advanced Industrial Science and Technology (AIST) Tsukuba Japan,3 Research and Development Headquarter ROHM Co., Ltd. Kyotp Japan2 Advanced Power Electronics Research Center National Institute of Advanced Industrial Science and Technology (AIST) Tsukuba Japan,1 Corporate Ramp;D Center, Toshiba Corp. Kawasaki Japan2 Advanced Power Electronics Research Center National Institute of Advanced Industrial Science and Technology (AIST) Tsukuba Japan
Show AbstractFor ultra-high voltage power devices with blocking voltage capability over 20 kV, the carrier concentration for the epitaxially grown drift layer is required around 3x1014 cm-3. In order to meet this requirement, the background carrier concentration for the epitaxial layer should be controlled lower than 1x1014 cm-3. In general, it is considered much easier to obtain surface smoothness for C-face than Si-face, for the growth of very thick layer, such as 250 µm, because the former is likely to be free from step bunching. However for the C-face epitaxial growth, the lowest background carrier concentration reported so far was 4.2x1014 cm-3 [1]. In the current study, the epitaxial growth parameters which affect significantly to the background carrier concentration have been examined to realize lower background carrier concentration than 1x1014 cm-3. The multiple-wafer (8 x 3-inch) horizontal hot-wall CVD epitaxial reactor [2] was employed. In adjusting each parameter to decrease the background carrier concentration, some restriction was found as surface morphology deterioration, such as appearance of triangular-defects or even frosty feature. The growth temperature was kept at 1725 oC throughout the experiment. The main factor which controls the background concentration is nitrogen donor, and its origin is assumed to be both taking air in when the wafers are loaded and degassing from the graphite furnace parts. They had been minimized to be ignored. It has been found that lowering the growth pressure from 5.8 to 1.8 kPa and increasing the growth rate from ~15 to ~30 µm/h are more effective than increasing C/Si ratio from 1.0 to 1.2, for reducing the background carrier concentration in our experimental range. The optimum parameter combination made it possible to achieve 7.6 x1013 cm-3 as the background carrier concentration within a whole area of specular 3-inch wafer.
[1] J. Nishio, C. Kudou, K. Tamura, K. Masumoto, K. Kojima and T. Ohno, Mat. Sci. Forum 778-780 (2014) 109.
[2] C. Kudou, K. Tamura, T. Aigo, W. Ito, J. Nishio, S. Ito, K. Kojima and T. Ohno, Mat. Res. Soc. Symp. Proc. Vol. 1433 (2012) H1.2.
This work was supported by Council for Science, Technology and Innovation(CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics/Consistent R&D of next-generation SiC power electronics” (funding agency: NEDO)
5:15 PM - EP2.4.08
High Growth Rate 3C-SiC Growth: From Hetero-Epitaxy to Homo-Epitaxy
Francesco La Via 1,Grazia Litrico 1,Ruggero Anzalone 1,Andrea Severino 1,Salvatore Coffa 1
1 CNR-IMM Catania Italy,2 STMicroelectronics Catania Italy,1 CNR-IMM Catania Italy
Show AbstractThe grow of thick 3C-SiC layers can be extremely interesting for the realization of power devices in the region below a breakdown voltage of 800 V where DC-DC converter and DC-AC inverter should be realized for electric vehicles or hybrid cars. Then to overcome this limitation, generally silicon power devices are used for this important application but it is necessary to use very heavy and expensive heat sinkers to reduce the device temperature (due to the high currents) because of the low band gap and low thermal conductivity of the silicon substrate. For these applications, 3C-SiC is the ideal material because it has high channel mobility with almost the same characteristics of the hexagonal polytypes. The limitation to these applications are essentially due to the poor quality of this material that is grown on the silicon substrate and presents a high density of defects starting from this interface. Several studies have been performed in the past years to try to solve this problem but it has been observed that for some defects (stacking faults) it is extremely difficult to decrease the density. In the last years it has been observed that to improve the quality and to reduce the stress it is necessary to work on the structure of the substrate (compliance substrates) in order to force the system to reduce the defects increasing the thickness of the layer. Furthermore, it has been reported that, using the typical bulk growth techniques used for 4H-SiC, it is possible to growth bulk 3C-SiC wafers, improving considerably the quality of the material. These two approaches have not succeeded until now to grow good quality material for the realization of power devices. Several problems connected to the high stress of the grown films and to the high density of stacking faults have slowed down the progress of this research. In this work high growth rate CVD processes have been used to try to reduce the stacking faults density and to obtain a large 6 inches wafer where these power devices can be realized. In a first step a high growth rate (30 μm/h) process using TCS has been used to grow 50 mm thick 3C-SiC layer on (001) Si. Then the silicon substrate was etched and a further grow was performed at higher temperature (1600 °C) and higher growth rate (90 μm/h) to obtain the final thickness of 250 μm. The obtained 3C-SiC 6 inches wafers show a good morphology, low defect density and low stress. These samples have been characterized by HRXRD rocking curve, m-Raman, TEM, AFM and SEM to determine the crystal quality, the density of defects and the surface topography. The effect of the etching process, of the growth rate and of the C/Si ratio on the growth and the defect density will be reported and discussed in this work and compared with different 3C-SiC processes and approaches.
5:30 PM - EP2.4.09
Atomic Structures of Misfit Defects at 3C-SiC/Si (001) Interface Studied by Conventional and Aberration-Corrected High-Resolution Transmission Electron Microscopes
Cai Wen 2,Wei Wan 2,Fanghua Li 2,Dong Tang 3,Jin Zou 4
1 School of Science Southwest University of Science and Technology Mianyang China,2 Institute of Physics Chinese Academy of Sciences Beijing China,2 Institute of Physics Chinese Academy of Sciences Beijing China3 FEI Company Eindhoven Netherlands4 The University of Queensland Brisbane Australia
Show AbstractThe core structures of interfacial misfit defects of a 3C-SiC film grown on the Si (001) substrate were investigated using a 200 kV conventional and a 300 kV spherical aberration (Cs) corrected high-resolution transmission electron microscope (HRTEM), respectively. Different areas of the [110] experimental HRTEM images that do not directly reflect the projected structure were transformed into the structure maps through the image deconvolution method based on the pseudo-weak phase object approximation (PWPOA). The deconvolution processing plays the role in restoring the true structure that was distorted due to the contrast transfer function modulation and enhancing the resolution of the restored structure up to the information limit of the microscope.
According to the prediction given by the PWPOA, the atoms of Si and C have been recognized straight-forwardly by analyzing the different behavior of image contrast change in the deconvoluted images for the two kinds of atoms with the increase of crystal thickness. The Si and C atomic columns in the dumbbells separated from each other as small as 0.109 nm have been resolved clearly.
Thus from the conventional HRTEM observation, four types of misfit dislocations, namely S1a and CSS type 90° Lomer dislocations, 60° dislocations (probable the shuffle set), and 90° partial dislocations associated with stacking faults are indentified as the key strain relaxation lattice defects at the interface. However, the type of perfect 60° dislocation cannot be determined from the deconvoluted image due to the insufficient microscope information limit.
Then from the Cs-corrected HRTEM observation with the microscope information limit reaching 0.08 nm, a stacking fault near the interface and four interfacial misfit dislocations have been determined at atomic level. The stacking fault has been determined to be of intrinsic type with two atomic layers, the carbon layer labeled “a” and silicon layer labeled “B”, extracted out from the perfect AaBbCc stacking sequence. The atomic configurations of the core structure for both interfacial Lomer dislocations have been displayed to be of the CSS type with the 5/7 membered ring structure, and those for the two 60° dislocations to be of the shuffle type with the terminated {111} planes end at a pair of Si and C atoms. This implies that for 3C-SiC/Si (001), the dissociation of a 60° shuffle dislocation needs a high energy so that the 60° shuffle dislocations are stable at the interface. On the contrary, it is hardly possible to find the 60° glide dislocations at the interface because they are frequently dissociated into 30° and 90° partial dislocations. This has been confirmed in Tang et al. (2007) and our work, respectively.
Symposium Organizers
Francesca Iacopi, Griffith University
Camilla Coletti, Istituto Italiano di Tecnologia
Sei-Hyung Ryu, Cree Inc.
Stephen E. Saddow, University of South Florida
Carl-Mikael Zetterling, KTH Royal Institute of Technology
EP2.5: Novel Integrated Applications
Session Chairs
Camilla Coletti
Feng Zhao
Thursday AM, March 31, 2016
PCC North, 200 Level, Room 228 A
10:00 AM - *EP2.5.01
Recent Development in 4H-SiC Microelectromechanical Devices
Feng Zhao 1,Allen Lim 1,Chih-Fang Huang 2
1 Washington State Univ Vancouver United States,2 National Tsing Hua University Hsinchu Taiwan
Show AbstractThere are applications that demand microelectromechanical systems (MEMS) to operate reliably in hostile environments. Among different materials, SiC has been identified as a desirable material of choice due to its superior electrical, mechanical, and chemical properties. These properties include the wide bandgap energy (3.2 eV in 4H-polytype), high thermal conductivity (close to copper), large Young’s modulus (500 GPa), excellent resistance to mechanical wear and almost all chemicals, and inertness to corrosive medium and radiation. This presentation reviews the development of single crystalline SiC (4H-SiC) MEMS devices including a series of actuators and resonators and characterization results of their static and dynamic properties.
10:30 AM - EP2.5.02
Residual Stress Effect on Silicon Carbide Micro-Resonators Static and Dynamic Performance
Atieh Ranjbar Kermany 3,James Bennett 2,George Brawley 2,Neeraj Mishra 1,Warwick Bowen 2,Francesca Iacopi 3
1 Queensland Micro- and Nanotechnology Centre Griffith University Nathan Australia,3 Environmental Futures Research Institute Griffith University Nathan Australia,2 School of Mathematics and Physics The University of Queensland Brisbane Australia1 Queensland Micro- and Nanotechnology Centre Griffith University Nathan Australia3 Environmental Futures Research Institute Griffith University Nathan Australia
Show AbstractCubic silicon carbide (3C-SiC) is a leading material for MEMS due to its excellent mechanical properties when Si has limitations. The tensile mean stress within the film further influences the dynamic (frequency (f) and quality factor (Q)) and static behaviour (intrinsic bending) of double-clamped (d-c) and single-clamped (s-c) microbeams respectively. We have recently shown that fxQ product of ~1012 Hz, within a factor of two of the maximum theoretical limit set by the thermoelastic dissipation, can be achieved for a d-c beam made of SiC through the application of high tensile mean stress, outperforming the highest reported fxQ products state-of-the-art in silicon nitride microstrings [1].
To better understand the dynamic performance, we analysed the parameters influencing the f and Q of epitaxial SiC d-c beams for mass sensing applications. We experimentally observe that both f and Q are affected by the residual mean stress, and the beam length. In addition, the Q is further influenced by the film quality, the string clamping condition, and clearly by the ambient pressure.
In the case of s-c beam resonator, the mean stress within the film is released because of the free end. However, the gradient stress results in the bending of the beam [2]. This intrinsic bending could be applied favourably in MEMS actuators. However, flat structures are required in applications such as atomic force microscopy, and most resonant sensors. As a result, it is important to understand, control, and engineer the intrinsic bending depending on the application.
We investigated the residual stress influence on SiC(100) s-c beam intrinsic bending by comparing the FEM analysis to the SEM micrographs of experimentally fabricated s-c beams. The SiC residual stress was input in the FEM software (IntelliSuite) by subdividing the modelled film into multiple layers, and assigning to each partial layer, its experimentally measured stress value and thickness following the layer-by-layer measured stress profile, taken from our recent work [3].
We observe from both FEM and SEM that for a 200 µm length and 50 µm width, the s-c beam has downward intrinsic bending for thicknesses bellow 80 nm, almost zero ~80 nm, and upward bending for thicknesses above 80 nm. In addition, the degree of bending is further influenced by the beam length. Consequently, we could tailor the intrinsic bending of SiC(100) s-c beam by simply selecting the appropriate thickness and length.
[1] Kermany et al.,"Microresonators with Q-factors over a million from highly stressed epitaxial silicon carbide on silicon," Appl. Phys. Lett., vol. 104, p. 081901, 2014.
[2] Drieenhuizen et al., "Comparison of techniques for measuring both compressive and tensile stress in thin films," Sens. Actuators A: Phys., vol. 37, pp. 756-765, 1993.
[3] F. Iacopi et al., "Evidence of a highly compressed nanolayer at the epitaxial silicon carbide interface with silicon," Acta Mater., vol. 61, pp. 6533-6540, 2013.
10:45 AM - EP2.5.03
Laser Irradiation Influence on Si/3C-SiC/Si Heterostructures for Subsequent 3C-SiC Membrane Elaboration
Jean-Francois Michaud 1,Rami Khazaka 2,Marc Portail 2,Gudrun Andrae 3,J. Bergmann 3,Daniel Alquier 1
1 University of Tours Tours France,1 University of Tours Tours France,2 CRHEA Valbonne France2 CRHEA Valbonne France3 Leibniz Institute of Photonic Technology Jena Germany
Show AbstractSince last decades, silicon carbide (SiC) is the subject of intensive research and development activities due to its huge electrical and physico-chemical properties. Among the different polytypes, only the cubic one (3C-SiC) can be hetero-epitaxially grown on cheap silicon substrates, which presents serious advantages for Micro-Electro-Mechanical-Systems (MEMS) applications.
The recent development of multi-stacked Si/SiC heterostructures has demonstrated the possibility to obtain a (110)-oriented 3C-SiC membrane on a 3C-SiC pseudo-substrate, using a silicon layer grown by Low Pressure Chemical Vapor Deposition as a sacrificial one. However, the (110) orientation of the 3C-SiC membrane led to a rough and facetted surface which could hamper its use for the development of new MEMS devices [1]. Then, the surface quality of the 3C-SiC membrane has been improved by means of an optimized growth process and we succeeded to obtain a (111) oriented 3C-SiC film, resulting in a smoother surface [2].
The silicon surface has a direct consequence on the surface quality of the subsequent 3C-SiC epilayer as the Si film acts as a substrate for the 3C-SiC growth. Consequently, as further in-situ improvements seem challenging, we tried to improve the quality of the Si film using pulsed irradiation by KrF excimer laser (248 nm). Consecutively to the irradiation, the samples have been characterized by X-Ray diffraction (XRD) and atomic force microscopy (AFM). XRD measurements did not demonstrated any improvement of the crystalline quality of the silicon film. However, the laser irradiation has a direct influence on the surface of the silicon epilayer as we succeeded to reduce the roughness by a factor 2. Based on this progress, we succeeded to grow 3C-SiC films on the irradiated silicon epilayer and the roughness of this subsequent 3C-SiC film is also half the one observed on non-irradiated silicon regions.
These preliminary results illustrate that the laser irradiation is a promising alternative to improve the surface morphology of SiC/Si/SiC layer stack heteroepitaxially grown on silicon substrates. Such smooth SiC structures accessible with our process could be the starting point for the achievement of new MEMS devices, for example in medical or harsh environment applications.
[1] J.F. Michaud, M. Portail, T. Chassagne, M. Zielinski and D. Alquier, Microelectron. Eng. 105, 65 (2013).
[2] R. Khazaka, E. Bahette, M. Portail, D. Alquier and J.F. Michaud, Mater. Lett. 160, 28 (2015).
11:30 AM - EP2.5.04
APTES-Modified 4H-SiC Test Device Structures for Biomedical Applications
Taeseop Lee 1,Sewoong Jung 1,Anders Hallen 2,Carl-Mikael Zetterling 2,Sang-Mo Koo 1
1 Kwangwoon Univ Seoul Korea (the Republic of),2 KTH, Royal Institute of Technology Stockholm Sweden
Show AbstractHetero structures between SiC and organosilane have a potential for applications in the field of biomedical research, due to its nontoxic, biocompatibility, chemical stability under physiological conditions, and ability for selective functionalization toward specific targets. The organosilane-functionalized SiC surface can be used as a linker layer for the attachment of biomolecules toward SiC. Recent experimental studies on surface functionalization of SiC have been focused on the formation of covalently bonded self-assembled monolayer (SAM) of organic molecules.
This work presents hetero structures between SiC and 3-aminopropyltriethoxysilane (APTES), and device performances of APTES-modified 4H-SiC lateral field effect transistors (FETs).
The starting materials are n-type 4H-SiC wafers (ND ~5×1018/cm3) with an n-type epi-layer (ND ~1×1016/cm3). A 2% volume fraction solution of APTES (98%) in toluene (99.8%) was used for 1h followed by ultrasonic bath to minimize the non-specific attachment of APTES to the SiC surface. Following the deposition of APTES, the samples were treated in ultrasonic bath for 10min in toluene and for 1min in isopropanol (99%) to remove loosely adsorbed APTES molecules. The fabricated devices were examined by using atomic force microscopy (AFM) and Fourier transform infrared spectroscopy (FTIR). Current-voltage (I-V) characteristics of the device were measured by using a Keithley 4200 semiconductor parameter analyzer.
In the case of APTES modification, the FTIR spectra present the bands around 2900 cm-1. It is ascribed to the C-H groups, indicating the presence of APTES substitution in the modified SiC.
The APTES film on the 4H-SiC surface was dense and homogeneous with the height of ~20nm from AFM results. Hence the formation of APTES was accomplished and the APTES molecules were densely covered on the 4H-SiC surface with virtually normal molecular orientation, where silane groups were firmly attached onto the SiC surface with amine functional groups serving as surface groups. The monolayer could prevent leakage currents, unspecific adsorption and the surface decomposition in aqueous electrolyte.
The drain current of lateral FETs was decreased about 3 times when the APTES was functionalized. Similar experimental studies on FET based Si biosensors have also been reported. This result is due to the linking of APTES to SiC surface resulted in a surface terminating –NH3+ and positive charge of the amine group. The result and discussion of FETs with the attaching biomolecules such as biotin or streptavidin to APTES SAM will also be presented.
This work was supported by a grant from the fundamental R&D Program for “Ultra high purity SiC material” funded by the MOTIE, Republic of Korea, by the NRF funded by the Ministry of Science, by IDEC and by a Research Grant from Kwangwoon University in 2015.
11:45 AM - EP2.5.05
Surface Functionalization of 3C SiC/Si Film via a Vapor Phase Silanization Approach for Glycan Binding
Bei Wang 2,Oren Cooper 3,Neeraj Mishra 2,Joe Tiralongo 3,Francesca Iacopi 2
1 Queensland Micro- and Nanotechnology Centre Griffith University Nathan Australia,2 Environmental Futures Research Institute Griffith University Nathan Australia,3 Institute for Glycomics Griffith University Gold Coast Australia
Show AbstractSilicon carbide (SiC) is considered as a promising substrate material for biosensing and biomedical applications over silicon (Si), due to its high degree of chemical and mechanical stability, biocompatibility, and compatibility with the current device fabrication technology on silicon [1]. The cubic phase SiC (3C SiC) can be grown epitaxially on silicon, offering numerous opportunities for bioelectronic devices and microelectromechanical and nanoelectromechanical systems (MEMS and NEMS) [2]. To make SiC practically viable for bio-applications, it is essential to create a stable inorganic/organic heterointerfaces between SiC and biomolecues with the functional organic layers uniformly and densely attached. This process is known as functionalization of SiC surface and can be realized by a few wet chemistry methods, e.g. silanization, etc. [3]. Differing from the processing routes in the literature, we here demonstrate a novel vapor phase approach to functionalize 3C SiC/Si surface for the first time. We induce hydroxyl groups on 3C SiC/Si surface via an Inductively Coupled Plasma (ICP) treatment with oxygen, and then allow these hydroxyl groups to react with the alkoxy groups of organosilane molecules through a vapor phase silanization approach at 120 °C under vacuum. The static water contact angle of the treated 3C SiC/Si surface increases significantly, indicative for the change from hydrophilic to hydrophobic layers on 3C SiC/Si after silanization. The post glycan print scans on these 3C SiC/Si slides reveal various glycan spots, demonstrating the successful binding of glycans on the functionalized 3C SiC/Si surface. These printed glycan spots are comparable to those found on the glass epoxy slides, showing comparable functional group density. This unique method for organic functionalization of 3C SiC/Si exhibits uniform and dense functional organic layers on the surface for glycan binding, and may pave the way for future fabrication of patterned functionalized SiC cantilevers on silicon for glycan microarray technology.
References
[1] S. Saddow, A. Agrawal, “Advances in Silicon Carbide Processing and Applications”, Norwood: Artech House, MA, 2004.
[2] B.V. Cunning, M. Ahmed, N. Mishra, A.R. Kermany, B. Wood, F. Iacopi, “Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers”, Nanotechnology, 25 (2014) 325301
[3] S.J. Schoell, M. Sachsenhauser, A. Oliveros, J. Howgate, M. Stutzmann, M.S. Brandt, C.L. Frewin, S.E. Saddow, I.D. Sharp, “Organic Functionalization of 3C-SiC Surfaces”, ACS Applied Materials & Interfaces, 5 (2013) 1393-1399
12:00 PM - EP2.5.06
Robust 3C-SiC Implantable Neural Interfaces for Brain Machine Interfaces
Evans Bernardin 3,Christopher Frewin 2,Abhishek Dey 1,Richard Everly 4,Joe Pancrazio 5,Stephen Saddow 1
3 Chemical and Biomedical Engineering University of South Florida Tampa United States,2 Crystal Cybernetics LLC Tampa United States1 Electrical Engineering University of South Florida Tampa United States4 University of South Florida Tampa United States5 University of Texas at Dallas Dallas United States
Show AbstractMillions of people around the world have physical disabilities which are the result of damage to the central nervous system (CNS). In addition thousands more have lost limbs due to wartime violence and have suffered damage to their peripheral nervous system (PNS). A therapeutic for these types of injuries which has shown great promise in initial demonstrations is the brain machine interface (BMI) [1]. The invasive intracortical neural interface (INI) is a BMI which has shown an increased utility as it provides a closed loop control system through bi-directional signaling between the device and specific neural populations [1]. Unfortunately, these devices have a major underlying issue preventing their increased acceptance, mainly their questionable long-term reliability, which manifests itself as anything from signal degradation to complete functional loss over time [2].
INI construction materials have been linked to the overall long-term reliability [3]. Cubic silicon carbide (3C-SiC), a chemically inert, physically robust semiconductor, has shown high levels of neural viability through extensive testing in vitro [4]. The in vivo glial and neural response of C57BL/6J mice to 3C-SiC passive implants of the same form fit as the A16 NeuroNexus Si probe was studied against a positive control of silicon (Si) [5]. After 35 days in vivo, immunohistochemistry indicated Si led to an increased inflammatory response and an overall decrease in neural presence, whereas 3C-SiC showed minimal inflammatory reaction and neuronal processes remained in contact with the implant.
We have developed 3C-SiC for use in optogenetics. Planar microelectrode arrays have been developed from 3C-SiC and the bio- and hemo-compatible insulator amorphous SiC (a-SiC) [6]. While this work is on-going, a considerable amount of progress has been made which will be reported. ‘Metal free’ neural interfaces are also being developed and will be presented. 3C-SiC shows a tremendous amount of promise to finally allow the INI to perform its intended function – long-term, reliable neural interfacing for cybernetic interfacing as well as efficient, closed-loop neural modulation for such diseases as Parkinson’s, Alzheimer’s, and amyotrophic lateral sclerosis (ALS), just to name a few.
References
[1] J. P. Donoghue, Neuron, vol. 60, pp. 511-21, Nov 6 2008.
[2] P. J. Rousche and R. A. Normann, Journal of Neuroscience Methods, vol. 82, pp. 1-15, Jul 1 1998.
[3] V. S. Polikov, P. A. Tresco, and W. M. Reichert, Journal of Neuroscience Methods, vol. 148, p. 18, 2005/08/08 2005.
[4] C. L. Frewin, et al., Journal of Molecular Recognition, vol. 22, pp. 380-8, Sep-Oct 2009.
[5] C. L. Frewin, C. Locke, L. Mariusso, E. J. Weeber, and S. E. Saddow, Neural Engineering (NER), 6th International IEEE/EMBS Conference on, pp. 661 - 664, 2013.
[6] S. E. Saddow, in Silicon Carbide Biotechnology, S. E. Saddow, Ed., 2nd ed Oxford: Elsevier, 2016, UK ISBN 978-0-12-802993-0 (in-press)
12:15 PM - EP2.5.07
Continuous Glucose Monitoring by Passive Sensing of SiC Implant
Fabiola Araujo Cespedes 1,Stephen Saddow 1,Gokhan Mumcu 1
1 University of South Florida Temple Terrace United States,
Show AbstractA platform system for continuous glucose sensing is proposed based on passive remote measurement of an implantable silicon carbide (SiC) sensor via remote external detection. The implant sensor consists of a SiC based antenna patch with the long-term objective to be implanted subcutaneously and act as a passive sensor for several years. The material of the antenna has proven to have great sensing potentiality, while also being biocompatible and hemocompatible. The external circuity consists of two external antenna, an external-to-the-body transmitting antenna (EBTx) and an external-to-the-body receiving antenna (EBRx).
The detection system is based on passive measurement as follows. The resonance frequency of the passive antenna shifts as a function of blood gluocse levels. The EBTx sends a signal towards the passive antenna, which is reflected back to the EBRx. The signal reflected back to the EBRx undergoes both an amplitude and a phase variation as a function of the glucose level.
Preliminary trials were performed using 6010 Copper Duroid as the substrate material for the antenna patch, later to be replaced with 4H-SiC silicon carbide. During the trials, a petri dish was filled with animal fetal blood albumen (FBA) combined with D-glucose. Trials were repeated varying the ratios of the D-glucose and the microwave scattering parameters measured using a vector analyzer: The insertion loss, S21, was measured between the EBTx and EBRx and both amplitude and phase shifts dependent on glucose recorded. The return loss, S11, of the passive antenna was measured to confirm a glucose-dependent shift in resonant frequency. The ultimate objective is to remotely detect glucose levels by indirect measurement of these variations. Progress to date will be presented along with numerical simulations performed using HFSS.
12:30 PM - EP2.5.08
Electrochemical Study of Graphene Thin-Film Electrodes on 3C SiC/Si for Symmetric Supercapacitors
Bei Wang 2,Mohsin Ahmed 2,Mohamad Khawaja 3,Marco Notarianni 5,Dayle Goding 1,Bharati Gupta 4,John Boeckl 6,Arash Takshi 3,Nunzio Motta 4,Stephen Saddow 3,Francesca Iacopi 2
1 Queensland Micro- and Nanotechnology Centre Griffith University Nathan Australia,2 Environmental Futures Research Institute Griffith University Nathan Australia,3 Electrical Engineering Department University of South Florida Tampa United States3 Electrical Engineering Department University of South Florida Tampa United States,4 Institute for Future Environments Queensland University of Technology Brisbane Australia,5 Plasma-Therm LLC St. Petersburg United States1 Queensland Micro- and Nanotechnology Centre Griffith University Nathan Australia4 Institute for Future Environments Queensland University of Technology Brisbane Australia6 Wright-Patterson AFB, Air Force Research Laboratory Dayton United States
Show AbstractGraphene is one of the most promising electronic materials nowadays, due to its unique chemical, physical and electronic properties in a highly ordered sp2 carbon domain [1]. Graphene thin film can be synthesized from epitaxial SiC films on silicon, offering high-quality, transfer free and large scale production of graphene, also referred as SiC-derived graphene, at a wafer level. This approach suggests an ideal platform to integrate graphene thin film with scale-down applications on silicon chips – e.g. microelectromechanical and nanoelectromechanical systems (MEMS and NEMS), and other miniaturized devices [2]. In our recent work, we demonstrated a nickel-assistant thin film approach to synthesize graphene on highly corrugated 3C SiC surface on silicon wafers, the first report for its use in on-chip supercapacitors [3]. SiC acts as both the template and the source of carbon. Specific capacitance of up to 65 F g-1 can be obtained from a 3 M KCl aqueous electrolyte and the highly accessible surface area of graphene underlying the corrugated 3C SiC film plays an important role in the ionic charge storage. However, the energy storage systems based on this SiC-derived graphene platform have not been studied intensively and the cyclic performance of the graphene sample in different electrolytes or at a higher operating voltage window (> 1 V) remains unknown. Herein, for the first time, we systematically study the electrochemical properties of these graphene-on-wafer samples in various electrolytes by means of Cyclic Voltammetry (CV), galvanostatic charge discharge tests and Electrochemical Impedance Spectroscopy (EIS) within a symmetric supercapacitor cell. The outcomes of this work will advance the knowledge on energy storage systems with graphene thin film electrodes from epitaxial SiC and benefit the design and fabrication of on-chip interdigitated supercapacitors.
References
[1] A.K. Geim, K.S. Novoselov, “The rise of graphene”, Nature Materials, 6 (2007) 183-191
[2] B.V. Cunning, M. Ahmed, N. Mishra, A.R. Kermany, B. Wood, F. Iacopi, “Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers”, Nanotechnology, 25 (2014) 325301
[3] M. Ahmed, M. Khawaja, M. Notarianni, B. Wang, D. Goding, B. Gupta, J.J. Boeckl, A. Takshi, N. Motta, S.E. Saddow, F. Iacopi, “A thin film approach for SiC–derived graphene as an on-chip electrode for supercapacitors”, Nanotechnology, 26 (2015) 434005
EP2.6: Graphene
Session Chairs
Camilla Coletti
Francesca Iacopi
Thursday PM, March 31, 2016
PCC North, 200 Level, Room 228 A
2:30 PM - *EP2.6.01
Graphene and Hybrid Graphene-Metal Plasmons for Terahertz Modulation and Detection
Michael Fuhrer 1
2 Center for Nanophysics and Advanced Materials University of Maryland College Park United States,1 Monash Centre for Atomically Thin Materials Monash University Monash 3800 Australia,
Show AbstractGraphene ribbons support two-dimensional (2D) dispersive plasmons whose frequency can be tuned in the THz range through the ribbon width and carrier density. I will discuss a scheme for THz detection in which THz light is resonantly absorbed by plasmons in graphene strips, creating hot electrons which relax slowly due to the weak electron-phonon coupling in graphene. Metal contacts to graphene of two different types are used to create an asymmetry, and the photoexcited hot electrons diffuse primarily to one contact resulting in a photovoltage or photocurrent. This hot electron photothermoelectric effect in graphene provides a highly efficient detection mechanism at room temperature[1] with sensitivity >700 V/W and noise equivalent power of <20 pW/Hz1/2, competitive with the best commercial room temperature THz detectors. However our device is ~7 orders of magnitude faster, with characteristic timescales <100 ps[1,2].
To enhance the detector efficiency we have exploited the plasmon resonance in graphene. Large area single-layer epitaxial graphene on (0001) semi-insulating (resistivity > 1 x 109 Ohm-cm) SiC is used as a starting material. We use patterned arrays of graphene ribbons tilted at an angle to bimetallic contact arrays to create a plasmonically enhanced photodetector whose response is maximized at the gate-tunable plasmon resonance[3]. We have also identified a new hybrid metal-graphene plasmon resonance in which the graphene plays the role of a tunable inductor[4]. In these metal-graphene plasmonic arrays the resonant absorption can be tuned to near the thin-film limit of 50%, or in high-mobility graphene a resonant transmission near 100% can be achieved, realizing a large tunable absorbtion for frequency-selective detectors, or a gate-controlled THz modulator.
[1] X. Cai, et al., Nature Nanotechnology 9, 814 (2014).
[2] M.-H. Kim, et al., Physical Review Letters, 110, 247402 (2013).
[3] X. Cai, et al., Nano Letters 15, 4295 (2015).
[4] M.M. Jadidi, et al., Nano Letters 15, 7099 (2015).
3:00 PM - *EP2.6.02
Recent Progress in the Epitaxial Graphene Formation on 3C-SiC/Si Substrates
Maki Suemitsu 1
1 RIEC Tohoku Univ Sendai Japan,
Show AbstractBy graphitizing the top few layers of 3C-SiC thin films heteroepitaxially grown on Si substrates, epitaxial graphene (EG) can be formed on Si wafers. Besides its good compatibility with the Si planar technology, this technology provides a way to control the interfacial (graphene/SiC) and the stacking (Bernal/non-Bernal) structures of EG by simply tuning the crystallographic orientation of the Si substrate. The electronic structures (metallic/semiconducting) of the graphene can be tuned as well. History of the EG formation on SiC/Si will be reviewed, which includes gas-source MBE growth of 3C-SiC on Si, surface chemical analyses of graphene, and state-of-the-art technologies to improve the quality of EG. Recent observation on the charge states at the EG/SiC interface will also be addressed.
3:30 PM - EP2.6.03
Correlation between Morphology and Transport Properties of Quasi-Free-Standing Monolayer Graphene
Yuya Murata 1,Torge Mashoff 2,Makoto Takamura 3,Shinichi Tanabe 3,Hiroki Hibino 3,Fabio Beltram 2,Stefan Heun 1
1 NEST, Istituto Nanoscienze-CNR and Scuola Normale Superiore Pisa Italy,2 Center for Nanotechnology Innovation @ NEST, Istituto Italiano di Tecnologia Pisa Italy3 NTT Basic Research Laboratories, NTT Corporation Atugi Japan1 NEST, Istituto Nanoscienze-CNR and Scuola Normale Superiore Pisa Italy,2 Center for Nanotechnology Innovation @ NEST, Istituto Italiano di Tecnologia Pisa Italy
Show AbstractQuasi-free-standing monolayer graphene (QFMLG), obtained by intercalating hydrogen at the interface of buffer layer and SiC(0001), is efficiently decoupled from the substrate and a promising material for wafer-scale graphene-based nanoelectronics.1-3 However, the mobility of QFMLG (~3000 cm2V-1s-1) is limited to a value lower than exfoliated graphene on SiO2, and the carrier scattering has not been fully understood. Recently it has been reported that the mobility of QFMLG depends on the substrate temperature during the hydrogen intercalation process, and the highest mobility is obtained at 700-800°C.4 These measurements suggested that the carrier scattering is mainly caused by charged impurities at 600 and 800°C, and at 950°C defects cause additional scattering. We have used scanning tunneling microscopy (STM) to study the surface structure of QFMLG formed at several hydrogen intercalation temperatures, and investigated the relationship with transport measurements.5
Our STM observations reveal that the QFMLG formed at 600°C and 800°C shows small dark spots with a diameter of 1.5 nm, depth of 15-25 pm, and density of 1×1013 cm-2, while samples formed at 1000°C show large dark spots with diameter 4-10 nm, depth 250 pm, and density 6×1010 cm-2. The dark spots at 600°C and 800°C partially align with a periodicity of 1.8 nm, corresponding to the quasi-(6x6) reconstruction of the buffer layer. This implies that hydrogen intercalation in our samples is not complete at 600°C and 800°C, and the remaining patches of Si dangling bonds are observed as dark spots. Since the depth of the dark spot at 1000°C corresponds to the height of a SiC(0001) bilayer, they are identified as holes in the SiC substrate, probably due to etching by hydrogen at high temperature. This is consistent with transport measurements and suggests that the incomplete hydrogen intercalation at 600 and 800°C scatters carriers as charged impurities, while the holes in the SiC substrate at 1000°C act as defects.
We conclude that a higher mobility of QFMLG can be obtained by optimizing the conditions for H intercalation while staying below the temperature at which holes appear in SiC substrate.
In the presentation, we will also discuss our recent resluts on the Si dangling bonds obtained in low temperature STM.
References
1) C. Riedl, C. Coletti, T. Iwasaki, A. A. Zakharov, and U. Starke, Phys. Rev. Lett. 103, 246804 (2009).
2) F. Speck, J. Jobst, F. Fromm, M. Ostler, D. Waldmann, M. Hundhausen, H. B. Weber, and Th. Seyller, Appl. Phys. Lett. 99, 122106 (2011).
3) S. Goler, C. Coletti, V. Piazza, P. Pingue, F. Colangelo, V. Pellegrini, K. V. Emtsev, S. Forti, U. Starke, F. Beltram, and S. Heun, Carbon 51, 249 (2013).
4) S. Tanabe, M. Takamura, Y. Harada, H. Kageshima, and H. Hibino, Jpn. J. Appl. Phys. 53, 04EN01 (2014).
5) Y. Murata, T. Mashoff, M. Takamura, S. Tanabe, H. Hibino, F. Beltram, and S. Heun, Appl. Phys. Lett. 105, 221604 (2014).
3:45 PM - EP2.6.04
Multi-Layer Graphene on SiC(000-1): Thermal Decomposition versus Chemical Vapor Deposition
Domenica Convertino 1,Ameer Al-Temimy 1,Antonio Rossi 1,Vaidotas Miseikis 1,Camilla Coletti 1
1 Center for Nanotechnology Innovation @ NEST, Istituto Italiano di Tecnologia Pisa Italy,
Show AbstractEpitaxial growth of graphene by thermal decomposition of silicon carbide (SiC) is a classical approach to obtain large-area continuous films directly on a semi-insulating substrate [1][2]. Notably, the two different basal planes of the hexagonal SiC polytypes, i.e, SiC(0001) (Si-face) and SiC (000-1) (C-face), show significantly different growth modes for graphene. In particular, the graphene layers obtained on the C-face lack a defined azimuthal orientation (i.e., turbostratic graphene) so that each layer behaves as an isolated graphene layer and is electronically decoupled from the neighboring ones. For this reason, on this type of graphene, remarkable carrier mobilties have been measured [3]. A drawback of the growth via thermal decomposition of SiC(000-1) is that the number of layers grown can be hardly controlled. Recently, we have achieved the growth of few to many layers graphene on the C-face of SiC via a classical chemical vapor deposition (CVD) approach that makes possible a much finer control on the number of grown layers [4].
This work aims at comparing the structural, chemical and electronic properties of graphene grown on the C-face of SiC in a resistively heated cold-wall reactor by using the two different growth approaches: i.e., thermal decomposition and chemical vapor deposition. Specifically, CVD growth was carried out with methane as carbon precursor as described in [4] and thermal decomposition with the parameter set reported in [5]. Investigation of the structural, chemical and electronic properties was performed by using atomic force microscopy (AFM), Raman spectroscopy, scanning electron microscopy (SEM), low energy electron diffraction (LEED), and Hall effect measurements. The number of graphene layers obtained was determined from time to time via attenuation of the SiC signal in the Raman spectra [6] and by the absorption in the infrared region by using Fourier transform infrared (FTIR) spectroscopy [4].
The possibility to grow with a rapid and tailored CVD process a high number of graphene layers (up to 90) with good crystallinity is extremely interesting for a number of electronic and optoelectronic applications. In particular, such turbostratic graphene has been shown to represent a favorable platform for obtaining high performance THz saturable absorbers, which would pave the way to novel graphene-based mode-locked THz lasers [5].
[1] P.N. First et al., MRS Bull. 35 296–305 (2011).
[2] U. Starke et al., MRS Bull. 37 1177–86 (2012).
[3] C. Berger et al., Science 312 (5777), 1191-1196 (2006).
[4] F. Bianco et al., Optics Express 23 (9), 11632-11640 (2015).
[5] A. Candini et al., Beilstein J. Nanotechnol. 6, 711-719 (2015).
[6] S. Shivaraman et al., J.Electron. Mater. 38 (6), 725-730 (2009).
4:30 PM - EP2.6.05
Establishing the Growth Law of Graphene on SiC as a Function of Annealing Temperature
Bharati Gupta 1,Francesca Zarotti 4,Francesca Iacopi 3,Anna Sgarlata 4,Massimo Tomellini 2,Nunzio Motta 1
1 CPME School and IFE Queensland University of Technology Brisbane Australia,4 Dipartimento di Fisica Università di Roma Tor Vergata Rome Italy3 Queensland Micro and Nanotechnology Centre Griffith University Nathan Australia2 Dipartimento di Scienze e Tecnologie Chimiche Università di Roma Tor Vergata Rome Italy
Show AbstractBy using X-ray Photoelectron Spectroscopy (XPS) and Scanning Tunneling Microscopy we have been able to follow the time evolution of graphene layers obtained by annealing 3C SiC(111)/Si(111) crystals at different temperatures. Analysis of atomic resolution images and of the carbon signal provides a clear picture of the graphene formation. We have been able to visualise the first steps of graphene formation on the surface of SiC and to follow the evolution of the graphene thickness as a function of the annealing time, determining a power growth law with exponent 0.5. We show that a kinetic model, based on a bottom-up growth mechanism, provides a full explanation to the evolution of the graphene thickness as a function of time, allowing to calculate the effective activation energy of the process and the energy barriers, in excellent agreement with previous theoretical results. Our study provides a complete and exhaustive picture of Si out-diffusion from SiC, establishing the conditions for a perfect control of the graphene growth by Si sublimation.
4:45 PM - EP2.6.06
Structural and Electronic Properties of Li Intercalated Graphene on 4H-SiC(0001): Experiment and Theory
Leif Johansson 1,Nuala Caffrey 1,Chao Xia 1,Rickard Armiento 1,Igor Abrikosov 1,Chariya Jacobi 1
1 Dep of Physics, Chemistry and Biology Linkoping University Linkoping Sweden,
Show AbstractGraphene grown via the thermal decomposition of silicon carbide is a promising route to obtain homogeneous large area graphene sheets directly on a semi-conducting substrate. A disadvantage of the method is that, when grown on Si-terminated SiC(0001), the first carbon layer is covalently bonded to the surface and does not display the electronic properties characteristic of graphene. It can, however, be effectively decoupled from the substrate by the intercalation of, for example, alkali metal atoms.
We have carried out detailed ARPES (Angle Resolved Photoelectron Spectroscopy) studies of the band structure of monolayer graphene samples, before and after Li deposition at room temperature as well as after subsequent heating to 300°C. Directly after Li deposition we observe a change from the 6√3x6√3-R30° reconstruction associated with the carbon buffer layer to a √3x√3-R30° reconstruction, together with the appearance of a second π-band. The √3x√3-R30° pattern would indicate that Li atoms either occupy 1/3 of the π-bonds on the graphene surface or are adsorbed in the hollow sites between the graphene layers. Upon heating to 300°C, this √3x√3-R30° pattern fades away and the electronic band structure changes again significantly. The π-bands become significantly sharper and have a distinctly different dispersion. The position of the Dirac point is also shifted closer to the Fermi energy from approximately 1.4 eV to 0.6 eV.
To understand these observations, we performed density functional theory band structure calculations for Li intercalation in free-standing bilayer graphene for different stacking of the layers and for different LiCx configurations, where x is 4, 12, 16 and 64, as well as for Li-intercalated graphene on the SiC(0001) surface.
Our combined experimental and theoretical results show that, after Li deposition and subsequent heating, Li both intercalates underneath the buffer layer - decoupling it from the substrate - and between the two carbon layers. In the process, it becomes energetically more favorable for the carbon layers to become AA-stacked rather than Bernal stacked. We show that the π-bands around the K-point closely resemble the calculated band structure of a LiC12 system, where the symmetry dictates the observed band structure.
5:00 PM - EP2.6.07
Non-Contact Characterization of Epitaxial Graphene Using a Microwave Cavity
Jan Obrzut 1,Caglar Emiroglu 2,Oleg Kirillov 1,Yanfei Yang 2,Randolph Elmquist 1
1 NIST Gaithersburg United States,1 NIST Gaithersburg United States,2 Department of Physics Georgetown University Washington United States
Show AbstractSurface resistance of monolayer graphene on SiC is investigated in a microwave cavity. Mono-layer graphene is epitaxially formed on high purity 330 µm-thick 4H-SiC(0001) wafers by annealing the substrates at 1900°C in argon at 101-105 kPa using a controlled, repeatable Si sublimation process. Non-gated quantum Hall resistance measurements are performed at temperatures from 1.5 K to 30 K with magnetic flux density up to ± 9 T. The sequence of quantized transverse resistance at the Landau filling factors ν = ±6 and ±2, and the absence of the Hall plateau at ν = 4 indicate mono-layer graphene. In particular, a well-resolved quantized Hall resistance plateau of 12.906 kΩ at ν = ±2 with vanishing longitudinal resistivity proves that the growth process stops at one monolayer of high quality graphene. In a parallel experiment, non-contact measurements of the surface resistance are carried out in a microwave cavity on monolayer specimen annealed under the same conditions. That cavity is made of an air-filled standard WR-90 rectangular waveguide operating at the TE103 mode of 7.435 GHz. Based on the cavity perturbation method, the non-contact measurement involves monitoring the variation in the quality factor of the cavity as the specimen is progressively inserted into the cavity in a quantitative correlation with the specimen surface area. The resonant microwave cavity measurement is sensitive to the surface and bulk conductivity, and since no additional processing is required, it preserves the integrity of the conductive graphene layer. It allows characterization with high speed, precision and efficiency, compared to transport measurements where sample contacts must be defined and applied in multiple processing steps.