Symposium Organizers
Jeffery Bielefeld, Intel Corporation
Mikhail Baklanov, North China University of Technology (NCUT)
Vincent Jousseaume, CEA-LETI
Eiichi Kondoh, University of Yamanashi
Symposium Support
Air Liquide
Applied Materials
CEA-LETI
ED9.1: Low-K Materials I
Session Chairs
Mikhail Baklanov
Jeffery Bielefeld
Tuesday PM, April 18, 2017
PCC North, 100 Level, Room 128 B
11:30 AM - *ED9.1.01
Boron-Based Solids for Advanced Interconnect Applications
Michelle Paquette 1
1 , University of Missouri–Kansas City, Kansas City, Missouri, United States
Show AbstractAggressive scaling trends in integrated circuit manufacturing call for novel materials to meet projected performance requirements. Sought after materials for the back end of the line include low-dielectric-constant (low-k) dielectrics, etch stops, diffusion barriers, hardmasks, spacers, and other patterning-assist layers. For decades, the semiconductor industry has relied overwhelmingly on silicon-based materials to fill these needs, but it is becoming increasingly difficult to develop variants that simultaneously meet all of the required metrics. Boron-based solids have long been known for their robust mechanical, chemical, and thermal properties. These, combined with a very low dielectric constant, tunable optical and electrical properties, and flexible deposition procedures, make boron-based solids a compelling addition or alternative to silicon-based solids for a range of interconnect applications. This talk will cover potential uses of boron-based solids, including BN, BC, and BCN, for interconnect applications, through a comparison of their properties relative to Si-based solids and other state-of-the-art interconnect materials, while touching on deposition methods and precursors, tunability of properties, stability, etch chemistry, and future research directions.
12:00 PM - *ED9.1.02
Material Innovations for Future BEOL Interconnects
E. Ryan 1 , Nicholas Licausi 1 , Benjamin Briggs 2 , Xunyuan Zhang 1 , Xuan Lin 1 , James Kelly 2 , Lars Liebmann 1 , Son Nguyen 2
1 , GLOBALFOUNDRIES, Albany, New York, United States, 2 , IBM, Clifton Park, New York, United States
Show AbstractScaling integrated circuit technology deeper into the nanoscale regime has provided improved performance with smaller die size. However, the shrinking back-end-of-line (BEOL) interconnects are increasingly limiting overall product performance due the resistance-capacitance (RC) delay, which is dominated by R increasing exponentially with interconnect wire size. Managing the BEOL RC while maintaining yield and reliability has required material innovations (lower-k materials, improved metallization, etc.) and structural and integration adjustments (asymmetric line/space, self-aligned vias, etc.). The latter drive additional material innovations.
We present here an overview of how BEOL RC scaling has been managed through structural/architectural integration advances and the limitations of these approaches as interconnects scale to <36nm pitch. How the optimization of integration drives the need for material innovations will be the focus of the presentation. For example, the exponentially increasing R with line width requires maximizing Cu area. This can be accomplished by thinning the liner/barrier (which has been difficult to do while maintaining good reliability), by making wider lines with smaller space between lines, and making higher aspect ratio lines. However, these approaches have tradeoffs to manage, which drive additional material innovation. For example, tall lines are harder to fill with metal creating yield and reliability problems driving the need for improved metallization. And making asymmetric line/space interconnects to reduce R results in higher C and increases TDDB failure risk, which drives the need for more robust dielectric materials at lower k or reliable air gaps. The need for more robust materials to withstand TDDB is also driven by lithographic patterning, especially multipatterning, due to inadequate overlay scaling and increasing variation. Alternative integration schemes can mitigate the effects of lithographic variations, but these require additional material innovations. Eventually, non-Cu metals may outperform Cu, but these present additional integration needs, which will be reviewed.
This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.
12:30 PM - ED9.1.03
Metal-Organic Frameworks as Gap Filling Low-K Dielectric Material in Advanced Interconnects
Mikhail Krishtab 1 2 , Ivo Stassen 3 , Rob Ameloot 3 , Geoffrey Pourtois 1 , Silvia Armini 1 , Stefan de Gendt 1 2
1 , imec, Leuven Belgium, 2 Department of Chemistry, KU Leuven, Leuven Belgium, 3 Centre for Surface Chemistry and Catalysis, KU Leuven, Leuven Belgium
Show AbstractOne of the key roadblocks on the way towards continuous downscaling of k-value in traditionally used organosilica-based low-k dielectrics are the remarkable degradation of mechanical stability upon increasing porosity and the integration induced damage. The latter issue can be alleviated by switching to the alternative integration schemes based on formation of metal wires first such as patterning of sacrificial dielectric or direct metal etch. Meanwhile the challenge of filling of the high-aspect ratio inter-metal gaps with mechanically robust dielectric material persists. Metal-organic frameworks (MOFs) were suggested as possible candidates for replacement of porous organosilicas due to appealing combination of large intrinsic porosity and crystallinity of the framework [1]. However the incorporation of metal-organic framework compounds into the structure of interconnects remains barely explored. Our work focuses on the growth of hydrophobic isostructural frameworks ZIF-8 (Zn2+) and ZIF-67 (Co2+) into metal-first 90 nm pitch test vehicles using a solvent-free approach. The approach consists in conversion of thin films or particles of ZnO or CoOx formed on top of the copper metal pattern to the appropriate frameworks by exposing them to 2-methylimidazole precursor at elevated temperatures (T = 90-120oC). We examined the conversion process on both blanket and patterned substrates as a function of conversion process parameters (time, temperature, pressure) and as a function of the material passivating the copper lines. We found that the key parameter defining the morphology of the growing polycrystalline MOF layer is the amount of water generated as a by-product of the conversion reaction and retained on the sample surface. The excessive content of the adsorbed water results in uncontrollable oxidation of the underlying metal surface and in high mobility of the intermediate metal-organic phase from which the MOF crystallization starts. The effect is more evident in the case of Co-based ZIF-67 framework. The electrical properties of ZIF-8 and ZIF-67 frameworks such as effective k-value, leakage current and breakdown voltage were measured on the patterned test structures. The experimental study was complemented by ab-initio calculation of dielectric constant and its contributions for the MOFs of interest. The electronic and ionic terms of dielectric constant estimated for ZIF-8 framework are equal to 1.81 and 0.60, respectively, and agree well with the previously reported experimental values [2]. The analogous calculation for Co-based ZIF-67 gives 2.13 and 0.45. The larger value of the electronic term in ZIF-67 is attributed to the increased electronic polarizability of the framework due to high-spin state Co2+ ions in its nodes.
[1] K. Zagorodniy, G. Seifert, and H. Hermann, Appl. Phys. Lett., vol. 97, no. 25, p. 251905, 2010.
[2] S. Eslava et al., Chem. Mater., vol. 25, no. 1, pp. 27–33, 2013.
12:45 PM - ED9.1.04
Silica Aerogel Low-K Films towards Inter Layer Dielectric (ILD)
Ashok Mahajan 1
1 Department of Electronics, North Maharashtra University, Jalgaon India
Show AbstractNow a days, highly porous silica aerogel is a promising material towards porous low-k material for advanced nanoelectronics to reduce the interconnect delay, crosstalk noise and power consumption in ULSI circuits. This paper investigates synthesis and characterization of silica aerogel thin films by using sol-gel method. Coating solution was prepared using tetraethyl orthosilicate as a source of Si with solvent ethanol, DI water and HF (0.01M) as acid catalyst to boost the reaction rate and to incorporate the low polar bonds in film matrix in the proportion of 1:4:2:0.4, respectively. Aerogel films were obtained by aging in solvent to replace the pore material followed by liquid CO2 supercritical drying. The thickness and refractive index of the deposited films were measured by using elipsometry and is observed to be 195nm and 1.13, respectively. Deposition of SiO2 in film matrix and incorporation of polar bonds is validated from the FTIR and EDAX spectra. The nanoporous structure of low-k films was confirmed by using FE-SEM and observed pore diameter is in the range of 4.91nm to 14.94nm. Surface properties were evaluated using AFM. Further, Metal Insulator Semiconductor (MIS) structure is formed by depositing Aluminium metal as the top electrode through shadow mask. The dielectric constant is determined from C-V curve and is observed to be 1.8. These deposited silica aerogel films can have application as inter layer dielectric material.
ED9.2: Memory Applications
Session Chairs
Vincent Jousseaume
John Zhang
Tuesday PM, April 18, 2017
PCC North, 100 Level, Room 128 B
2:30 PM - *ED9.2.01
The N3XT 1,000× of Computing Energy Efficiency
H.-S. Philip Wong 1
1 Department of Electrical Engineering and Stanford SystemX Alliance, Stanford University, Stanford, California, United States
Show Abstract21st century information technology (IT) must process, understand, classify, and organize vast amount of data in real-time. 21st century applications will be dominated by memory-centric computing operating on Tbytes of active data with little data locality. At the same time, massively redundant sensor arrays sampling the world around us will give humans the perception of additional “senses” blurring the boundary between biological, physical, and cyber worlds. Abundant-data processing, which comprises real-time big-data analytics and the processing of perceptual data in wearable devices, clearly demands computation efficiency well beyond what can be achieved through business as usual.
The key elements of a scalable, fast, and energy-efficient computation platform that may provide another 1,000× in computing performance (energy-execution time product) for future computing workloads are: massive on-chip memory co-located with highly energy-efficient computation, enabled by monolithic 3D integration using ultra-dense and fine-grained massive connectivity. There will be multiple layers of analog and digital memories interleaved with computing logic, sensors, and application-specific devices. We call this technology platform N3XT – Nanoengineered Computing Systems Technology. N3XT will support computing architectures that embrace sparsity, stochasticity, and device variability, including those that are neuromorphic and learning-based.
In this talk, I will give an overview of nanoscale memory and logic technologies for implementing N3XT. I will give examples of nanosystems that have been built using these technologies, including the use of carbon nanotubes, new non-volatile memories, and two-dimensional layered materials such as graphene for interconnects, and provide projections on their eventual performance.
Acknowledgments: This work is supported in part by STARnet SONIC, NSF, and the Stanford SystemX Alliance.
References:
[1] M. Aly, “Energy-Efficient Abundant-Data Computing: The N3XT 1,000X,” IEEE Computer, pp. 24 – 33, December 2015.
[2] H.-S. P. Wong and S. Salahuddin, “Memory Leads the Way to Better Computing,” invited paper, Nature Nanotechnology, Vol. 10, pp. 191 – 194 (2015)
3:00 PM - ED9.2.02
Mechanism for Bipolar Resistive Switching in Annealed GO Thin Films
Pooja Saini 1 , Manjari Singh 2 , S. Singh 2 , Ajit Mahapatro 1
1 , University of Delhi, Delhi India, 2 , National Physical Laboratory, Delhi India
Show AbstractCarbon nanomaterials have been extensively studied from last few decades due to their exceptional and numerous applications. Graphene oxide consists of large number of oxygen containing group’s hydroxyl, epoxide and carboxyl attached to the basal plane and at the edges. These functional groups make GO hydrophilic in nature which can be easily dispersed in water and other organic solvents. Therefore it’s easy to make its thin film for future electronic devices.
This work explains the bipolar resistive switching with a switching ratio of the order of ~ (6 ±4) x103 at threshold voltage 3.5± 0.5V and -1.4± 0.5V during +ve and –ve bias cycles, respectively, in annealed GO thin films devices, prepared by spin coating the GO on metal substrateM1= (ITO, Al, Au) followed by annealing at 100oC, 200oC, 300o and 400oC. The GO/M1 thin films have been characterized using the advanced imaging and spectroscopic tools, including XRD, Raman, FESEM and FTIR. The device is fabricated by depositing the top metal electrode M2= (Al, Au) by thermal deposition technique through shadow masking. Current-voltage (I-V) characteristics of resulting devices M2/GO(T)/M1 were measured by sweeping the DC voltage in a cycle 0 → + V → - 0 → - V → 0. The appropriate mechanism of fillamentary model describes the BRS process, and is understood by analyzing the results of electronic transport measurements recorded through I-V characteristics in M2/GO/M1 structures, examining the chemical structures and presence of functional groups in the GO thin films using FTIR and XRD, and locating the material contents in the GO thin films using the XPS spectroscopy. The currently demonstrated annealed GO thin film based bipolar resistive switching behaviour can be used as future non-volatile memory application.
3:15 PM - ED9.2.03
Reduction of Interface Trap in Poly-Si Channel for 3D NAND Device through Dielectric Recovery Process
Dong Uk Lee 1 , Sangwoo Pak 3 , Daemyoung Lee 1 , Yihun Kim 1 , Haechang Yang 1 , Sanghoo Hong 1 , Seungjun Lee 2 , Eun Kyu Kim 3
1 NAND Product Engineering Group, SKhynix Inc., Icheon Korea (the Republic of), 3 Department of Physics, Hanyang University, Seoul Korea (the Republic of), 2 Process and Technology Group, SKhynix Inc., Seoul Korea (the Republic of)
Show AbstractA three dimensional (3D) NAND device is the most important electrical device because it is able to overcome the scale limitation of conventional electric devices and meet the operating performance of the information storage such as the solid-state drive for application of the big data analysis with the artificial intelligence. The 3D NAND device consists of the charge trap layer and the poly-Si channel into the vertical and cylindrical string structure for improve the density of memory device. However, the channel poly Si layer around dielectric layer of string structure in the 3D NAND device has a lot of grain boundary which are able to affect the conductance variation of poly-Si channel and increase the interface trap between the tunneling oxide and poly-Si. Especially, the interface and bulk trap can degrade the oxide layer after an applied erase/write (E/W) cycling process. The retention properties of the 3D NAND device depend on the oxide degradation by the interface trap, the bulk trap, and the trap assisted tunneling. The time to failure model has a strong relationship with the device degradation which is related with the tunneling oxide degradation by Folwer-Nordheim tunneling during E/W process. In this study, we investigated the interface trap behavior between the barrier engineered tunneling oxide and poly-Si channel layer after applied E/W cycling by using the deep level transient spectroscopy (DLTS). A defect state of Ec-0.51 eV was measured after deposition process for tunneling oxide on the poly-Si channel. After thermal annealing process in order to improve channel conductance, the three hole trap states with the activation energies and capture-cross sections(σ) of Ev+0.28 eV (σ=2.94x10-21 cm-2), Ev+0.53 eV (σ=9.03x10-13 cm-2), and Ev+1.0 eV appeared. These defects could be affecting the charge loss behavior of electron localized into the charge trap layer at retention mode of the 3D NAND device. When E/W cycling pulse bias applied at ±10 V for 100 ms at 25oC and 85oC, respectively, the electron traps of Ec-0.03 eV, Ec-0.15 eV, and Ec-0.44 appeared. Also, the dielectric recovery effect during applied the E/W delay pulse at 85oC related with the Arrhenius relation could be decreasing the density of the interface trap. We will discuss the defect states depending on the E/W cycling condition with dielectric recovery effect and the reliability modeling for understanding charge loss mechanism of the 3D NAND device.
ED9.3: Advanced Integration
Session Chairs
Tuesday PM, April 18, 2017
PCC North, 100 Level, Room 128 B
4:00 PM - *ED9.3.01
Selective Surface Modification for ALD and SAM Deposition
Yves Chabal 1 , David Michalak 2 , Rami Hourani 2 , Joseph Klesko 1
1 , University of Texas at Dallas, Richardson, Texas, United States, 2 , Intel Corporation, Hillsboro, Oregon, United States
Show AbstractCleaning and chemical modification of surfaces represent the key initial steps for selective deposition. Control of surface chemistry using in situ characterization makes it possible to develop selective ALD and SAM deposition. In this talk, we illustrate this approach for deposition on both dielectrics and metals, combining spectroscopic techniques (Infrared absorption, X-ray photoemission, Low energy ion scattering), imaging (atomic force microscopy) and contact angle measurements with first principles calculations.
The first example addresses the potential selective deposition on two dielectrics surfaces, Si3N4 and SiO2. Both surfaces can be cleaned in dilute HF solutions with different resulting surface composition. While partially etched SiO2 surfaces are terminated with hydroxyl groups (hydrophilic), the chemical nature of HF-etched Si3N4 surfaces is much more complex and sensitive to processing steps. We find that immediate rinsing in deionized water after HF etching yields smooth silicon nitride surfaces with clear evidence for Si-F surface termination. LEIS experiments and XPS measurement as a function of gentle sputtering with Gas cluster ion beams confirm that the F is all located at the surface and in the form of Si-F (estimated at 70% monolayer). Hydrolysis in water is very slow at room temperature, but can be achieved at high temperature (~90 % removal at 70 oC for 30 min). In addition to F, we find that there is also surface -NH2 species, as evidenced by IR active -NH2 bending modes at 1550 cm-1, which we estimate to be only ~17 % monolayer from analysis of reaction with aldehyde molecules. However, this coverage appears sufficient to protect the Si3N4 surface. Finally, LEIS and XPS indicate that there is oxygen at the surface, which could either be in the form of -OH or Si-O-Si. Contact angle measurements confirm that the surfaces are hydrophilic, pointing to some -OH termination and functionalization with alkylsiloxanes reveals that ~37 % of the surface contains Si-OH. In summary, the sum of the concentrations (70 %, 17 %, 37 % in ML), i.e. exceeding 1 ML, suggests that the etched surface is atomically rough. Overall, these findings provide a method for selective deposition by using first aldehyde reaction for Si3N4 functionalization, followed by silane reaction for SiO2 functionalization.
On metal surfaces, precleaning and surface stabilization is particularly important because the deposition environment is not ultra-high vacuum. Both wet chemical and gas phase treatments are possible and lead to surfaces with little oxidation, stabilized by adsorbates (atoms or molecules). We show how in situ IR spectroscopy provides information that makes it possible to control the chemical composition of the surfaces and the initial nucleation process during ALD. In general, selectivity can be achieved between metal and dielectric surfaces by lowering the temperature, thereby preventing nucleation on dielectrics but not on metal surfaces.
4:30 PM - *ED9.3.02
New Material and Integration Innovations to Enable Advanced Interconnect Scaling
Larry Zhao 1 , Artur Kolics 1 , Kristof Croes 2 , Zsolt Tokei 2
1 , Lam Research, Tualatin, Oregon, United States, 2 , imec, Leuven Belgium
Show AbstractCobalt is one of the alternative metals under investigation to replace Copper as interconnect wiring material. Cu interconnects require a metal barrier such as PVD Ta-based film to prevent Cu diffusion into the dielectric surrounding the Cu wires. The presence of this highly resistive metal barrier imposes a fundamental limitation for Cu interconnect scaling. As interconnect dimensions become smaller, the relative cross section area of Copper with respect to the total metal cross section area also becomes smaller. As a result, the line resistance of Cu interconnects could be higher than that of an alternative metal interconnects even if the alternative material has a higher resistivity than Cu as long as no barrier is required for the alternative metal. To study the feasibility of barrierless metal interconnects, a novel test structure was used to study Co diffusion into dielectrics by measuring C-V, I-V, and time dependent dielectric breakdown. It has been found that some carbon doped oxide low-k films exhibit excellent resistance to Co diffusion under both thermal stressing and electrical field. In addition to new materials, innovations in integration schemes are also required to continue interconnect scaling. One such innovation is the so-called Co via prefill scheme where selective bottom-up ELD Co process is used to fill the via, followed by conventional damascene metallization scheme to fill the trench. Key benefits and challenges of this via prefill integration scheme will be also discussed in this paper.
5:00 PM - ED9.3.03
Low Damage ULK Etching by Means of High Boiling Point Organic Condensation
Romain Chanson 1 , Nicolas Holtzer 2 , Philippe Lefaucheux 2 , Remi Dussart 2 , Peng Shen 3 , Keiichiro Urabe 3 , Kaoru Maekawa 6 , Koichi Yatsuda 4 , Shigeru Tahara 5 , Jean-Francois de Marneffe 1
1 , imec, Leuven Belgium, 2 , GREMI/University of Orleans, Orleans France, 3 , Air Liquide Laboratories, Tsukuba Japan, 6 , TEL Technology Center America, Albany, New York, United States, 4 , Tokyo Electron Limited, Minato-ku Japan, 5 , Tokyo Electron Miyagi Limited, Miyagi Japan
Show AbstractPlasma processes, using low temperature substrate cooling, are investigated to etch highly porous organo-silicate ultra-low-k (ULK) dielectrics for interconnect applications. The objective of the experiment is to minimize the plasma induced damage which appears through methyl depletion and moisture uptake. This study shows that high boiling point organic (HBPO) reagents can be successfully used to fill the pores by micro-capillary condensation at temperatures up to -20°C, and efficiently protect the low-k material during the plasma etching. The micro-capillary condensation properties of selected high boiling point organics will be described as well as their retention time in the porous structure. The micro-capillary condensation parameters (partial pressure, temperature) is linked to the vapor pressure of the reagent, but also to its surface affinity to the ULK dielectric. Plasma etch, using a low temperature (-50°C) ICP SF6/HBPO mixture, do enable good pattern transfer at 45nm 1/2 pitch using a metal hard mask approach, as well as efficient protection of the low-k dielectric.
Acknowledgements: this project has received funding from the European Union's Horizon 2020 research and innovation program under the Marie Sklodowska-Curie grant agreement No 708106
5:15 PM - ED9.3.04
Integration of Ultralow-K Dielectrics Using a Template Replacement Approach
Liping Zhang 1 2 , Jean-Francois de Marneffe 1 , Gayle Murdoch 1 , Victor Vega Gonzalez 1 , Alicja Lesniewska 1 , Patrick Verdonck 1 , Nancy Heylen 1 , Lichen Zha 1 , Chen Wu 1 , Scott Leffert 3 , Zsolt Tokei 1 , Juergen Boemmels 1 , Stefan de Gendt 1 2
1 , imec, Heverlee Belgium, 2 Department of Chemistry, KU Leuven, Leuven Belgium, 3 , SBA Materials, San Jose, California, United States
Show AbstractIntegration of ultralow-k dielectrics by a conventional damascene approach is becoming increasingly difficult as critical dimensions scale down. The present work investigates an alternative integration approach based on a “dielectric-last” scheme. The metal structure is first formed by patterning a sacrificial template material. After template removal, porous low-k dielectric is embedded into the spacing between the metal wires. The proposed method eliminates plasma-induced low-k damage, as well as barrier penetration issues.
A Liquid Phase Self-Assembly low-k dielectric (k~2.3) is used for the gap-filling purpose. By optimizing the spin coating conditions, a void free gap-filling structure are achieved with 45 nm and 22 nm spacing. The impact of low-k gap-filling process on the metal structures is investigated. The low-k porogen removal processes can induce formation of Cu2O and subsequent Cu migration, leading to detrimental electrical performance. Proper protection of the copper structures and tuning of the low-k curing process are thus adopted.
Also, the integration scheme for dual damascene structure is explored. Formation of upper metal layers requires surface planarization on various gap-filling structures, which can be performed by chemical mechanical polishing. The surfactants present in the CMP slurry penetrate into the porous low-k, leading to dielectric degradation. A post cleaning step is therefore needed to remove the slurry residues and restore the k value to pristine level.
Finally, using a Meander-Fork vehicle, the inter-metal dielectric properties are evaluated by RC and IV measurements. High electrical yield (> 80%) is obtained with integrated porous low-k showing promising effective k-values (< 2.45) and breakdown voltages (5.7-8.6 MV/cm), confirming the promise of this specific integration approach.
5:30 PM - ED9.3.05
Periodic Mesoporous Organosilica Films for Low-K Application—Promises and Challenges
Murad Redzheb 1 2 , Oguzhan Orkut Okudur 3 2 , Pascal Van Der Voort 1 , Silvia Armini 2
1 Department of Inorganic and Physical Chemistry, Gent University, Gent Belgium, 2 , imec, Leuven Belgium, 3 Department of Materials Engineering, KU Leuven, Leuven Belgium
Show AbstractPeriodic mesoporous organosilica (PMO) films are considered to be a promising low-k candidate for future generation ultra-large scale integration. The main advantages pointed out are the ordered porosity which is shown theoretically and experimentally to result in improved Young's modulus as compared to a low-k with disordered pores, the open porosity of more than 50% obtainable without pore collapse and self-hydrophobization at T>300°C. We found the synthesis of PMO films using cetyltrimethylammonium chloride (CTAC) to be the least dependent on ambient conditions during deposition and most reliable to obtain. Nevertheless, CTAC is an ionic surfactant and ionic surfactants have been reported to be detrimental to the low-k’s electrical reliability.
Taking advantage of the fact that the synthesis procedure we employ results in an ordered film only within a 30 minutes window, we were able to obtain an ordered, long range p6mm, and a disordered, wormlike, porosity films from the same solution. The difference in pore organization was established by XRD and TEM. This approach allows for a reliable comparison of the effect of the ordered pores, particularly 2D hexagonal, on Young’s modulus because the two films we compare have the same pore size distribution, obtained from toluene EP measurements, and are expected to have similar to each other matrix connectivity. Due to the employed synthesis approach, the disordered porosity film, as compared to the ordered one, has 0.05 g/cm3 higher density, inferred from XRR, and 4% lower open porosity, calculated from toluene EP measurements. The Young’s modulus of the film with wormlike pores was 1.7 GPa higher than the modulus of the film with p6mm ordered pores. We rationalize the results in light of the anisotropy caused by the p6mm pore organization, film shrinkage which occurs during the thermal decomposition of the template and the density difference.
We evaluated the electrical reliability of PMO films templated with an ionic surfactant in comparison to a non-ionic surfactant and to a commercial k2.2 spin-on film by measuring stress-induced leakage current. A comparison of hydrophobized films differing in the nature of the templating agent revealed lower breakdown field of 5.7 MV/cm for the CTAC-templated film as compared to 6.3 MV/cm for the film templated with a non-ionic surfactant. Furthermore, the high field, 4 MV/cm, leakage current was observed to be about two times larger, 1.8x10-3 A/cm2, for the film templated with an ionic surfactant as compared to that with a non-ionic. On the other hand, the lowest leakage current of 1.6x10-9 A/cm2 at 1 MV/cm, an order lower than that of the BrijS10-templated film, was measured for the CTAC-templated PMO. Finally, the high field leakage current observed for the film templated with ionic surfactant was similar to the one observed for a commercial spin-on film. Based on these electrical results, CTAC seems to be an acceptable templating agent for low-k films.
5:45 PM - ED9.3.06
Thermal Stability of Low-K Dielectrics for 3D Sequential Integration
Sylvain Beaurepaire 1 2 3 , Chloe Guerin 1 2 , Fabien Deprat 1 2 , Patrice Gonon 1 3 , Ahmad Bsiesy 1 3 , Christophe Licitra 1 2 , Guillaume Freychet 1 2 4 , Mireille Maret 1 4 , Claire Fenouillet-Beranger 1 2 , Vincent Jousseaume 1 2
1 , Université Grenoble Alpes, Grenoble France, 2 , CEA LETI MINATEC Campus, Grenoble France, 3 , LTM UGA/CNRS/CEA, Grenoble France, 4 , CNRS SIMAP, Grenoble France
Show Abstract
A multitude of new product opportunities are now possible thanks to 3D integration schemes. With a 3D sequential integration technology, such as CoolCubeTM, vertically stacking layer of devices (CMOS over CMOS) leads to a reduction of interconnect length and RC delay. This monolithic integration aims at avoiding routing congestion in the Back-End-Of-Line (BEOL), to allows very high 3D via density as well as gains in power and performances [1,2].
For this 3D sequential integration, it has been shown that several interconnect levels should be integrated between the different active layers of devices [3]. These intermediate BEOL levels, which integrate low-k dielectrics, have to support the top FET thermal budget. Therefore, in order to fulfill the CoolCubeTM requirements (stability up to 500 °C during 2 hours [4]), low-k dielectric properties must be carefully studied. Indeed, the top FET thermal budget can greatly influence material properties and generate defects in these films (such as dangling bonds due to carbon depletion). Thus, understanding the link between structure changes and defects occurring at temperature beyond materials deposition and BEOL process have to be thorough.
In this work, the impact of thermal treatments (between 400°C and 700°C) on different porous SiOCH thin films deposited by PECVD was investigated. Although SiOCH low-k thin films are already widely used in the microelectronic industry, their properties are rarely characterized under temperatures of 500°C and beyond. Several sets of deposition conditions (leading to different porosities and dielectric constants) combined with various annealing parameters (temperature, duration) were studied. The change of the material properties was followed using Fourier transformed infrared spectroscopy (FTIR), spectroscopic ellipsometry, ellipso-porosimetry (EP), grazing incidence small angle X-ray scattering (GISAXS) and electrical characterizations (I(V), C(V)).
A change of the film structure and its composition with a loss of methyl-group starting between 500°C and 600°C was well observed, becoming clearly preponderant above 600°C. Detailed studies of porosity show complex and opposite effects between creation of porosity, film shrinkage and change of pore size – which are dependent of annealing temperature. Moreover, low-k films electrical characteristics are deeply affected upon thermal annealing from 500°C, for all porosities. Finally, correlations between electrical properties, material structure and creation of defects during the annealing will be presented.
[1] L. Young-Joon et al, ICCAD, 2009, 645-651
[2] P. Batude et al, IEEE VLSI, 2015, T48-T49
[3] A. Ayres et al, IEEE S3S, 2015
[4] C. Fenouillet-Beranger et al, IEEE IEDM, 2014, 27.5.1-27.5.4
ED9.4: Poster Session
Session Chairs
Wednesday AM, April 19, 2017
Sheraton, Third Level, Phoenix Ballroom
9:00 PM - ED9.4.01
Atomic Layer Deposition of Boron Carbide for Interconnect Applications
Lauren Dorsett 1 , Suhaib Malik 1 , Thuong Nguyen 1 , Anthony Caruso 1 , Sean King 2 , Jeffery Bielefeld 2 , Michelle Paquette 1
1 , University of Missouri–Kansas City, Kansas City, Missouri, United States, 2 , Intel Corporation, Hillsboro, Oregon, United States
Show AbstractAs the semiconductor industry endeavors to scale integrated circuit dimensions—decreasing layer thicknesses while increasing the aspect ratio of fillable features—the need for novel interconnect materials with highly specialized properties continues to rise. Meeting the requirements for the numerous types of materials needed, including low-k dielectrics, etch stops, metal diffusion barriers, hardmasks, spacer layers, and other pattern-assist layers, with traditional silicon-based materials is becoming increasingly challenging. As an alternative to silicon, amorphous hydrogenated boron carbide (a-BC:H), grown through plasma-enhanced chemical vapor deposition (PECVD), has been demonstrated to possess excellent dielectric properties, combined with very high Young’s modulus, electrical properties rivaling those of SiOC:H variants, very good chemical stability, and unique and useful etch chemistry. However, a problem with PECVD growth that will limit its long-term utility is its inability to scale while maintaining uniform, conformal coatings for very thin films. Here, we will describe progress toward the development of a novel atomic-layer-deposition-based process for the growth of BC films on metal (copper) and/or dielectric (SiO2) substrates.
9:00 PM - ED9.4.02
Plasma Enhanced Chemical Vapor Deposition of Al2O3 Films Using Dimethylaluminum Isopropoxide without Additional Oxygen Sources
Wonjin Ban 1 , Sungyool Kwon 1 , Seonhee Jang 1 , Jaeyoung Yang 2 , Donggeun Jung 1
1 , Sungkyunkwan University, SUWON-SI, SE, Korea (the Republic of), 2 , TES Co., Ltd, Yongin Korea (the Republic of)
Show AbstractAl2O3 films were prepared by plasma enhanced chemical vapor deposition using a dimethylaluminum isopropoxide precursor without additional oxygen sources. The chemical properties and potential application to dry etch hardmask of deposited Al2O3 films were studied. The stoichiometry and contamination of Al2O3 films with deposition temperatures between 30 and 500 °C were investigated by X-ray photoelectron spectroscopy. The O/Al ratios at 300-500 °C were between 1.53 and 1.55, in a good agreement with the formula Al2O3. The carbon contents were between 8.3 and 9.7 at. %. The O/Al ratio in the film deposited at 30 °C showed the relatively higher value of 2.04. Its carbon content was 47.1 at. %, which was much higher carbon content considered, possibly due to insufficient decomposition of the precursor at such a low temperature. In addition to chemical analysis of deposited Al2O3 films, the etch resistance was investigated by plasma reactive ion etching using C4F8, CH2F2, Ar and O2. The etch selectivity of Al2O3 film deposited at 400 °C to SiO2 was 9.13.
9:00 PM - ED9.4.03
Electrical Properties of Low-K SiCOH Films Deposited with the Phenyltrimethoxysilane Single Precursor
Sungyool Kwon 1 , Wonjin Ban 1 , Donggeun Jung 1
1 , Sungkyunkwan University, Suwon Korea (the Republic of)
Show AbstractUltra-large-scale integration devices, which contain metallization and interlayer dielectric films, have continuously been shrunk for improving performance. Thus, resistance-capacitance delays (RC delay) have become a significant issue, limiting the true capacity of these otherwise more efficient devices. In order to mitigate this problem, low relative dielectric constant (low-k; k ≤ 3.0) films have been demanding. In this work, the porous SiCOH films was deposited with the phenyltrimethoxysilane precursor in plasma enhanced chemical vapor deposition system. The k values of the films from 2.11 to 3.2 were obtained with the various plasma deposition powers after the thermal annealing process. The Fourier transform infrared (FTIR) analysis showed the relation between the chemical structure and the k value. As the area ratio of (C-Hx)/(Si-O) bonds increased, the k value of the annealed film decreased because of the decrease of the film density by removing the thermally unstable hydrocarbon bondings in the deposited SiCOH film. Our experiment shows the deposited SiCOH film using a PTMS single precursor was suitable for the low-k material.
9:00 PM - ED9.4.04
Evaluation of New Spin-On Deposited Ultra Low-K Films Developed for Gap Filling Application
Yingjie Wang 1 , Chunhui Liu 1 , R. N. Nenashev 2 , N. M. Kotova 2 , K. Vorotilov 2 , Jing Zhang 1 , Mikhail Baklanov 1
1 , North China University of Technology, Beijing China, 2 , Moscow Technological University (MIREA), Moscow Russian Federation
Show AbstractSince the first integrated circuit was invented in 1958, the Si-based Microelectronic technology has been developing very quickly. However, starting from the technology nodes 100 nm and below, the resistance-capacitance delay, cross-talk noise and power dissipation in interconnects became critical and the conventional PECVD SiO2 as interconnect dielectric and Al metallization have become not applicable anymore. As a result, the low dielectric constant materials have become one of the hot research topics in the field of microelectronics. Presently selected potential candidates for future (7 nm and beyond) generations of ULSI devices include new spin-on deposited organosilicate (OSG) materials like Periodic Mesoporous Organosilicates (PMO). PMO have ordered porosity and certain concentration of bridging -CH2- groups. It has been assumed that the ordered porosity and bridging -CH2- groups allow to improve and control the mechanical properties and plasma resistance, but scaling of k-value in this material by gradual increase in porosity is coupled with degradation of its mechanical and electrical properties, so we have to take a balance between the dielectric constant and the reliability.
In this paper, we focus our research on new the sol-gel derived with spin on deposition technology nanoporous thin films, which has low dielectric constant, and compatibility with existent ULSI technology. Using EP, FTIR, XRR, AFM, surface acoustic wave spectroscopy (SAWS) and other methods the impact of water / silanol groups ratio, porogen content and BTMSE content on the porosity, pore size distribution, electrical properties and Young's modulus and other properties are explored. By changing deposition conditions various low-k films with dielectric constant from 3.0 to 1.7 have been deposited and evaluated.
It is found that refractive index and porosity increases with porogen loading. It is found that BTMSE content and water/silanol groups ratio has a large impact on porosity. Mechanism of BTMSE, porogen content, water/silanol ratio and curing conditions on low-k films properties will be discussed. The developed films have relatively low skeleton refractive index (1.4 instead of 1.5 in traditional OSG materials), which allows achievement of low dielectric constant at relatively low porosity. The deposited films have perfect gap filling capability, which is important for new integration approaches.
9:00 PM - ED9.4.05
Effect of Carbon Bridge Content on Spin-On Copolymer PMO Films
K. Vorotilov 1 , A. Sigov 1 , R. N. Nenashev 1 , N. M. Kotova 1 , Konstantin Mogilnikov 2 , Yingjie Wang 3 , Jing Zhang 3
1 , Moscow Technological University, Moscow Russian Federation, 2 , Institute of Semiconductor Physics, Novosibirsk Russian Federation, 3 , North China University of Technology, Beijing China
Show AbstractAn effect of ethylene bridge content on the properties of alkylene bridges copolymer PMO films obtained by Chemical Solution Deposition (CSD) techniques is discussed. Copolymer PMO films were obtained by cohydrolisis of methyltrimethoxysilane and 1,2-Bis(trimethoxysilyl)ethane (BTMSE) in aprotic solvent. Evaporation-induced self-assembly process with Brij-30 as a surfactant is used. FTIR, ellipsometry, porosimetry, mechanical and electrical characterization techniques are used for films properties characterization. The films with 0-60% porosity were obtained. An effect of pH, water content in solution, synthesis temperature, porogen and ethylene bridge content, curing temperature on the films properties is discussed.
It is shown that hydrolysis conditions (first at all, water content) and bridge content have strong impact on the film properties.
The work is supported by the Russian Ministry of Education and Science.
Symposium Organizers
Jeffery Bielefeld, Intel Corporation
Mikhail Baklanov, North China University of Technology (NCUT)
Vincent Jousseaume, CEA-LETI
Eiichi Kondoh, University of Yamanashi
Symposium Support
Air Liquide
Applied Materials
CEA-LETI
ED9.5: Integration and Metallization
Session Chairs
Jeffery Bielefeld
Larry Zhao
Wednesday AM, April 19, 2017
PCC North, 100 Level, Room 128 B
9:00 AM - *ED9.5.01
CMP Challenges for Advanced Technology Nodes
John Zhang 1 , Haigou Huang 2 , Andrew Greene 3 , Ruilong Xie 1 , Soon-Cheon Seo 3 , Pietro Montanini 3 , Wei-Tsu Tseng 2 , Stan Tsai 1 , Matthew Malley 3 , Qiang Fang 2 , Raghuveer Patlolla 3 , Dinesh Koli 2 , Dechao Guo 3 , Donald Canaperi 3 , Charan Surisetty 3 , Jean Wynne 3 , Walter Kleemeier 1 , Cathy Labelle 1
1 Technology Development, GLOBALFOUNDRIES, Albany, New York, United States, 2 , Globalfoundries, Malta, New York, United States, 3 , IBM Research, Albany, New York, United States
Show AbstractThe CMP challenges for advanced technology nodes are discussed. Global and local uniformity challenges and their cumulative effects are presented. Uniformity improvements for advanced node integration were achieved through slurry, pad and platen optimization, innovative integration schemes, the reduction of incoming variation and the reduction of cumulative effects. We discuss reduction of typical defect types. Defects resulting from simple mechanisms (foreign material, polish residues) and those resulting from chemical and physical interactions (corrosion, chemical attack, scratches, physical migration) and strategies for control are studied. Defectivity reduction measures include new post-CMP clean chemicals, new slurries and pads and reduction of incoming defectivity. Finally we discuss an observed tradeoff between good defectivity and good uniformity.
9:30 AM - ED9.5.02
Controlling the Microstructure of Electroless Cobalt for Semiconductor Interconnect Applications
Kevin Musick 1 2 , Kathleen Dunn 1
1 , SUNY Polytechnic Institute, Albany, New York, United States, 2 , University at Albany, State University of New York, Albany, New York, United States
Show AbstractThe continued scale-down of interconnects to smaller technology nodes is challenging, in part, due to a copper microstructure that maintains an undesirably fine grain structure. This leads to shorter electromigration lifetimes and a higher resistivity as compared to bulk copper. Combined with the additional challenges of maintaining a continuous diffusion barrier free of pinholes, and a conductive seed layer as required for electrolytic plating it is imperative that materials be investigated —preferably ones with less stringent barrier/ seed requirements. One potential alternative is cobalt, which has previously been studied as a liner material, and as a component in capping layers for copper lines to prevent surface diffusion.
Electroless cobalt is particularly attractive because it does not require a continuous conductive seed layer, but may be initiated catalytically from an activated surface. Historically, many of the studies on electroless cobalt were concerned with its magnetic properties. Often high phosphorous content and a fine grain structure were desirable in these materials. However, the opposite is true in the case of interconnects. Though initially a high nucleation density may aid in filling patterned features, a large grain size and low impurity content are desirable to minimize resistivity. The options for improving this microstructure for interconnect use are limited, as was true in the case of pure copper, to industrially relevant annealing temperatures and short annealing times. We thus pursue a design of experiments (DOE) approach to optimizing the as-deposited microstructure and impurity content prior to annealing.
Imaging in a scanning transmission electron microscope (STEM), operated both conventional and scanning modes, is used in combination with energy dispersive x-ray spectroscopy (EDS) to visualize the cobalt microstructure, and quantify the variation of grain size and impurity content as a function of deposition conditions. Resistivity is measured by four point probe to quantify the impact of both grain size and phosphorus content on performance benchmarks. The resulting insights will be discussed in terms of better engineering the microstructure of cobalt in anticipation of its integration into semiconductor manufacturing.
9:45 AM - ED9.5.03
Insight into the Molecular Structure of Amino-Copper (II) Formates in Forming High Conductivity Copper Films for Printable Electronics
Chantal Paquet 2 , Ryan MacDonell 1 , Michael Schuurman 2 , Thomas Lacelle 1 , Xiangyang Liu 2 , Bhavana Deore 2 , Arnold Kell 2 , Patrick Malenfant 2
2 , National Research Council of Canada, Ottawa, Ontario, Canada, 1 Department of Chemistry, University of Ottawa, Ottawa, Ontario, Canada
Show AbstractMolecular inks are receiving increasing attention as replacements for particle-based conductive inks in printable electronics. These inks consist of metal-organic compounds that upon heating decompose into their metallic state yielding a conductive trace. Amino-copper carboxylates are a class of copper precursor inks that have demonstrated potential as molecular inks in printable electronics as they convert to metallic copper under mild conditions and as a result allow their use with low cost substrates such as PET. Despite numerous examples of their use as inks, little is known about the molecular factors that lead to their thermolysis at low temperatures or to their electrical properties.
In this presentation, we identify the factors and the mechanism that govern the thermal decomposition of amino-copper carboxylates. The structure of the amine was found to govern the onset of decomposition and the breadth of the decomposition reaction. DFT calculations are presented and illustrate how the structure of the amines, through hydrogen bonding, impacts the rearrangement of the formate to yield CO2 and a copper hydride. We next show how the dynamics of thermolysis along with the boiling point of the amines are the two dominate factors that influence film morphologies which in turn determine the volume resistivity of their sintered films. The results provide a means of molecular tailoring copper formates to achieve low volume resistivity copper films and low processing temperature, two key properties that qualify inks in printable electronics.
10:00 AM - ED9.5.04
Etching of Transition Metals (Co, Ni, Fe, Pt) Using Supercritical Fluids
Eiichi Kondoh 1
1 , University of Yamanashi, Kofu Japan
Show AbstractTransition metals shown in the title are hard-to-etch elements, as they produce nonvolatile compounds with halogens. Physical etching based on accelerated inert ions can define feature profiles but etch residues or re-deposition cannot be eliminated. This has become a serious issue as the feature size shrinks down to 10 nm in advanced metallization processes for gate metals and magnetoresistive memories. In this work, these transition metals were etching in supercritical CO2 ambient through a chelating chemistry at elevated temperatures (<300°C)
10:15 AM - ED9.5.05
Pore Surface Grafting of Porous Low-K Dielectrics by Selective Polymers
Askar Rezvanov 1 2 3 , Liping Zhang 1 4 , Mitsuhiro Watanabe 1 5 , Mikhail Krishtab 1 4 , Lin Zhang 6 , Alexey Zotovich 8 7 , Sergey Zyryanov 8 7 , Dmitriy Lopaev 7 , Nigel Hacker 6 , Patrick Verdonck 1 , Silvia Armini 1 , Evgeny Gornev 2 3 , Jean-Francois de Marneffe 1
1 , imec, Leuven Belgium, 2 , Moscow Institute of Physics and Technology, Dolgoprudny Russian Federation, 3 , Molecular Electronics Research Institute, Moscow Russian Federation, 4 , KU Leuven, Leuven Belgium, 5 , Interdisciplinary Graduate School of Medicine and Engineering, Kofu Japan, 6 , SBA Materials Inc, San Jose, California, United States, 8 , Faculty of Physics, Lomonosov Moscow State University, Moscow Russian Federation, 7 , Skobeltsyn Institute of Nuclear Physics, Lomonosov Moscow State University, Moscow Russian Federation
Show AbstractNowadays, porous organo-silicate low-k dielectrics with permittivity lower than 2.5 are under intense investigation for future interconnects. Their integration in back-end-of-line (BEOL) interconnect technological flow suffers from many issues, amongst them plasma damage caused by etching process. Several approaches for reducing the plasma damage were proposed, the most recent are Post-Porosity Plasma Protection/P4 (pores stuffing) and cryogenic etching. An alternative solution is based on pore walls passivation by selective deposition or grafting of permanent polymer filler, which suppress the need to remove it afterwards. This layer of polymer should be sufficiently thin to avoid too high increase of the intrinsic dielectric constant, but also provide enough protection against plasma reactive radicals. In this work the polymer grafting of pore sidewalls is studied as a protecting agent against processing damage. Polymethyl-methacrylate (PMMA), an improved polystyrene (PS-pro), and a tailored Plasma Damage Management polymer (PDM SHIELDTM UT002) are considered as potential candidates. PMMA and PS-pro show non-homogeneous grafting properties, while PDM coats the pore walls uniformly through the bulk of the porous low-k film. A k ~ 2.2 porous spin-on glass is used as vehicle for processing damage study. Around a monolayer is grafted on the pore walls, leading to a k-value increase up to △k ~ 0.2. Using grafted PDM, the porous low-k chemical stability, in 0.5% diluted HF, is significantly improved. Concerning plasma damage, at constant etch depth, methyl depletion is also significantly decreased after etching in TCP discharge (Ar, O2, CF4 plasmas), and mainly in CCP discharge (Ar/CF4 plasma which is typical for SiO2 – like materials etching) showing high polymerizing character, leading to similar damage depth as found for a reference OSG 2.55 low-k. Moisture uptake is however not improved, leading to significant drift of dielectric constant. To get better understanding of PDM protection during the plasma etching the specially designed downstream ICP set up was used. It is well known that the main damage of low-k materials comes from fluorine radicals and photons in vacuum ultraviolet range. PDM protection from F radicals only, VUV photons only and their joint effect was studied. Absolute values of photons and radicals coming on the samples surface were measured so that not only qualitative but also a quantitative analysis of PDM protection was performed.
ED9.6: Novel Processing Methods
Session Chairs
Yves Chabal
Eiichi Kondoh
Wednesday PM, April 19, 2017
PCC North, 100 Level, Room 128 B
11:00 AM - *ED9.6.01
3D Sequential Integration—Opportunities and Challenges in Low Temperature Process Modules
Claire Fenouillet-Beranger 1
1 , CEA/LETI, Grenoble France
Show AbstractAn alternative approach to conventional planar integration for future nodes is the monolithic 3D also called 3D VLSI or CoolCube
TM integration. Compared to TSV-based 3D ICs, monolithic offers the possibility to stack devices with alignment precision at the nm range enabling 3D contacts at the device level [1]. However, this integration faces the challenge of realizing a high performance transistor at the top level without impacting the electrical characteristics of the bottom one. One of the issues consists in integrating transistors with low temperature process steps. Bottom MOSFET tolerable thermal budget has been evaluated for state of the art advanced planar FDSOI technology with ultra-thin film made of enriched SiGe or Si, together with SiGe:B or SiC:P RSDs [2]. The silicide has been determined as the main contributor for the bottom MOSFET instability. The maximum top FET temperature is fixed at around 500°C 2h however this temperature can clearly be relaxed when the anneal duration is reduced or if the thermal stability of the bottom silicide is extended. In this context, an alternative Ni-based silicide, the Ni
0.9Co
0.1-based metal is being developed to achieve both main properties: low contact resistance and extended thermal stability [3].
In parallel, to take full benefit of 3D sequential integration and to avoid routing congestion in the upper BEOL, an intermediate BEOL (iBEOL) is mandatory between each tier [4]. If the combination of copper (Cu) with ultra-low-k (ULK) materials is widely used for standard BEOL thanks to their low resistivity and parasitic capacitance, the integration of Cu/ULK in the iBEOL faces a number of challenges. Main concern with copper metallization is contamination containment in case of wafer break during the Front-End-Of-Line (FEOL) process of the top MOS layer during the 3D sequential integration. Despite the fact that its intrinsic resistance is larger, tungsten (W) is very appealing in terms of integration as it has already been integrated in the FEOL of several products. As for the silicide, the iBEOL, must resist to top FET thermal budgets.
Thus, this paper focuses on 3DVLSI integration and applications and presents the recent advanced in terms of low temperature process modules development.
* corresponding author e-mail: [email protected][1] P. Batude et al., VLSI 2015
[2] C. Fenouillet-Beranger et al., IEDM 2014
[3] F. Deprat et al., AMC 2015
[4] Y.-J. Lee et al., ACM International Conference on Computer-Aided Design, pp. 539-546, Nov. 2012.
[5] C. Fenouillet-Beranger et al., IEDM 2014
11:30 AM - ED9.6.02
Self-Aligned Growth of 3D Nano-Bridge-Based Interconnects by Gas Phase Electrodeposition
Leslie Schlag 1 , Jun Fang 2 , Johannes Reiprich 1 , Heiko Jacobs 1
1 , TU Ilmenau FG Nanotechnologie, Ilmenau Germany, 2 Electrical Engineering, University of Minnesota, Minneapolis, Minnesota, United States
Show AbstractThis talk will present a self-aligned nanowire bonding process to form free-standing point-to-point electrical connections.[1] Wire diameters down to 200 nm and contact pads down to 1 µm will be shown. Moreover, the process is a parallel process to achieve a higher throughput when compared with any of the emerging serial-direct-write or established serial wirebonding methods. The presented process is based on a method that is best referred to as “gas phase electrodeposition”. The process has been described in parts before. [2,3] It is a localized material growth/deposition process which uses charged insulators to attract[4] or deflect[5] an incoming flux of charged material. Taking a closer look at the basic process, it becomes clear that gas phase electrodeposition shares some of the characteristics of electrodeposition in the liquid phase. However, it is a gas phase process with a much larger mean free path of the particles. The Debye length representing the screening length of Coulomb forces is also larger.[6] Despite this difference, it can grow nanostructures in selected domains in a programmable fashion by adjusting the dissipation current of the ionic species that arrive at the surface. For example, in the simplest case it was used to grow straight metallic nanowire arrays whose height and density were adjusted to vary across the substrate which in turn were used as contacts in photovoltaic devices.[3] In any event, charged material continues to deposit into locations where charge dissipation can occur, leading to a growth of extended structures much like what is observed in the liquid phase based electrodeposition/plating.
REFERENCES
[1] Approaching Gas Phase Electrodeposition: Process and Optimization to Enable the Self-Aligned Growth of 3D Nano-Bridge-Based Interconnects, J. Fang, L. Schlag, S. C. Park, Th. Stauden, J. Pezoldt, P. Schaaf, and H. O. Jacobs, Advanced Materials 2016, 28, 9.
[2] Mimicking Electrodeposition in the Gas Phase: A Programmable Concept for Selected-Area Fabrication of Multimaterial Nanostructures, J. J. Cole, E. C. Lin, C. R. Barry, H. O. Jacobs, Small 2010, 6, 10.
[3] Gas Phase Electrodeposition: A Programmable Multimaterial Deposition Method for Combinatorial Nanostructured Device Discovery, E. C. Lin, J. J. Cole, H. O. Jacobs, Nano Letters 2010, 10, 11.
[4] Submicrometer Patterning of Charge in Thin-Film Electrets, H. O. Jacobs, G. M. Whitesides, Science 2001, 291, 5509.
[5] Printing of Organic and Inorganic Nanomaterials Using Electrospray Ionization and Coulomb-Force-Directed Assembly, A. M. Welle, H. O. Jacobs, Applied Physics Letters 2005, 87, 26.
[6] Fringing Field Directed Assembly of Nanomaterials, C. R. Barry, H. O. Jacobs, Nano Letters 2006, 6, 12.
11:45 AM - ED9.6.03
The Effects of Organic Acids on Electrodeposited Cu Films in Sub-Micron Trenches
Tyler Pounds 2 , Karl Sieradzki 1 , Jonah Erlebacher 2
2 , Johns Hopkins University, Baltimore, Maryland, United States, 1 , Arizona State University, Tempe, Arizona, United States
Show AbstractCurrent electrodeposition processes that allow for defect free Cu film deposition in recessed features for integrated circuit metallization rely on additives to induce differential deposition rates across the varying profiles of recessed features. To date, the effects of several established additives are well characterized, leading to consensus on the mechanisms responsible for superconformal deposition (also termed “superfilling” or “bottom-up” deposition) and models that successfully describe the evolution of these deposited films. As IC feature sizes decrease, new methods for inducing superfilling Cu deposition and improving current techniques continue to be researched.
As a means of exploring new electrolyte chemistries for Cu electrodeposition in IC applications, this study explores the effects of several organic acids on Cu electrodeposition in sub-micron trenches. Under certain deposition conditions, these electrolytes are capable of producing dense Cu films in trenches in the absence of other additives through enhanced deposition rates at the bottom of the trenches relative to the sidewalls. The morphologies of the deposited films suggest that well known superfilling mechanisms do not sufficiently describe the observed difference in deposition rate. Applying the Butler-Volmer (BV) equation yields an appropriate fit to the experimental kinetic data yet results in unrealistic values for certain parameters. By comparing these results to those from depositions via Pb mediated UPD deposition, we propose that two contributing factors working in conjunction during depositions from organic acid containing electrolytes, seed layer effects and organic acid induced effects on film quality, resulted in the dense filling from the organic acid electrolytes. This work suggests electrolytes with minimal additives could be capable of producing defect free Cu films in recessed features at high deposition rates.
12:00 PM - ED9.6.04
The Impact of Solute Segregation on Grain Boundaries in Dilute Cu Alloys
Takanori Tsurumaru 1 2 , Luke Prestowitz 1 , Brendan O'Brien 1 , Kathleen Dunn 1
1 Nanosciences, State University of New York Polytechnic Institute, Albany, New York, United States, 2 Crystal Engineering, SUMCO Corporation, Kishima-gun, Kohoku-machi, Saga, Japan
Show AbstractThe performance of ultrafine wires in the back end of the line (BEOL) is degraded by the persistent polygranular microstructure in copper which introduces more diffusion pathways for copper atoms and which leads to faster electromigration failure times. To improve interconnect reliability, a Co-containing capping layer has been used to reduce surface diffusion. At other interfaces, alloying solutes have proposed to slow down grain boundary diffusion by increasing the activation energy for atomic motion, but the mechanisms are not well understood and there are many conflicting reports as to their efficacy. One challenge for improving interconnect performance through alloying is a lack of information regarding segregation interactions at grain boundaries and interfaces when minute concentrations are introduced into the copper lattice. Historically, solute was expected to pin GBs, increase resistivity, and reduce diffusivity by GB “stuffing”. More recent studies on GB interface states called ‘complexions’ suggest a more complicated relationship, which can explain these results as well as cases where segregation increases mobility or enhance diffusion. To apply complexion analysis in technologically relevant alloy systems, we are investigating dilute copper alloys created by co-electrodeposition or nanolaminate fabrication using a microfluidic device with separate inputs for solvent and solute. Alloys of interest include Cu(Co), and Cu(Au), along with more noble solutes to form Cu(Ag) and Cu(Au).
Secondary Ion Mass Spectrometry (SIMS) was used to analyze the incorporation of solute, while the impact on microstructure is evaluated using a combination of transmission electron backscattered diffraction (t-EBSD) and scanning transmission electron microscopy (STEM), to determine grain size and grain boundary orientation. For example, Ag could incorporated at ~3 at.% from a sulfate bath with alternating cycles of electrolytic and displacement reactions, and resulted in a grain size on the order of 2-5 microns, typical of pure copper films. In the case of Co solute, a citrate and boric acid bath for co-electrolytic plating incorporated 1.5 at% Co, but resulted in a fine grain size (~40 nm) which persisted even after annealing at 500°C for 5 hours. These observations are then correlated with grain boundary segregation and any changes in bonding across a decorated boundary, as quantified using energy dispersive X-ray spectroscopy (EDX) and/or energy dispersive electron energy loss spectroscopy (EELS). By understanding these interactions and pathways of alloying solutes in copper microstructures, we can more accurately predict alloying behavior and how they inhibit or promote grain boundary diffusion. Understanding how these alloys interact with grain boundary diffusion pathways and interfaces will enable grain boundary and interface engineering solutions to obstacles faced by semiconductor manufacturers as more aggressive feature sizes are pursued.
12:15 PM - ED9.6.05
Growth and Characterization of Ultrathin Conformal Nickel Films by Plasma-Enhanced Atomic Layer Deposition
Pouyan Motamedi 1 2 , Ken Bosnick 1 , Kenneth Cadien 2
1 , National Institute for Nanotechnology, Edmonton, Alberta, Canada, 2 , University of Alberta, Edmonton, Alberta, Canada
Show AbstractThere is a great interest in various branches of advanced materials industry for development of novel methods and improvement of existing ones to deposit conformal ultrathin metallic films. Microelectromechanical systems, thin film transistors, fuel cells, and solar heaters are just a few prominent examples, where ultrathin metal films can realize their potentials. In most of these applications, achieving the capacity to deposit a conformal thin film on a three-dimensional structure is the key factor. Atomic layer deposition is known for its potential for growth of conformal thin films with exceptional degree of control over thickness. This study evaluates and compares two methods for preparation of conformal nickel films. The first method involves direct atomic layer deposition of metallic films through using an organometallic precursor and hydrogen plasma. The results of this method are then compared with those of an indirect method; in which conformal nickel oxide films were deposited using the same organometallic precursor and oxygen plasma, followed by reduction in the furnace, in the presence of hydrogen gas. A full suite of characterization methods were conducted, in order to assess and compare the chemical composition, growth rate, surface roughness, mass density, crystallinity, and optical properties of the films. In order to establish the conformality of the films, deposition was also carried out on aluminum oxide foams, which were then investigated through scanning electron microscopy, whose the initial results will be presented.
12:30 PM - ED9.6.06
A Comprehensive Comparison of Scanning Laser Annealing and Microwave Annealing for Ion Implanted Si
Zhao Zhao 1 , Joe Hillman 2 , Manny Oropeza 2 , Terry Alford 1
1 , Arizona State University, Tempe, Arizona, United States, 2 , Universal Laser Systems, Scottsdale, Arizona, United States
Show AbstractThe most widely used annealing method for ion implanted Si is rapid thermal annealing (RTA). Several alternatives to RTA have emerged, including laser annealing and microwave (MW) annealing. They are quite attractive because they both offer higher degrees of dopant activation. However, few studies have compared the dopant activation and recrystallization of laser and MW annealing against energy density that is absorbed in those two processes. In our study, we have compared the dopant activation against the absorbed energy density per area, and have shown that the laser annealing achieves the similar or even lower sheet resistance and recrystallization by using only ~1/7 of energy density per area that is required by MW annealing. This is due to the surface heating in laser annealing. Our calculations shows that MW energy is absorbed uniformly across the entire depth of Si wafer, and only 0.03% of MW energy is absorbed by the extremely thin amorphous Si surface and used for dopants activation and recrystallization. However, almost 14% of the laser energy is absorbed by the amorphous Si surface and used for dopants activation and recrystallization. Due to this high energy absorption efficiency at the amorphous layer during laser annealing, only a small amount of laser energy is required to achieve the same dopant activation and recrystallization. The relatively high diffusion depth in laser annealing makes it ideal for deep-well formation with a uniform dopant concentration. The diffusion-less annealing achieved by MW annealing provides a marked benefit for shallow junction devices.
12:45 PM - ED9.6.07
Interface-Controlled Carrier Transport in Metal-Lutetium Oxide-Metal Structures Deposited by Electron-Beam Evaporation Technique
Khalid Mahmood 1
1 , Government College University Faisalabad, Faisalabad Pakistan
Show AbstractNano-thin films of Lu2O3 with 80nm thickness have been deposited on metal-coated glass substrates in metal-insulator-metal (MIM) geometry by electron-beam evaporation technique. High field and temperature dependent electrical characterization on grown MIM structures have been investigated in symmetric electrode configuration using Al, Cr or Cu metals. The temperature dependent I-T characteristic features have been found to support the conduction mechanism across MIM systems to be an electrode-limited process except for Al-Lu2O3-Al device, which show Poole-Frenkel mechanism. The associated parameters such as activation energy, coefficient of barrier lowering and effective height of Schottky barrier at zero biasing have been evaluated at different values of temperature and electric field and discussed according to various conduction mechanisms.
ED9.7: Low-K Materials II
Session Chairs
Vincent Jousseaume
E. Ryan
Wednesday PM, April 19, 2017
PCC North, 100 Level, Room 128 B
2:45 PM - *ED9.7.01
Establishing the Relationship between Low-K Dielectric Properties and Intrinsic Conduction and Degradation Mechanisms
Chen Wu 1 , Yunlong Li 1 , Kristof Croes 1
1 , imec, Leuven Belgium
Show AbstractAdvanced interconnect technologies require the continuous development of reliable low-k dielectric materials [1]. Since the porosity of low-k dielectrics keeps increasing and the dielectric spacing keeps decreasing, this development becomes more and more challenging [2]. One major screening criterion for low-k materials is to have sufficient electrical reliability including maintaining a low capacitance, a low leakage current and sufficient long dielectric failure time under electrical stress.
However, due to the lack of reliable characterization methods and techniques, the intrinsic low-k material properties have not yet been systematically correlated to the material electrical performance. For example, the role of material porosity and porogen residues on electrical performance is not yet fully understood [3]. In addition, by using integrated test vehicles, the decoupling of intrinsic and extrinsic degradation mechanisms under electrical stress is complicated [4]. Together with a limited knowledge of the physics behind these degradation mechanisms, this could easily lead to incorrect theories and models. Due to the reasons mentioned above, many reliability issues remain unsolved in the field of low-k dielectric research.
These unsolved tasks led to the motivation of this work. Our first research goal is to study the intrinsic electrical conduction of low-k materials and to investigate the possible influence from different material parameters. The second task is to study the intrinsic low-k material degradation mechanisms, including the understanding of different parameters during material degradation, such as, stress induced leakage current and flat band voltage shift. Based on these learnings, we established the relationship between low-k dielectric properties and intrinsic electrical reliability performance.
[1] K. Maex, M. R. Baklanov, D. Shamiryan, F. Iacopi, S. H. Brongersma and Z. S. Yanovitskaya, Journal of Applied Physics 93, 8793 (2003).
[2] M. R. Baklanov, P. Ho, and E. Zschech, Advanced Interconnects for ULSI Technology, Wiley, Chichester, (2012).
[3] C. Wu, Y. Li, M. R. Baklanov and K. Croes, ECS Journal of Solid State Science and Technology 4, N3065 (2015).
[4] L. Zhao, M. Pantouvaki, K. Croes, Zs. Tokei, Y. Barbarin, C. Wilson, M. Baklanov, G. Beyer, and C. Claeys, Applied Physics Letter 99, 222110 (2011).
3:15 PM - ED9.7.03
Experimental Study of Plasma-Induced Damage in Cryogenic Etching of Porous Low-K Dielectrics in CF3Br and CF4
Askar Rezvanov 1 2 , Andrey Miakonkikh 3 , Konstantin Rudenko 3 , Alexey Vishnevskiy 4 , Evgeny Gornev 1 2 , Mikhail Baklanov 5
1 , Moscow Institute of Physics and Technology, Dolgoprudny Russian Federation, 2 , Molecular Electronics Research Institute, Moscow Russian Federation, 3 , Institute of Physics and Technology of Russian Academy of Sciences, Moscow Russian Federation, 4 , Moscow Technological University, Moscow Russian Federation, 5 , North China University of Technology, Beijing China
Show AbstractPlasma processing (patterning) is one of the most important and critical steps during the integration of ultralow-k materials into microelectronic devices. Organosilicate based low-k materials are degrading (damaged) during the etching and other plasma based processes due to high porosity and relatively large pore size. The active radicals, ions, VUV photons from plasma deeply penetrate into pores and modify the pore wall chemical structure. The hydrophobic methyl groups are replaced by hydrophilic OH groups. As a result of the moisture adsorption, considerable increase of the k-value and leakage current is observed. In this work the low temperature (0°C ÷ -120°C) etching of organosilicate low-k dielectrics in CF3Br and CF4 plasmas is studied. Chemical composition of pristine film and etched films were measured by FTIR. Reduction of plasma-induced damage (PID) at low process temperature is observed. It is shown that the plasma damage reduction is related to protective effects of accumulated reaction products (CHxFyBrz, SiBrx) in case of CF3Br plasma. Decrease in the sample temperature leads to increase in Br* and F* radical surface adsorption which results in etch rate raise. Bromine containing reaction products are less efficient for low-k surface protection against the plasma damage. All reaction products could be removed after etch by thermal annealing and the pores become empty. In the case of CF4 plasma, the thickness of CFx polymer on low-k surface rises with the temperature reduction which is measured by ellipsometry. The temperature reduction strongly mitigates diffusion of fluorine containing species into CFx polymer/low-k interface and this effect reduces the etch rate and damage of low-k material. At high process temperatures (0°C ÷ -40°C) the thickness of the polymer is sufficiently small to prevent F* radicals diffusion. Further, with the temperature reduction, the polymer thickness is increasing and the effective penetration of F* radicals are decreased. Results of in situ after-etch treatment in low-density hydrogen ICP plasma and characterization of plasmas composition also will be presented.