Symposium EP01 : Materials for Beyond the Roadmap Devices in Logic, Memory and Power

Among high mobility channel materials, germanium is a unique candidate which offers both high hole and electron mobilities required for future CMOS. Forming a high-quality MOS interface is mandatory to bring out the full potential of Ge, while maintaining sufficient gate stack reliability is also compulsory on real devices. Recent reliability studies on Ge gate stack pointed out that the BTI of GeO₂-based gate stack is a serious concern, while the use of Si-passivation layer on Ge shows potential to satisfy the reliability requirements [1]. An epitaxial grown Si passivation layer enables the use of a similar high-k/SiO₂ gate stack, which has been intensively studied on Si devices. The presence of an SiO₂ interface layer also makes band engineering possible by forming an interface dipole at the high-k/SiO₂ interface [2]. On Ge pFETs, high hole mobility and superior NBTI reliability has been successfully demonstrated using a Si passivation layer [3]. In contrast, it is more challenging to achieve low Dit [4] and superior gate stack reliability on Ge nFET [5], even with a Si passivation layer. This presentation describes a way to achieve low Dit (5x10¹⁰ cm^-2eV^-1 around mid-gap) and superior gate stack reliability (effective oxide trap density of low x10⁸ cm^-2 at Eox=3.5 MV/cm) by using a Si-cap layer. While thinning down the Si-cap layer to an optimum thickness reduces Dit and improves electron mobility, while it increases the effective oxide trap density and degrades reliability because of the quantization in Si-cap layer and/or increase in the amount of Ge in the SiO₂ interface layer [6]. To improve the gate stack reliability, La- or Mg-induced interface dipole is formed at the HfO₂/SiO₂ interface by inserting a thin ALD cap layer [7]. The interface dipole energetically decouples the electron traps in the high-k and the channel electrons, resulting in smaller V_TH or V_FB shift. Insertion of ALD LaSiO or MgOx is found to also suppress intermixing between HfO₂ and SiO₂, resulting in a 2-3x Dit reduction. Significant further Dit reduction is demonstrated by performing high-pressure anneal (HPA) in H₂, lowering the Dit level down to 5x10¹⁰ cm^-2eV^-1 (1/20x) around mid-gap. Additionally, this presentation will also discuss EOT scalability and V_TH tunability on Si-passivated Ge nMOS gate stack.

[1] J. Franco et al., IEDM 2013, p. 397.
[2] Y. Yamamoto et al., JJAP 46, p. 7251 (2007).
[3] J. Mitard et al., VLSI 2014, p. 34.
[4] C. H. Lee et al., IEDM 2010, p. 416.
[5] H. Arimura et al., IEDM 2015, p. 588.
[6] P. Ren et al., VLSI 2016, p. 32.
[7] H. Arimura et al., IEDM 2016, p. 834.

The use of high mobility SiGe channels in CMOS technology has been impeded by the presence of a high interface defect density between the SiGe and oxide layers. Ge-O_x suboxide bonds at the interface are the main source of these defects. By selectively forming Si-O_x bonds or suppressing formation of Ge-O_x bonds, the interface defect density can be minimized. The higher heat of formation of SiO_x compared with GeO_x can be used to selectively remove GeO_x using an oxygen scavenging metal as the MOSCAP gate metal [1,2]. Previously, Al gate metal has been demonstrated as reducing D_it for Al₂O₃. In the present work, Al gate metal is used to attain an even lower D_it using HfO₂ as the oxide and an optimized forming gas anneal. In this work, thermally deposited aluminum was used as an oxygen scavenging gate metal to achieve an ultra-low defect density of 3x10¹¹ eV^-1cm^-2 on ALD deposited Al₂O₃ and HfO₂ oxides on Si_0.3Ge_0.7(100). Aluminum gate metal MOSCAPs were also shown to have an order of magnitude lower leakage current than nickel gate MOSCAPS sweeping from -2 to 2 V_g. Ni gated MOSCAP showed a higher maximum capacitance (2.1 μF/cm²) in comparison with Al gated MOSCAPs (1.5 μF/cm²) due to the growth of Al₂O₃ during oxygen scavenging. STEM-EDS and EELS results confirm the oxygen scavenging mechanism by showing a silicon rich, sub 5Å thick SiGe-oxide interface.

References
[1] Kim, H., McIntyre, P. C., Chui, C. O., Saraswat, K. C. & Stemmer, S. Engineering chemically abrupt high-k metal oxide/silicon interfaces using an oxygen-gettering metal overlayer. J. Appl. Phys. 96, 3467–3472 (2004).
[2] Liu, C. W., Östling, M. & Hannon, J. B. New materials for post-Si computing. MRS Bull. 39, 658–662 (2014).

The high mobility semiconductor Ge is limited by the high resistance of its n-type contacts due to the Fermi level pinning (FLP) of Schottky barriers (SBs) close to the valence band maximum (VBM). It turns out that this pinning occurs only for SBs of elemental metals whereas the compound metals like germanides and silicides have a different experimental behavior [1]. This ‘extrinsic behavior’ in which the Schottky pinning factor, S, depends on both metal and semiconductor facet is potentially very useful and can be exploited to reduce the large n-Ge SBH. We studied this SBH effect using density functional supercell calculations. The S factor is found to vary from 0.5 to 0.3 for silicides on Si(100) to Si (111), and to 0.3 to 0.2 for germanides on Ge(100) to Ge(111), with also a strong dependence of the effective charge neutrality level’ on the facet. This behaviour is found to be consistent with early experimental results for Si(100) and Si(111) of Tung [2]. Interestingly, it contradicts some later experimental data for Ge [3], however the ability to make abrupt epitaxial Ge/germanide interfaces is much more difficult for the germanide system than for silicides [3], and it is proposed that the calculated germanide results are used as guidance for the Ge system.
[1] T Nishimura, T Yajima, A Toriumi, APX 9 085201 (2016)
[2] R Tung, JVST B 11 1546 (1993)
[3] P S Y Lim, Y C Yeo, APL 101 172103 (2012); Y Deng, S Zaima, Thin Solid films 557 84 (2014)

Future electronic systems may employ monolithic or heterogeneous integration of various material systems such as III-V, Ge, and Si to sustain the historical trend of performance enhancement of metal-oxide-semiconductor field-effect transistors (MOSFETs) for high performance and low power logic applications and to enable hybrid circuits consisting of nano-electronic and photonic devices on the Si platform.
In this paper, we present our recent research advances in heterogeneous integration of III-V and Ge-based devices on the Si substrate. In the first part, we discuss the application of the interfacial misfit (IMF) technique which is capable of relieving strain resulting from the large lattice mismatch between two materials and minimizing the formation of threading dislocations. A very thin buffer with sub-120 nm was used prior to the growth of the high-quality channel materials with this technique. Two integration schemes will be covered including the co-integration of vertically-stacked nanowire GaSb p-channel FETs (pFETs) and InAs n-channel FETs (nFETs) as well as the co-integration of Ge pFETs and InAs nFETs on Si substrates using common contact formation, digital etch, and gate stack formation modules. In the second part, we discuss our research effort to enable large-scale monolithic integration of opto-electronic devices for low cost and multi-functional opto-electronic integrated chips (OEICs). The monolithically integrated InGaAs FETs and GaAs/AlGaAs lasers on a Si substrate will be presented. The high-quality layers for the realization of InGaAs transistors and lasers were grown using molecular beam epitaxy (MBE) on a Si substrate using Ge and GaAs buffer layers. The InGaAs FETs show good electrical characteristics with high drive current, high I_ON/I_OFF ratio, and small subthreshold swing. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers were also realized at room temperature with a spectral linewidth of less than 0.5 nm.

Tunnel Field Effect Transistors have the potential to reduce the power consumption in logic operating at very low off-state current levels and at moderate switching speed. Key metrics include a high on-state current with a high I_on/I_off-ratio that needs to be combined with a low hysteresis. A low subthreshold slope combined with a high transconductance are needed to meet these requirements.
III-V nanowire Tunnel Field-Effect Transistors have demonstrated hysteresis-free operation of 48 mV dec with a I_on of 10 µA/µm for V_gs=0.3 V. Statistical analysis of a large number of transistors with subthermal operation show that the subthreshold slope mainly is limiting I_on for low V_ds (0.1) while g_m is limiting for higher V_ds (0.3V). Enhancing the transistor performance is thus not only related to the subthreshold slope, but also the on-state performance is critical. III-V heterostructures offers an excellent opportunity based on the wide range of the combinations possible.
The understanding of how different defects contribute to the measured I-V characteristics is essential to identify routes to improve the performance. Bulk traps, interface states, and oxide defects all contribute in different ways, as well as the possible contribution from gap states formed around the band edges. The different contributions may be quantified by careful I-V spectroscopy, demonstrating that such defects can be controlled on a sufficient level for advantageous Tunnel Field-Effect operation.
This work is supported by the Swedish Foundation for Strategic Research and the Swedish Research Council.

The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. We combine these two advantages and demonstrate for the first time a molybdenum disulfide (MoS₂) 2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack. This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 μA/μm, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS₂ negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied. In this talk, we will review the experimental progress at Purdue University on MoS₂ n-type 2D NC-FETs, WSe₂ p-type 2D NC-FETs, and nano-membrane β-Ga₂O₃ NC-FETs for wide bandgap CMOS applications.

Advanced logic CMOS devices require aggressive shrinking for performance and cost. Among many parameters to be scaled, it is particularly difficult to achieve the lowest threshold voltage (Vt) for p-FET (Field Effect Transistors) devices because of higher process sensitivity due to Fermi-level pinning and oxygen out-diffusion at high-k metal gate stacks. These challenges demand work function engineering for the future technologies. For reducing P-FET Vt, increasing the effective work function (EWF) can be one solution. There have been reports that oxygen has the property to boost the work function of the metals such as titanium silicon nitride, molybdenum and tantalum carbide [1-3].
In this paper, we demonstrate a method to reduce the p-FET Vt without the penalties associated with typical gate stack processing. We selected a Transition Metal Composite (here after, Metal-A) having a p-band edge work function as the metal gate for p-FET. Metal-A is deposited using Atomic Layer Deposition (ALD) on high-k dielectric layers, and also it is carefully treated using a modified oxidation method. Measurements from fully integrated advanced transistors showed around 80 mv of Vt modulation without degradation of the inversion thickness (T_inv), which means no increase of equivalent oxide thickness (EOT) through the modified oxidation.
For further understanding of the oxidation effect on EWF (Effective Work Function) change, ab-initio investigation was performed using stacks of Metal-A on a High-K layer (here, Hafnium oxide, HfO₂ was chosen as a general material). We computed the EWF from the interface dipole and the vacuum work function of the metal, which can eliminate the need to compute the band offsets. Thus, it avoids the errors introduced in the band structure and the valence band offset calculations.
By comparing EWF values computed for a defect-free-reference against EWF values for the same reference containing oxygen defects at or near the HfO₂/Metal-A interface, we found that the presence of oxygen vacancies (Vo) and oxygen interstitials (Oi) plays a big role in modulating the interface dipole. Furthermore, when oxygen interstitials are incorporated in the bulk Metal-A, the resulting EWF is substantially higher. Based on the simulation, we explain the physical mechanism of EWF modulation (accordingly, Vt modulation) obtained in the above experiments: (1) the oxygen atoms diffused from Metal-A replace Vo in high-k layer and also modify the dipole configuration and (2) the residual oxygen interstitials in the Metal-A also increase the bulk EWF value. These results clearly demonstrate the possibility of EWF engineering towards the p-FET band edge in advanced FETs through the proposed modified oxidation method.
[1] H. Luan, et.al., App. Phys. Lett, vol. 88, p. 142113, 2006.
[2] Z. Li, et. al., J. Electrochem. Soc., vol. 155 pp. H481-H484, 2008.
[3] W. Mizubayashi, et. al., VLSI Technology, 2008 Symposium on pp. 42-43, 2008.

We report the depletion of silicon dopants at the surface of epitaxially grown in-situ doped InAs layers. The lower concentration of Si doping at the surface is technologically significant as it leads to increase in contact resistance.
The depletion of Si was observed in metal-organic chemical vapor deposition (MOCVD) grown Si doped InAs layers as well as in InAs layers grown by atomic layer epitaxy (ALE). In situ doping was employed to make InAs layers with [Si] concentration from 2E18 to 8E19 cm^-3.
Secondary ion mass spectrometry (SIMS) was used to study the Si profile in the Si doped InAs layers. It was found that the silicon depletion was larger for higher doping levels of Si in the bulk of the InAs layer. The Si depletion extends to about 5 nm from the InAs surface. We have employed Ultra-Low Energy (ULE-) SIMS (250 – 400 eV Cs+ ion impact energy) to demonstrate that the Si depletion width extends well beyond the InAs native oxide thickness and SIMS surface transient depth.
The top 8 nm of the InAs layers were controllably etched by self-limited digital etching to remove the Si depleted region. The SIMS Si profile of etched InAs does not exhibit Si depletion, thus suggesting that depletion of Si atoms near the surface takes place during the layer growth.
Co-doping the InAs layer with silicon and zinc (a p-type dopant) did not change the Si depletion profile near the surface. This suggests that the depletion of the silicon atoms near the surface is not a result of an electrical field induced by surface pinning [1].

References:
1. E. F. Schubert, Doping in III-V Semiconductors, Cambridge university press, 1993.

An attractive approach to realizing enhancement-mode (E-mode) GaN-based lateral heterojunction power transistors is to recess the barrier layer under the gate electrode, and thus remove the inherent positive polarization charges to obtain positive threshold voltage V_TH [1]. To suppress the gate leakage, the barrier layer should be replaced by insulating gate dielectric, forming a fully recessed MIS-FET or partially recessed MIS-HEMT. High electron mobility in the gate-controlled channel is maintained in MIS-HEMT with a thin barrier layer. However, the manufacturing of MIS-HEMT faces challenge in V_TH uniformity control due to difficulties in precisely controlling the recess etching depth. In addition, the buried-channel MIS-HEMT typically exhibits worse V_TH thermal stability than the surface-channel MIS-FET [4] as a result of the floating dielectric/AlGaN interface. Thus, the E-mode fully recessed MIS-FET possesses practical benefits in terms of manufacturing capability and device stability.
Obtaining high-quality interface with low D_it is one of the most critical challenges in MIS-gate. According to a first-principles calculation study, the GaN surface states distribution can be modified by nitridation with the shallow trap (i.e. close to E_C) density greatly reduced [2]. Interface protection is another technique to prevent the GaN surface from degradation at high temperatures (~ 800 ^oC) [3] at which high-quality gate dielectric is deposited. The high temperature is necessary to obtain a densified dielectric film with reduced defect density. With these techniques, SiN_x gate dielectric (with the benefits of large conduction band offset of ~2.3 eV with GaN and relatively high dielectric constant of 7) deposited at 780 ^oC by LPCVD (low pressure chemical vapor deposition) is successfully integrated with recessed-gate structure to obtain E-mode MIS-HEMT/FET with enhanced V_TH stability and gate dielectric reliability.
Both MIS-FETs and MIS-HEMTs exhibit small hysteresis △V_TH < 0.1 V and low subthreshold swing SS ~ 97 mV/dec, benefiting from the greatly improved interface quality. As fully-recessed gate can reduce the sensitivity of V_TH on the recess depth, higher V_TH uniformity is obtained in MIS-FET. The MIS-FET also has more positive V_TH (~2.4 V) than MIS-HEMT (~0.4 V). R_ON of MIS-FET (~13 Ω●mm) is slightly larger than that of the MIS-HEMT (~10 Ω●mm) due to lower MIS-channel electron mobility. The MIS-FET has a much better V_TH stability than the MIS-HEMT, benefiting from the limited movement of E_F at dielectric/GaN interface. In addition to thermal stability, the V_TH of MIS-FET also shows better stability in long time NBTI stress.
In summary, surface nitridation and interface protection play critical roles in enabling a high-quality dielectric/III-N interface with low D_it. The fully recessed MIS-FET possesses many advantages in larger recess-depth tolerance, more possitive V_TH, and higher V_TH stability.

Silicon germanium (SiGe) channels are being developed for CMOS technology due to their high intrinsic carrier mobility. The superior properties of SiGe can be utilized only if SiGe-high k interfaces with a low interface defect density (D_it) can be fabricated. Germanium oxide (GeO_x) is known to be the source of interface defects and by selective reduction, selective removal of GeO_x, or selective formation of interfacial silicon oxide (SiO_x), low-defect interfaces can be formed. Previously, ozone has been employed to form a GeO₂ rich interlayer on high Ge content SiGe to passivate the interface (1). In this work, a new method, selective oxidation with ozone nano laminate, was employed; in this method, ozone pulses are dispersed evenly within the HfO₂ during ALD HfO₂ deposition. Optimized ozone pulsing between 5nm thick HfO₂ oxide layers reduced the defect density by 60% compared to standard HfO₂ ALD on the same samples. With the ozone nanolaminate and optimized forming gas anneal, an interface defect density of D_it=5x10¹¹ eV^-1cm² with accumulation capacitance of 1.75uF/cm² was demonstrated for the HfO₂/Si_0.7Ge_0.3 interface. The distribution of the defect density across the band gap was calculated according to full interface state model and integrated Dit of <1x10¹¹ eV^-1cm² was obtained. High resolution STEM images shows thin interface and Si enriched composition compared to the bulk was observed in STEM-EELS and EDS analysis. The data demonstrates that dry selective oxidation can be used to form the SiOx layer required to passivate Si_0.7Ge_0.3(001).

References
Ando et al, IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 3, MARCH 2017

In recent years, much effort has been made to find alternative materials and geometries to achieve ultra-small stable electronic devices. Among all, high electron mobility transistors (HEMTs) are very promising in terms of both high carrier mobility and high breakdown voltage. However, the commonly used AlGaN/GaN interface still shows limitations, such as high defect concentrations and gate leakage, that need to be overcome. For this reason, the exploration of novel ternary and quaternary nitrides, as well as the engineering of their lattice parameters, band gaps and their relationship, have been encouraged.
Transition metal nitrides (TMN) have recently received increasing attention due to their unique electronic and structural properties [1]. The optoelectronic properties of Sc_xGa_1-xN are very interesting for HEMTs: ScN and GaN are stable in two different structures, therefore, as x increases from 0 (GaN) to 0.5 (Sc_0.5Ga_0.5N) the wurtzite structure distorts, the c/a ratio decreases, eventually producing a structural phase transition to a non-polar 5-fold coordinated hexagonal crystal structure. In the composition range around this phase transition, Sc_xGa_1-xN shows unique properties, such as huge piezoelectric constant, high electron mobility, and good lattice match with GaN.
Another interesting TMN material for electronic application is FeGaN [2]. If GaN is doped with small concentration of iron, the thin film shows semi-insulating properties with high quality structure and high resistivity. When FeGaN is employed in HEMTs, its semi-insulating behaviour will better isolate the device by lowering the leakage from both the gate and the substrate interfaces.
In addition, the quaternary material FeScGaN is expected to show intermediate properties between the two ternary TMN materials. Thus, if it is employed in ScGaN/GaN HEMTs, the gate leakage will decrease without introducing lattice-mismatch defects at the FeScGaN/ScGaN interface.
To successfully employ these novel materials in HEMT devices, it is then necessary to achieve deep knowledge of both their electronic and structural properties. For this reason, ScGaN, FeGaN and FeScGaN thin films are grown on sapphire using Electron Beam Epitaxy technique and then fully characterized. HR-TEM, STEM, XRD are used to explore the change in the microstructure of all the thin films for different TM content. SIMS is employed to calculate both the TM element content and the level of impurities in each film. Finally, the electron mobility, band gap and Raman shift are reported to investigate the electronic and optical properties of these materials and their dependence on the TM concentration.
These TMNs show high-quality crystal structures and larger band gap for higher TM content; from these preliminary results ScGaN, FeGaN and FeScGaN seem to be promising materials for enhanced electronic devices.

[1] M.A. Moram S. Zhang, J Mater Chem A, 2014,2, 6042-6050
[2] A. Bonanni, Semicond Sci Technol, 2007, 22, R41-R56

Introduction
The effect of the annealing temperature on the perpendicular magnetic anisotropy (PMA) of composite structures was studied. We merged a MgO/CoFeB bilayer [1] and an ultra-thin [Co/Pd]6 multilayer separated by a non-magnetic Ta spacer [2] of variable thickness tTa. Composite magnetic structures with PMA are technologically relevant in developing high-density memory devices.
Experimental Procedure
The stacks were deposited using magnetron sputtering at room temperature in the absence of an external magnetic field. Thermally oxidized (100) Si wafers were used as substrates. After deposition, samples were heat-treated for 2 hrs. at 250, 300, or 350 C in a high-vacuum magnetic annealing oven with a field of 5 kOe perpendicular to the film plane. Magnetic properties were studied by using an alternating gradient magnetometer (AGM) where magnetization vs. applied
magnetic field (M-H) hysteresis loops were obtained with either out-of-plane or in-plane magnetic fields.
Results
Hysteresis loops show sharp switching characteristics indicating ferromagnetic coupling between the MgO/CoFeB bilayer and the Co/Pd multilayers. Structures lacking a Ta layer show not PMA regardless of whether or not they were magnetically annealed. PMA is obtained after inserting a Ta layer and is observed even in the as-prepared state [3].
Conclusions
Our results show that Ta layer is essential for obtaining perpendicular axis in the composite MgO/CoFeB/Ta/[Co/Pd]6 structure. Composite structures retain PMA upon magnetic annealing up to 350 C. The ferromagnetic exchange was strong enough to switch MgO/CoFeB and [Co/Pd]6 together, with the magnetic moment either lying along the film plane when tTa = 0, or pulled out of the film plane when tTa ≠ 0. No antiparallel magnetic coupling was observed within the Ta thickness interval explored (0 ≤ tTa ≤ 0.7 nm). Perpendicular composite structures with sharp magnetization reversal and annealing stability are relevant in perpendicular CoFeB-based magnetic tunnel junctions for the development of gigabit-scale nonvolatile memory.

Ultra-shallow junctions have become more desirable in the semiconductor industry as devices have continued to shrink in size and non-planar devices such as FinFETs and 3D nanostructures have become more common. Semiconductor devices are traditionally doped using a combination of ion implantation or spin-on dopant and thermal diffusion techniques; however, these have limitations such as crystalline damage, use of hazardous chemicals, or glassy skin formation. Monolayer doping (MLD) is an attractive alternative for forming sub-50 nm junctions. A dopant-containing compound forms a conformal self-assembled monolayer on the surface, then is capped with an insulating oxide and activation via rapid thermal anneal to form an ultra-shallow junction. The monolayers are formed with a phosphorous-containing compound for n-type doping, and a boron-containing compound for p-type doping. Techniques such as SIMS and sheet resistance measurements are used to characterize junctions and doping profiles. P+N and N+P diodes are fabricated and characterized. An in-house process for fabricating MOSFETs utilizing MLD for source/drain doping is developed. Electrical data on sub-50 nm emitter diodes and MOSFETs will be presented.

Ferroelectric Zr doped in HfO₂ as gate stack has been intensively and extensively investigated to integrate with FETs due to following current CMOS architectures and feasibility ALD (atomic layer deposition) supercycle approach [1][2]. The bi-stable state feature of hysteresis loops by ferroelectric materials satisfies the demands of voltage amplification concept for negative capacitance (NC) [3][4] and storage signal purpose for memory [5].
The discussion about NC reliability with sub-2.3k_bT/q SS and wake-up effect is demonstrated. The ferroelectric (FE) coercive voltage for dipole switching is effectively reduced to a practicable NC onset voltage (<1V) after wake-up. This is one of ferroelectric characteristics for complete dipole switching beyond coercive voltage [6]. In order to observe this phenomenon of NC-FETs, the 5nm FE-HZO FETs are performed double sweep with the range from small to large. In order to reach the FE/NC region, the applied voltage needs high enough for complete dipole switching, and coercive E-field approaches to 2MV/cm. A gradual transition of ferroelectricity with crystallization temperature increasing results in subthreshold swing (SS) < 60mV/dec and hysteresis loop formation. The device by gate-last is more stable than that of gate-first due to well Source/Drain activation. It is promising to use ultra-thin FE-HZO as the guidelines for NC and memory applications. To develop a practicable FE-coercive/NC-onset voltage is an important issue for evaluating this technology.
The authors are grateful for the funding support from the National Science Council (MOST 105-2628-E-003-002-MY3, 106-2221-E-003-029-MY3 & 106-2622-8-002-001), process supported by National Nano Device Laboratories (NDL) & Nano Facility Center (NFC), Taiwan.
Reference:
[1] M. H. Lee et al, IEEE J. of the Electron Device Society, vol. 3, no. 4, pp. 377-381, 2015.
[2] M. H. Lee et al, IEEE Electron Device Letter, vol. 36, no. 4, pp. 294-296, 2015.
[3] S. Salahuddin and S. Datta, NanoLetters, vol. 8, no. 2, pp. 405-410, 2008.
[4] S. Salahuddin and S. Datta, in IEDM Tech. Dig., 2008, pp. 693-696.
[5] J. Müller et al, in Symp. on VLSI Technology and Circuits, 2012, pp. 25-26.
[6] P. Sharma et al, in Symp. on VLSI Technology and Circuits, 2017, pp. T154-T155.

In the continuous scaling down of the device for logic circuits, germanium has been considered as a candidate for high performance logic device because of its high mobility. [1,2] However, one of the most difficult challenge in realizing high performance device on germanium is the reduction of source/drain (S/D) resistance because of its low dopant solubility. [3] The use of the shallow metal S/D is a likely way to solve this limitation. The research of germanide/germanium Schottky junction has been popular in recent years. [4] In this paper, we propose a simple, novel and reliable technique to modulate the barrier height of NiGe/n-Ge contact formed by microwave annealing (MWA) with capping another pure metal on top of NiGe. [5,6] The physical and electrical properties of capping metals on NiGe/n-Ge Schottky junctions will be discussed by depositing various work function metals (Al (4.26 eV), Ti (4.33 eV), Ni (5.15 eV) and Pt (5.65 eV)) [7,8] as capping metals.
After DHF cleaning on (100)-oriented n-type Ge substrate, the 10-nm-thick Ni was deposited by physical vapor deposition (PVD). Next, MWA (5.8 GHz, 600W, in N₂ ambient, for 150 s) was performed for NiGe alloy formation. The X-ray diffraction (XRD) pattern shows that NiGe was the only phase formed by MWA. The transmission electron microscopy (TEM) figure shows that the 10-nm-thick Ni was consumed completely and transformed into a smooth and 20-nm-thick NiGe was formed by MWA. And the energy dispersive spectroscopy (EDS) analysis is consistent with XRD pattern on NiGe composition. Afterwards, various 100-nm-thick metals with different work function were deposited by PVD including Al, Ti, Ni and Pt.
Upon completion of the process mentioned above, we obtained NiGe Schottky junctions with various work function metals as capping metal. The first thing we want to mention is the ION/IOFF ratio. With different work function metals as capping metal including Al, Ti, Ni and Pt, the ION/IOFF ratio at +/- 1V are 2.89×10⁴, 6.50×10⁴, 9.12×10⁴ and 1.31×10⁵ respectively. Furthermore, we obtain the difference of Schottky barrier height (SBH) from 0.570 eV to 0.591 eV between Al and Pt as capping metal. These two results indicate that with different work function metals as capping layer, we can modulate the SBH of NiGe/n-Ge junction so that we can improve the ION/IOFF ratio. The last thing we want to mention is the ideality factor. The ideality factors of Al, Ti, Ni and Pt as capping metal are 1.28, 1.21, 1.13 and 1.12 respectively indicating that the higher work function of capping metal is the more approaching-to-one ideality factor is. In conclusion, by choosing higher work function metal as capping metal on NiGe, we can improve the performances of the NiGe/n-Ge Schottky diode with higher on current, ION/IOFF ratio, lower leakage current and closer to one ideality factor by SBH modulation. This is simple, novel and suitable technique for fabricating high performance Schottky Ge pMOSFET.

Among the members of tin-chalcogenides family, the narrow-band semiconductor SnTe has recently emerged as a 3D crystalline topological insulator (TCI) exhibiting band inversion at the L point where certain crystalline symmetries allow the protection of robust topological states at the surface. We investigated the electronic band structures of pristine P-doped SnTe doped using density functional theory (DFT) calculations followed by synthesis. The substitution of a Sn vacancy by P maintained the intrinsic band inversion at the L point but the direct band gap reduced to 30 meV upon the incorporation of spin orbit coupling (SOC), which is relatively smaller than the experimentally observed band gap of pristine SnTe. The experimental methods for P-doped SnTe synthesis was based on the vapor-liquid-solid technique. The morphology of the synthesized crystals was exotic in the form of micro-needles, as a consequence, it led to the amplification of signal arising from the topological surface states due to the reduction of surface area to volume ratio. Moreover, the modified effective mass, lattice imperfection and related charge carrier conductivity acted as our motivation to implement them in Ferro-electric Field Effect Transistor (FeFET). The application of a cyclic potential resulted in an exceptionally large memory window of 3.1 V accompanied by a drastic current change within a certain potential range.

We present some recent results on the transient electron transport that occurs within bulk alloys of zinc-magnesium-oxide. These results are obtained using an ensemble semi-classical three-valley Monte Carlo simulation approach. Starting with steady-state electron transport simulations, we find that, for electric field strengths in excess of 180 kV/cm, that the steady-state electron drift velocity associated with these alloys exceeds that associated with bulk wurtzite gallium nitride. We also present evidence that suggests that the negative differential mobility exhibited by the velocity-field characteristic associated with alloys of zinc-magnesium-oxide is not related to transitions to the upper valleys. The transient electron transport that occurs within this alloy is then studied by examining how electrons, initially in thermal equilibrium, respond to the sudden application of a constant electric field. From these transient electron transport results, we conclude that for devices with dimensions smaller than 0.1 microns, gallium nitride based devices will offer the advantage, owing to their superior transient electron transport, while for devices with dimensions greater than 0.1 microns, electron devices based on alloys of zinc-magnesium-oxide will offer the advantage, owing to their superior high-field steady-state electron transport. The device implications of these results will be explored. Our results show that the Monte Carlo simulations of the materials response to the instant change of the electric field could be used for establishing the figures of merit for materials applications for short channel ultra high-speed semiconductor devices.

We study how electrons, initially in thermal equilibrium, drift under the action of an applied electric field within bulk wurtzite zinc oxide. We find that the optimal cut-off frequency ranges from around 50.3 GHz when the device thickness is set to 1000 nm to about 11.5 THz when the device thickness is set to 10 nm. These results suggest that zinc oxide holds great promise for future high-speed electron device applications.

Unlike graphene, the existence of bandgaps in transition metal dichalcogenides such as MoSe₂ offers an attractive possibility of using single layer MoSe₂ field-effect transistors (FETs) in low-power switching devices and photodetectors. Yet, the fabrication demands and the physics of MoSe₂, among other reasons, suggest that multilayer MoSe₂ may be more attractive than single layer MoSe₂ for FET applications in a thin-film transistor configuration. In this presentation, we explore the optoelectronic properties of bottom-gate multilayer MoSe₂ phototransistors fabricated on SiO₂/Si substrates with mechanically exfoliated flakes. Our MoSe₂ phototransistors exhibit decent field-effect mobilities (> 50 cm² V^-1 s^-1) and high on/off-current ratio (> 10⁶). For 650 nm incident laser, the device shows high photoresponsivity (> 500 A W^-1) , high detectivity (> 10¹¹ jones) and a fast response time (< 2 ms) at room temperature. These optoelectronic properties are better than those of MoSe₂ phototransistors reported in literature. These results demonstrate a compelling case of multilayer MoSe₂ phototransistors for applications in photodetectors.

Unlike graphene, the existence of direct bandgaps in transition metal dichalcogenides such as MoS₂ offers an attractive possibility of using single layer MoS₂ in optoelectronic devices. Because of the absence of dangling bonds in MoS₂, surface treatment such as ultraviolet-ozone (UV-O₃) treatment is necessary before the deposition of high-k dielectrics on MoS₂ to fabricate optoelectronic devices such as phototransistors. However, little interest has been given to the effect of UV-O₃ treatment on the optoelectronic properties of single layer MoS₂. In this presentation, we systematically investigate the effect of UV-O₃ treatment on the photoluminescence of mechanically exfoliated single layer MoS₂ flakes. We observe photoluminescence quenching in single layer MoS₂, accompanied by reduction and broading of MoS₂ Raman modes with increasing UV-O₃ treatment time. X-ray photoelectron spectroscopy confirms the formation of oxygen bonding. We demonstrate that the formation of oxygen bonding upon exposure to UV-O₃ treatment leads to a direct-to-indirect bandgap transition in single-layer MoS₂. These results also demonstrate the significant impact of UV-O₃ treatment on the optoelectronic properties of single layer MoS₂ suggesting the importance of using optimized process conditions.

Unlike graphene, the existence of direct bandgaps in transition metal dichalcogenides such as MoS₂ offers an attractive possibility of using single layer MoS₂ in transistors, sensors, optoelectronic devices, and flexible systems. Because of the absence of dangling bonds in MoS₂, surface treatment such as ultraviolet-ozone (UV-O₃) treatment is necessary before the deposition of high-k dielectrics on MoS₂ to fabricate various devices. However, little interest has been given to the effect of surface oxidation of single layer MoS₂ by UV-O₃ treatment. In this presentation, we systematically investigate the effect of UV-O₃ treatment on the monolayer MoS₂ thin films obtained by chemical vapor deposition (CVD). We observe photoluminescence quenching in monolayer MoS₂ thin films with increasing UV-O₃ treatment time. We also observe the reduction and broading of MoS₂ Raman modes with increasing UV-O₃ treatment time. X-ray photoelectron spectroscopy indicates the nature of oxygen bonding changes with increasing UV-O₃ treatment time. These results demonstrate the significant impact of surface oxidation by UV-O₃ treatment on monolayer MoS₂ thin films suggesting the importance of using optimized surface treatment conditions for device applications.

The introduction of III-V materials onto a Si-platform has been of tremendous interest for a very long time. III-V compound semiconductors high electron mobility and direct bandgap properties have been deemed to be the solution to the scaling problems in Si CMOS (complementary metal oxide semiconductor) transistor, through the use of high mobility channel and light emitting devices for optical interconnects. The application of such technology, however, is hindered by numerous issues. The considerable lattice mismatch between Si and high mobility III-V materials (i.e., (In)GaAs, InAs, GaSb, and InSb) and the lack of processes that are amiable to Si manufacturing environment for surface passivation, gate stack dielectric, and metal contacts schemes are some of them. Furthermore, as the substrate cost difference between III-V wafers and Si wafers is significant, a way to reuse and recycle the III-V substrates or create new III-V-on-Si substrates is needed.

In this work, a variety of solutions to bridge the lattice constant gap and to realize III-V CMOS and III-V laser on Si-based substrates will be highlighted. A combination of high-temperature annealing, migration enhanced epitaxy and buffer engineering techniques was developed on a Si-based substrate to minimise anti-phase boundary and threading dislocation defects. Two different buffer engineering were explored, an approximately 800nm-thick graded InAlAs buffer for lattice constant = InP lattice constant and a thinner interfacial misfit (IMF) buffer for lattice constants ≥ 6.0Å. The graded buffer approach was deployed to demonstrate InGaAs nFET and InGaAs n-FET monolithically integrated with AlGaAs/GaAs multiple quantum well laser on GeOI (germanium on insulator) substrate. Furthermore, the IMF sub-120 nm buffer approach allows integration of highly mismatch materials on GeOI substrate without having to go through a thick graded buffer process. This buffer technique alleviates some of the fabrication process challenges caused by the significant step height difference which exists where the graded buffer was used and allows a common gate stack formation processes to be developed. The use of IMF buffer enables demonstration of novel III-V (InAs) n-FET and (GaSb) p-FET or InAs n-FET and Ge p-FET monolithically integrated on the same Si-based substrate with excellent I_ON performance. Some III-V (InAs and InSb) and Ge(Sn) photodetectors grown on Si-based substrate operating at the mid-IR range will also be presented. Lastly, GaAs/Si heterogeneous wafer bonding with a specific bond energy of 478 mJ/m2 was realized at an annealing temperature as low as 140°C following a plasma activation step. This can potentially be combined with epitaxial lift-off processes to create new III-V on insulator wafers. The work done in this report was supported by the Singapore National Research Foundation through a Competitive Research Program (Grant No: NRF-CRP6-2010-4).

The voltage controlled charge-density-wave (CDW) phase transition in quasi-2D 1T-TaS₂ offers a possibility of using the switching behavior of these macroscopic quantum states for electronic applications. We have recently demonstrated a frequency tunable oscillator based on an integrated graphene–h-BN–TaS₂ device that is capable of operating at room temperature [1]. The carrier concentrations in the nearly commensurate (NC) and incommensurate (IC) CDW phases in 1T-TaS₂, which are utilized for switching the device, are very high, on the order of 10²¹ cm^-3 and 10²² cm^-3, respectively. The high carrier concertation creates conditions for resilience to the total ionizing dose (TID) effect, which is radiation damage to semiconductor device in space and high-energy accelerator environment. In conventional MOSFET, electron–hole pairs generated in the oxide during TID irradiation can accumulate in the oxide layers and interfaces, leading to the shifts in the threshold voltage and increase in the leakage current. Unlike conventional field-effect-transistors (FETs), the 1T-TaS₂ device is a two-terminal CDW device, in which the switching is controlled by the source-drain voltage rather than the gate voltage. No gate oxide is needed for its operation [1]. In this work, we evaluate the TID response of 1T-TaS₂ CDW devices by examining the current-voltage (I-V) characteristics under X-ray irradiation at doses up to 1 Mrad(SiO₂). We find that the threshold voltage, V_TH, for the abrupt resistance change shifts by only ~2%, the resistance of the CDW states changes by less than ~2 % (low resistive state) and ~6.5 % (high resistive state), and the self-sustained voltage oscillations in this 1T-TaS₂ oscillator function well after the full irradiation sequence [2]. The obtain results indicate that 1T-TaS₂ CDW devices are promising for applications in space and other high-radiation environments.

The work at UC Riverside was supported, in part, by NSF EFRI 2-DARE project: Novel Switching Phenomena in Atomic MX₂ Heterostructures for Multifunctional Applications and by UC-National Lab Collaborative Research and Training Program.

[1] G. Liu, B. Debnath, T. R. Pope, R. K. Lake, T. T. Salguero and A. A. Balandin, Nature Nanotechnology, 11, 845 (2016).
[2] G. Liu, E. X. Zhang, C. D. Liang, M. A. Bloodgood, T. T. Salguero, D. M. Fleetwood, A. A. Balandin, IEEE Electron Device Letters (accepted, 2017) 10.1109/LED.2017.2763597.

Silicon-on-Insulator (SOI) technology possesses many advantages over bulk silicon such as the reduction of parasitic capacitances, excellent subthreshold slope, elimination of latch up and resistance to radiation [1]. For these reasons, SOI is the preferred technology for high-speed, high-temperature, and low-power microelectronic devices. SOI MOSFET devices employ a buried insulating thin layer, usually made of SiO₂ to electrically isolate devices from the bulk semiconductor. Due to the poor thermal conductance, the buried dielectric layer thermally insulates the MOSFET from the bulk [2]. Consequently, the heat generated in SOI MOSFETs causes a larger temperature rise than in bulk devices under similar conditions, and this self-heating effect results in reduced carrier mobility and a corresponding decrease in the transconductance and speed. The self-heating effect can have significant impact on the device reliability as well.
This paper is an attempt to understand the effects of heat generation in SOI technology using a multiscale simulation and modeling scheme developed at Arizona State University in collaboration with IMEC in Belgium [3]. This scheme allows for simulation of carrier self-heating in the device and the corresponding thermal transport at the interconnect level, both at the same time. Previous work has successfully simulated self-heating in bulk devices, but this work strives to model the self-heating in SOI devices.
This scheme involves two components: 1). A numerical device level simulator that uses the Monte Carlo (MC) method to solve the Boltzmann transport equation (BTE) which is coupled with a Poisson solver to evaluate the charge distribution, while a self- consistent, energy balance equation is solved for optical and acoustic phonons to account for the self-heating effects. 2). The device simulator is coupled to a Silvaco module which solves for thermal transport in circuit interconnects using the Fourier law. Hence this multi-scale thermal simulation and modeling scheme is capable of analyzing thermal effects in nanoscale integrated electronics.


[1] R. Chau, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros, and M. Metz, “Silicon nano-transistors and breaking the 10 nm physical gate length barrier,” in Proc. Device Res. Conf., Jun. 2003, pp. 123–126.
[2] T. Numata and S. Takagi, “Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2161–2167, Dec. 2004.
[3] S. S. Qazi, A.R. Shaik, R.L. Daugherty, A. Laturia, X. Guo, E. Bury, B. Kaczer, K. Raleva and D.Vasileska, “Multi-scale modeling of self-heating effects in silicon nanoscale devices”, proceedings of the 15th International Conference on Nanotechnology (IEEE NANO), Rome, Italy, pp. 1461 - 1464, 2015.

Two-dimensional hafnium diselenide (HfSe2) and hafnium disulfide (HfS2) have impressive theoretical properties but are among the less well-studied transition metal dichalcogenides. Further research is needed to realize high-performance Hf-based devices. We investigated the air stability of mechanically exfoliated layers of HfSe2 and HfS2 via atomic force microscopy and Raman spectroscopy studies. With continued exposure to air, the surface of HfSe2 progressively transforms from HfSe2 to HfOx and Se, as confirmed by changes in Raman spectra and by the appearance of Se-rich, spire-like features. We determined that sample thickness, total time of air exposure and and exfoliation in a glove box versus in air all affect the degree of transformation. HfS2 was much more stable in air and served as a comparison for the study of HfSe2. This work lays out initial steps toward controlling the behavior of HfSe2 surfaces, which can inform future efforts to fabricate Hf-based transistors.

The integration of complementary metal-oxide-semiconductor field effect transistors (CMOSFET) with photonics requires photodetectors to operate at hundreds of giga hertz (GHz). This can be achieved by scaling down the size of photodetectors ^[1]. But a smaller device volume will reduce the light absorption, resulting in a poorer photosensitivity. High gain photodetectors such as avalanche photodetectors are often employed for such applications. Unfortunately, such photodetectors suffer from excessive avalanche noises in particular when the devices operate at high gain. In this work, we develop a novel core-shell nanowire phototransistor that has a gain of 10⁶ and a potential 3dB bandwidth of ~300 GHz. The device is made on a highly doped p-type silicon nanowire that is patterned out of the device layer of a silicon-on-insulator (SOI) wafer. A section of the nanowire is doped to be n-type by self-assembled molecular monolayers ^[2-3], forming a core-shell pn junction around the nanowire like a structure of “a ring on a finger”. For an appropriate nanowire width, the pn junction will pinch off the nanowire channel without voltage bias. Under light illumination, the channel will open, inducing a high saturation photocurrent. Experimental results show that the nanowire phototransistors show a photoresponsivity of 10⁶ A/W with a potential 3dB bandwidth of 300GHz.

References
[1] O. Hayden, R. Agarwal, and C. M. Lieber, “Nanoscale avalanche photodiodes for highly sensitive and spatially resolved photon detection,” Nat. Mater. 5(5), 352–356 (2006).
[2] Ho, J. C. et al. Controlled nanoscale doping of semiconductors via molecular monolayers. Nat. Mater. 7, 62–67 (2008).
[3] Guan, B. et al. Nanoscale Nitrogen Doping in Silicon by Self-Assembled Monolayers. Sci. Rep. 5, 12641 (2015).

This work explores the thermal and electrical characteristics of CMOS devices and circuits using a multiscale dual-carrier approach. Simulating for electron and hole transport simultaneously allows for complementary logic gates to be simulated at the device level, while current and voltage continuity are maintained at the circuit level. Further, the electrical model couples with a multiscale thermal solver, which solves for electron-phonon and hole-phonon interactions at the device level and phonon-phonon thermal transport in the packaging level. This methodology allows for the study of package level thermal transport without sacrificing the nuances of device self-heating, ultimately providing a more comprehensive understanding of how these interactions affect power consumption in CMOS systems.

The electrical model is comprised of an ensemble Monte Carlo simulator coupled with a Poisson solver. This framework provides accurate electrical characteristics in quasi-static regimes by iteratively solving for the potential profile and the electric fields then simulating the effect of the electric field on charge carriers. The Monte Carlo simulator solves the Boltzmann Transport by balancing each particle’s movement in real and momentum space with the collision integral through probabilistic scattering mechanisms. This framework provides current and voltage characteristics for each device; current and voltage continuity are maintained by solving at the circuit level.

Similarly, the methodology for simulating thermal characteristics includes two scales. At the device scale, the energy balance equation determines the transfer of energy from charge carriers to phonons. High-energy electrons or holes relinquish energy to optical and acoustic phonons through scattering and optical phonons decay into acoustic phonons. At the package level, a Fourier law solver simulates the subsequent conduction of heat in the form of lattice vibrations.

This framework proved effective in previous simulations for the electro-thermal characteristics in NMOS devices. This work demonstrates the effectiveness of the dual-carrier electrical solver in simulating CMOS circuits. Future work requires the coupling the dual-carrier electrical solver with the previously proven thermal solver to provide comprehensive electro-thermal simulations of CMOS systems.

The memory effects in a memristor can be realized through the switching behavior between two distinct resistance states, low resistance state (LRS) and high resistance state (HRS) driven by low pulse voltages. ZnO-based thin films such as undoped ZnO, Mg-doped ZnO, Na-doped ZnO and Mn-doped ZnO have attracted considerable interest as promising resistive switching materials. Gallium doping electrically modulates the behavior of ZnO to suit low power switching behavior. Non-lattice oxygen ions and oxygen vacancies as detected by XPS are found to play important role in imparting forming-free resistive switching behavior.All deposition for fabrication of device has been done by dual ion beam sputtering(DIBS).

To start with fabrication of device, a 60 nm thick Ga-doped ZnO thin film as switching layer is deposited over bottom electrode (BE) Au/SiO2/Si, at a substrate temperature of 100 °C, with DIBS background pressure of 1 × 10^-8mBar and Ar:O₂ (1:4) (flow rate in sccm), respectively. Finally, circular Au electrodes of 300 µm is deposited on the surface of switching layer. Similarly, Al/ZnO/Al/SiO₂/Si device is fabricated to compare the electrode and doping effect using Ar:O₂ (2:3) and substrate temperature of 400 °C. The current-voltage (I-V) characteristics of the device are measured using Keithley 2612A sourcemeter and Everbeing probe-station. Al(BE)/ZnO interface has been observed by cross-sectional high-resolution transmission electron microscopy (HR-TEM) using HR-TEM: JEOL JEM-2010 for formation of any AlO_x layer. X-ray photoelectron spectroscopy (XPS) having PHOIBOS 100 analyzer with an Al Kα radiation (1486.6 eV) as an excitation source, has been utilized to analyze the binding energy and the composition of each element in switching layer.
I-V characteristics are measured by sweeping a DC voltage in sequence of 0-10 mV-0--10 mV-0 in steps of 1 mV and 0-(+8 V)- 0-(-8 V)-0 in steps of 0.5 V for both devices respectively with a compliance current of 1 mA. I-V of Al/ZnO/Al (AZA) shows device with varying ramp rate exhibiting decreasing hysteresis with increasing ramp rate. Similarly I-V for Au/Ga-ZnO/Au (AuGZAu) conforms to zero crossing of I-V hysteresis loop and shrinking of loop area with increasing ramp rate. Device sets and resets to lower voltage as compared to AZA device. XPS of the switching layer conforms to presence of oxygen vacancies and non-lattice oxygen ions which assist in switching. An amorphous AlO_x interfacial layer (~4-5 nm) [5] formed at Al(BE)/ZnO interface as confirmed by HRTEM for the device in high resistance state (HRS) state which assists in set/reset process.

Ga doping increases conductivity of ZnO film and hence sets and resets at lower voltages. AuGZAu device depicts unipolar memristive behavior as it shows pinched hysteresis with varying frequency, whereas AZA behaves as an ideal bipolar memristor with good endurance and retention. AuGZAu device can be utilized for low power resistive switching.

Herein, we have reported on structural, chemical and electronic properties of two-dimensional (2D) tin disulfide (SnS₂) crystals grown on silicon dioxide (SiO₂) substrates by vapor-phase method. High-resolution annular dark-field (ADF) scanning transmission electron microscope (STEM) analysis indicate that the SnS₂ crystals crystallize in 1T phase, which is in consistent with the ab-initio density functional theory (DFT) calculations predicting that SnS₂ stabilizes 1T phase at ground state. Photoluminescence (PL) and ultraviolet-visible (UV-vis) spectroscopy measurements suggest that the SnS₂ crystals have an indirect band gap of 2.20 eV and 2.35 eV, respectively, which is in good agreement with the DFT-calculated band gap of 2.31 eV. The electrical transport measurements performed on back-gated field-effect transistors (FETs) exhibit n-type semiconductor characteristics of the SnS₂ crystals. High-angle annular dark-field (HAADF) STEM imaging and STEM energy dispersive X-ray (EDX) chemical analysis demonstrate that the SnS₂ crystals are chemically homogeneous with a stoichiometric S/Sn atomic ratio of 2. Electron energy loss spectroscopy (EELS) and X-ray photoelectron spectroscopy (XPS) analysis present the characteristic Sn and S peaks of SnS₂, confirming the phase purity of the SnS₂ crystals. Ultraviolet photoelectron spectroscopy (UPS) measurements of the SnS₂ crystals provide an ionization potential of 7.51 eV, which is in a perfect agreement with the DFT-calculated ionization potential of 7.51 eV. Resonance Raman spectroscopy in conjunction with ab-initio DFT calculations reveal the characteristic first-order and second-order Raman modes of 1T phase of the SnS₂ crystals. Angle-resolved polarized Raman spectroscopy (ARPRS) mappings with different polarization angles show unique edge features of the SnS₂ crystals.

The performance of ultrafine wires in the back end of the line (BEOL) is degraded by the persistent polygranular microstructure in copper which introduces more diffusion pathways for copper atoms and which leads to faster electromigration failure times. To improve interconnect reliability, Co-containing capping layers have been used to reduce surface diffusion. Applying the same logic to other interfaces, alloying solutes have been proposed to slow down grain boundary diffusion by increasing the activation energy for atomic motion, but the mechanisms are not well understood and there are many conflicting reports as to their efficacy. One challenge for improving interconnect performance through alloying is a lack of information regarding segregation interactions at grain boundaries and interfaces when minute concentrations are introduced into the copper lattice. Historically, solute was expected to pin GBs, increase resistivity, and reduce diffusivity by GB “stuffing”. More recent studies on GB interface states called ‘complexions’ suggest a more complicated relationship, which can explain these results as well as cases where segregation increases mobility or enhance diffusion. To apply complexion analysis in technologically relevant alloy systems, we are investigating dilute copper alloys created by co-electrodeposition or nanolaminate fabrication using a microfluidic device with separate inputs for solvent and solute. Alloying copper with cobalt may offer a means for stabilizing grain boundaries against electromigration void formation in advanced interconnects. Here we present a means for co-depositing dilute copper alloys, using Co and Ag as the solutes of interest. Microstructure and compositional analysis are presented.
Initial work in the co-deposition of dilute copper alloys has yielded insights into the plating requirements, microstructure and composition of the subsequent films. Additional refinements to the process and analysis are being pursued for comparison to alloys deposited in our 300 mm processing line. Less Co diffusion is observed than expected from literature values of the diffusivity, even under fairly aggressive conditions (500°C for 5 hours). Microstructural analysis with concurrent SIMS testing is used to describe these results in terms of the recrystallization of the alloy. In particular, we discuss whether or not the presence of the alloying element influences the final microstructure of the film and provide a mechanistic explanation for these observations.

In filamentary resistive switching memory cells (RRAM) the resistance of the on-state, R_on, is determined by the limiting (compliance) current, I_cc, by the relation R_on~1/I_ccⁿ, where the exponent n in many RRAM cells with a metal atom filament is close to unity¹. Our RRAM cells are MIM Cu/TaO_x/I structures with 25nm TaO_x and inert electrode I=Pt,Rh, or Ru. We show that at low I_cc (roughly <50μA), the resulting high resistance R_on (~100kΩ) is fragile and operatively undefined as any read operation is bound to disturb its R_on value. The R_on can increase or decrease depending on the read voltage polarity, read voltage starting point, read voltage ramp rate and its sweep direction. In contrast, a set operation performed at a high I_cc (>150μA) leads to a stable, low resistance R_on independent of reasonably chosen reading conditions. For I_cc<50 μA, the measured R_on will return different values depending whether the measurement within a 100mV voltage interval started at 0.0V, -0.1V or +0.1V. The highly resistive conductive filament (CF) is fragile and subject to small displacement of individual atoms or defects, charging and discharging reactions. The starting point of the applied voltage determines (non)-equilibrium conditions for Cu⁺, oxygen O^2-, and oxygen vacancy V_o charge states and electron concentrations, all of which impact the properties of CF. For highly resistive CF, most read measurements tend to decrease R_on. The underlying strengthening of the CF, ascribed to aggregation or displacement of Cu⁺, V_o, and O^2-, is, often, impermanent and auto-reversible upon suspension of the read operation. However, the rate of atomic displacement depends strongly on the voltage ramp rate. In general, we find that the R_on resistance decreases with decreasing ramp rate which was has been varied from 10V/s to 0.1V/s. The geometric shape of CF, is approximated by that of a truncated cone. The bulk part of the resistance resides at the tip of CF. As soon as the current exceeds I_cc ,used at the set operation, it generates at the tip high electric field which depending on its polarity causes new transport of Cu⁺, O^2-, and V_o. The voltage ramp rate determines the time scale of the ionic transport at high fields. Thus ramp rate dependence gives insight into the time scales of the ionic transport. The R_on disturbances by electric fields yield insight into the transient mechanisms for CF formation and rupture.
One implication is that during reset operations the differences between high R_on values are brought to the same value before the filament is ruptured, i.e. the reset is rendered independent of the set operation conditions in contrast to a low resistance CF². The ionic mechanisms and the time scales involved that lead to the change of R_on during the read and reset operations will be discussed in detail.

[1] T. Liu, Y. Kang, S. El-Helw, T. Potnis, M. Orlowski, Jap. J. Appl. Phys. 52, (2013) 084202
[2] G. Ghosh, M. Orlowski, IEEE Trans. Elect. Dev. 62(9) (2015) 2850-56

Molybdenum disulfide (MoS₂) with atomic-scale flatness has potential candidate in the applications of high speed and low-power logic devices due to its scalability and intrinsic high-mobility. However, to realize 2D materials as to be viable technology, large-area growth with high quality and uniformity must be pre-requisite. Here, we present the simple and highly uniform growth of four layered molybdenum disulphide (MoS₂) on 2 inch wafer scale substrate via the combination strategy of sputtered molybdenum trioxide (MoO₃) and post sulfurization of chemical vapour deposition (CVD). The spatial spectroscopic analysis of Raman and PL mapping shows that as-synthesized MoS₂ thin film exhibit extremely high uniformity on 2-inch sapphire substrate. With this approach, we assembled almost 1200 MoS₂ transistors integrated on Si wafer that yield high density and extremely uniformity (device yield of ~95%, average mobility of ~0.8 cm²V^-1s^-1, and log on-off ratio of ~4.3). And, the quantitative analysis using pulsed I-V measurement with millisecond time scale could achieve more intrinsic device parameters suppressing the charge trapping of 2D materials-based device.

Silicon Carbide (SiC) based insulated gate bipolar transistor is a promising candidate for use in high voltage power devices, due to faster switching and high voltage blocking capabilities. The type of dielectric layer used in SiC power devices plays an important role in how the device performs. While SiC based transistors are commercialized, the combination of Silicon dioxide (SiO₂) and SiC interface had compatibility concerns, and cannot sustain higher electric fields. An alternative is to replace the conventionally used SiO₂ with high-K dielectrics that can sustain high electric fields. This approach has been attempted earlier with Hafnium dioxide (HfO₂) as the main gate dielectric and sandwiching SiO₂ between of HfO₂ and SiC. Earlier research work has shown initial reduction and then increase in forward voltage drop (V_f)/ON state resistance (R_ON) with respect to temperature. However, there is no complete analysis of the static characteristics using HfO₂-SiO₂ as dielectric stack at higher temperatures. The purpose of this work is to understand the influence of HfO₂ on the capacitance and switching characteristics at higher temperatures. This work highlights the changes in electrical characteristics by varying lattice temperature from 300 K to 700 K. The structure of the device is modeled by using Sentaurus TCAD. Apart from usual drift-diffusion and recombination models, lombardi model has been used to take mobility degradation at the interface into consideration. Uniform trap distribution up to the conduction band and the exponential distribution closer to the conduction band edge is defined within the band gap of SiC in the dielectric interface. Breakdown voltage (BV), switching characteristics using a clamped inductive load and variation of miller capacitance with respect to temperature is analyzed along with static characteristics. The doping of p-well and thickness of dielectric has been designed to adjust threshold voltage(V_th) closer to 3.5 V. It is to be noted that V_th generally reduces with an increase in temperature. The I_c-V_g and I_c-V_ccurves at different temperatures are simulated. As expected, the reduction in V_th and transconductance (g_m) has been observed from the I-V curves with increase in temperature. It has been observed that the saturation of trapping occurs at a lower gate voltage with the increase in temperature. The carrier lifetime in the buffer region is calculated using doping and temperature dependent carrier lifetime model. The turn off characteristics and ON state energy (E_ON) / OFF state energy (E_OFF) with respect to temperature are simulated. It has been observed that the temperature has more influence on E_ON compared to E_OFF. The influence of external gate resistance (R_g) on the switching characteristics will be discussed in the full paper.

Although silicon-based electronics are used to power light-emitting diodes and electric vehicles, their utility in high power applications is limited by a low breakdown voltage. Wide-bandgap semiconductors, such as gallium nitride and related alloys have been proposed as alternatives, but the effective p-type doping at high concentrations remains elusive. For example, Mg dopant activation following ion implantation, selective diffusion, and metal-organic vapor deposition requires high temperature annealing which may disrupt active device structure. In the case of molecular-beam epitaxy, surfactants and co-dopants such as O and Si have been explored, but the concentration of substitutional Mg is often limited, leading to limited p-type doping efficiency. Here, we are developing a novel approach to enhance the p-type doping of GaN and related allows. We describe a combined computational-experimental approach consisting of focused ion-beam (FIB) nano-implantation of Mg in GaN during molecular-beam epitaxy (MBE), followed by computational and experimental ion channeling studies of the Mg incorporation mechanisms. This approach is likely to result in p-type doping at ultra-high concentrations, without the need for subsequent high temperature annealing. We will discuss the development of a modified Mg-Ga alloy source for nano-implantation and our progress towards its implementation in a modular MBE-FIB system. We also present our Monte Carlo-Molecular dynamics simulations of ion channeling in wurtzite GaN crystals, and discuss our progress towards quantifying the influence of growth and annealing sequences on Ga and/or N vacancy formation and the result substitutional vs interstitial incorporation of Mg in GaN. We have examined the influence of Mg defect type in GaN on the [0001], [10-10], and [11-20] channeling yields.

Niobium oxides have recently been demonstrated as excellent candidates to make memristors and memdiodes in neuristor circuits for application in neuromorphic computing. The Poole-Frenkel conduction in the niobium oxide layer is very sensitive to localized temperature and Joule heating. Additionally, thermal confinement and overheating in eventual microelectronics devices may result in significant degradation of performance and reliability. Therefore, it’s of great importance to understand and quantify thermal transport in these oxides. However, very few papers about thermal properties of niobium oxides have been published. Here, we report the first thermal conductivity (k) measurement of amorphous niobium oxide (a-Nb2O5-d) thin films by Time-domain Thermoreflectance (TDTR) method. We observe very low k of a-Nb2O5-d thin films (around 1 W/m-K) that are tunable (about 80% change) through varying oxygen vacancy concentrations (d). Additionally, the thickness dependence of k in a-Nb2O5-d films is studied to explore the influence of size effects in the context of locons, diffusons, and propagons. To complement this discussion, longitudinal wave velocities and vibrational energy spectra are measured by the picosecond acoustic method and Fourier-transform infrared (FTIR) spectroscopy, respectively.

Highly oriented 0.90[PbZr_0.53Ti_0.47] 0.10[La_0.2Scc_0.8]O_3-δ (PLZTS) thin films were deposited on La_0.67Sr_0.33MnO₃ (LSMO) coated MgO (100) substrates utilizing the laser ablation process in oxygen atmosphere. The optimized PLZTS depositions were conducted at a substrate temperature of 700 °C in the experimental setup (KrF excimer laser λ = 248 nm, f = 5 Hz, energy/pulse 270 mJ) and subsequently annealed at the same temperature for 30 minutes in an ultrapure oxygen atmosphere. The (100) orientation of the PLZTS films was obtained from x-ray diffraction results. The nearly stochiometric of fabricated thin films were obtained from the high-resolution X-ray photoemission spectroscopic (XPS) data. Atomic force microscopic (AFM-Veeco) result in contact mode suggests a homogeneous distribution of grains with surface roughness ~ 3.5 nm, and the grains are interconnected with distinct grain and grain boundaries. Piezo force microscopy (PFM) measurements, operated in single frequency excitation, suggests the presence of ferroelectric domains. at ambient conditions. The temperature dependent dielectric measurements carried out on LSMO/PLZTS/Pt metal-ferroelectric-metal capacitors in 100-600 K and frequency (10²-10⁶ Hz) exhibits a broad dielectric maximum. At room temperature, we observed high dielectric constant ~ 650 at 10² Hz. Ferroelectricity of the thin films was ascertained from the observation of well-saturated hysteresis loops with P_r = 22.35 µc/cm² and E_c =92.46kV/cm respectively at frequency 2kHz. The high dielectric constant, low losses and excellent ferroelectric PLZTS thin film capacitor insights into its potential application in electronic devices

Due to the increasing power demands, there is a need for more efficient, high power switching devices. GaN sees a lot of promise as a mean to meet this demand due to good on-resistance vs. breakdown voltage relationship. As a result, GaN-based electronic devices have seen a great deal of success in high power applications. The development of first generation GaN power devices has focused on lateral architectures, such as high-electron mobility transistors (HEMTs), fabricated in thin GaN layers grown on foreign substrates (e.g., sapphire, SiC, and Si). HEMTs achieve their high electron mobility with a lateral heterostructure
Despite the successful demonstration of GaN HEMTs in various power applications, these lateral devices have several drawbacks which significantly limit their performance especially for high power and high voltage applications (e.g., > 1,200V). These lateral devices suffer from several major degradation mechanisms including current-collapse, dynamic on-resistance, and an inability to support avalanche breakdown performance. Furthermore, at higher operation powers, lateral HEMTs become less attractive, since the blocking voltage is held laterally, the device length must increase in order to increase the breakdown voltage.

Recently, bulk GaN substrates have become widely available, thus enabling a new generation of GaN power devices based on vertical architectures. These vertical GaN power transistors hold the blocking voltage vertically, which allows the devices to achieve very high breakdown voltages without increasing device area. As in a lateral device, a heterostructure is used to create 2DEG. However the electrons are drawn by the drain into the bulk. Because of this, current collapse is not as much a concern in these devices since most of the conduction path is not near the trap rich surface. Current blocking layers (CBLs) are employed to confine the current to an aperture directly beneath the gate. Typically, p-GaN is used for the CBL, however, growing the p-GaN layer via metal organic chemical vapor deposition (MOCVD) results in the Mg being passivated by H, and therefore the hypothetical >3eV blocking layer is not achieved.

Therefore, there is impetus to explore other materials for CBL applications, such as SiO₂, however, previous work on SiO₂ CBL’s neglected thermal considerations. This work simulated using Silvaco TCAD two GaN Vertical HEMT devices, one with a conventional p-GaN CBL and one with a SiO₂ CBL under both isothermal and non-isothermal conditions. At V_D = 20 V and VG = 0 V, the SiO₂ devices saw more heating, possessing a hotspot of 396 K, compared to the 379 K hotspot of the p-GaN device. In spite of the increased heating, the on-resistance was still lower for the SiO₂ CBL device (0.266 mΩ cm²) than that of the conventional p-GaN CBL device (0.331 mΩ cm²).

Copper is the dominant material used in electrical conductors due to its availability and excellent electrical conductivity. However as the electronic devices are getting smaller concerns regarding the ampacity of copper conductors have arisen. Moreover poor mechanical properties and relatively high weight resistivity of copper wires and cables have motivated researchers to develop new materials and systems for power transmission. Carbon nanotubes (CNTs) offer high electrical and thermal conductivity, excellent mechanical properties and ampacity 1000 times higher than copper. Although these outstanding properties make CNTs a very promising candidate, complex and costly processing impedes their application as a sole conductor. On the other hand previous research has shown that utilizing CNTs as a filler in a metallic matrix can simplify the processing and results in remarkable properties. In this case interfacial interactions between the two phases significantly influence the morphology and properties of the composite.
In this report electrospinning was utilized to produce Cu-CNT nano-fibers. The effect of CNT surface treatment and electrospinning parameters on the morphology and electrical conductivity of copper-CNT electrospun fibers were studied. For this purpose four different types of CNTs (pristine, oxidized, exfoliated and thiol activated) in different concentrations were used. Also two types of polymeric carriers were studied. Results showed that generally CNT introduction will decrease the uniformity and smoothness of the Cu-CNT fibers. Above a certain critical concentration, fibers cannot be produced. Pristine CNTs have the lowest and exfoliated CNTs have the highest critical concentration. Exfoliated CNTs with concentration as high as 5 wt% yields very smooth fibers with high uniformity which can improve the electrical conductivity. Also, it was shown that although PVP application as the carrier polymer makes the electrospinning process easier, PVA produces fibers with higher smoothness and uniformity. It should be noted that that in nano-scale surface smoothness has a significant effect in the conductivity of fibers.

The through silicon via (TSV) is one of 3D integration methods to achieve high density interconnects with a good electrical performance and a small form factor on wafer level. In this work, we investigated the TSV filling performance dependent on the functional groups of levelers such as amines, imines, pyridines and pyrrolidones. To elucidate the behavior of functional groups in TSV filling, the mass adsorption rate was measured using quartz crystal microbalance (QCM) and electrochemical QCM (EQCM). It was found that the amines only exhibited the void-free filling in TSV, whereas other functional groups showed the void in TSV. This could be inferred that the amine favored the local adsorption on the top edge of via during electroplating, as evidenced by low mass adsorption rate of QCM and the large difference of mass adsorption rate between QCM and EQCM.

In the panel level packaging, it is necessary to control the thickness uniformity of electroplated Cu redistribution layer because non-uniform thickness of Cu electrodeposits is resulted in severe electrical resistance fluctuation. In this work, we studied the thickness uniformity of Cu electrodeposits in the presence of organic additive containing imine functional group modified with different degrees of quaternization. The degree of quaternization of imine functional group was controlled to be in the range of 0 to 100 % using the dimethyl sulfate solvent. The surface morphology and thickness uniformity of Cu electrodeposits were characterized by optical microscopy and confocal laser microscopy. In the case of adding the organic additive containing the imine functional group modified without quaternization into Cu electroplating solution, the shape of Cu electrodeposit represented dome shape with poor uniformity. Additionally, excessive dish-shaped surface was formed with the degree of quaternization of 100 %. However, with the degree quaternization of 50 %, the flat shape of Cu electrodeposits with high uniform thickness was obtained.

HfO2 makes a very useful ferroelectric oxide because it is thermodynamically stable in contact with Si, unlike the traditional ferroelectrics PZT and SBT. HfO2 can be brought into the ferroelectric Pca2 phase either by suitable thermal annealing process or by use of alloying or dopants such as group III elements Y, Sc, Al, or N at the O site, or the group IV elements Si, Ge, Zr. Si, Ge, and N could be called efficient dopants in that only a small fraction is needed [1]. However, some of them introduce gap states which will act as traps, or encourage leakage currents, or in the worst case breakdown. Trivalent dopants act by creating O vacancies which lower the mean O coordination and thus stabilise the lower symmetry phase [2]. We recall that previously N and Y were shown to behave beneficially in removing the gap states due to O vacancies from the gap band, but this is true only if they are adjacent to the vacancy [3,4]. We find that ‘efficient’ dopants are less satisfactory in that they will not necessarily be close to the vacancies, so their gap states are not removed. Ge is found to have too small a gap. Si does not introduce gap states.
1 A Toriumi et al, IEDM (2016)
2 J P Goff et al, PRB 59 797 (1999)
3 K Xiong, J Robertson, JAP 99 044105 (2006)
4 D Liu, J Robertson, APL 94 042904 (2009)

The mechanism of stability of the phases of HfO₂, ZrO₂, and HZO (Hf_xZr_1-xO₂) were systematically investigated with density functional theory molecular dynamics (DFT-MD) to determine the mechanism for HZO having a much larger process window for formation the ferroelectric phase as compared to doped HfO₂ or ZrO₂. For the bulk states, the monoclinic phase (“m”) is about 80 mV per formula unit more stable than either the orthorhombic ferroelectric (“f”) phase or tetragonal (t-phase) for all three oxides. The surface free energies of the (001), (110), and (111) surfaces of all three oxides were calculated using an identical DFT technique. For all three oxides, the (111) face has the lowest surface free energies consistent with experimental data on columnar HZO grains showing [111] is the preferred growth direction. However, the surface free energy for all direction are nearly degenerate between HfO₂, ZrO₂, and HZO; therefore, even for nanocrystal formation the surface free energy does not favor f-phase formation. The effect of stress/strain was calculated by determining the free energy of formation as a function of the volume of the unit cell. When the oxides are grown in the low density amorphous phase but a post deposition anneal is perform for crystallization. The crystalline forms are more dense than the amorphous forms and the DFT calculation show that a higher surface area per unit cells will greatly favor f-phase formation. However, the effect is nearly identical for HfO₂, ZrO₂, and HZO; this is consistent with experiments showing the molar volumes of HfO₂ and ZrO₂ being within 2%. Instead, formation of nanocrystalites is hypothesized to be the source of the enhanced processing window for HZO. Experimental data is consistent with partial phase separation in HZO. Atom probe tomography imaging of the chemical composition of TiN/5 nm HZO/Si(001) ferroelectric films show an asymmetric distribution of the Hf and Zr within the HZO layer with the Zr being concentrated near the TiN/HZO interface; this is consistent with ZrO₂ having a 100C lower crystallization temperature than HfO₂ and therefore initiate the crystallization starting on the TiN(111) surface. It is hypothesized that the nanocrystals which template on TiN(111) can produce the interfacial stress/strain needed to stabilize f-phase formation; high resolution TEM shows regions of epitaxial alignment between HZO and TiN consistent with this mechanism.
Funding by LAM Research is gratefully acknowledged.

The 2011 discovery of a ferroelectric phase in doped hafnium oxide [1] and hafnium zirconium oxide solid solution [2] re-established the competitiveness of ferroelectric memory technologies. Mainly driven by the outstanding scalability and CMOS-compatibility of this new ferroelectric material, classical concepts such as FRAM, FeFET and FTJ are reentering the race for leading edge embedded and stand-alone memory solutions [3-6]. Especially the FeFET concept with its simple one-transistor cell design, non-destructive and low power read operation appears to be the main beneficiary of this new development. Scalability to the 2X nm node [3] and highly yielding memory arrays in the Mbit range are currently being demonstrated for hafnium oxide based FeFETs [7]. Nevertheless, a fundamental material understanding is needed to identify the main parameters improving the ferroelectric performance of the hafnium oxide thin films.
In this contribution we give an overview of the main parameters and their impact on the ferroelectric behavior of hafnium oxide. The thickness dependence and the directly associated consequence for the doping concentration of the film will be reviewed. The impact of different thermal treatments will be also discussed in relation to CMOS process flows, illustrating how the thermal budget of subsequent processes in the entire process flow can distinctively change the ferroelectric film properties. Furthermore, specific treatment conditions will be shown, which are further enhancing the ferroelectric properties of hafnium oxide films.

[1] T. Böscke et al., Applied Physics Letters 99 (10), 102903-102903, 2011
[2] J. Müller et al., Applied Physics Letters 99 (11), 112901-112901, 2011
[3] J. Müller et al., Symposium on VLSI Technology (VLSIT), pp. 25-26, 2012
[4] P. Polakowski, IEEE 6th International Memory Workshop (IMW), pp. 1-4, 2014
[5] K. Florent et al., Symposium on VLSI Technology (VLSIT), pp. T158-T159, 2017
[6] S. Fujii et al., Symposium on VLSI Technology (VLSIT), 2016
[7] S. Dünkel et al., IEEE International Electron Devices Meeting (IEDM), accepted for publication, 2017

Following the first report on ferroelectricity in Si-doped HfO₂ thin film in 2011 [1], fluorite-type ferroelectrics have attracted great interest in the field of ferroelectricity [2]. Even with an extremely small film thickness of ~10 nm, they could have remanent polarization as high as 15 – 30 μC/cm², which is already comparable to that of much thicker perovskite-type ferroelectric films [2]. Moreover, they are environmental-friendly with an absence of Pb and have deposition techniques (atomic layer deposition), mature enough for mass production [2]. Thus, they are considered highly promising for both memory and energy devices [2]. Especially, the field-induced phase transition in fluorite-type ferroelectrics enables energy storage, energy harvesting and solid-state-cooling comparable to or even better than the previous candidates [3].
The crystallographic origin of the unexpected ferroelectricity is now believed to be a formation of Pca2₁ orthorhombic phase [2]. However, this phase cannot be found in phase diagrams of bulk HfO₂ and ZrO₂, and the monoclinic phase is always a stable phase under process conditions. To understand the formation of the unexpected orthorhombic phase, various thermodynamic causes such as surface energy, interface/grain boundary energy, stress, and doping were suggested [2,4]. From a comprehensive comparison of our experimental results to the theoretical models, we suggested that the kinetic mechanism of phase transition should also be considered [5,6]. In this presentation, therefore, the thermodynamic/kinetic origin of the formation of orthorhombic phase in fluorite-type ferroelectrics and their properties will be comprehensively examined.
[1] T. S. Boescke et al., Appl. Phys. Lett. 99, 102903 (2011).
[2] M. H. Park et al., Adv. Mater. 28, 7956 (2015).
[3] M. H. Park et al., Nano Energy 12, 131 (2015).
[4] R. Materlik et al., J. Appl. Phys. 117, 134109 (2016).
[5] M. H. Park et al., Nanoscale, 9, 9973 (2017).
[6] M. H. Park et al., submitted to Nanoscale.

We discuss dopant effects on the ferroelectricity of HfO₂. We prepared many kinds of doped HfO₂ with both cations (Y, Sc, Al, Si, Ge, Zr, Nb) and anion (N)^[1]. We found not only dopant-dependent but also dopant-independent contributions to ferroelectric properties. The former one obviously comes from dopant atomic nature such as ionic charge or size, while the latter one is the point we are interested in.
Total polarization P_SW as a function of the dopant concentration X, in which X and P_SW denote the dopant ratio in total atoms including anion and the absolute value of polarization at V=0, respectively. A small amount of N doping enables to achieve the ferroelectric HfO₂, while Zr slowly and Ge moderately help the ferroelectric phase formation of HfO₂. More interestingly, the sensitivity curve seems to be similar in shape irrespective of dopant species^[2]. This fact suggests that HfO₂ ferroelectricity is achieved by HfO₂ intrinsic properties. In HfO₂ and ZrO₂, the structural phase transitions from the tetragonal to monoclinic phases are understandable from the martensitic transition viewpoint. In the doped HfO₂ case, it is inferred that the ferroelectric orthorhombic phase may be along this phase transition. In that sense, the dopant may help to increase the kinetic barrier against stabilizing the monoclinic phase irrespective of dopant species.

Acknowledgnment
This work was supported by JST-CREST Grant Numbers JPMJCR14F2, Japan.

References
[1] L. Xu, A. Toriumi et al., Appl. Phys. Express 9, 091501 (2016).
[2] L. Xu, A. Toriumi et al., J. Appl. Phys. 122, 124104 (2017).

Today, in the era of the Internet of Things era, the demands on enhanced integrated functionalities and on energy efficiency are even more important as the system miniaturization. Despite the fact that new paradigms in computing consider possible future roles of neuromorphic and quantum computing, it appears that, at least for next decade, CMOS will continue to play a dominant role. One of the remaining challenges for transistors with nanometer dimensions is the voltage scaling, today saturated at value near 0.7V. Today’s CMOS is a multi-material, three dimensional technology, which exploits quantum effects in semiconductors. However, the voltage supply of most advanced CMOS technologies is saturated due to incompressible thermionic subthreshold slope of the MOSFET, having as limit 60mV/decade at room temperature. In recent years, tremendous research efforts have been dedicated to devising new types of so called subthermionic steep slope switches, where the principle of the MOSFET switch is replaced with physical mechanisms that can provide such steeper transition between OFF and ON state, such as band-to-band tunneling and impact ionization. The goal is to enable further supply voltage scaling down to 0.2-0.3V, where logic state distinguishability is still granted with an improvement of energy efficiency of about 100x. Another idea is to apply a radically new technology booster on MOSFET and extend his life, by amplifying the gate signal using a differential negative capacitance (NC) in the gate stack. This could be done in a similar way in which a differential negative resistor would amplify a small signal. The result is a transistor body factor smaller than unity, reflecting the differential surface potential amplification, possible because of ferroelectric materials that can provide such a negative capacitance in the transistor gate stack.
In this paper, we will review, discuss and provide some concrete examples of how to achieve such sub-unity m factors by the negative capacitance effect materials to boost both MOSFETs and tunnel FETs performance at sub-10nn channel dimensions. The paper will discuss theoretical and experimental matching and stabilization conditions for NC and quantitative performance improvement in NC-MOSFETs and NC-Tunnel FETs by using PZT and, most interesting, ferroelectricity in doped high-k capacitors. The role of mono-domains versus multi-domains in ferroelectrics showing negative capacitance will be clarified. Moreover, we will present investigations about the very important role of gate leakage current in order to exploit the NC effect.
Overall, the paper will demonstrate that a deep sub-unity body factor by negative capacitance effect of field effect transistors can be engineered and applied for both MOSFETs and Tunnel FETs and stands as one of the most universal performance booster at nanoscale.

Two-dimensional (2D) semiconductors such as transition metal dichalcogenides have great potential as post-silicon channel materials that could suppress short channel effects. However, 2D semiconductors still suffer from the thermal limit for the subthreshold swing, as long as conventional metal-insulator-semiconductor (MIS) structures are employed. To overcome the fundamental limit, we introduce the metal-insulator transition material VO₂ as a contact electrode in an atomically thin WSe₂-based MIS transistor. Polycrystalline VO₂ films with thicknesses of ~ 50 nm were grown on Al₂O₃ by the pulsed layer deposition method and observed to show the metal-insulator transition near 340 K. The VO₂ films were etched down to ~ 1 μm in width. Then, few-layer WSe₂ was transferred directly onto the VO₂ wire so that the VO₂ served as one of the contact electrodes. After defining another electrode by depositing Ti/Au on WSe₂, a gate dielectric of hexagonal boron nitride was transferred, followed by the definition of the gate electrode. The WSe₂ transistor is on the off-state, with the VO₂ electrode being in the insulating phase at room temperature. However, the drain current shows abrupt and discontinuous increase at a given gate voltage, suggesting that the insulator-to-metal transition in VO₂ is induced thermally by Joule heating. Since the on-off switching is governed by the phase-transition in the VO₂ electrode, the subthreshold slope is, in principle, expected not to be limited by the thermal voltage. We observe a relatively small value of 150 mV/decade for the subthreshold slope in this transistor, but this is still larger than the thermal limit of 60 mV/decade. We envision that the subthreshold slope could be further improved by employing single crystalline VO₂ as well as a high-k gate dielectric such as HfO₂. This work is an important first step in demonstrating steep-slope transistors based on 2D semiconductors.

Over the last couple of decades, there have been continuous efforts to scale down both logic and memory components of microelectronic devices to nano regimes in the pursuit of enhancing speed and storage density, respectively [1]. However, with reducing the dimension of these devices, the significant energy losses in the form of heat has been one of the key issues for the microelectronic industry [2]. In order to continue further improvement in device-level or even bring next breakthrough in computing devices, a novel physical mechanism beyond-CMOS concept is needed to be explored.
The electric-field manipulation of magnetism in mutltiferrroic based devices promises to reach in the energy landscape of atto-Joule (aJ) range for per bit operation in logic and memory devices [3]. Among other multiferroic materials, BiFeO₃ (BFO) exhibits robust magnetoelectric coupling at room temperature [4]. The canted antiferromagnetically aligned spins in BFO, give arise to the weak ferro-magnetism due to the Dzyaloshinskii–Moriya(DM) interaction, causes strong exchange interaction with ultrathin ferromagnet, e.g. CoFe, which can be exploited to electrically control the spin valve device [5]. Here we have demonstrated scaling behavior of applied voltage to electrically control the spin-valve devices at room temperature by engineering the strain state and doping level in BFO thin films. We show that with reducing the thickness of BFO layer down to 20 nm along with 10-15 % of La doping, the switching voltage can be reduced to sub volt regime (~150 mV). Besides this, we have shown large angle dependent exchange bias in these system that can be reversible controlled by electric field. The magnetic coupling of BFO with CoFe in these devices is strongly stabilized by its ferroelectric (FE) ordering. Orientation of the device structure with respect of the BFO FE domains play a crucial role in determining the degree of exchange bias and its manipulation with electric field. In addition to these findings, enhancement of magnetoelectric coupling with miniaturization of these devices down to ferroelectric domain size (~ 200 nm) provides a pathway to integrate BFO as a key material in the fabrication process for ultra-low energy, non-volatile beyond-CMOS computing.

[1] Ferain I. et al., "Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors" Nature 479 310-316 (2011).
[2] Meindl J. D et al., "Limits on silicon nanoelectronics for terascale integration." Science 293 2044-2049 (2001).
[3] Manipatruni S., et al., "Spin-orbit logic with magnetoelectric nodes: A scalable charge mediated nonvolatile spintronic logic" arXiv preprint arXiv:1512.05428 (2015).
[4] Wang J. et al., Epitaxial BiFeO₃ multiferroic thin film heterostructures. Science 299, 1719–1722 (2003)
[5 Heron J. T. et al., "Deterministic switching of ferromagnetism at room temperature using an electric field", Nature 516, 370–373 (2014).

According to the ITRS projections, the level of the current density will soon increase to ~5.35 MA/cm2 at the half-pitch width of 7 nm. There is no existing technology with the breakdown current density high enough to sustain such currents. No feasible interconnect solutions are known for the beyond-the-roadmap nanoscale devices. Scaling deep to the nanoscale range presents problems for conventional metals due to their polycrystalline structure, surface roughness and increased electrical resistivity owing to the electron–boundary scattering. In this presentation, we report the results of our investigation of quasi one-dimensional (1D) van der Waals metals as possible materials for ultimately down-scaled interconnects. Unlike copper some transitional metal trichalcogenides (TMTs) MX₃ (where M = Mo, W, and other transition metals; X = S, Se, Te) can be exfoliated or grown into quasi-1D single crystals without grain boundaries, surface roughness or dangling bonds. As a result, the onset of electromigration can be delayed to higher current densities. We have demonstrated prototype interconnects implemented with quasi-1D TaSe₃ nanowires with the current density exceeding J_B~32 MA/cm², which is an order of magnitude higher than that for the Cu interconnects [1]. The reliability of the prototype quasi-1D van der Waals metallic interconnects has been tested using the temperature-dependent low-frequency noise (LFN) spectroscopy. The LFN spectrum at elevated temperatures are directly correlated with the electromigration failure mechanisms in interconnects. The LFN data can be used for extracting the information about the vacancy migration along the nanowires and the onset of the electromigration failure. The noise activation energies extracted from the two commonly accepted physical models, the Dutta–Horn model and the empirical noise model in metals, have shown an excellent agreement with the activation energies obtained from the industry standard electromigration mean-time-to-failure (MTF) tests [2]. The obtained results suggest that the quasi-1D van der Waals metals are promising candidates for the ultimately downscaled local interconnects.

This project was supported, in part, by the by the Emerging Frontiers of Research Initiative (EFRI) 2-DARE project: Novel Switching Phenomena in Atomic MX2 Heterostructures for Multifunctional Applications (NSF EFRI-1433395) and by National Science Foundation (NSF) grant #1404967 to A.A.B. on defect engineering in materials.

[1] M. A. Stolyarov, G. Liu, M. A. Bloodgood, E. Aytan, C. Jiang, R. Samnakay, T. T. Salguero, D. L. Nika, S. L. Rumyantsev, M. S. Shur, K. N. Bozhilov, and A. A. Balandin, “Breakdown current density in h-BN-capped quasi-1D TaSe3 metallic nanowires,” Nanoscale, 8, 15774 (2016).
[2] G. Liu, S. Rumyantsev, M. A. Bloodgood, T. T. Salguero, M. Shur, and A. A. Balandin, “Low-frequency electronic noise in quasi-1D TaSe3 van der Waals nanowires,” Nano Lett., 17, 377 (2017).

Transition metal disilicides which have tunable work-functions, are of significant interest as contact silicides. Moreover, selective deposition of silicides obviates the need for lithography onto complicated 3D structures on sub 10 nm 3D devices. Metallic tungsten (W) deposition on H-terminated Si in preference to OH-terminated SiO₂ via a selective ALD process has been demonstrated using WF₆ and SiH₄ or Si₂H₆ by B. Kalanyan et al. In these processes, SiH₄(g) or Si₂H₆(g) are considered a sacrificial reductant for W film by forming SiF₄(g) and SiHF₃ as byproducts: 2WF₆(g) + 1.5Si₂H₆(g) à W(s) + SiHF₃(g) + 3.5H₂(g) + 2SiF₄(g) + HF(g). Here, we demonstrated that sub-stoichiometric silicide, MoSi_x (x=0.4 – 1.1), can also be selectively deposited on a nanometer scale on H-terminated Si (001) but not on silicon oxide and silicon nitride using MoF₆ and Si₂H₆.
X-ray photoelectron spectroscopy (XPS) was used to investigate the chemical composition of MoSi_x at each experimental step. The growth rate of MoSi_x on Si was ~0.8 Å/cycle or higher thus even 5 selective ALD cycles are sufficient for deposition of contacts. By dosing extra Si₂H₆ pulses after 5 ALD cycles, more Si could be selectively inserted into the film. To confirm an in-situ selective deposition as well as the thickness of the film, MoSi_x was deposited on a sample patterned with SiO₂ and Si₃N₄ and cross-section of the patterned sample was observed using tunneling electron microscope (TEM). From the TEM image, selectivity of MoSi_x on Si over SiO₂ and Si₃N₄ was 100%. From in-situ STM, MoSi_x on Si had a conformal and atomically flat surface with root mean square (RMS) roughness of 2.8 Å. Post-annealing in a ultra-high vacuum at 500°C for 3 mins further decreased the RMS roughness to 1.7 Å. A 900°C spike anneal on the MoSi_x film under the 5% H₂/N₂ atmosphere showed RMS roughness of 4.75 Å measured by ex-situ AFM. A resistance of the 900°C annealed MoSi_x film was obtained using 4-probe measurement. The resistance of the film was determined to be ~500 µohm-cm using a sheet approximation model. The high selectivity achieved on patterned samples shows that this process should be applicable for selective contact silicide deposition on the nano scale.

Nonvolatile spintronics based VLSIs, which are composed of memory cells of magnetic tunnel junctions (MTJ) with high endurance and high speed operation, are attracting much interest for realization of low power consumption edge devices with the arrival of the IoT era [1-3]. Perpendicular anisotropy CoFeB-MgO based MTJ (p-MTJ) with a synthetic ferrimagnetic (SyF) reference layer is a building block in the nonvolatile memory cells [4,5]. Thermal tolerance for annealing at temperature of 400C is required for the integration of the p-MTJs using standard CMOS back-end-of line process. We have demonstrated 10 nm diameter CoFeB-MgO based p-MTJs with the thermal tolerance of 400C [7]. Here, we review development in the p-MTJs [8-10]. In particular, we describe about the material design knowledge of the controlling boron composition of CoFeB free layer, variation of magnetic properties in the reference layer by high temperature annealing, and dependence of the MTJ properties on the sputtering gas species.
This work was supported by STT-MRAM R&D program under Industry-Academic collaboration of CIES consortium, JSPS-EPSRC Core to Core Program, JST-ACCEL, and JST-OPERA.

References:
[1] H. Ohno et al., Tech. Dig. -Int. Electron Devices Meet. 2010, 9.4.1.
[2] T. Endoh et al., IEEE J. Emerging and Selected Topics in Circuits and Systems, Vol. 6, 109 (2016).
[3] T. Hanyu et al., Proceedings of the IEEE, 104, 10, pp.1844-1863 (2016).
[4] S. Ikeda et al., Nature Mater. 9, 721 (2010).
[5] H. Sato et al., Jpn. J. Appl. Phys. 56, 0802A6 (2017).
[6] H. Sato et al., Jpn. J. Appl. Phys. 53, 04EM02 (2014).
[7] H. Honjo et al., 2015 Symp. on VLSI Tech. Dig. of Tech. Paper 2015, T161.
[8] H. Honjo et al., IEEE Trans. Mag. 52, 3401104 (2016).
[9] H. Honjo et al., AIP Adv. 7, 055913 (2017)/.
[10] H. Honjo et al., IEEE Trans. Mag. 53, 2501604 (2017).

The introduction of functionally improved materials such as magnetic heterostructures in magnetic tunnel junctions (MTJs) is a major driver to enable the continued down-scaling of circuit density and performance enhancement in logic and memory devices beyond the roadmap. In this talk, I will discuss current research advances in multifunctional and complex material systems, especially in engineering and patterning of complex stacks of thin films at the atomic scale.
Understanding and control of the factors affecting the interfacial phenomena at the CoFeB|MgO interface in a MTJ, from which the perpendicular magnetic anisotropy (PMA) of the CoFeB originates, are crucial to the realization of MTJ’s full potential. Efficient manipulation of PMA using an applied voltage, known as the voltage-controlled magnetic anisotropy (VCMA) effect, offers significant energy savings over electric-current-controlled alternative memory devices. Ab initio studies in the literature revealed a dependence of the VCMA effect on the oxidation state of interfacial Fe atoms in an Fe/MgO interface and on the heavy metal insertion layers at the CoFeB/MgO interface. This work addresses experimentally the dependence on the VCMA effect of oxide and metallic insertion layers in the MTJs. For oxide insertion layers, an atomic layer deposited lead zirconium titanate (PZT) layer in a MgO/PZT/MgO structure resulted in a 40% increase in the VCMA coefficient, despite the PZT layer being amorphous. For metallic insertion layers, Mg was found to be the most effective and a 1.1-1.3nm layer improved the VCMA coefficient by more than a factor of 3 and gave rise to the highest perpendicular magnetic anisotropy and saturation magnetization, as well as to the best CoFe and MgO crystallinity. These results demonstrate that a precise control over the material’s type and oxidation level in the MTJ is crucial for the development of electric-field-controlled perpendicular magnetic tunnel junctions with low write voltages.
Finally, to address the high density integration challenges of MTJs, a generalized methodology, combining thermodynamic assessment and kinetic verification of surface reactions, will be presented to define atomic layer etching processes that enable the patterning of these complex magnetic and noble metal heterostructures, including etching efficacy, directionality, and selectivity at the atomic scale.

Emerging memories have the potential to disrupt the memory hierarchy if they satisfy stringent requirements needed to integrate them into a high-density memory. As traditional memory ( DRAM and NAND) scaling is becoming increasingly difficult, various emerging memories are being considered as options for future memory scaling as well as for niche applications in compute systems. In this talk we will specifically discuss traditional memory scaling issues, fundamental limitations, scaling and integration challenges associated with emerging memories like Ox-ReRAM, Metal-ReRAM and STTRAM.

Redox-based resistive random access memories (ReRAM) are one of the key technologies for revolutionizing the memory device market in the near future. The performance of ReRAM devices position them as ideal candidates for Storage Class Memories, whose purpose is to fill the cost-performance gap between the DRAM and NAND flash technologies. Tantalum oxide (TaO_x) is one of the most promising materials for the integration as an insulator in ReRAM devices, showing high endurance and high switching speed. The resistive switching in TaO_x-based devices is commonly explained by the filamentary valence change mechanism, in which the formation / dissolution of a conductive filament plays a key role in switching between different resistance states. However, the filament structure, its exact composition and its impact on the performance of the devices are still a matter of debate. We targeted these questions by performing a detailed study of the electronic transport through conductive filaments in TaO_x-based ReRAM devices in the low-resistance state (LRS or ON state) at temperatures from 300 K down to 2 K. To further understand the origin of the transport properties of the filaments, we also measured, in the van der Pauw (vdP) geometry, substoichiometric TaO_x thin films which, for certain compositions, exhibit the same transport behavior as conductive filaments in the ReRAM devices. Thus, by studying the substoichiometric TaO_x films, it was possible to learn more about the conduction mechanisms in the filaments.
The conductance of the TaO_x ReRAM devices shows two different regimes in the measured temperature range. At higher temperatures, the conductance exhibits a T ^1/2 dependence, while at lower temperatures, an exp(–T ^1/2) dependence is observed. The temperature range where the transition between the two regimes takes place varies slightly from device to device. A positive magnetoresistance is observed in the low temperature regime, and it decays exponentially with increasing temperature. These features were also observed in the substoichiometric TaO_x films with x ∼ 0.5, both for conductance and for magnetoresistance. For these films, Hall measurements give a very high carrier concentration of the order of 10²² cm^-3 and a low Hall mobility of 0.1 cm²V^-1s^-1. The carrier concentration is of the same order of magnitude as the one measured in a reference Ta film. Furthermore, this Ta film shows the same distinctive T ^1/2 behavior corresponding to the aforementioned high temperature regime of the conductance in the TaO_x devices and vdP samples. This T ^1/2 behavior is commonly reported for disordered metals where quantum corrections to the conductivity dominate the transport. Based on these experimental findings we propose a model where the transport properties of both TaO_x ReRAM devices and TaO_x vdP samples are determined by a percolation path of disordered Ta granules.

Resistive switching (RS) plays an important role of Resistive Random Access Memory (ReRAM). The formation and rupture of conductive filaments have been widely accepted as an origin of RS mechanism especially in binary Transition Metal Oxides (TMOs). “Forming” by applying electrical stress to a pristine cell is an initial process generally required to create conductive filaments in TMO layers between top and bottom metal electrodes. The forming exhibits some analogies with dielectric breakdown of thin SiO₂ films [1]. In this study, we examine Time-Dependent Forming (TDF) characteristics in Pt/NiO/Pt RS cells.
Two kinds of Pt bottom electrode (BE) on a SiO₂/p-Si substrate were prepared, deposited either by Electron Beam (EB) evaporation or RF Sputtering (SP). A sample with the Pt/NiO/Pt cells using Pt BE deposited by EB or SP is referred to as EB-Pt samples or SP-Pt samples, respectively. A NiO film as a resistance change layer was deposited on the BE by rf reactive sputtering. Pt top electrodes were deposited on the NiO layer by EB evaporation. The time to forming (t_form) in the cells was measured while keeping a constant applied voltage. Cell resistance remains almost unchanged before forming. After forming, all of the cells in both samples were confirmed to show repeatable RS characteristics.
Cross-sectional Transmission Electron Microscopy (TEM) uncovers that Pt BE and NiO layers in EB-Pt samples contain granules, and that those in SP-Pt samples exhibits a columnar polycrystalline structure with a grain diameter of tens of nm. Moreover, the layers in EB-Pt samples exhibit diffraction peaks by both (111) and (200) planes and columns of the layers in SP-Pt samples are preferentially oriented to the [111] direction as confirmed by X-ray diffraction curves. NiO crystallinity is turned out to strongly depend on the BE crystallinity [1].
TDF measurements reveal that the slope of Weibull distribution (Weibit) of t_form is clearly different between EB-Pt samples (1.5) and SP-Pt samples (0.9). These values are independent of NiO thickness, applied voltage, initial resistance, and surface roughness of cells. Furthermore, the Weibits normalized by cell sizes according to the area scaling law overlay each other. These results indicate that formation of the filaments at forming follows a weakest-link theory, and that weakest spots are almost randomly distributed in a NiO film according to Poisson statistics, each of which can contribute conductive paths locally generated by an electrical stress.
We also confirm inverse correlation between variation of initial resistance and that of time to forming. The different values of the slope of Weibits between EB-Pt and SP-Pt samples are considered to originate from a difference of NiO crystallinity. These results suggest that distribution of grain boundaries is the key to form the conductive filaments in NiO by the forming.
[1] Y. Nishi, et al, J. Appl. Phys. 120, 115308 (2016).

In the next generation of digital technology, which includes forward-looking consumer electronics and the internet-of-things, non-volatile memory will play a decisive role where flash memory is currently the key player. However, as flash memory fails to meet the commercial demands of scalability and endurance, the industry is looking for an alternative where resistive memory devices are leading candidates. Organic resistive memories are of particular interest because of their low-cost solution-processability and synthetic tunability. However, to date, they have been lacking reproducibility, endurance, retention, switching speed, and the mechanistic understanding required for commercial translation. In this report, we demonstrate a resistive memory device with a spin-coated active layer of a transition metal complex where we have achieved unprecedented reproducibility (~350 devices), fast switching (<30 ns), excellent endurance (~10¹² cycles), and retention (>10⁶ s). We establish a definitive switching mechanism via in-situ Raman and UV-Vis-spectroscopy alongside spectroelectrochemistry and quantum chemical calculations and find that the redox state of the ligands determines the switching states of the device while the counterions control the hysteresis. Both in terms of device performance and understanding, this study presents a significant step forward in organic resistive memory technology [1,2].

[1] Goswami, Sreetosh, et al. "Robust resistive memory devices using solution-processable metal-coordinated azo aromatics." Nature Materials (2017), DOI: 10.1038/NMAT5009
[2] Valov, Ilia, and Michael Kozicki. "Non-volatile memories: Organic memristors come of age." Nature Materials (2017): nmat5014

Resistive switching (RS) phenomenon of TiO₂-based resistive random access memory (ReRAM) can be explained with the formation and rupture of a conductive filament (CF) in the TiO₂ layer. However, the origin of a CF is still unknown and switching mechanism has not been fully clarified yet. In this work, a transition to a resistance state different from low resistance state (LRS) or high resistance state (HRS) at specific forming processes in Pt/TiO₂/Pt stack structures was discovered.
TiO₂ layers were deposited on Pt(70 nm)/Ti(5 nm)/SiO₂/Si substrates by a reactive radio-frequency sputtering method. The thickness of the TiO₂ layer was varied from 10 nm to 40 nm. Pt