John Robertson, Cambridge University
Jesus del Alamo, Massachusetts Institute of Technology
Andrew Kummel, University of California, San Diego
Masaaki Niwa, Tohoku University
EP01.01: Ge Gate Stacks and Integration
Jesus del Alamo
Tuesday AM, April 03, 2018
PCC North, 200 Level, Room 224 A
10:30 AM - EP01.01.01
Novel Gate Stack Engineering for High Mobility Ge nFETs
Hiroaki Arimura1,Daire Cott1,Roger Loo1,Kurt Wostyn1,Guillaume Boccardi1,Jacopo Franco1,Sonja Sioncke1,Qi Xie2,Fu Tang3,Xiaoqiang Jiang3,Michael Givens3,Eddie Chiu4,Jerome Mitard1,Dan Mocuta1,Nadine Collaert1
imec1,ASM Belgium2,ASM International3,HPSP4Show Abstract
Among high mobility channel materials, germanium is a unique candidate which offers both high hole and electron mobilities required for future CMOS. Forming a high-quality MOS interface is mandatory to bring out the full potential of Ge, while maintaining sufficient gate stack reliability is also compulsory on real devices. Recent reliability studies on Ge gate stack pointed out that the BTI of GeO2-based gate stack is a serious concern, while the use of Si-passivation layer on Ge shows potential to satisfy the reliability requirements . An epitaxial grown Si passivation layer enables the use of a similar high-k/SiO2 gate stack, which has been intensively studied on Si devices. The presence of an SiO2 interface layer also makes band engineering possible by forming an interface dipole at the high-k/SiO2 interface . On Ge pFETs, high hole mobility and superior NBTI reliability has been successfully demonstrated using a Si passivation layer . In contrast, it is more challenging to achieve low Dit  and superior gate stack reliability on Ge nFET , even with a Si passivation layer. This presentation describes a way to achieve low Dit (5x1010 cm-2eV-1 around mid-gap) and superior gate stack reliability (effective oxide trap density of low x108 cm-2 at Eox=3.5 MV/cm) by using a Si-cap layer. While thinning down the Si-cap layer to an optimum thickness reduces Dit and improves electron mobility, while it increases the effective oxide trap density and degrades reliability because of the quantization in Si-cap layer and/or increase in the amount of Ge in the SiO2 interface layer . To improve the gate stack reliability, La- or Mg-induced interface dipole is formed at the HfO2/SiO2 interface by inserting a thin ALD cap layer . The interface dipole energetically decouples the electron traps in the high-k and the channel electrons, resulting in smaller VTH or VFB shift. Insertion of ALD LaSiO or MgOx is found to also suppress intermixing between HfO2 and SiO2, resulting in a 2-3x Dit reduction. Significant further Dit reduction is demonstrated by performing high-pressure anneal (HPA) in H2, lowering the Dit level down to 5x1010 cm-2eV-1 (1/20x) around mid-gap. Additionally, this presentation will also discuss EOT scalability and VTH tunability on Si-passivated Ge nMOS gate stack.
 J. Franco et al., IEDM 2013, p. 397.
 Y. Yamamoto et al., JJAP 46, p. 7251 (2007).
 J. Mitard et al., VLSI 2014, p. 34.
 C. H. Lee et al., IEDM 2010, p. 416.
 H. Arimura et al., IEDM 2015, p. 588.
 P. Ren et al., VLSI 2016, p. 32.
 H. Arimura et al., IEDM 2016, p. 834.
11:00 AM - EP01.01.02
Scavenging Gate Metal for Reducing Defect Density in SiGe MOSCAP Devices
Emily Thomson1,Mahmut Sami Kavrik1,Andrew Betts1,Andrew Kummel1
The use of high mobility SiGe channels in CMOS technology has been impeded by the presence of a high interface defect density between the SiGe and oxide layers. Ge-Ox suboxide bonds at the interface are the main source of these defects. By selectively forming Si-Ox bonds or suppressing formation of Ge-Ox bonds, the interface defect density can be minimized. The higher heat of formation of SiOx compared with GeOx can be used to selectively remove GeOx using an oxygen scavenging metal as the MOSCAP gate metal [1,2]. Previously, Al gate metal has been demonstrated as reducing Dit for Al2O3. In the present work, Al gate metal is used to attain an even lower Dit using HfO2 as the oxide and an optimized forming gas anneal. In this work, thermally deposited aluminum was used as an oxygen scavenging gate metal to achieve an ultra-low defect density of 3x1011 eV-1cm-2 on ALD deposited Al2O3 and HfO2 oxides on Si0.3Ge0.7(100). Aluminum gate metal MOSCAPs were also shown to have an order of magnitude lower leakage current than nickel gate MOSCAPS sweeping from -2 to 2 Vg. Ni gated MOSCAP showed a higher maximum capacitance (2.1 μF/cm2) in comparison with Al gated MOSCAPs (1.5 μF/cm2) due to the growth of Al2O3 during oxygen scavenging. STEM-EDS and EELS results confirm the oxygen scavenging mechanism by showing a silicon rich, sub 5Å thick SiGe-oxide interface.
 Kim, H., McIntyre, P. C., Chui, C. O., Saraswat, K. C. & Stemmer, S. Engineering chemically abrupt high-k metal oxide/silicon interfaces using an oxygen-gettering metal overlayer. J. Appl. Phys. 96, 3467–3472 (2004).
 Liu, C. W., Östling, M. & Hannon, J. B. New materials for post-Si computing. MRS Bull. 39, 658–662 (2014).
11:15 AM - EP01.01.03
Face Dependence of Schottky Barrier Heights and Weak Fermi Level Pinning of Metal Germanides and Silicides on Ge
Yuzheng Guo2,Hongfei Li1,John Robertson1
University of Cambridge1,Swansea University2Show Abstract
The high mobility semiconductor Ge is limited by the high resistance of its n-type contacts due to the Fermi level pinning (FLP) of Schottky barriers (SBs) close to the valence band maximum (VBM). It turns out that this pinning occurs only for SBs of elemental metals whereas the compound metals like germanides and silicides have a different experimental behavior . This ‘extrinsic behavior’ in which the Schottky pinning factor, S, depends on both metal and semiconductor facet is potentially very useful and can be exploited to reduce the large n-Ge SBH. We studied this SBH effect using density functional supercell calculations. The S factor is found to vary from 0.5 to 0.3 for silicides on Si(100) to Si (111), and to 0.3 to 0.2 for germanides on Ge(100) to Ge(111), with also a strong dependence of the effective charge neutrality level’ on the facet. This behaviour is found to be consistent with early experimental results for Si(100) and Si(111) of Tung . Interestingly, it contradicts some later experimental data for Ge , however the ability to make abrupt epitaxial Ge/germanide interfaces is much more difficult for the germanide system than for silicides , and it is proposed that the calculated germanide results are used as guidance for the Ge system.
 T Nishimura, T Yajima, A Toriumi, APX 9 085201 (2016)
 R Tung, JVST B 11 1546 (1993)
 P S Y Lim, Y C Yeo, APL 101 172103 (2012); Y Deng, S Zaima, Thin Solid films 557 84 (2014)
11:30 AM - EP01.01.04
Heterogeneous Integration of III-V and Ge-Based Devices on the Si Platform
Xiao Gong1,Sachin Yadav1,Annie Kumar1,Shuh-Ying Lee2,Kian Hua Tan2,Wan Khai Loke2,Kian Hui Goh1,Bowen Jia2,Satrio Wicaksono2,Soon Fatt Yoon2,Gengchiau Liang1,Yee Chia Yeo1
National University of Singapore1,Nanyang Technological University2Show Abstract
Future electronic systems may employ monolithic or heterogeneous integration of various material systems such as III-V, Ge, and Si to sustain the historical trend of performance enhancement of metal-oxide-semiconductor field-effect transistors (MOSFETs) for high performance and low power logic applications and to enable hybrid circuits consisting of nano-electronic and photonic devices on the Si platform.
In this paper, we present our recent research advances in heterogeneous integration of III-V and Ge-based devices on the Si substrate. In the first part, we discuss the application of the interfacial misfit (IMF) technique which is capable of relieving strain resulting from the large lattice mismatch between two materials and minimizing the formation of threading dislocations. A very thin buffer with sub-120 nm was used prior to the growth of the high-quality channel materials with this technique. Two integration schemes will be covered including the co-integration of vertically-stacked nanowire GaSb p-channel FETs (pFETs) and InAs n-channel FETs (nFETs) as well as the co-integration of Ge pFETs and InAs nFETs on Si substrates using common contact formation, digital etch, and gate stack formation modules. In the second part, we discuss our research effort to enable large-scale monolithic integration of opto-electronic devices for low cost and multi-functional opto-electronic integrated chips (OEICs). The monolithically integrated InGaAs FETs and GaAs/AlGaAs lasers on a Si substrate will be presented. The high-quality layers for the realization of InGaAs transistors and lasers were grown using molecular beam epitaxy (MBE) on a Si substrate using Ge and GaAs buffer layers. The InGaAs FETs show good electrical characteristics with high drive current, high ION/IOFF ratio, and small subthreshold swing. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers were also realized at room temperature with a spectral linewidth of less than 0.5 nm.
EP01.02: InGa, GaN and Nanowires
Tuesday PM, April 03, 2018
PCC North, 200 Level, Room 224 A
1:30 PM - EP01.02.01
III-V Nanowire Tunnel Field Effect Transistors with a SubThreshold Slope of Under 60 mV/Decade
Lund University1Show Abstract
Tunnel Field Effect Transistors have the potential to reduce the power consumption in logic operating at very low off-state current levels and at moderate switching speed. Key metrics include a high on-state current with a high Ion/Ioff-ratio that needs to be combined with a low hysteresis. A low subthreshold slope combined with a high transconductance are needed to meet these requirements.
III-V nanowire Tunnel Field-Effect Transistors have demonstrated hysteresis-free operation of 48 mV dec with a Ion of 10 µA/µm for Vgs=0.3 V. Statistical analysis of a large number of transistors with subthermal operation show that the subthreshold slope mainly is limiting Ion for low Vds (0.1) while gm is limiting for higher Vds (0.3V). Enhancing the transistor performance is thus not only related to the subthreshold slope, but also the on-state performance is critical. III-V heterostructures offers an excellent opportunity based on the wide range of the combinations possible.
The understanding of how different defects contribute to the measured I-V characteristics is essential to identify routes to improve the performance. Bulk traps, interface states, and oxide defects all contribute in different ways, as well as the possible contribution from gap states formed around the band edges. The different contributions may be quantified by careful I-V spectroscopy, demonstrating that such defects can be controlled on a sufficient level for advantageous Tunnel Field-Effect operation.
This work is supported by the Swedish Foundation for Strategic Research and the Swedish Research Council.
2:00 PM - EP01.02.02
Steep Slope Hysteresis-Free Negative Capacitance MoS2 Transistors
Purdue University1Show Abstract
The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. We combine these two advantages and demonstrate for the first time a molybdenum disulfide (MoS2) 2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack. This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 μA/μm, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied. In this talk, we will review the experimental progress at Purdue University on MoS2 n-type 2D NC-FETs, WSe2 p-type 2D NC-FETs, and nano-membrane β-Ga2O3 NC-FETs for wide bandgap CMOS applications.
3:30 PM - EP01.02.03
Novel p-Band Edge Work Function Modulation for Advanced FETs
Bum Ki Moon1,Ohseong Kwon2,Rajan Pandey1,Hyun-Jin Cho1,Choonghyun Lee3,Jingyun Zhang3,Rohit Galatage1,Robin Chao3,Nicolas Loubet3,Veeraraghavan Basker3,Hemanth Jagannathan3,Walter Kleemeier1
GlobalFoundries1,Samsung Electronics2,IBM Research3Show Abstract
Advanced logic CMOS devices require aggressive shrinking for performance and cost. Among many parameters to be scaled, it is particularly difficult to achieve the lowest threshold voltage (Vt) for p-FET (Field Effect Transistors) devices because of higher process sensitivity due to Fermi-level pinning and oxygen out-diffusion at high-k metal gate stacks. These challenges demand work function engineering for the future technologies. For reducing P-FET Vt, increasing the effective work function (EWF) can be one solution. There have been reports that oxygen has the property to boost the work function of the metals such as titanium silicon nitride, molybdenum and tantalum carbide [1-3].
In this paper, we demonstrate a method to reduce the p-FET Vt without the penalties associated with typical gate stack processing. We selected a Transition Metal Composite (here after, Metal-A) having a p-band edge work function as the metal gate for p-FET. Metal-A is deposited using Atomic Layer Deposition (ALD) on high-k dielectric layers, and also it is carefully treated using a modified oxidation method. Measurements from fully integrated advanced transistors showed around 80 mv of Vt modulation without degradation of the inversion thickness (Tinv), which means no increase of equivalent oxide thickness (EOT) through the modified oxidation.
For further understanding of the oxidation effect on EWF (Effective Work Function) change, ab-initio investigation was performed using stacks of Metal-A on a High-K layer (here, Hafnium oxide, HfO2 was chosen as a general material). We computed the EWF from the interface dipole and the vacuum work function of the metal, which can eliminate the need to compute the band offsets. Thus, it avoids the errors introduced in the band structure and the valence band offset calculations.
By comparing EWF values computed for a defect-free-reference against EWF values for the same reference containing oxygen defects at or near the HfO2/Metal-A interface, we found that the presence of oxygen vacancies (Vo) and oxygen interstitials (Oi) plays a big role in modulating the interface dipole. Furthermore, when oxygen interstitials are incorporated in the bulk Metal-A, the resulting EWF is substantially higher. Based on the simulation, we explain the physical mechanism of EWF modulation (accordingly, Vt modulation) obtained in the above experiments: (1) the oxygen atoms diffused from Metal-A replace Vo in high-k layer and also modify the dipole configuration and (2) the residual oxygen interstitials in the Metal-A also increase the bulk EWF value. These results clearly demonstrate the possibility of EWF engineering towards the p-FET band edge in advanced FETs through the proposed modified oxidation method.
 H. Luan, et.al., App. Phys. Lett, vol. 88, p. 142113, 2006.
 Z. Li, et. al., J. Electrochem. Soc., vol. 155 pp. H481-H484, 2008.
 W. Mizubayashi, et. al., VLSI Technology, 2008 Symposium on pp. 42-43, 2008.
3:45 PM - EP01.02.04
Near Surface Depletion of Silicon Dopants in Epitaxially Grown Silicon Doped InAs
Guy Cohen1,Marinus Hopstaken1,Michael Saccomanno1,William Spratt1,Paul Solomon1,Christian Lavoie1,Renee Mo1,Sang-Moon Lee2,Jungtaek Kim2,Woo-Bin Song2,Doron Cohen Elias3
IBM T.J. Watson Research Center1,Samsung Electronics Co.2,Soreq Nuclear Research Center3Show Abstract
We report the depletion of silicon dopants at the surface of epitaxially grown in-situ doped InAs layers. The lower concentration of Si doping at the surface is technologically significant as it leads to increase in contact resistance.
The depletion of Si was observed in metal-organic chemical vapor deposition (MOCVD) grown Si doped InAs layers as well as in InAs layers grown by atomic layer epitaxy (ALE). In situ doping was employed to make InAs layers with [Si] concentration from 2E18 to 8E19 cm-3.
Secondary ion mass spectrometry (SIMS) was used to study the Si profile in the Si doped InAs layers. It was found that the silicon depletion was larger for higher doping levels of Si in the bulk of the InAs layer. The Si depletion extends to about 5 nm from the InAs surface. We have employed Ultra-Low Energy (ULE-) SIMS (250 – 400 eV Cs+ ion impact energy) to demonstrate that the Si depletion width extends well beyond the InAs native oxide thickness and SIMS surface transient depth.
The top 8 nm of the InAs layers were controllably etched by self-limited digital etching to remove the Si depleted region. The SIMS Si profile of etched InAs does not exhibit Si depletion, thus suggesting that depletion of Si atoms near the surface takes place during the layer growth.
Co-doping the InAs layer with silicon and zinc (a p-type dopant) did not change the Si depletion profile near the surface. This suggests that the depletion of the silicon atoms near the surface is not a result of an electrical field induced by surface pinning .
1. E. F. Schubert, Doping in III-V Semiconductors, Cambridge university press, 1993.
4:00 PM - EP01.02.05
Enhancement-Mode GaN-Based MIS-FETs and MIS-HEMTs
Mengyuan Hua1,Kevin J Chen1
Hong Kong University of Science and Technology1Show Abstract
An attractive approach to realizing enhancement-mode (E-mode) GaN-based lateral heterojunction power transistors is to recess the barrier layer under the gate electrode, and thus remove the inherent positive polarization charges to obtain positive threshold voltage VTH . To suppress the gate leakage, the barrier layer should be replaced by insulating gate dielectric, forming a fully recessed MIS-FET or partially recessed MIS-HEMT. High electron mobility in the gate-controlled channel is maintained in MIS-HEMT with a thin barrier layer. However, the manufacturing of MIS-HEMT faces challenge in VTH uniformity control due to difficulties in precisely controlling the recess etching depth. In addition, the buried-channel MIS-HEMT typically exhibits worse VTH thermal stability than the surface-channel MIS-FET  as a result of the floating dielectric/AlGaN interface. Thus, the E-mode fully recessed MIS-FET possesses practical benefits in terms of manufacturing capability and device stability.
Obtaining high-quality interface with low Dit is one of the most critical challenges in MIS-gate. According to a first-principles calculation study, the GaN surface states distribution can be modified by nitridation with the shallow trap (i.e. close to EC) density greatly reduced . Interface protection is another technique to prevent the GaN surface from degradation at high temperatures (~ 800 oC)  at which high-quality gate dielectric is deposited. The high temperature is necessary to obtain a densified dielectric film with reduced defect density. With these techniques, SiNx gate dielectric (with the benefits of large conduction band offset of ~2.3 eV with GaN and relatively high dielectric constant of 7) deposited at 780 oC by LPCVD (low pressure chemical vapor deposition) is successfully integrated with recessed-gate structure to obtain E-mode MIS-HEMT/FET with enhanced VTH stability and gate dielectric reliability.
Both MIS-FETs and MIS-HEMTs exhibit small hysteresis △VTH < 0.1 V and low subthreshold swing SS ~ 97 mV/dec, benefiting from the greatly improved interface quality. As fully-recessed gate can reduce the sensitivity of VTH on the recess depth, higher VTH uniformity is obtained in MIS-FET. The MIS-FET also has more positive VTH (~2.4 V) than MIS-HEMT (~0.4 V). RON of MIS-FET (~13 Ω●mm) is slightly larger than that of the MIS-HEMT (~10 Ω●mm) due to lower MIS-channel electron mobility. The MIS-FET has a much better VTH stability than the MIS-HEMT, benefiting from the limited movement of EF at dielectric/GaN interface. In addition to thermal stability, the VTH of MIS-FET also shows better stability in long time NBTI stress.
In summary, surface nitridation and interface protection play critical roles in enabling a high-quality dielectric/III-N interface with low Dit. The fully recessed MIS-FET possesses many advantages in larger recess-depth tolerance, more possitive VTH, and higher VTH stability.
4:30 PM - EP01.02.06
Selective Surface Oxidation with Ozone Nano-Laminate for Low Interface Defects at HfO2-SiGe
Mahmut Sami Kavrik1,Emily Thomson1,Andrew Betts1,Andrew Kummel1
University of California, San Diego1Show Abstract
Silicon germanium (SiGe) channels are being developed for CMOS technology due to their high intrinsic carrier mobility. The superior properties of SiGe can be utilized only if SiGe-high k interfaces with a low interface defect density (Dit) can be fabricated. Germanium oxide (GeOx) is known to be the source of interface defects and by selective reduction, selective removal of GeOx, or selective formation of interfacial silicon oxide (SiOx), low-defect interfaces can be formed. Previously, ozone has been employed to form a GeO2 rich interlayer on high Ge content SiGe to passivate the interface (1). In this work, a new method, selective oxidation with ozone nano laminate, was employed; in this method, ozone pulses are dispersed evenly within the HfO2 during ALD HfO2 deposition. Optimized ozone pulsing between 5nm thick HfO2 oxide layers reduced the defect density by 60% compared to standard HfO2 ALD on the same samples. With the ozone nanolaminate and optimized forming gas anneal, an interface defect density of Dit=5x1011 eV-1cm2 with accumulation capacitance of 1.75uF/cm2 was demonstrated for the HfO2/Si0.7Ge0.3 interface. The distribution of the defect density across the band gap was calculated according to full interface state model and integrated Dit of <1x1011 eV-1cm2 was obtained. High resolution STEM images shows thin interface and Si enriched composition compared to the bulk was observed in STEM-EELS and EDS analysis. The data demonstrates that dry selective oxidation can be used to form the SiOx layer required to passivate Si0.7Ge0.3(001).
Ando et al, IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 3, MARCH 2017
4:45 PM - EP01.02.07
Characterization of ScGaN, FeGaN and FeScGaN as Alternative Materials for High Electron Mobility Transistors (HEMTs)
Simona Pace1,2,Bin Zou2,Robert Davies2,Michelle Moram1
University of Cambridge1,Imperial College London2Show Abstract
In recent years, much effort has been made to find alternative materials and geometries to achieve ultra-small stable electronic devices. Among all, high electron mobility transistors (HEMTs) are very promising in terms of both high carrier mobility and high breakdown voltage. However, the commonly used AlGaN/GaN interface still shows limitations, such as high defect concentrations and gate leakage, that need to be overcome. For this reason, the exploration of novel ternary and quaternary nitrides, as well as the engineering of their lattice parameters, band gaps and their relationship, have been encouraged.
Transition metal nitrides (TMN) have recently received increasing attention due to their unique electronic and structural properties . The optoelectronic properties of ScxGa1-xN are very interesting for HEMTs: ScN and GaN are stable in two different structures, therefore, as x increases from 0 (GaN) to 0.5 (Sc0.5Ga0.5N) the wurtzite structure distorts, the c/a ratio decreases, eventually producing a structural phase transition to a non-polar 5-fold coordinated hexagonal crystal structure. In the composition range around this phase transition, ScxGa1-xN shows unique properties, such as huge piezoelectric constant, high electron mobility, and good lattice match with GaN.
Another interesting TMN material for electronic application is FeGaN . If GaN is doped with small concentration of iron, the thin film shows semi-insulating properties with high quality structure and high resistivity. When FeGaN is employed in HEMTs, its semi-insulating behaviour will better isolate the device by lowering the leakage from both the gate and the substrate interfaces.
In addition, the quaternary material FeScGaN is expected to show intermediate properties between the two ternary TMN materials. Thus, if it is employed in ScGaN/GaN HEMTs, the gate leakage will decrease without introducing lattice-mismatch defects at the FeScGaN/ScGaN interface.
To successfully employ these novel materials in HEMT devices, it is then necessary to achieve deep knowledge of both their electronic and structural properties. For this reason, ScGaN, FeGaN and FeScGaN thin films are grown on sapphire using Electron Beam Epitaxy technique and then fully characterized. HR-TEM, STEM, XRD are used to explore the change in the microstructure of all the thin films for different TM content. SIMS is employed to calculate both the TM element content and the level of impurities in each film. Finally, the electron mobility, band gap and Raman shift are reported to investigate the electronic and optical properties of these materials and their dependence on the TM concentration.
These TMNs show high-quality crystal structures and larger band gap for higher TM content; from these preliminary results ScGaN, FeGaN and FeScGaN seem to be promising materials for enhanced electronic devices.
 M.A. Moram S. Zhang, J Mater Chem A, 2014,2, 6042-6050
 A. Bonanni, Semicond Sci Technol, 2007, 22, R41-R56
EP01.03: Poster Session
Tuesday PM, April 03, 2018
PCC North, 300 Level, Exhibit Hall C-E
5:00 PM - EP01.03.01
Annealing Stability in MgO/CoFeB/Ta/[Co/Pd]n Composite Structures
Te-Ho WuShow Abstract
The effect of the annealing temperature on the perpendicular magnetic anisotropy (PMA) of composite structures was studied. We merged a MgO/CoFeB bilayer  and an ultra-thin [Co/Pd]6 multilayer separated by a non-magnetic Ta spacer  of variable thickness tTa. Composite magnetic structures with PMA are technologically relevant in developing high-density memory devices.
The stacks were deposited using magnetron sputtering at room temperature in the absence of an external magnetic field. Thermally oxidized (100) Si wafers were used as substrates. After deposition, samples were heat-treated for 2 hrs. at 250, 300, or 350 C in a high-vacuum magnetic annealing oven with a field of 5 kOe perpendicular to the film plane. Magnetic properties were studied by using an alternating gradient magnetometer (AGM) where magnetization vs. applied
magnetic field (M-H) hysteresis loops were obtained with either out-of-plane or in-plane magnetic fields.
Hysteresis loops show sharp switching characteristics indicating ferromagnetic coupling between the MgO/CoFeB bilayer and the Co/Pd multilayers. Structures lacking a Ta layer show not PMA regardless of whether or not they were magnetically annealed. PMA is obtained after inserting a Ta layer and is observed even in the as-prepared state .
Our results show that Ta layer is essential for obtaining perpendicular axis in the composite MgO/CoFeB/Ta/[Co/Pd]6 structure. Composite structures retain PMA upon magnetic annealing up to 350 C. The ferromagnetic exchange was strong enough to switch MgO/CoFeB and [Co/Pd]6 together, with the magnetic moment either lying along the film plane when tTa = 0, or pulled out of the film plane when tTa ≠ 0. No antiparallel magnetic coupling was observed within the Ta thickness interval explored (0 ≤ tTa ≤ 0.7 nm). Perpendicular composite structures with sharp magnetization reversal and annealing stability are relevant in perpendicular CoFeB-based magnetic tunnel junctions for the development of gigabit-scale nonvolatile memory.
5:00 PM - EP01.03.02
Doping Silicon Using Self-Assembled Monolayers for Ultra-Shallow Diffused Layers
Jenna Doran1,Megan Detwiler1,Scott Williams1,Santosh Kurinec1
Rochester Institute of Technology1Show Abstract
Ultra-shallow junctions have become more desirable in the semiconductor industry as devices have continued to shrink in size and non-planar devices such as FinFETs and 3D nanostructures have become more common. Semiconductor devices are traditionally doped using a combination of ion implantation or spin-on dopant and thermal diffusion techniques; however, these have limitations such as crystalline damage, use of hazardous chemicals, or glassy skin formation. Monolayer doping (MLD) is an attractive alternative for forming sub-50 nm junctions. A dopant-containing compound forms a conformal self-assembled monolayer on the surface, then is capped with an insulating oxide and activation via rapid thermal anneal to form an ultra-shallow junction. The monolayers are formed with a phosphorous-containing compound for n-type doping, and a boron-containing compound for p-type doping. Techniques such as SIMS and sheet resistance measurements are used to characterize junctions and doping profiles. P+N and N+P diodes are fabricated and characterized. An in-house process for fabricating MOSFETs utilizing MLD for source/drain doping is developed. Electrical data on sub-50 nm emitter diodes and MOSFETs will be presented.
5:00 PM - EP01.03.03
Coercive Voltage of Dipole Switching on Ferroelectric Hf1-xZrxO2 for Steep Subthreshold Swing Operation
Min-Hung Lee1,Chun-Yu Liao1
National Taiwan Normal University1Show Abstract
Ferroelectric Zr doped in HfO2 as gate stack has been intensively and extensively investigated to integrate with FETs due to following current CMOS architectures and feasibility ALD (atomic layer deposition) supercycle approach . The bi-stable state feature of hysteresis loops by ferroelectric materials satisfies the demands of voltage amplification concept for negative capacitance (NC)  and storage signal purpose for memory .
The discussion about NC reliability with sub-2.3kbT/q SS and wake-up effect is demonstrated. The ferroelectric (FE) coercive voltage for dipole switching is effectively reduced to a practicable NC onset voltage (<1V) after wake-up. This is one of ferroelectric characteristics for complete dipole switching beyond coercive voltage . In order to observe this phenomenon of NC-FETs, the 5nm FE-HZO FETs are performed double sweep with the range from small to large. In order to reach the FE/NC region, the applied voltage needs high enough for complete dipole switching, and coercive E-field approaches to 2MV/cm. A gradual transition of ferroelectricity with crystallization temperature increasing results in subthreshold swing (SS) < 60mV/dec and hysteresis loop formation. The device by gate-last is more stable than that of gate-first due to well Source/Drain activation. It is promising to use ultra-thin FE-HZO as the guidelines for NC and memory applications. To develop a practicable FE-coercive/NC-onset voltage is an important issue for evaluating this technology.
The authors are grateful for the funding support from the National Science Council (MOST 105-2628-E-003-002-MY3, 106-2221-E-003-029-MY3 & 106-2622-8-002-001), process supported by National Nano Device Laboratories (NDL) & Nano Facility Center (NFC), Taiwan.
 M. H. Lee et al, IEEE J. of the Electron Device Society, vol. 3, no. 4, pp. 377-381, 2015.
 M. H. Lee et al, IEEE Electron Device Letter, vol. 36, no. 4, pp. 294-296, 2015.
 S. Salahuddin and S. Datta, NanoLetters, vol. 8, no. 2, pp. 405-410, 2008.
 S. Salahuddin and S. Datta, in IEDM Tech. Dig., 2008, pp. 693-696.
 J. Müller et al, in Symp. on VLSI Technology and Circuits, 2012, pp. 25-26.
 P. Sharma et al, in Symp. on VLSI Technology and Circuits, 2017, pp. T154-T155.
5:00 PM - EP01.03.04
Boosting Performance of NiGe/n-Ge Schottky Contact with Modulation of Effective Schottky Barrier Height by Capping Metals with Different Work Function
Yu-Che Chou1,Yu-Hsi Lin1,2,Chung-Chun Hsu1,Chen-Han Chou1,Chao-Hsin Chien1
Institute of Electronics, National Chiao-Tung University1,School of Software and Microelectronics, Peking University2Show Abstract
In the continuous scaling down of the device for logic circuits, germanium has been considered as a candidate for high performance logic device because of its high mobility. [1,2] However, one of the most difficult challenge in realizing high performance device on germanium is the reduction of source/drain (S/D) resistance because of its low dopant solubility.  The use of the shallow metal S/D is a likely way to solve this limitation. The research of germanide/germanium Schottky junction has been popular in recent years.  In this paper, we propose a simple, novel and reliable technique to modulate the barrier height of NiGe/n-Ge contact formed by microwave annealing (MWA) with capping another pure metal on top of NiGe. [5,6] The physical and electrical properties of capping metals on NiGe/n-Ge Schottky junctions will be discussed by depositing various work function metals (Al (4.26 eV), Ti (4.33 eV), Ni (5.15 eV) and Pt (5.65 eV)) [7,8] as capping metals.
After DHF cleaning on (100)-oriented n-type Ge substrate, the 10-nm-thick Ni was deposited by physical vapor deposition (PVD). Next, MWA (5.8 GHz, 600W, in N2 ambient, for 150 s) was performed for NiGe alloy formation. The X-ray diffraction (XRD) pattern shows that NiGe was the only phase formed by MWA. The transmission electron microscopy (TEM) figure shows that the 10-nm-thick Ni was consumed completely and transformed into a smooth and 20-nm-thick NiGe was formed by MWA. And the energy dispersive spectroscopy (EDS) analysis is consistent with XRD pattern on NiGe composition. Afterwards, various 100-nm-thick metals with different work function were deposited by PVD including Al, Ti, Ni and Pt.
Upon completion of the process mentioned above, we obtained NiGe Schottky junctions with various work function metals as capping metal. The first thing we want to mention is the ION/IOFF ratio. With different work function metals as capping metal including Al, Ti, Ni and Pt, the ION/IOFF ratio at +/- 1V are 2.89×104, 6.50×104, 9.12×104 and 1.31×105 respectively. Furthermore, we obtain the difference of Schottky barrier height (SBH) from 0.570 eV to 0.591 eV between Al and Pt as capping metal. These two results indicate that with different work function metals as capping layer, we can modulate the SBH of NiGe/n-Ge junction so that we can improve the ION/IOFF ratio. The last thing we want to mention is the ideality factor. The ideality factors of Al, Ti, Ni and Pt as capping metal are 1.28, 1.21, 1.13 and 1.12 respectively indicating that the higher work function of capping metal is the more approaching-to-one ideality factor is. In conclusion, by choosing higher work function metal as capping metal on NiGe, we can improve the performances of the NiGe/n-Ge Schottky diode with higher on current, ION/IOFF ratio, lower leakage current and closer to one ideality factor by SBH modulation. This is simple, novel and suitable technique for fabricating high performance Schottky Ge pMOSFET.
5:00 PM - EP01.03.05
Exotic Needle-Like Crystals of Phosphorus Doped SnTe Dirac Materials—Synthesis and Applications in Memory/Micro-Sensor Devices
Sayan Sarkar1,Prashant Sarswat1,Michael Free1
University of Utah1Show Abstract
Among the members of tin-chalcogenides family, the narrow-band semiconductor SnTe has recently emerged as a 3D crystalline topological insulator (TCI) exhibiting band inversion at the L point where certain crystalline symmetries allow the protection of robust topological states at the surface. We investigated the electronic band structures of pristine P-doped SnTe doped using density functional theory (DFT) calculations followed by synthesis. The substitution of a Sn vacancy by P maintained the intrinsic band inversion at the L point but the direct band gap reduced to 30 meV upon the incorporation of spin orbit coupling (SOC), which is relatively smaller than the experimentally observed band gap of pristine SnTe. The experimental methods for P-doped SnTe synthesis was based on the vapor-liquid-solid technique. The morphology of the synthesized crystals was exotic in the form of micro-needles, as a consequence, it led to the amplification of signal arising from the topological surface states due to the reduction of surface area to volume ratio. Moreover, the modified effective mass, lattice imperfection and related charge carrier conductivity acted as our motivation to implement them in Ferro-electric Field Effect Transistor (FeFET). The application of a cyclic potential resulted in an exceptionally large memory window of 3.1 V accompanied by a drastic current change within a certain potential range.
5:00 PM - EP01.03.06
Transient Electron Transport Within Bulk Wurtzite Zinc-Magnesium-Oxide Alloys Subjected to High-Fields
Stephen O'Leary2,Walid Hadi1,Poppy Siddiqua2,Michael Shur3
Florida State University1,University of British Columbia2,Rensselaer Polytechnic Institute3Show Abstract
We present some recent results on the transient electron transport that occurs within bulk alloys of zinc-magnesium-oxide. These results are obtained using an ensemble semi-classical three-valley Monte Carlo simulation approach. Starting with steady-state electron transport simulations, we find that, for electric field strengths in excess of 180 kV/cm, that the steady-state electron drift velocity associated with these alloys exceeds that associated with bulk wurtzite gallium nitride. We also present evidence that suggests that the negative differential mobility exhibited by the velocity-field characteristic associated with alloys of zinc-magnesium-oxide is not related to transitions to the upper valleys. The transient electron transport that occurs within this alloy is then studied by examining how electrons, initially in thermal equilibrium, respond to the sudden application of a constant electric field. From these transient electron transport results, we conclude that for devices with dimensions smaller than 0.1 microns, gallium nitride based devices will offer the advantage, owing to their superior transient electron transport, while for devices with dimensions greater than 0.1 microns, electron devices based on alloys of zinc-magnesium-oxide will offer the advantage, owing to their superior high-field steady-state electron transport. The device implications of these results will be explored. Our results show that the Monte Carlo simulations of the materials response to the instant change of the electric field could be used for establishing the figures of merit for materials applications for short channel ultra high-speed semiconductor devices.
5:00 PM - EP01.03.07
Potential Performance of Zinc Oxide Based Devices—A Transient Electron Transport Analysis
Stephen O'Leary2,Walid Hadi1,Poppy Siddiqua2,Michael Shur3
Florida State University1,University of British Columbia2,Rensselaer Polytechnic Institute3Show Abstract
We study how electrons, initially in thermal equilibrium, drift under the action of an applied electric field within bulk wurtzite zinc oxide. We find that the optimal cut-off frequency ranges from around 50.3 GHz when the device thickness is set to 1000 nm to about 11.5 THz when the device thickness is set to 10 nm. These results suggest that zinc oxide holds great promise for future high-speed electron device applications.
5:00 PM - EP01.03.08
High Photosensitivity Multilayer MoSe2 Phototransistors
Hyejoo Lee1,Woong Choi1
Kookmin University1Show Abstract
Unlike graphene, the existence of bandgaps in transition metal dichalcogenides such as MoSe2 offers an attractive possibility of using single layer MoSe2 field-effect transistors (FETs) in low-power switching devices and photodetectors. Yet, the fabrication demands and the physics of MoSe2, among other reasons, suggest that multilayer MoSe2 may be more attractive than single layer MoSe2 for FET applications in a thin-film transistor configuration. In this presentation, we explore the optoelectronic properties of bottom-gate multilayer MoSe2 phototransistors fabricated on SiO2/Si substrates with mechanically exfoliated flakes. Our MoSe2 phototransistors exhibit decent field-effect mobilities (> 50 cm2 V-1 s-1) and high on/off-current ratio (> 106). For 650 nm incident laser, the device shows high photoresponsivity (> 500 A W-1) , high detectivity (> 1011 jones) and a fast response time (< 2 ms) at room temperature. These optoelectronic properties are better than those of MoSe2 phototransistors reported in literature. These results demonstrate a compelling case of multilayer MoSe2 phototransistors for applications in photodetectors.
5:00 PM - EP01.03.09
Optoelectronic Properties of Ultraviolet-Ozone-Treated Single Layer MoS2 Crystals
Hae In Yang1,Sunyeong Park1,Woong Choi1
Kookmin University1Show Abstract
Unlike graphene, the existence of direct bandgaps in transition metal dichalcogenides such as MoS2 offers an attractive possibility of using single layer MoS2 in optoelectronic devices. Because of the absence of dangling bonds in MoS2, surface treatment such as ultraviolet-ozone (UV-O3) treatment is necessary before the deposition of high-k dielectrics on MoS2 to fabricate optoelectronic devices such as phototransistors. However, little interest has been given to the effect of UV-O3 treatment on the optoelectronic properties of single layer MoS2. In this presentation, we systematically investigate the effect of UV-O3 treatment on the photoluminescence of mechanically exfoliated single layer MoS2 flakes. We observe photoluminescence quenching in single layer MoS2, accompanied by reduction and broading of MoS2 Raman modes with increasing UV-O3 treatment time. X-ray photoelectron spectroscopy confirms the formation of oxygen bonding. We demonstrate that the formation of oxygen bonding upon exposure to UV-O3 treatment leads to a direct-to-indirect bandgap transition in single-layer MoS2. These results also demonstrate the significant impact of UV-O3 treatment on the optoelectronic properties of single layer MoS2 suggesting the importance of using optimized process conditions.
5:00 PM - EP01.03.10
Surface Oxidation of Monolayer MoS2 Thin Film by Ultraviolet-Ozone Treatment
Changki Jung1,Woong Choi1
Kookmin University1Show Abstract
Unlike graphene, the existence of direct bandgaps in transition metal dichalcogenides such as MoS2 offers an attractive possibility of using single layer MoS2 in transistors, sensors, optoelectronic devices, and flexible systems. Because of the absence of dangling bonds in MoS2, surface treatment such as ultraviolet-ozone (UV-O3) treatment is necessary before the deposition of high-k dielectrics on MoS2 to fabricate various devices. However, little interest has been given to the effect of surface oxidation of single layer MoS2 by UV-O3 treatment. In this presentation, we systematically investigate the effect of UV-O3 treatment on the monolayer MoS2 thin films obtained by chemical vapor deposition (CVD). We observe photoluminescence quenching in monolayer MoS2 thin films with increasing UV-O3 treatment time. We also observe the reduction and broading of MoS2 Raman modes with increasing UV-O3 treatment time. X-ray photoelectron spectroscopy indicates the nature of oxygen bonding changes with increasing UV-O3 treatment time. These results demonstrate the significant impact of surface oxidation by UV-O3 treatment on monolayer MoS2 thin films suggesting the importance of using optimized surface treatment conditions for device applications.
5:00 PM - EP01.03.11
Heterogeneous Integration of Low Power Electronics with High-Performance Photonics for Ultra Low Power Nanosystems
Satrio Wicaksono1,Kian Hua Tan1,Wan Khai Loke1,Shuh-Ying Lee1,Bowen Jia1,Chiew Yong Yeo1,Soon Fatt Yoon1,Xiao Gong2,Sachin Yadav2,Annie Kumar2,Kian Hui Goh2,Yuan Dong2,Gengchiau Liang2,Yee Chia Yeo2
Nanyang Technological University1,National University of Singapore2Show Abstract
The introduction of III-V materials onto a Si-platform has been of tremendous interest for a very long time. III-V compound semiconductors high electron mobility and direct bandgap properties have been deemed to be the solution to the scaling problems in Si CMOS (complementary metal oxide semiconductor) transistor, through the use of high mobility channel and light emitting devices for optical interconnects. The application of such technology, however, is hindered by numerous issues. The considerable lattice mismatch between Si and high mobility III-V materials (i.e., (In)GaAs, InAs, GaSb, and InSb) and the lack of processes that are amiable to Si manufacturing environment for surface passivation, gate stack dielectric, and metal contacts schemes are some of them. Furthermore, as the substrate cost difference between III-V wafers and Si wafers is significant, a way to reuse and recycle the III-V substrates or create new III-V-on-Si substrates is needed.
In this work, a variety of solutions to bridge the lattice constant gap and to realize III-V CMOS and III-V laser on Si-based substrates will be highlighted. A combination of high-temperature annealing, migration enhanced epitaxy and buffer engineering techniques was developed on a Si-based substrate to minimise anti-phase boundary and threading dislocation defects. Two different buffer engineering were explored, an approximately 800nm-thick graded InAlAs buffer for lattice constant = InP lattice constant and a thinner interfacial misfit (IMF) buffer for lattice constants ≥ 6.0Å. The graded buffer approach was deployed to demonstrate InGaAs nFET and InGaAs n-FET monolithically integrated with AlGaAs/GaAs multiple quantum well laser on GeOI (germanium on insulator) substrate. Furthermore, the IMF sub-120 nm buffer approach allows integration of highly mismatch materials on GeOI substrate without having to go through a thick graded buffer process. This buffer technique alleviates some of the fabrication process challenges caused by the significant step height difference which exists where the graded buffer was used and allows a common gate stack formation processes to be developed. The use of IMF buffer enables demonstration of novel III-V (InAs) n-FET and (GaSb) p-FET or InAs n-FET and Ge p-FET monolithically integrated on the same Si-based substrate with excellent ION performance. Some III-V (InAs and InSb) and Ge(Sn) photodetectors grown on Si-based substrate operating at the mid-IR range will also be presented. Lastly, GaAs/Si heterogeneous wafer bonding with a specific bond energy of 478 mJ/m2 was realized at an annealing temperature as low as 140°C following a plasma activation step. This can potentially be combined with epitaxial lift-off processes to create new III-V on insulator wafers. The work done in this report was supported by the Singapore National Research Foundation through a Competitive Research Program (Grant No: NRF-CRP6-2010-4).
5:00 PM - EP01.03.12
Total Ionizing Dose Effects on the 1T-TaS2 Charge-Density-Wave Devices—Possibility of Radiation Hard Applications
Ruben Salgado1,Guanxiong Liu1,Enxia Zhang2,Chundong Liang2,Matthew Bloodgood3,Tina Salguero3,Daniel Fleetwood2,Alexander Balandin1
University of California, Riverside1,Vanderbilt University2,University of Georgia3Show Abstract
The voltage controlled charge-density-wave (CDW) phase transition in quasi-2D 1T-TaS2 offers a possibility of using the switching behavior of these macroscopic quantum states for electronic applications. We have recently demonstrated a frequency tunable oscillator based on an integrated graphene–h-BN–TaS2 device that is capable of operating at room temperature . The carrier concentrations in the nearly commensurate (NC) and incommensurate (IC) CDW phases in 1T-TaS2, which are utilized for switching the device, are very high, on the order of 1021 cm-3 and 1022 cm-3, respectively. The high carrier concertation creates conditions for resilience to the total ionizing dose (TID) effect, which is radiation damage to semiconductor device in space and high-energy accelerator environment. In conventional MOSFET, electron–hole pairs generated in the oxide during TID irradiation can accumulate in the oxide layers and interfaces, leading to the shifts in the threshold voltage and increase in the leakage current. Unlike conventional field-effect-transistors (FETs), the 1T-TaS2 device is a two-terminal CDW device, in which the switching is controlled by the source-drain voltage rather than the gate voltage. No gate oxide is needed for its operation . In this work, we evaluate the TID response of 1T-TaS2 CDW devices by examining the current-voltage (I-V) characteristics under X-ray irradiation at doses up to 1 Mrad(SiO2). We find that the threshold voltage, VTH, for the abrupt resistance change shifts by only ~2%, the resistance of the CDW states changes by less than ~2 % (low resistive state) and ~6.5 % (high resistive state), and the self-sustained voltage oscillations in this 1T-TaS2 oscillator function well after the full irradiation sequence . The obtain results indicate that 1T-TaS2 CDW devices are promising for applications in space and other high-radiation environments.
The work at UC Riverside was supported, in part, by NSF EFRI 2-DARE project: Novel Switching Phenomena in Atomic MX2 Heterostructures for Multifunctional Applications and by UC-National Lab Collaborative Research and Training Program.
 G. Liu, B. Debnath, T. R. Pope, R. K. Lake, T. T. Salguero and A. A. Balandin, Nature Nanotechnology, 11, 845 (2016).
 G. Liu, E. X. Zhang, C. D. Liang, M. A. Bloodgood, T. T. Salguero, D. M. Fleetwood, A. A. Balandin, IEEE Electron Device Letters (accepted, 2017) 10.1109/LED.2017.2763597.
5:00 PM - EP01.03.13
Understanding Self-Heating Effects in Silicon-on-Insulator (SOI) MOSFET Devices
Dragica Vasileska2,Suleman Qazi1,2,Xiong Zhang2,Payam Mehr2,Katerina Raleva3,Trevor Thornton2
University of Engineering and Technology1,Arizona State University2,University Sts Cyril and Methodius3Show Abstract
Silicon-on-Insulator (SOI) technology possesses many advantages over bulk silicon such as the reduction of parasitic capacitances, excellent subthreshold slope, elimination of latch up and resistance to radiation . For these reasons, SOI is the preferred technology for high-speed, high-temperature, and low-power microelectronic devices. SOI MOSFET devices employ a buried insulating thin layer, usually made of SiO2 to electrically isolate devices from the bulk semiconductor. Due to the poor thermal conductance, the buried dielectric layer thermally insulates the MOSFET from the bulk . Consequently, the heat generated in SOI MOSFETs causes a larger temperature rise than in bulk devices under similar conditions, and this self-heating effect results in reduced carrier mobility and a corresponding decrease in the transconductance and speed. The self-heating effect can have significant impact on the device reliability as well.
This paper is an attempt to understand the effects of heat generation in SOI technology using a multiscale simulation and modeling scheme developed at Arizona State University in collaboration with IMEC in Belgium . This scheme allows for simulation of carrier self-heating in the device and the corresponding thermal transport at the interconnect level, both at the same time. Previous work has successfully simulated self-heating in bulk devices, but this work strives to model the self-heating in SOI devices.
This scheme involves two components: 1). A numerical device level simulator that uses the Monte Carlo (MC) method to solve the Boltzmann transport equation (BTE) which is coupled with a Poisson solver to evaluate the charge distribution, while a self- consistent, energy balance equation is solved for optical and acoustic phonons to account for the self-heating effects. 2). The device simulator is coupled to a Silvaco module which solves for thermal transport in circuit interconnects using the Fourier law. Hence this multi-scale thermal simulation and modeling scheme is capable of analyzing thermal effects in nanoscale integrated electronics.
 R. Chau, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros, and M. Metz, “Silicon nano-transistors and breaking the 10 nm physical gate length barrier,” in Proc. Device Res. Conf., Jun. 2003, pp. 123–126.
 T. Numata and S. Takagi, “Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2161–2167, Dec. 2004.
 S. S. Qazi, A.R. Shaik, R.L. Daugherty, A. Laturia, X. Guo, E. Bury, B. Kaczer, K. Raleva and D.Vasileska, “Multi-scale modeling of self-heating effects in silicon nanoscale devices”, proceedings of the 15th International Conference on Nanotechnology (IEEE NANO), Rome, Italy, pp. 1461 - 1464, 2015.
5:00 PM - EP01.03.14
Air Stability of 2D Hafnium Dichalcogenides
Antonio Cruz1,Zafer Mutlu1,Mihri Ozkan1,Cengiz Ozkan1
University of California, Riverside1Show Abstract
Two-dimensional hafnium diselenide (HfSe2) and hafnium disulfide (HfS2) have impressive theoretical properties but are among the less well-studied transition metal dichalcogenides. Further research is needed to realize high-performance Hf-based devices. We investigated the air stability of mechanically exfoliated layers of HfSe2 and HfS2 via atomic force microscopy and Raman spectroscopy studies. With continued exposure to air, the surface of HfSe2 progressively transforms from HfSe2 to HfOx and Se, as confirmed by changes in Raman spectra and by the appearance of Se-rich, spire-like features. We determined that sample thickness, total time of air exposure and and exfoliation in a glove box versus in air all affect the degree of transformation. HfS2 was much more stable in air and served as a comparison for the study of HfSe2. This work lays out initial steps toward controlling the behavior of HfSe2 surfaces, which can inform future efforts to fabricate Hf-based transistors.
5:00 PM - EP01.03.15
High Performance Silicon Core-Shell Junction Field Effect Phototransistor by Monolayer Doping
Jiajing He1,Huimin Wen1,Yaping Dan1
Shanghai Jiao Tong University1Show Abstract
The integration of complementary metal-oxide-semiconductor field effect transistors (CMOSFET) with photonics requires photodetectors to operate at hundreds of giga hertz (GHz). This can be achieved by scaling down the size of photodetectors . But a smaller device volume will reduce the light absorption, resulting in a poorer photosensitivity. High gain photodetectors such as avalanche photodetectors are often employed for such applications. Unfortunately, such photodetectors suffer from excessive avalanche noises in particular when the devices operate at high gain. In this work, we develop a novel core-shell nanowire phototransistor that has a gain of 106 and a potential 3dB bandwidth of ~300 GHz. The device is made on a highly doped p-type silicon nanowire that is patterned out of the device layer of a silicon-on-insulator (SOI) wafer. A section of the nanowire is doped to be n-type by self-assembled molecular monolayers [2-3], forming a core-shell pn junction around the nanowire like a structure of “a ring on a finger”. For an appropriate nanowire width, the pn junction will pinch off the nanowire channel without voltage bias. Under light illumination, the channel will open, inducing a high saturation photocurrent. Experimental results show that the nanowire phototransistors show a photoresponsivity of 106 A/W with a potential 3dB bandwidth of 300GHz.
 O. Hayden, R. Agarwal, and C. M. Lieber, “Nanoscale avalanche photodiodes for highly sensitive and spatially resolved photon detection,” Nat. Mater. 5(5), 352–356 (2006).
 Ho, J. C. et al. Controlled nanoscale doping of semiconductors via molecular monolayers. Nat. Mater. 7, 62–67 (2008).
 Guan, B. et al. Nanoscale Nitrogen Doping in Silicon by Self-Assembled Monolayers. Sci. Rep. 5, 12641 (2015).
5:00 PM - EP01.03.16
Multiscale Modeling of Thermal and Electrical Characteristics in Silicon CMOS Devices
Robin Daugherty1,Abdul Shaik1,Dragica Vasileska1
Arizona State University1Show Abstract
This work explores the thermal and electrical characteristics of CMOS devices and circuits using a multiscale dual-carrier approach. Simulating for electron and hole transport simultaneously allows for complementary logic gates to be simulated at the device level, while current and voltage continuity are maintained at the circuit level. Further, the electrical model couples with a multiscale thermal solver, which solves for electron-phonon and hole-phonon interactions at the device level and phonon-phonon thermal transport in the packaging level. This methodology allows for the study of package level thermal transport without sacrificing the nuances of device self-heating, ultimately providing a more comprehensive understanding of how these interactions affect power consumption in CMOS systems.
The electrical model is comprised of an ensemble Monte Carlo simulator coupled with a Poisson solver. This framework provides accurate electrical characteristics in quasi-static regimes by iteratively solving for the potential profile and the electric fields then simulating the effect of the electric field on charge carriers. The Monte Carlo simulator solves the Boltzmann Transport by balancing each particle’s movement in real and momentum space with the collision integral through probabilistic scattering mechanisms. This framework provides current and voltage characteristics for each device; current and voltage continuity are maintained by solving at the circuit level.
Similarly, the methodology for simulating thermal characteristics includes two scales. At the device scale, the energy balance equation determines the transfer of energy from charge carriers to phonons. High-energy electrons or holes relinquish energy to optical and acoustic phonons through scattering and optical phonons decay into acoustic phonons. At the package level, a Fourier law solver simulates the subsequent conduction of heat in the form of lattice vibrations.
This framework proved effective in previous simulations for the electro-thermal characteristics in NMOS devices. This work demonstrates the effectiveness of the dual-carrier electrical solver in simulating CMOS circuits. Future work requires the coupling the dual-carrier electrical solver with the previously proven thermal solver to provide comprehensive electro-thermal simulations of CMOS systems.
5:00 PM - EP01.03.17
Dual Ion Beam Sputtered Low Power high Endurance Resistive Switch with Memristive Behaviour
IIT INdore1Show Abstract
The memory effects in a memristor can be realized through the switching behavior between two distinct resistance states, low resistance state (LRS) and high resistance state (HRS) driven by low pulse voltages. ZnO-based thin films such as undoped ZnO, Mg-doped ZnO, Na-doped ZnO and Mn-doped ZnO have attracted considerable interest as promising resistive switching materials. Gallium doping electrically modulates the behavior of ZnO to suit low power switching behavior. Non-lattice oxygen ions and oxygen vacancies as detected by XPS are found to play important role in imparting forming-free resistive switching behavior.All deposition for fabrication of device has been done by dual ion beam sputtering(DIBS).
To start with fabrication of device, a 60 nm thick Ga-doped ZnO thin film as switching layer is deposited over bottom electrode (BE) Au/SiO2/Si, at a substrate temperature of 100 °C, with DIBS background pressure of 1 × 10-8mBar and Ar:O2 (1:4) (flow rate in sccm), respectively. Finally, circular Au electrodes of 300 µm is deposited on the surface of switching layer. Similarly, Al/ZnO/Al/SiO2/Si device is fabricated to compare the electrode and doping effect using Ar:O2 (2:3) and substrate temperature of 400 °C. The current-voltage (I-V) characteristics of the device are measured using Keithley 2612A sourcemeter and Everbeing probe-station. Al(BE)/ZnO interface has been observed by cross-sectional high-resolution transmission electron microscopy (HR-TEM) using HR-TEM: JEOL JEM-2010 for formation of any AlOx layer. X-ray photoelectron spectroscopy (XPS) having PHOIBOS 100 analyzer with an Al Kα radiation (1486.6 eV) as an excitation source, has been utilized to analyze the binding energy and the composition of each element in switching layer.
I-V characteristics are measured by sweeping a DC voltage in sequence of 0-10 mV-0--10 mV-0 in steps of 1 mV and 0-(+8 V)- 0-(-8 V)-0 in steps of 0.5 V for both devices respectively with a compliance current of 1 mA. I-V of Al/ZnO/Al (AZA) shows device with varying ramp rate exhibiting decreasing hysteresis with increasing ramp rate. Similarly I-V for Au/Ga-ZnO/Au (AuGZAu) conforms to zero crossing of I-V hysteresis loop and shrinking of loop area with increasing ramp rate. Device sets and resets to lower voltage as compared to AZA device. XPS of the switching layer conforms to presence of oxygen vacancies and non-lattice oxygen ions which assist in switching. An amorphous AlOx interfacial layer (~4-5 nm)  formed at Al(BE)/ZnO interface as confirmed by HRTEM for the device in high resistance state (HRS) state which assists in set/reset process.
Ga doping increases conductivity of ZnO film and hence sets and resets at lower voltages. AuGZAu device depicts unipolar memristive behavior as it shows pinched hysteresis with varying frequency, whereas AZA behaves as an ideal bipolar memristor with good endurance and retention. AuGZAu device can be utilized for low power resistive switching.
5:00 PM - EP01.03.18
Structural, Chemical and Electronic Properties of 1T-SnS2
Zafer Mutlu1,Ryan Wu2,Bishwajit Debnath1,Mihri Ozkan1,Roger Lake1,K. Andre Mkhoyan2,Cengiz Ozkan1
University of California, Riverside1,University of Minnesota2Show Abstract
Herein, we have reported on structural, chemical and electronic properties of two-dimensional (2D) tin disulfide (SnS2) crystals grown on silicon dioxide (SiO2) substrates by vapor-phase method. High-resolution annular dark-field (ADF) scanning transmission electron microscope (STEM) analysis indicate that the SnS2 crystals crystallize in 1T phase, which is in consistent with the ab-initio density functional theory (DFT) calculations predicting that SnS2 stabilizes 1T phase at ground state. Photoluminescence (PL) and ultraviolet-visible (UV-vis) spectroscopy measurements suggest that the SnS2 crystals have an indirect band gap of 2.20 eV and 2.35 eV, respectively, which is in good agreement with the DFT-calculated band gap of 2.31 eV. The electrical transport measurements performed on back-gated field-effect transistors (FETs) exhibit n-type semiconductor characteristics of the SnS2 crystals. High-angle annular dark-field (HAADF) STEM imaging and STEM energy dispersive X-ray (EDX) chemical analysis demonstrate that the SnS2 crystals are chemically homogeneous with a stoichiometric S/Sn atomic ratio of 2. Electron energy loss spectroscopy (EELS) and X-ray photoelectron spectroscopy (XPS) analysis present the characteristic Sn and S peaks of SnS2, confirming the phase purity of the SnS2 crystals. Ultraviolet photoelectron spectroscopy (UPS) measurements of the SnS2 crystals provide an ionization potential of 7.51 eV, which is in a perfect agreement with the DFT-calculated ionization potential of 7.51 eV. Resonance Raman spectroscopy in conjunction with ab-initio DFT calculations reveal the characteristic first-order and second-order Raman modes of 1T phase of the SnS2 crystals. Angle-resolved polarized Raman spectroscopy (ARPRS) mappings with different polarization angles show unique edge features of the SnS2 crystals.
5:00 PM - EP01.03.19
The Impact of Solute Segregation on Grain Boundaries in Dilute Cu Alloys
Takanori TsurumaruShow Abstract
The performance of ultrafine wires in the back end of the line (BEOL) is degraded by the persistent polygranular microstructure in copper which introduces more diffusion pathways for copper atoms and which leads to faster electromigration failure times. To improve interconnect reliability, Co-containing capping layers have been used to reduce surface diffusion. Applying the same logic to other interfaces, alloying solutes have been proposed to slow down grain boundary diffusion by increasing the activation energy for atomic motion, but the mechanisms are not well understood and there are many conflicting reports as to their efficacy. One challenge for improving interconnect performance through alloying is a lack of information regarding segregation interactions at grain boundaries and interfaces when minute concentrations are introduced into the copper lattice. Historically, solute was expected to pin GBs, increase resistivity, and reduce diffusivity by GB “stuffing”. More recent studies on GB interface states called ‘complexions’ suggest a more complicated relationship, which can explain these results as well as cases where segregation increases mobility or enhance diffusion. To apply complexion analysis in technologically relevant alloy systems, we are investigating dilute copper alloys created by co-electrodeposition or nanolaminate fabrication using a microfluidic device with separate inputs for solvent and solute. Alloying copper with cobalt may offer a means for stabilizing grain boundaries against electromigration void formation in advanced interconnects. Here we present a means for co-depositing dilute copper alloys, using Co and Ag as the solutes of interest. Microstructure and compositional analysis are presented.
Initial work in the co-deposition of dilute copper alloys has yielded insights into the plating requirements, microstructure and composition of the subsequent films. Additional refinements to the process and analysis are being pursued for comparison to alloys deposited in our 300 mm processing line. Less Co diffusion is observed than expected from literature values of the diffusivity, even under fairly aggressive conditions (500°C for 5 hours). Microstructural analysis with concurrent SIMS testing is used to describe these results in terms of the recrystallization of the alloy. In particular, we discuss whether or not the presence of the alloying element influences the final microstructure of the film and provide a mechanistic explanation for these observations.
5:00 PM - EP01.03.21
Instability of High Resistance Conductive Filaments in RRAM Cells During the Read Operation
Mohammad Al-Mamun1,Marius Orlowski1
Virginia Tech1Show Abstract
In filamentary resistive switching memory cells (RRAM) the resistance of the on-state, Ron, is determined by the limiting (compliance) current, Icc, by the relation Ron~1/Iccn, where the exponent n in many RRAM cells with a metal atom filament is close to unity1. Our RRAM cells are MIM Cu/TaOx/I structures with 25nm TaOx and inert electrode I=Pt,Rh, or Ru. We show that at low Icc (roughly <50μA), the resulting high resistance Ron (~100kΩ) is fragile and operatively undefined as any read operation is bound to disturb its Ron value. The Ron can increase or decrease depending on the read voltage polarity, read voltage starting point, read voltage ramp rate and its sweep direction. In contrast, a set operation performed at a high Icc (>150μA) leads to a stable, low resistance Ron independent of reasonably chosen reading conditions. For Icc<50 μA, the measured Ron will return different values depending whether the measurement within a 100mV voltage interval started at 0.0V, -0.1V or +0.1V. The highly resistive conductive filament (CF) is fragile and subject to small displacement of individual atoms or defects, charging and discharging reactions. The starting point of the applied voltage determines (non)-equilibrium conditions for Cu+, oxygen O2-, and oxygen vacancy Vo charge states and electron concentrations, all of which impact the properties of CF. For highly resistive CF, most read measurements tend to decrease Ron. The underlying strengthening of the CF, ascribed to aggregation or displacement of Cu+, Vo, and O2-, is, often, impermanent and auto-reversible upon suspension of the read operation. However, the rate of atomic displacement depends strongly on the voltage ramp rate. In general, we find that the Ron resistance decreases with decreasing ramp rate which was has been varied from 10V/s to 0.1V/s. The geometric shape of CF, is approximated by that of a truncated cone. The bulk part of the resistance resides at the tip of CF. As soon as the current exceeds Icc ,used at the set operation, it generates at the tip high electric field which depending on its polarity causes new transport of Cu+, O2-, and Vo. The voltage ramp rate determines the time scale of the ionic transport at high fields. Thus ramp rate dependence gives insight into the time scales of the ionic transport. The Ron disturbances by electric fields yield insight into the transient mechanisms for CF formation and rupture.
One implication is that during reset operations the differences between high Ron values are brought to the same value before the filament is ruptured, i.e. the reset is rendered independent of the set operation conditions in contrast to a low resistance CF2. The ionic mechanisms and the time scales involved that lead to the change of Ron during the read and reset operations will be discussed in detail.
 T. Liu, Y. Kang, S. El-Helw, T. Potnis, M. Orlowski, Jap. J. Appl. Phys. 52, (2013) 084202
 G. Ghosh, M. Orlowski, IEEE Trans. Elect. Dev. 62(9) (2015) 2850-56
5:00 PM - EP01.03.22
Highly Uniform and Wafer-Scale Integrated MoS2 Transistors
Yonghun Kim1,Eun-Joo Seo1,Dong-Ho Kim1,Jongjoo Rha1,Byungjin Cho2
Korea Institute of Materials Science1,Chungbuk National University2Show Abstract
Molybdenum disulfide (MoS2) with atomic-scale flatness has potential candidate in the applications of high speed and low-power logic devices due to its scalability and intrinsic high-mobility. However, to realize 2D materials as to be viable technology, large-area growth with high quality and uniformity must be pre-requisite. Here, we present the simple and highly uniform growth of four layered molybdenum disulphide (MoS2) on 2 inch wafer scale substrate via the combination strategy of sputtered molybdenum trioxide (MoO3) and post sulfurization of chemical vapour deposition (CVD). The spatial spectroscopic analysis of Raman and PL mapping shows that as-synthesized MoS2 thin film exhibit extremely high uniformity on 2-inch sapphire substrate. With this approach, we assembled almost 1200 MoS2 transistors integrated on Si wafer that yield high density and extremely uniformity (device yield of ~95%, average mobility of ~0.8 cm2V-1s-1, and log on-off ratio of ~4.3). And, the quantitative analysis using pulsed I-V measurement with millisecond time scale could achieve more intrinsic device parameters suppressing the charge trapping of 2D materials-based device.
5:00 PM - EP01.03.23
An Analysis of Static and Dynamic Characteristics of 12KV 4H-SiC n-IGBT using HfO2-SiO2 Dielectric Stack at High Temperatures
Siva Prasad Kotamraju1,Pavan Kumar Vudumula1
Indian Institute of Information Technology Sricity1Show Abstract
Silicon Carbide (SiC) based insulated gate bipolar transistor is a promising candidate for use in high voltage power devices, due to faster switching and high voltage blocking capabilities. The type of dielectric layer used in SiC power devices plays an important role in how the device performs. While SiC based transistors are commercialized, the combination of Silicon dioxide (SiO2) and SiC interface had compatibility concerns, and cannot sustain higher electric fields. An alternative is to replace the conventionally used SiO2 with high-K dielectrics that can sustain high electric fields. This approach has been attempted earlier with Hafnium dioxide (HfO2) as the main gate dielectric and sandwiching SiO2 between of HfO2 and SiC. Earlier research work has shown initial reduction and then increase in forward voltage drop (Vf)/ON state resistance (RON) with respect to temperature. However, there is no complete analysis of the static characteristics using HfO2-SiO2 as dielectric stack at higher temperatures. The purpose of this work is to understand the influence of HfO2 on the capacitance and switching characteristics at higher temperatures. This work highlights the changes in electrical characteristics by varying lattice temperature from 300 K to 700 K. The structure of the device is modeled by using Sentaurus TCAD. Apart from usual drift-diffusion and recombination models, lombardi model has been used to take mobility degradation at the interface into consideration. Uniform trap distribution up to the conduction band and the exponential distribution closer to the conduction band edge is defined within the band gap of SiC in the dielectric interface. Breakdown voltage (BV), switching characteristics using a clamped inductive load and variation of miller capacitance with respect to temperature is analyzed along with static characteristics. The doping of p-well and thickness of dielectric has been designed to adjust threshold voltage(Vth) closer to 3.5 V. It is to be noted that Vth generally reduces with an increase in temperature. The Ic-Vg and Ic-Vccurves at different temperatures are simulated. As expected, the reduction in Vth and transconductance (gm) has been observed from the I-V curves with increase in temperature. It has been observed that the saturation of trapping occurs at a lower gate voltage with the increase in temperature. The carrier lifetime in the buffer region is calculated using doping and temperature dependent carrier lifetime model. The turn off characteristics and ON state energy (EON) / OFF state energy (EOFF) with respect to temperature are simulated. It has been observed that the temperature has more influence on EON compared to EOFF. The influence of external gate resistance (Rg) on the switching characteristics will be discussed in the full paper.
5:00 PM - EP01.03.24
Enhancing P-Type Doping of GaN for Power Electronics—A Combined Computational Experimental Approach
Timothy Johnson1,James Delaney1,Timothy Jen1,Jiaheng He1,R.S. Goldman1
University of Michigan1Show Abstract
Although silicon-based electronics are used to power light-emitting diodes and electric vehicles, their utility in high power applications is limited by a low breakdown voltage. Wide-bandgap semiconductors, such as gallium nitride and related alloys have been proposed as alternatives, but the effective p-type doping at high concentrations remains elusive. For example, Mg dopant activation following ion implantation, selective diffusion, and metal-organic vapor deposition requires high temperature annealing which may disrupt active device structure. In the case of molecular-beam epitaxy, surfactants and co-dopants such as O and Si have been explored, but the concentration of substitutional Mg is often limited, leading to limited p-type doping efficiency. Here, we are developing a novel approach to enhance the p-type doping of GaN and related allows. We describe a combined computational-experimental approach consisting of focused ion-beam (FIB) nano-implantation of Mg in GaN during molecular-beam epitaxy (MBE), followed by computational and experimental ion channeling studies of the Mg incorporation mechanisms. This approach is likely to result in p-type doping at ultra-high concentrations, without the need for subsequent high temperature annealing. We will discuss the development of a modified Mg-Ga alloy source for nano-implantation and our progress towards its implementation in a modular MBE-FIB system. We also present our Monte Carlo-Molecular dynamics simulations of ion channeling in wurtzite GaN crystals, and discuss our progress towards quantifying the influence of growth and annealing sequences on Ga and/or N vacancy formation and the result substitutional vs interstitial incorporation of Mg in GaN. We have examined the influence of Mg defect type in GaN on the , [10-10], and [11-20] channeling yields.
5:00 PM - EP01.03.25
Tunable Thermal Conduction in Amorphous Niobium Oxide by Oxygen Vacancy Concentration
Zhe Cheng1,Alex Weidenbach1,Marshall Tellekamp1,Brian Foley1,William Doolittle1,Samuel Graham1
Georgia Institute of Technology1Show Abstract
Niobium oxides have recently been demonstrated as excellent candidates to make memristors and memdiodes in neuristor circuits for application in neuromorphic computing. The Poole-Frenkel conduction in the niobium oxide layer is very sensitive to localized temperature and Joule heating. Additionally, thermal confinement and overheating in eventual microelectronics devices may result in significant degradation of performance and reliability. Therefore, it’s of great importance to understand and quantify thermal transport in these oxides. However, very few papers about thermal properties of niobium oxides have been published. Here, we report the first thermal conductivity (k) measurement of amorphous niobium oxide (a-Nb2O5-d) thin films by Time-domain Thermoreflectance (TDTR) method. We observe very low k of a-Nb2O5-d thin films (around 1 W/m-K) that are tunable (about 80% change) through varying oxygen vacancy concentrations (d). Additionally, the thickness dependence of k in a-Nb2O5-d films is studied to explore the influence of size effects in the context of locons, diffusons, and propagons. To complement this discussion, longitudinal wave velocities and vibrational energy spectra are measured by the picosecond acoustic method and Fourier-transform infrared (FTIR) spectroscopy, respectively.
5:00 PM - EP01.03.27
Dielectric and Ferroelectric Behaviors of PZT Thin Films Modified by Rare Earth Metals (La3+, Sc3+) for Ferroelectric Memory Applications
Mohan Bhattarai1,Karuna Mishra1,Alvaro Instan1,Sita Dugu1,Ram Katiyar1
University of Puerto Rico, Rio Piedras1Show Abstract
Highly oriented 0.90[PbZr0.53Ti0.47] 0.10[La0.2Scc0.8]O3-δ (PLZTS) thin films were deposited on La0.67Sr0.33MnO3 (LSMO) coated MgO (100) substrates utilizing the laser ablation process in oxygen atmosphere. The optimized PLZTS depositions were conducted at a substrate temperature of 700 °C in the experimental setup (KrF excimer laser λ = 248 nm, f = 5 Hz, energy/pulse 270 mJ) and subsequently annealed at the same temperature for 30 minutes in an ultrapure oxygen atmosphere. The (100) orientation of the PLZTS films was obtained from x-ray diffraction results. The nearly stochiometric of fabricated thin films were obtained from the high-resolution X-ray photoemission spectroscopic (XPS) data. Atomic force microscopic (AFM-Veeco) result in contact mode suggests a homogeneous distribution of grains with surface roughness ~ 3.5 nm, and the grains are interconnected with distinct grain and grain boundaries. Piezo force microscopy (PFM) measurements, operated in single frequency excitation, suggests the presence of ferroelectric domains. at ambient conditions. The temperature dependent dielectric measurements carried out on LSMO/PLZTS/Pt metal-ferroelectric-metal capacitors in 100-600 K and frequency (102-106 Hz) exhibits a broad dielectric maximum. At room temperature, we observed high dielectric constant ~ 650 at 102 Hz. Ferroelectricity of the thin films was ascertained from the observation of well-saturated hysteresis loops with Pr = 22.35 µc/cm2 and Ec =92.46kV/cm respectively at frequency 2kHz. The high dielectric constant, low losses and excellent ferroelectric PLZTS thin film capacitor insights into its potential application in electronic devices
5:00 PM - EP01.03.28
Thermal TCAD Simulations of Silicon Dioxide Conduction Blocking Layers in GaN Vertical High Electron Mobility Transistors
Izak Baranowski1,Houqiang Fu1,Hong Chen1,Xuanqi Huang1,Jossue Montes1,Tsung-Han Yang1,Yuji Zhao1
Arizona State University1Show Abstract
Due to the increasing power demands, there is a need for more efficient, high power switching devices. GaN sees a lot of promise as a mean to meet this demand due to good on-resistance vs. breakdown voltage relationship. As a result, GaN-based electronic devices have seen a great deal of success in high power applications. The development of first generation GaN power devices has focused on lateral architectures, such as high-electron mobility transistors (HEMTs), fabricated in thin GaN layers grown on foreign substrates (e.g., sapphire, SiC, and Si). HEMTs achieve their high electron mobility with a lateral heterostructure
Despite the successful demonstration of GaN HEMTs in various power applications, these lateral devices have several drawbacks which significantly limit their performance especially for high power and high voltage applications (e.g., > 1,200V). These lateral devices suffer from several major degradation mechanisms including current-collapse, dynamic on-resistance, and an inability to support avalanche breakdown performance. Furthermore, at higher operation powers, lateral HEMTs become less attractive, since the blocking voltage is held laterally, the device length must increase in order to increase the breakdown voltage.
Recently, bulk GaN substrates have become widely available, thus enabling a new generation of GaN power devices based on vertical architectures. These vertical GaN power transistors hold the blocking voltage vertically, which allows the devices to achieve very high breakdown voltages without increasing device area. As in a lateral device, a heterostructure is used to create 2DEG. However the electrons are drawn by the drain into the bulk. Because of this, current collapse is not as much a concern in these devices since most of the conduction path is not near the trap rich surface. Current blocking layers (CBLs) are employed to confine the current to an aperture directly beneath the gate. Typically, p-GaN is used for the CBL, however, growing the p-GaN layer via metal organic chemical vapor deposition (MOCVD) results in the Mg being passivated by H, and therefore the hypothetical >3eV blocking layer is not achieved.
Therefore, there is impetus to explore other materials for CBL applications, such as SiO2, however, previous work on SiO2 CBL’s neglected thermal considerations. This work simulated using Silvaco TCAD two GaN Vertical HEMT devices, one with a conventional p-GaN CBL and one with a SiO2 CBL under both isothermal and non-isothermal conditions. At VD = 20 V and VG = 0 V, the SiO2 devices saw more heating, possessing a hotspot of 396 K, compared to the 379 K hotspot of the p-GaN device. In spite of the increased heating, the on-resistance was still lower for the SiO2 CBL device (0.266 mΩ cm2) than that of the conventional p-GaN CBL device (0.331 mΩ cm2).
5:00 PM - EP01.03.29
Effect of Carbon Nanotube Surface Treatment on Morphology and Electrical Properties of Cu-CNT Electrospun Nano Fibers
Farhad Daneshvar1,Tan Zhang1,Hung-Jue Sue1,Atif Aziz2,Mark Welland2
Polymer Technology Center, Texas A&M University1,Nanoscience Center, University of Cambridge2Show Abstract
Copper is the dominant material used in electrical conductors due to its availability and excellent electrical conductivity. However as the electronic devices are getting smaller concerns regarding the ampacity of copper conductors have arisen. Moreover poor mechanical properties and relatively high weight resistivity of copper wires and cables have motivated researchers to develop new materials and systems for power transmission. Carbon nanotubes (CNTs) offer high electrical and thermal conductivity, excellent mechanical properties and ampacity 1000 times higher than copper. Although these outstanding properties make CNTs a very promising candidate, complex and costly processing impedes their application as a sole conductor. On the other hand previous research has shown that utilizing CNTs as a filler in a metallic matrix can simplify the processing and results in remarkable properties. In this case interfacial interactions between the two phases significantly influence the morphology and properties of the composite.
In this report electrospinning was utilized to produce Cu-CNT nano-fibers. The effect of CNT surface treatment and electrospinning parameters on the morphology and electrical conductivity of copper-CNT electrospun fibers were studied. For this purpose four different types of CNTs (pristine, oxidized, exfoliated and thiol activated) in different concentrations were used. Also two types of polymeric carriers were studied. Results showed that generally CNT introduction will decrease the uniformity and smoothness of the Cu-CNT fibers. Above a certain critical concentration, fibers cannot be produced. Pristine CNTs have the lowest and exfoliated CNTs have the highest critical concentration. Exfoliated CNTs with concentration as high as 5 wt% yields very smooth fibers with high uniformity which can improve the electrical conductivity. Also, it was shown that although PVP application as the carrier polymer makes the electrospinning process easier, PVA produces fibers with higher smoothness and uniformity. It should be noted that that in nano-scale surface smoothness has a significant effect in the conductivity of fibers.
5:00 PM - EP01.03.30
The Effect of Leveler on the Via Filling Performance in Copper Electroplating—A Case Study of Functional Groups
SangHoon Jin1,Sung-Min Kim1,Yugeun Jo1,Woon Young Lee1,Min Hyung Lee1
Korea Institute of Industrial Technology1Show Abstract
The through silicon via (TSV) is one of 3D integration methods to achieve high density interconnects with a good electrical performance and a small form factor on wafer level. In this work, we investigated the TSV filling performance dependent on the functional groups of levelers such as amines, imines, pyridines and pyrrolidones. To elucidate the behavior of functional groups in TSV filling, the mass adsorption rate was measured using quartz crystal microbalance (QCM) and electrochemical QCM (EQCM). It was found that the amines only exhibited the void-free filling in TSV, whereas other functional groups showed the void in TSV. This could be inferred that the amine favored the local adsorption on the top edge of via during electroplating, as evidenced by low mass adsorption rate of QCM and the large difference of mass adsorption rate between QCM and EQCM.
5:00 PM - EP01.03.31
The Study on Thickness Uniformity of Copper Electrodeposits Controlled by the Degree of Quaternization of Imine Functional Group
Yugeun Jo1,Sung-Min Kim1,SangHoon Jin1,Woon Young Lee1,Min Hyung Lee1
Korea Institute of Industrial Technology1Show Abstract
In the panel level packaging, it is necessary to control the thickness uniformity of electroplated Cu redistribution layer because non-uniform thickness of Cu electrodeposits is resulted in severe electrical resistance fluctuation. In this work, we studied the thickness uniformity of Cu electrodeposits in the presence of organic additive containing imine functional group modified with different degrees of quaternization. The degree of quaternization of imine functional group was controlled to be in the range of 0 to 100 % using the dimethyl sulfate solvent. The surface morphology and thickness uniformity of Cu electrodeposits were characterized by optical microscopy and confocal laser microscopy. In the case of adding the organic additive containing the imine functional group modified without quaternization into Cu electroplating solution, the shape of Cu electrodeposit represented dome shape with poor uniformity. Additionally, excessive dish-shaped surface was formed with the degree of quaternization of 100 %. However, with the degree quaternization of 50 %, the flat shape of Cu electrodeposits with high uniform thickness was obtained.