Chairs
Gailon Brehm, Texas Instruments Inc
Jim Mikkelson, Vitesse Semiconductor
Hidetoshi Nishi, Fujitsu Laboratories Ltd
John Parsey, Motorola Inc
In the sessions below, "*" indicates an invited paper.
SESSION C1: MATERIALS AND CHARACTERIZATION
Chairs: John M. Parsey and Gailon Brehm
Monday Morning, March 31, 1997
Salon 13
8:30 AM *C1.1
pHEMT AND HBT PROCESSING IN THE 90's, Paul Saunier, Darrell Hill, Texas Instruments Inc, Dallas, TX.
Both pHEMT and HBT have been demonstrating microwave (and millimeter wave) state-of-the-art performances in the past decade. As GaAs enters the commercial world, low-cost and reproducibility while maintaining reliability are becoming priorities to ensure success.
For the pHEMT, fabrication of the material is of course critical. The tendency is to rely on the (MBE) ''vendor'' (in house or external) for quality control and to grow only very limited number of structures (one is best!). One of the critical steps for pHEMT is, of course, the gate recess. We are in the process of implementing a selective gate recess with an etch stop layer. This emphasizes again the need to work with material suppliers as the threshold voltage is determined by the growth. For the HBT, reliability is critical and we have shown that starting with low dislocation density substrate is necessary as well as growing the epitaxial layers with low defect density and low hydrogen incorporation. InGaAs is used for low emitter resistance. GaInP emitter offers the crucial advantage of selective etching for improved manufacturing. Base layer uses carbon and indium doping for reliable high doping levels. In HBT processing, the emitter contact is refractory to provide a reliable, low resistance contact. The base layer surface is ledge passivated for reliability. The emitter airbridges provide reduced thermal resistance. Finally, base ballasting is used to achieve thermal stability without sacrificing efficiency.
For both pHEMT and HBT, Statistical Process Control is necessary and will be discussed.
9:15 AM *C1.2
DEVELOPMENT AND CURRENT STATUS OF 150MM GaAs SUBSTRATES, David C. Miller, Thomas Anderson, Johnathan B. Whitlock, Andy Souzis, Lawrence Unick, Litton Systems Inc, Airtron Div, Morris Plains, NJ.
There appears to be no technical impediment to producing large GaAs substrates. Single crystals over 10 inches in diameter and weighing 25 kg have been grown with high yields. Airtron has manufactured over 3,000 150 mm GaAs substrates, many with properties that approach those of current 100 mm wafers. All major substrate manufacturers have demonstrated 6 capability.
The motivation to utilize larger diameter substrates for device production is based on the requirement to reduce costs and make money at ever lower device selling prices. This process has been relentless in the silicon industry since the very beginning and the same factors such as the die size of the devices being manufactured, run rate of the part and availability of capital can be expected to apply to III-V compound substrates and devices. Beyond strictly financial issues, GaAs producers trying to achieve lower line widths and increased automation may not find equipment with the required performance capable of handling less than 150 mm wafers. There are also several issues unique to GaAs which will further impact the economics of converting to 150 mm, the most obvious being their much higher up front cost. Others include their weight, fragility and the high value of gallium. Fortunately, breakage rates observed so far in manufacturing 150 mm substrates are the same as for 100 mm. Obtaining low particulate, damage-free and ion-free surfaces is more difficult with GaAs than with silicon and has proven to be even more difficult at 150 mm. Hence, it will be very important to establish which substrate parameters truly impact device yields and determine specifications to optimize cost and performance accordingly. 150 mm wafers must also perform in both ion implantation and epitaxial processes. Preliminary results will be presented indicating that good uniform epi can be grown by MOCVD and MBE. Results of implantation uniformity to be reported are based upon 4wafers, cut off center from 150 mm ingots.
10:15 AM C1.3
CHARACTERIZATION OF DEEP CENTERS IN UNDOPED SEMI-INSULATING GaAs SUBSTRATE BY NORMALIZED THERMALLY STIMULATED CURRENT SPECTROSCOPY: COMPARISON OF 100-mm AND 150-mm WAFERS, Zhaoqiang Fang, David C. Look, Wright State Univ, Dept of Physics, Dayton, OH.
A well established characterization method for investigating deep traps in semi-insulating (SI) GaAs is thermally stimulated current (TSC) spectroscopy; however, TSC is not considered to be a quantitative technique because it involves carrier mobility, lifetime, and geometric factors, which are either unknown or poorly known. In this paper we first show how to quantify a TSC spectrum, by normalizing with infrared (hv = 1.13 eV) photocurrent, and then apply this quantitative method (called NTSC) to study the macroscopic distribution of deep centers across the diameters of undoped SI GaAs wafers. Also, we study the effects of various boule and wafer annealing recipes on the NTSC spectrum.
In the past decade GaAs substrate diameters have moved from 50 mm to 75 mm to 100 mm, and now 150-mm wafers are available from several manufacturers. In this work, 100-mm and 150-mm wafers, grown by both low-pressure (LP) and high-pressure (HP) liquid-encapsulated Czochralski (LEC) techniques, are characterized by the NTSC method. In comparison with 100-mm wafers, 150-mm wafers grown by both LP- and HP-LEC techniques show: 1) a decrease of dark current (DC) and photocurrent (PC) at T > 200 K due to an increase of compensating acceptors; and 2) a decrease of NTSC traps, T(0.63 eV) at 220 K and T (0.31 eV) at 140 K, and an increase of T (0.50 eV) at 200 K. In the 150-mm LP-LEC wafer, we also find: 1) a new trap T at 240 K, which is also observed in SI GaAs irradiated with 1-MeV electrons; and 2) good uniformity in the DC at 220 K
10:30 AM C1.4
FLEXIBLE PRODUCTION OF III-V DEVICE TYPES WITH ANALYSES OF MULTIVARIATE ARRAY PADS (MAPs), Jon W. Erickson, Salman Mitha, Charles Evans & Associates, Redwood City, CA.
Practical III-V production lines are optimized for a given device type, but in principle can produce many other devices, too. Numerous practical barriers must be overcome to create a compound semiconductor foundry analogous to that for Si. We describe a general minimax approach to chart the local parameter space toward the design target of a new device type. We use the concept of multivariate array pads (MAPs) to generalize traditional idea of ''lot splits'' in which the parameters of a single lot, device array, or production run are or spread across the parameter space of interest. Such MAPs can be created in the wafer mask process within scribe lines to minimize costs, and of suitable dimensions (at least 100 x 100 m) for subsequent analysis by secondary mass spectrometry (SIMS). For example, the concentration of C, Mg, or Si in a p-n junction may be varied continuously across a wafer, or stepwise in descrete devices. A set of arrays may be used to study effects of further processing (e.g., different annealing conditions), while electrical and optical characterization provide inexpensive qualitative inputs for sophisticated device modeling software, to yield powerful insights into device parameters. More expensive SIMS characterization (of dopant levels and stoichiometry) can be limited to a few representative pads, providing quantitative calibration of the electrical and optical results so as to reduce the overall costs. New products crated by device performance that has already been optimized (e.g., the bandgap of a highly efficient LED) may be the most profitable.
10:45 AM *C1.5
MULTI-WAFER MOLECULAR BEAM EPITAXY FOR PSEUDOMORPHIC HEMT STRUCTURES, William E. Quinn, Christopher J. Santana, Raytheon Co, Advanced Device Center, Andover, MA.
The rapidly expanding market for wireless communications equipment has increased the demand for GaAs based microwave devices.. At Raytheon's Advanced Device Center, two Riber multiwafer MBE systems are used to grow pseudomorphic HEMT (P-HEMT) based devices which are inserted into a number of communications products. In the early 1990s, multiwafer molecular beam epitaxy (MBE) systems were a rarity. The demand for GaAs epitaxial structures was low, and single wafer MBE systems could easily meet a fab line's 3 inch wafer requirements. Today, multiwafer MBEs have become a necessity, as a number of manufacturers have switched to 4" wafers and fabrication line starts can be greater than 10,000 wafers per year. The degree of success one has in operating multiwafer MBE systems lies as much in the operatic procedures as in the manufacturer of the MBE equipment. Throughput and uptime must be maximized to reduce wafer costs. Particularly important for our multiwafer MBE systems is the source reload procedure. The large volumes and surface axes of the growth chambers mandate that contamination during source reload be minimized, and that removal of contamination during bakeout be facilitated by improving the pumping speed for contaminants. Calibration after bakeout consists of a number of specific structures grown to determine the quality of GaAs, AlGaAs and InGaAs layers of the P-HEMT. To monitor wafer to wafer consistency throughout the growth cycle, we use room temperature photoluminescence (PL), a nondestructive technique. The talk will discuss operational procedures used to achieve high throughput and equipment modifications made to increase uptime, and reduce source reload time.
11:15 AM *C1.6
METAL ORGANIC CHEMICAL VAPOR DEPOSITION OF III-V MATERIALS FOR MICROWAVE DEVICES: PAST, PRESENT AND FUTURE, Eric Armour, Doug Collins, C. Beckham, M. Pelczynski, Pete Zawadzki, Richard A. Stall, EMCORE Corp, Somerset, NJ.
Metal Organic Chemical Vapor Deposition (MOCVD) is emerging as a viable technology for commercial production of III-V based FET, HEMT, and HBT device structures. Present MOCVD reactors are capable of multiple 100 mm and 150 mm wafer growths. We will discuss the current capabilities of MOCVD in terms of thickness, compositional, and doping uniformities, and interface abruptness. Typical device structures discussed will include advanced FETs, HBTs, and pseudomorphic HEMTs. In order to achieve the required accuracy and reproducibility in a manufacturing setting, measurement and control of thickness and composition are desirable, and have recently become feasible. These tools enable MOCVD to compete with MBE for good control, while offering substantially lower production costs and higher throughputs. We will also examine the prospect for large diameter wafers and thin structures of cluster tool based, single wafer systems with cassette-to-cassette operation.
11:45 AM C1.7
DEPOSITION OF A GaS EPITAXIAL FILM ON GaAs USING A S-As EXCHANGE REACTION, Qingsheng Xin, Xiaoyang Zhu, Southern Illinois Univ, Dept of Chem & Biochem, Carbondale, IL.
Cubic phase GaS, a new wide bandgap semiconductor, has emerged as an ideal passivation/dielectric layer for GaAs devices, such as MISFET. We demonstrate the growth of a GaS epitaxial thin film on GaAs(100) using a simple photochemical treatment with HS. In the reaction, the growth of GaS is accomplished via the replacement of As in the GaAs lattice by the photochemically generated S atom, while As is etched from the substrate as arsenic sulfide. The surface of the resulting GaS thin film (20 - 50 ) is characterized by a sharp (2 x 1) low energy electron diffraction pattern, indicating excellent crystalline quality. In many ways, the method shown here is similar to UV oxidation in silicon technology and may be incorporated into various GaAs device technologies.
SESSION C2: MATERIALS AND PROCESSING
Chairs: Jim Mikkelson and Hidetoshi Nishi
Monday Afternoon, March 31, 1997
Salon 13
1:30 PM *C2.1
MBE-BASED HBT PRODUCTION FOR HIGH-VOLUME COMMERCIAL APPLICATIONS, Dwight C. Streit, A. K. Oki, M. D. Lammert, T. R. Block, M. M. Hoppe, TRW, Inc., Redondo Beach, CA.
We report the high-volume production of heterojunction bipolar transistors using an MBE-based HBT process that has resulted in Fe world wide insertion of GaAs-based HBTs into commercial products. HBT monolithic microwave integrated circuits have specific yield, performance, and cost benefits for wireless applications compared to HEMT or MESFET-based circuits. These benefits result in high-yield MMICs with small die sizes that require only standard optical processing, and achieve efficient high-linearity performance with amplitude and phase control that is ideal for both analog and digital communication systems. Although the advantages of HBTs are well known, only recently have they become widely available in commercial products such as cellular phones and wireless networks, as we now ship over 3,000,000 HBT integrated circuits per month to commercial users. We present here the MBE growth. material characterization, device processing, reliability, and commercial applications of these HBT products.
The trade-off between performance, processing complexity, reliability, and yield demands that the HBT device profile and processing techniques be carefully optimized. We use an HBT profile that achieves breakdown voltage BVceo = 12 V with a 700 nm collector, fT = 42 GHz and fmax = 73 GHz at Ic = 40 kA/cm with an 80 nm base Be-doped to 1x10 cm, and low emitter resistance with TiPtAu refractory metal contacting an InGaAs emitter layer. In order to minimize field returns and associated costs, commercial applications actually demand that products be nearly as robust as required for high-reliability flight applications. We have performed over 10 device hours of reliability testing over the past 5 years, and have consistently achieved device and circuit lifetimes exceeding 10 h at 125C. No other growth or doping technique has achieved these levels of reliability. As a result, TRW HBT MMICs have found broad acceptance in commercial products both for their performance and for their reliability benefits.
2:15 PM C2.3
FABRICATION AND CHARACTERIZATION OF ASYMMETRIC TRIPLE-BARRIER TUNNELING STRUCTURE GROWN BY MOLECULAR BEAM EPITAXY, Dong-Wan Roh, Gyungock Kim, Seung-Won Paek, ETRI, Dept of Research, Taejon, SOUTH KOREA.
We report fabrication and characterization of asymmetric AlAs/GaAs (001) triple-barrier structures (TBS), grown by molecular beam epitaxy, for the probe of the enhanced electron tunneling and -X electron transfer. The epilayer was confirmed using the various analysis techniques: cross sectional transmission electron microscopy (XTEM), double-crystal x-ray diffraction (DXRD), etc. The various size mesas ranging from 0.7 x 2 to 30 x 30 , were fabricated using the photolithography techniques with lift-off process. The dry etching method was adopted for the submicron size mesas in avoid the shortcomings of the wet etching, such as undercutting, isotropic etching at edges. The various dry etching techniques-magnetically enhanced reactive ion etching (MERIE), reactive ion beam etching (RIBE), chemically assisted ion beam etching (CAIBE)- were used to isolate the GaAs emitter mesa. The surface morphology after etching and etched cross-section was observed to compare each dry etching method using scanning electron microscopy (SEM). The I-V measurement at room temperature shows large enhancement of the resonant tunneling peak current through the ground quantum well states. The -X electron interlayer intervalley transfers through the lower X valley confined states of the AlAs barrier were also identified. Dependence of the device characteristics on mesa size and magnetic field will be presented.
2:45 PM *C2.4
CURRENT STATUS OF UNDERSTANDING AND CONTROL OF COMPOUND SEMICONDUCTOR SURFACES AND INTERFACES FOR HIGH-SPEED DEVICES, Hideki Hasegawa, Hokkaido Univ, Res Ctr for Interface Quantum Electronics, Sapporo, JAPAN.
As compared with silicon, surfaces and interfaces of compound semiconductors are known to be difficult to control, resulting in difficulty in surface passivation of devices as well as in absence of insulated gate devices. Use of Schottky gate structures is a currently accepted remedy for the latter. However, Schottky barrier heights (SBH) on some materials such as InP, InGaAs and InAlAs are low, and cause severe gate leakage problems on InP-based FET devices. As the devices feature sizes are further scaled down, such surface and interface related issues are expected to become even more important due to increased surface to volume ratio. The purpose of this paper is to present and discuss the present status of understanding and control of compound semiconductor surfaces, insulator semiconductor (I-S) interfaces and metal-semiconductor (M-S) interfaces with a particular emphasis on the key processing issues related to performance and reliability of high speed devices. First, various properties of surface and interface states as related to the performance and reliability of high speed devices are presented together with the dynamic behavior of the states up to microwave frequencies. Then, the origin of surface and interface states at I-S and M-S interfaces and the mechanism of Fermi level pinning are discussed, followed by a review of various recent attempts to control I-S and M-S interfaces by improved processing technologies. Finally, recent approaches and results obtained by the author's group to control the I-S interface by a silicon interface control layer (Si ICL) technique and to control the M-S interface by in-situ electrochemical process are presented and discussed.
3:15 PM C2.5
DAMAGE-FREE, PHOTON-ASSISTED CRYOETCHING OF GaAs, Jyh-Tsung Hsieh, National Tsing Hua Univ, Dept of Electrical Engr, Hsinchu, TAIWAN; Huey-Liang Hwang, National Tsing Hua Univ, Dept of Electrical Engr, Hsinchu, TAIWAN; S. Horng, Syncrotron Radiation Research Ctr, Hsinchu, TAIWAN.
High-resolution, damage-free etching of GaAs and related compound semiconductor materials is an increasingly important requirement in the fabrication of advanced photonic and electronic device structures, especially for the etching of one-dimensional (' 'wires'') and zero dimensional (''dots'') quantum-confined structures. In the case of etch defined quantum-confined structures, damage may actually render the devices inoperable for feature sizes less than 100 nm. In this study, we present a high-resolution, damage-free etching technique for GaAs which utilizes excimer laser (193 nm) and syncrotron radiation light source (adjustable in wavelength) to excite a physisorbed layer of Cl on a cryogenically cooled sample. The etch rate has been characterized as a function of several parameters including Cl partial pressure, substrate temperature, laser fluence, and light wavelength. Surface reaction mechanism will be discussed in details. The surface damage and contamination have been studied with Auger electron spectroscopy, photoluminescence, Raman spectroscopy, and Schottky-barrier measurements. On the other hand, sidewall damage measurement was carried out by fabricating wires with different widths and etching them for different conditions and then measuring the conductance. We derived a satisfactory result in structure contour and quantitative damage analysis and thus prove the photon-assisted photocryoetching is a damage-free technique for dry etching.
3:30 PM C2.6
COMPARISON OF DRY ETCH DAMAGE IN GaAs/AlGaAs HETEROJUNCTION BIPOLAR TRANSISTORS EXPOSED TO ECR AND ICP Ar PLASMAS, Jewon Lee, Cammy R. Abernathy, Stephen J. Pearton, Univ of Florida, Dept of MS&E, Gainesville, FL; Fan Ren, Bell Labs, Lucent Technologies, Murray Hill, NJ; C. Constantine, C. Barratt, Plasma Therm IP, St Petersburg, FL; Randy J. Shul, Sandia National Laboratories, Albuquerque, NM.
A detailed study has been performed of the damage introduced into GaAs/AlGaAs heterojunction bipolar transistors during exposure to two different types of high ion density plasma used for mesa formation during device fabrication, namely Electron Cyclotron Resonance (ECR) and Inductively Coupled Plasma (ICP). Base and emitter sheet resistance increase with plasma source power in both systems until well-defined values where ion energy falls below threshold values for defect creation. Under these conditions there is no measurable effect on device layer sheet resistance, dc current gain or base-collector reverse breakdown voltage. The basic reason for this window of damage-free processing conditions is identified as the suppression of cathode self-bias as the high density plasma source power is increased. Ion energy, ion flux and plasma exposure time may all have an effect on HBT device parameters.
3:45 PM C2.7
SELECTIVE LATERAL ETCHING METHOD FOR AlGaAs/GaAs HETEROJUNCTION BIPOLAR TRANSISTOR, Dong Hyun Kim, KAIST, Dept of Electrical Eng, Kusong-dong, SOUTH KOREA; Hee Chul Lee, KAIST, Dept of Electrical Engr, Taejon, SOUTH KOREA.
Selective etching process is an important step in fabrication of semiconductor devices having heterojunctions. Many solutions for selective etching have been studied at AlAs/GaAs and other III-IV systems. Selective etching have mainly been used to control precisely etching process with multilayer structure including stopping layer. In the case of AlGaAs/GaAs system, most of the reports were confined to AlAs/GaAs system with x 0.4 which has relatively many DX centers and low carrier mobility in the device and degrades the device performance. In this presentation, selective lateral etching is performed for AlAs/GaAs system with AlAs composition of 0.3 along the direction perpendicular to sidewall of mesa structure. This lateral etching process can be applied to reduce extrinsic base-collector capacitance of AlAs/GaAs heterojunction bipolar transistor, which results in high speed performance of the HBT devices. For AlAs/GaAs system, selective lateral etching was studied with redox solution (I/KI). The test epistructure have one heterojunction composed of GaAs and AlAs layers and was grown by means of molecular beam epitaxy. As a function of concentration ratio of I/KI, strip direction, pH and stirring speed, etching selectivity between GaAs and AlAs was measured and observed with scanning electron microscopy. The etching was carried out with stirring solution at room temperature. The stripes have the different directions with tilted angles from the [110] direction. To increase the undercutting of AlAs with respect to GaAs, the sidewalls of SiN were used. As a result of C-V measurements performed for conventional and lateral etched HBTs of 3 m x 20 m emitter size of 12 emitter fingers, the capacitance of lateral-etched device was reduced to about 50 of conventional value. This process can be also applied to optical waveguide and variable area diode.
4:00 PM C2.8
COMPARISON OF HIGH DENSITY PLASMAS FOR THE ETCHING OF InGaAlP ALLOYS, Jin Hong, Jewon Lee, E. S. Lambers, Cammy R. Abernathy, Stephen J. Pearton, Univ of Florida, Dept of MS&E, Gainesville, FL; W. S. Hobson, Bell Labs, Lucent Technologies, Murray Hill, NJ.
Electron Cyclotron Resonance (ECR) and Inductively Coupled Plasma (ICP) were compared for patterning of InGaAlP alloys in CH-based plasma chemistry. High microwave power (1000 W) ECR CH/H/Ar discharge produce etch rates for InGaP, AlInP and AlGaP of 2,000 min at moderate rf power levels (150 W) and low pressure (1.5 mTorr). While lower etch rates for the alloys were obtained under ICP CH/H/Ar conditions, which might be due to the lower dc bias, we achieved selectivities of 3 10 for InGaP over AlInP and AlGaP. Low dc bias is expected to induce less ion damage in real device structure. Furthermore, ICP etching provided smoother surface morphology. The RMS surface roughness for InGaP at moderate source power and high rf power (35050 W) under ICP conditions is 4.0 nm, in contrast to 20 nm under ECR conditions. As a whole, high density Inductively Coupled Plasmas appear to be promising candidates for the etching of InGaAlP alloys.
4:15 PM C2.9
INDUCTIVELY COUPLED PLASMA ETCH DAMAGE IN GaAs AND InP SCHOTTKY DIODES, Jewon Lee, Cammy R. Abernathy, Stephen J. Pearton, Univ of Florida, Dept of MS&E, Gainesville, FL; Fan Ren, W. S. Hobson, Bell Labs, Lucent Technologies, Murray Hill, NJ; Randy J. Shul, Sandia National Laboratories, Albuquerque, NM; C. Constantine, C. Barratt, Plasma Therm IP, St Petersburg, FL.
The effects of ion-induced damage in n- and p-type GaAs and p-type InP exposed to Inductively Coupled Plasma (ICP) Ar discharges were measured by diode ideality factor and barrier height measurements. At fixed rf chuck powers, the electrical characteristics of the diodes generally improve with increasing ICP source power because the incident ion energy is decreased. In the particular case of p-GaAs, the higher ion flux at high ICP source power leads to a degradation in barrier height. Exposure time and ion energy have a stronger influence than ion flux in all three materials. The results are compared to those obtained with Electron Cyclotron Resonance Ar plasmas and show the same basic trends. The clear result is that at moderate ICP source powers, the suppression of self-induced dc bias on the powered electrode leads to a lower amount of ion damage to the semiconductors than for conventional reactive ion etch discharges.
4:30 PM C2.10
STRUCTURAL AND ELECTRICAL CHARACTERIZATION OF THE GaAs/InP WAFER FUSED INTERFACE, K. Alexis Black, Univ of California-S Barbara, Dept of Materials, Santa Barbara, CA; Patrick Abraham, Yi-Jen Chiu, Univ of California-S Barbara, Dept of ECE, Santa Barbara, CA; John E. Bowers, Evelyn L. Hu, Univ of California-S Barbara, Dept of E&CE, Santa Barbara, CA; Ying-Lan Chang, Hewlett Packard Co, Palo Alto, CA; Dubravko Babic, Hewlett Packard Co, Communications & Optics Res, Palo Alto, CA.
Wafer fusing technology has been used for vertical-cavity surface emitting lasers (VCSEL), light emitting diodes, and a host of other applications, resulting in improved device performance. Despite its success, the mechanism of bonding and the extent of damage introduced at the interface during fusion are not well understood. We have used a combination of high resolution microscopy and multiple quantum well photoluminescence studies to assess these parameters critical to ultimate device performance and yield. Structural and electrical characterization of the GaAs/InP heterojunction will be presented. SIMS measurements of oxygen and carbon impurities at the interface are correlated with IV characteristics of p/p, p/n, and n/n GaAs/InP junctions. Photoluminescence results indicate unrecoverable damage in the form of misfit dislocations and residual strain as far away as 2000 from the interface. Some fusing conditions result in the presence of microvoids on the order of 10-90 nm. Optimal processing parameters for the minimization of such damage will be discussed.
4:45 PM C2.11
INTRINSIC CoGe/GaAs(100) OHMIC CONTACT WITHOUT ALLOYING, M. Mello, Rensselaer Polytechnic Inst, Dept of Physics, Troy, NY; Shyam P. Murarka, Rensselaer Polytechnic Inst, Dept of MS&E, Troy, NY; Toh-Ming Lu, Rensselaer Polytechnic Inst, Dept of Physics, Troy, NY; S. Lee, US Army Research Div, Dept of Armament Research, Dev & Engr, Watervliet, NY.
It is found that CoGe can be grown epitaxially on n-type GaAs(100) surface at a temperature as low as 200C under a conventional vacuum condition (10 Torr) using the partially ionized beam deposition technique developed in our lab. By varying the substrate temperature and the ion energy in the partially ionized beam deposition, one can form two typos of epitaxial orientations, namely CoGe(001)/GaAs(100) or CoGe(100)/GaAs(100). CoGe(001)/GaAs(100) has a 0.20 lattice mismatch and CoGe(100)/GaAs(100) has a 91.50 lattice mismatch. It is shown that the former forms an Ohmic contact and the latter gives a Schottky contact. These CoGe films are themselves alloy, but they do not react further with the substrate to form any new alloy. These metal contacts are therefore ''nonalloy'' contacts to the GaAs substrate. Possible mechanisms for the observed phenomena will be discussed. This particular strategy for Ohmic and Schottky contacts has potential applications in compound semiconductor devices.
SESSION C3: PROCESSING AND DEVICES
Chairs: Gailon Brehm and John M. Parsey
Tuesday Morning, April 1, 1997
Salon 13
8:30 AM *C3.1
MULTILEVEL INTERCONNECT PROCESS FOR GaAs VLSI, Mark Schneider, Dave Johnson, Dave Forgerson, Vitesse Semiconductor, Camarillo, CA.
High speed, high density integrated circuits require complex multilevel metallization technologies to preserve the advantages of scaled high performance devices. The minimization of interconnection lengths and parasitic capacitances is especially important for GaAs digital VLSI circuits. We will describe a four layer metal interconnection process used for the manufacturing of GaAs circuits of up to 1,000,000 transistor complexity. The Vitesse HGaAs process is a refractory gate self-aligned E/D ion implanted MESFET process. In addition to local routing in the gate metal layer, four layers of aluminum metallization are provided. The metallization process Is based on traditional metallization processes used in the manufacture of silicon MOS integrated circuits. To reduce the parasitic capacitance of the interconnect lines, a polyimide interlayer dielectric process has been implemented. The replacement of SiO2 with polyimide led to a 7 to 10 speed improvement on typical gate array circuits. This process has been running in production for over three years. We will present the design rules and process steps for the interconnect process, as well as performance and reliability data for GaAs VLSI circuits.
9:00 AM *C3.2
RELIABILITY ISSUES IN GaAs-BASED HBTs, O. Ueda, A. Kawano, T. Takahashi, Y. Tomioka, T. Fujji, Hidetoshi Nishi, Fujitsu Laboratories Ltd, Atsugi, JAPAN.
In this paper, we review two major reliability issues in GaAs-based heterojunction bipolar transistors (HBTs), particularly InGaP/GaAs HBTs: degradation in current gain () and variation of turn-on voltage (V). In the case of AlGaAs/GaAs HBTs, the gradually decreased, then drastically degraded. After degradation, the device exhibits an increase in base current I, which has an ideality factor n2 in the Gummel plot. The activation energy E for the degradation was estimated to be 0.6 0.1 eV. On the other hand, in InGaP/GaAs HBTs, much higher reliability than in AlGaAs/GaAs HBTs was achieved although the degradation mode is similar. The estimated Ea and time to failure for InGaP/GaAs HBTs are 2.0 0.2 eV and 10 h at T = 200C, respectively, which are the highest values ever reported. We also review previously proposed degradation mechanisms for GaAs-based HBTs: hydrogen reactivation, microtwin-like defect formation, dark defect formation and carbon precipitation. In our case, two possible degradation mechanisms are derived from TEM analyses of degraded HBTs: formation of carbon precipitates in the base region and migration of metallic impurities from the base electrode to the base region. The second issue is associated with the exponential-like increase in V with operating time. The mechanism for the increase in V has been clarified based on reactivation of passivated carbon acceptors in the base region during operation. If the device suffers from H isolation, Vbe rapidly decreases at the initial stage, then exponentially increases. The first stage of V variation can be explained by the fact that a high density of hydrogen atoms migrating from the isolation region to the intrinsic base region, passivate the carbon atoms at the initial stage. From these results, one can expect that the use of He as an implant instead of H can solve this problem.
9:30 AM C3.3
INVESTIGATION OF FAILURE MECHANISMS OF PSEUDOMORPHIC HIGH ELECTRON MOBILITY TRANSISTORS BY HIGH RESOLUTION TRANSMISSION ELECTRON MICROSCOPY, Sean Hillyard, Chan-Shin Wu, Jay Malin, Clyde Fuller, Philip Basham, Ken Decker, Texas Instruments Inc, Dallas, TX.
Aluminum gallium arsenide/indium gallium arsenide pseudomorphic high electron mobility transistors (pHEMTs) life-tested under a variety of temperature and voltage conditions have been examined by high resolution transmission electron microscopy (TEM). Ambient temperature conditions ranged from room temperature to 207C (channel temperature approximately 257C) and bias conditions were varied over the operating range of the devices. Degradation at both the gate metal/semiconductor and passivation/semiconductor interfaces has been found and linked to electrical failure in the devices. Both TEM and electrical data for a variety of gate metals and life-testing conditions will be presented.
10:00 AM *C3.4
HIGH SPEED InP-BASED IC FABRICATION TECHNOLOGY FOR BOTH COMMERCIAL AND MILITARY SYSTEM INSERTION, Julia J. Brown, Adele E. Schmitz, Minh Le, Minh Hu, Hughes Research Laboratories, Malibu, CA.
InP-based electronic and optoelectronic device and circuit technology is maturing rapidly due to active world-wide research in a number of high speed applications[1]. The increasing demand for state-of-the-art millimeterwave technology in applications such as wireless local area networks (LANs) is one of the driving forces to produce such InP-based ICs for system insertion2-4. With this motivation, the research work at Hughes Research Laboratories in high speed InP-based ICs is focusing on advancing the fabrication technology for high yield and reproducibility without sacrificing the state-of-the-art performance. We will present studies of e-beam gate fabrication and gate recess processes. Here, we have utilized diagnostic tools such as focused ion beam milling and atomic force microscopy to optimize both the gate and recess etch profiles. In addition, we have performed an in-depth design of experiment to study the effects of the silicon nitride passivation technique on the performance of both InP and GaAs-based high speed devices. Finally, we have developed dry etch processes for both InP and GaAs backside via fabrication and addressed the via profile effect on eutectic die attach. This paper will report the recent progress in high speed InP-based ICs with particular emphasis on the fabrication technology development.
10:30 AM *C3.5
EPITAXY-ON-ELECTRONICS: MONOLITHIC INTEGRATION OF HETEROSTRUCTURE DEVICES ON COMMERCIALLY-PROCESSED GALLIUM ARSENIDE INTEGRATED CIRCUITS, Clifton G. Fonstad, MIT, Dept of Electrical Engr & Electronics, Cambridge, MA; J. F. Ahadian, S. G. Patterson, T. V. Praveen, Y. Royter, MIT, Cambridge, MA; Gale S. Petrich, Leslie A. Kolodziejski, MIT, Dept of Electrical Engr, Cambridge, MA; S. Prasad, MIT, Cambridge, MA.
Enhancing the functionality of conventional electronic circuits with optical and quantum-effect devices has long been recognized as a desirable, though challenging, goal. Hybriding, wafer-bonding, ad epitaxial lift-off have made progress addressing this need, but a monolithic integration technique is preferable. Monolithic integration on silicon VLSI has been hampered by the difficulty of III-V growth on Si, and on III-V substrates has been limited to small-scale integration when the electronic and optoelectronic technologies must both be developed. The success of commercial GaAs VLSI technology offers another solution. The Epitaxy-on-Electronics (EoE) process to be described uses a commercially processed GaAs IC as the starting point for the growth and fabrication of integrated heterostructure devices. In regions designated for these devices, the interconnect dielectric stack is etched to expose the underlying GaAs substrate. Conventional gas-source molecular beam epitaxy is used to grow the device heterostructure on the exposed substrate, and established procedures are used to fabricate the optoelectronic and/or quantum effect devices and interconnect them with the electronics. The GaAs IC process uses aluminum-based interconnects common in silicon technology. As such, the interconnects are degraded if exposed to excessive temperatures. This requires that the material growth cycle be carried out below 475C. The incompatibility of this growth temperature with traditional AlGaAs-based optoelectronics limited the performance of earlier EoE demonstrations. The use now of aluminum-free phosphide-based heterostructures, and further development of the key EoE process steps have resulted in a robust EoE technology. Examples of EoE O ICs incorporating LEDs, detectors, and MESFET electronics and an overview of the OPTOCHIP Project, a prototype EoE research foundry offered for the first time in 1996, will be presented to illustrate the capabilities and the state of the art of this technology. Recent work on the EoE integration of resonant tunneling diodes to form one-transistor cells for a GaAs static random access memory will also be described.
11:00 AM C3.6
PROCESSING OF HIGH-SPEED InGaAs DIODES, Seyed Ahmad Tabatabaei, G. A. Porkolab, S. Agarwala, S. A. Merritt, F. G. Johnson, O. King, M. Dagenais, Y. Chen, D. Stone, Univ of Maryland, Dept of Electrical Engr, College Park, MD.
This paper describes in detail the process flow for high-speed InGaAs diodes. It addresses the details of a low-damage etching process of InGaAs sidewalls, an improved surface preparation technique, polyimide passivation or pyrolytic-photoresist encapsulation, and flip chip die attach and mixed-signal packaging. The reliability and degradation mechanisms in fabricated diodes are studied as a function of varying process parameters. The improved device characteristics, and long-term stability are obtained by having a much less critical process to achieve optimum device performance.
11:15 AM C3.7
THERMAL STABILITY OF SULFUR-TREATED InAlAs DIODE, Masahiro Kobayashi, Jun Tanaka, Satoru Matsumoto, Hideki Hattori, Keio Univ, Dept of Electrical Engr, Yokohama, JAPAN.
It is known that sulfur treatment is available to InAlAs as well as GaAs. There is, however, few reports on the thermal stability of sulfur-treated (S-treated) InAlAs. The samples consisted of n-InP substrates followed by 50 nm n-InP buffer layer, 400 nm n-InAlAs donor layer, 250 nm undoped InAlAs Schottky layer and finally 50 nm undoped InGaAs. At first, backside ohmic contact was formed by evaporating AuGeNi followed by alloying at 350C for 900 sec in N. After removing InGaAs by citric acid, the sample was dipped into (NH solution at 50C for 1 min and immediately blown dry with N. Schottky contacts were formed by evaporating Au or Mo. After the annealing at 100500C for 10 min in N flow, current-voltage (I-V) measurement was performed. To study the characteristics of interface between metal and InAlAs, Auger Electron Microscopy (AES) and x-ray photoelectron spectroscopy (XPS) were also performed.
The n-factor of Au/untreated InAlAs diode after annealing at 300C was significantly degraded. After annealing at 350C, both of Au/untreated and S-treated InAlAs diode became ohmic. AES depth profiles indicated the outdiffusion of In to Au. From the results of XPS, it is appeared that Au sulfide was formed at the interface between Au and S-treated InAlAs. Mo/untreated InAlAs diode began to degrade at 400C, but Mo/S-treated InAlAs diode didn't reveal a significant degradation even at 500C. Although the outdiffusion of In to Mo was observed in AES depth profile of Mo/untreated InAlAs, such outdiffusion was not found in Mo/S-treated InAlAs. In addition, the results of XPS showed that stable Mo sulfide was formed at the interface between Mo and S-treated InAlAs. From these results, it is concluded that this Mo sulfide prevent the segregation of In. The combination of S treatment and Mo-based Schottky contact was expected to lead to InAlAs Schottky diode which has high thermal stability.
11:30 AM C3.8
C IMPLANTATION AND SURFACE DEGRADATION OF InGaP, Cathy B. Vartuli, Cammy R. Abernathy, Stephen J. Pearton, Univ of Florida, Dept of MS&E, Gainesville, FL; John C. Zolper, A. J. Howard, Sandia National Laboratories, Albuquerque, NM.
InGaP and related materials have attracted interest as a replacement for AlGaAs in heterojunction bipolar transistors and lasers. C ions were implanted alone, or with either N, Al, Ar or P co-implants, into InGaP at doses between 5 x 10 - 5 x 10 cm and the electrical activation was measured for annealing temperatures between 650 - 1000C. Capless proximity annealing preserves the surface to 900C, as measured by atomic force microscopy and scanning electron microscopy. The acceptor activation percentages are low ( 20) in all cases. This is consistent with a model in which C has a strong tendency for self compensation in InGaP.
11:45 AM C3.9
INTERMIXED QUANTUM WELL STRUCTURES AND THEIR ABSORPTION CHARACTERISTICS IN PASSIVE OPTICAL WAVEGUIDES, Chan Kam Tai, Chinese Univ of Hong Kong, Dept of Electron Engr, Hong Kong, HONG KONG; Han Dejun, Beijing Normal Univ, Inst of Low Energy Nuclear Physics, Beijing, CHINA; Zhuang Wanru, Chinese Academy of Sciences, Inst of Semiconductor, Beijing, CHINA; Wang Wenxun, Beijing Normal Univ, Inst of Low Energy Nuclear Physics, Beijing, CHINA.
We have shown that high energy ion implantation enhanced intermixing (HE-IIEI) technology for quantum well (QW) structures is a powerful technique which can be used to blue shift the bandgap energy of a QW structure and therefore decrease its bandgap absorption. Room temperature photoluminescence and guided-wave transmission measurements have been employed to investigate the amount of blue-shift of the bandgap energy of an intermixed QW structure and the reduction of bandgap absorption. Record large blue-shifts in photoluminescence peaks of 132 nm for a 4-QW InGaAs/InGaAsP/InP structure and 54 nm for a single QW InGaAs/GaAs structure have been demonstrated in the intermixed regions of the QW wafers, on whose non-intermixed regions, shifts as small as 5 nm and 1 nm, respectively, are observed. This feature makes this technology very attractive for selective intermixing in selected areas of a MQW structure. The dramatical reduction in band gap absorption for the InP based MQW structure has been investigated experimentally. It is found that the intensity attenuation is decreased from -364.8 dB/cm for the TE mode and -205 dB/cm for the TM mode in the non-intermixed control samples to -122 dB/cm for the TE mode and -86 dB/cm for the TM mode in the intermixed ones. Electro-absorption characteristics have also been clearly observed in the intermixed structure. Current-Voltage characteristics were employed to investigate the degradation of the p-n junction in the intermixed region.
Our results indicate that HE-IIEI is a very powerful technique to fabricate waveguides selectively on QW structures for various kinds of applications.