Jeffrey Gelpey, AST elektronik USA Inc
Terrence Riley, Advanced Micro Devices
Fred Roozeboom, Philips Research Laboratories
Shuichi Saito, NEC Corporation
- AG Associates
- Applied Materials, Inc.
- ASM America
- ASM Europe
- AST elektronik GmbH
- CGS Thermodynamics
- CVC Products, Inc.
- Eaton Thermal Processing Systems
- SensArray Corporation
- Vortek Industries, Ltd.
1997 Spring Exhibitor
Proceedings published as Volume 470
of the Materials Research Society
Symposium Proceedings Series.
In the sessions below "*" indicates an invited paper.
SESSION F1: MEASUREMENT
Chair: Jeffrey C Gelpey
Tuesday Afternoon, April 1, 1997
Nob Hill B
1:30 PM *F1.1
TEMPERATURE MEASUREMENT ISSUES IN RAPID-THERMAL PROCESSING, D. P. DeWitt, NIST, Gaithersburg, MD; F. Yates Sorrell, North Carolina State Univ, Dept of Mechanical & Aerospace Engr, Raleigh, NC; J. K. Elliott, Sensarray, Austin, TX.
Reliable radiometric temperature measurement has been a major challenge in making RTP more widely accepted. In order to meet roadmap requirements involving temperature uncertainty, uniformity and control, new techniques must be demonstrated and/or existing measurement methods must be substantially improved. Critical aspects of radiometric methods for temperature measurement are centered about three major issues: radiative and optical properties of the wafers, including layered systems; surface roughness effects; and reflected irradiation from lamp banks and chamber walls. A critical review of radiometric measurement methods is presented to assess the state of the art, to identity approaches and techniques of merit, and to develop insights on directions and ideas to explore. While several methods in current practice are successfully meeting current requirements, they have been developed primarily by experience and empiricism. These methods are chamber-specific solutions and, as such, transferring the techniques and experiences to other processing platforms will be challenging. Barriers to improved technology are identified which should be addressed in order to establish a more mature knowledge based upon measurement methods can be designed. Recent advances using thin-film optics have led to a improved understanding of the theory for predicting optical and radiative properties of silicon and layered systems. Measured radiative and optical properties, particularly at high temperatures and for rough surfaces, will be required to establish confidence in the properties knowledge base required for designing radiation thermometry methods. Considerations for improved radiometry to establish traceability and reliability of the temperature scale in the RTP environment involve choices of spectral bands (near-IR to mid-IR), radiometer types (fiber optic vs. imaging optics) and technique for inferring temperature from observed spectral radiances. In order to correct for, or minimize, lamp bank effects, it is necessary to understand the influence of chamber configuration on the irradiation distribution on the wafer viewing targets. Successful thermometry may require detailed radiation models. Further. chamber configurations with design features to control irradiation distributions and accommodate radiometer performances would be desirable.
2:00 PM F1.2
STUDY OF RELATIVE ACCURACY, REPEATABILITY AND LIFETIME OF THERMOCOUPLE INSTRUMENTED CALIBRATION WAFERS FOR RTP, Peter Vandenabeele, Wayne Renken, Sensarray, Mijlen, BELGIUM.
Thermocouple instrumented wafers have become the standard for calibration of temperature measurement in RTP. It is important to understand and quantify the temperature errors in using thermocouple wafers. A very stable RTP oven with lamp power control (C, 3 ) was used to study various temperature error effects of the thermocouple structures. A comparison was made between an older thermocouple structure and a new, optimized structure with the thermocouple deeper embedded in the wafer. The influence of using different thermocouple materials was studied.
The relative accuracy is defined as the error between thermocouples measuring the temperature on the same location in the oven. This accuracy is important for optimizing uniformity with multipoint thermocouple wafers. The offsets between different thermocouples are typically within 1C for the new structure. For the old structure, larger offsets are seen between different thermocouples (typically 5C). Extensive measurements on multiple thermocouples are recorded.
The repeatability is defined as the relative error when the same thermocouple is used in the same position in the oven . A first aspect is repeatability when the wafer is left in place (not leaded/unloaded). The long term repeatability under this condition was measured for more than 100 consecutive heating cycles of 30 seconds at temperatures up to 1150C. A second aspect of repeatability is the effect of loading and unloading the thermocouple wafer in the chamber. This effect was found to be a major contribution to repeatability errors of the old-style thermocouple structure.
During the repeatability runs, also the lifetime was measured. Initial measurements show a lifetime of at least a few hundred heating cycles up to 1150C, 30 s.
2:15 PM F1.3
3.3m PYROMETRY IN SINGLE SIDED RTA FROM 400-700C USING IN-SITU MEASUREMENT OF REFLECTION AND TRANSMISSION, Duane L. Marcy, Princeton Univ, Dept of Electrical Engr, Princeton, NJ; James C. Sturm, Princeton Univ, Dept of Electrical Engr, Princeton, NJ; Martin Benes, Suelika Chial, Princeton Univ, Dept of Electrical Engr, Princeton, NJ.
Pyrometry of silicon wafers under 700C at wavelengths over 1 um is difficult because lightly doped wafers become partially transparent, making the measurement of emissivity difficult. In this work we present initial results of 3.3 m pyrometry for 400 700C, measuring both reflection and transmission in-situ to determine emissivity. A modified commercial RTCVD reactor with 8'' wafer capability was used to study the temperature measurement of Si wafers over the range of 400-700C using top and bottom detectors. The bottom of the chamber has a thick quartz window through which heating power is introduced from a 3 zone quartz lamp housing. The bottom detector is mounted in the lamp housing focused on the Si wafer. The top detector is focused on the Si wafer through a Pyrex window. Each detector has a 3.3 m filter in line with the focusing optics. The top and bottom detectors measure both wafer radiation and reflection and transmission respectively using ''ripple'' techniques at 25 Hz. The measured transmission on a heavily doped wafer at all temperatures and a lightly doped wafer at high temperatures was zero, indicating no lamp radiation ''leaked'' around the wafer. For heavily doped wafers emissivity was independent of temperature and the measured temperature by pyrometry agreed well with that measured by thermocouple for 400 700C. For lightly doped wafers, emissivity was constant above 600C, but decreased sharply at low temperatures to near zero at 400C, due to the increased transparency of the wafer. Using fixed emissivity, the measured temperature severely underestimates the actual temperature below 600C. By calculating emissivity from the measured transmission, accurate temperature measurement was achieved from 400-700C without any a priori knowledge of the wafer.
2:30 PM F1.4
AN INTERACTIVE SYSTEM FOR WAFER EMISSIVITY ESTIMATION AS DETERMINED IN AN RTP CHAMBER, Maurizio Fulco, Onofrio Louis Russo, New Jersey Inst of Technology, Newark, NJ; Sergey Belikov, New Jersey Inst of Technology, Electronic Imaging Center, Newark, NJ; Walter F. Kosonocky, New Jersey Inst of Technology, Newark, NJ.
We demonstrate an interactive software system in which the emissivity of wafers can be estimated in situ using different models to obtain the most likely values. The system allows the data taker to introduce a choice of methods of simulation for the numerous emissivity models, in addition to the selection of design parameters necessary for the control of temperature uniformity. The objective of the interactive system is to obtain a better estimation of the wavelength dependent emissivity by using existing data such as the integrated emissivity, for example, as input information. Results for some of the models will be presented and compared to show variations in the models chosen.
The principal advantages offered by the system are the likely prospects of a realistic improvement and confident assessment for real-time temperature measurement and control in an RTP environment.
2:45 PM F1.5
OPTIMIZATION OF THE AST HOT LINER FOR SUBMICRON PRODUCTION, Terrence J. Riley, Advanced Micro Devices, Austin, TX; Rolf Bremensdorfer, Steven Marcus, AST Elektronik USA Inc, Tempe, AZ.
In an effort to develop an emissivity independent temperature measurement technique for the AST Rapid Thermal Processor (RTP), AST has conceived the Hot Liner. The Hot Liner is a coated silicon wafer which is permanently installed in the process chamber, immediately below the wafer. The pyrometer, which is calibrated to a production wafer, views the constant emissivity Hot Liner to produce repeatable temperatures on product wafers regardless of their back side emissivity.
Given the repeatability of the Hot Liner, the wafer temperature uniformity must then be optimized in order to achieve 0.25 m capable processing. AST has developed a methodology which incorporates process monitors (ion implanted test wafers) to establish process uniformity in addition to multiple thermocouple wafers to verify across wafer temperature uniformity. The process monitors are used to separately optimize the ramp and steady-state steps is the production recipe.
Utilizing the AST methodology to optimize processing with the Hot Liner has allowed AMD to significantly improve its RTA processing. The Hot Liner greatly decreases back side and pyrometer effects which yields limited wafer-to-wafer variation (<5C, 3). In combination with the optimization process, this results in excellent within wafer uniformity (<3C, 3).
3:30 PM F1.6
IMPACT OF EMISSIVITY-INDEPENDENT TEMPERATURE CONTROL IN RAPID THERMAL PROCESSING, Minseok Oh, Bell Labs, Lucent Technologies, Multilevel Interconnect Matls Development, Orlando, FL; David C. Brady, Bell Labs, Lucent Technologies, Orlando, FL.
Amorphous silicon is known to vary its emissivity at annealing temperatures over 500oC due to polycrystallization. This transition usually occurs during the ramp and the beginning of steady stages of the rapid thermal process. However, majority of current temperature control methods in RTP neglect time-dependent change of emissivity, and the temperature profile of process calibration is different from that of real annealing process. Various kinds of wafers with in-situ doped amorphous Si will be investigated using emissivity-independent temperature control. Some process parameters and material parameters, such as ramp rate and doping level, will be explored to study their influences on emissivity change, and consequently on electrical and optical parameters.
3:45 PM F1.7
RAPID-THERMAL ANNEALING AND OXIDATION OF SILICON WAFERS WITH BACK-SIDE FILMS, Anthony T. Fiory, Bell Labs, Lucent Technologies, Murray Hill, NJ.
Temperatures for lamp-heated rapid thermal processing of wafers with various back-side films were controlled by a Lucent Technologies pyrometer which uses ac ripple in reflected infrared radiation to compensate for the emissivities of wafer back sides. Temperature control for anneals of arsenic and boron implants was inferred from measurements of post-anneal sheet resistances. Temperature control for rapid thermal oxidation was inferred from ellipsometry measurements of oxide thicknesses. Results from wafer maps show dependences of effective process temperature distributions on back-side films comprised of one or more layers of silicon dioxide, silicon nitride, and amorphous or polycrystalline silicon. The emission radiation used to sense temperature as well as the lamp power required to control temperature vary with the spectral emissivities of the back-side films.
4:00 PM F1.8
EMISSIVITY-INDEPENDENT RAPID THERMAL PROCESSING USING RADIATION SHIELDS, Paul J. Timans, Roy N. Morishige, AG Associates, San Jose, CA ; Yuval Wasserman, AG Associates, Dept of Process Technology, San Jose, CA.
The stringent demands for process repeatability in advanced device fabrication technologies require that rapid thermal processing (RTP) systems provide process temperatures which are immune to the impact of surface coatings on the optical properties of wafer back sides. Simple RTP system configurations, in which the temperature is controlled by a pyrometer viewing the wafer's back side, are very vulnerable to changes in the emissivity of this surface. One method for emissivity-independent temperature control is to use an opaque hot-plate beneath the wafer as a radiation shield, which masks the wafer's back side from the lower bank of lamps and provides a target whose temperature can be monitored easily by a pyrometer or a thermocouple. This paper discusses the use of radiation shields for emissivity-independent temperature control and presents experimental results and a theoretical model which explains the origins of the emissivity independence. The theoretical calculations use a detailed model for the temperature dependent thermal radiative properties of the wafer combined with a simple, zero-dimensional analysis of radiation heat transfer in the system. The model is used to predict the dynamic temperature responses of the RTP system components, including a quartz isolation tube, the wafer, and the radiation shield.
4:15 PM F1.9
IMPROVED METHODS FOR EVALUATION OF RAPID THERMAL PROCESSORS, Tony Speranza, SEMATECH Inc, Austin, TX; James S. Nakos, IBM, Burlington, VT; Val Medina, Univ of Texas-Austin, Austin, TX; Sanjay K. Banerjee, Univ of Texas-Austin, Microelectronics Research Ctr, Austin, TX; Pat Lysaght, SEMATECH Inc, Austin, TX; Gary Williamson, Univ of Texas-Austin, Austin, TX; Don Lindholm, SEMATECH Inc, Austin, TX.
Rapid Thermal Processing continues to emerge as a mainstream manufacturing process. As temperature control requirements become more stringent, significant challenges arise in determining RTP system performance. SEMATECH has worked extensively on understanding sources of variation and developed improved methods for benchmarking commercial RTP systems.
The University of Texas has modeled common RTP monitor process conditions. These modeling results have been coupled with careful monitor fabrication, processing and measurement techniques. Results of high temperature studies indicate RTP performance can be predicted within 1C. This paper summarizes the issues, methods and results which allow for improved RTP system characterization.
4:30 PM F1.10
TEMPERATURE AND WAVELENGTH-DEPENDENT EMISSIVITY OF SILICON AND MULTILAYERS ON SILICON, Sufian Abedrabbo, Wei Chen, Feiming Tong, Nuggehalli Ravindra, New Jersey Inst of Technology, Dept of Physics, Newark, NJ; Arun K. Nanda, SEMATECH Inc, Matls & Bulk Processing Div, Autin, TX; Tony Speranza, Alexander M. Tello, SEMATECH Inc, Austin, TX.
The spectral transmittance, reflectance and emittance of silicon related materials and structures are measured simultaneously utilizing a special emissometer operating at near- and mid-IR spectral range and temperature range of 300 to 1500 K. Several kinds of samples have been considered here: a) multilayers of SiO/Si/SiO/poly-Si, with back side oxide of 1600 and 250 , respectively; b) double-side polished and single-side polished Si; c) SiO/Si with different oxide thicknesses; d) polysilicon. An analysis has been performed to interpret and compare the results obtained from these measurements.
For the multilayers of SiO/Si/SiO/poly-Si, it is interesting to note that for temperatures above 600C, the emissivity is independent of temperature and wavelength, for the back side oxide thickness of 1600 . The sample with the back side oxide of 250 is currently under investigation. It is found that at room temperature, the double-polished Si sample has negligible absorptance, while the single-side-polished Si has an appreciable absorptance. Concerning the SiO/Si, we find that there is a sinusoidal relation of emissivity as a function of the silicon dioxide thickness, in accord with the Applied Materials model. For polysilicon, we have compared the emissivity of front-side versus back-side as a function of wavelength and temperature.
4:45 PM F1.11
EMISSIVITY STUDIES ON AMORPHOUS Si/SiO/Si, Wei Chen, New Jersey Inst of Technology, Dept of Physics, Newark, NJ; Minseok Oh, Bell Labs, Lucent Technologies, Multilevel Interconnect Matls Development, Orlando, FL; Sufian Abedrabbo, Feiming Tong, Nuggehalli Ravindra, New Jersey Inst of Technology, Dept of Physics, Newark, NJ.
Experimental results of the temperature dependent emissivity of amorphous Si/SiO/Si in the temperature range of 300 to 1200 K have been reported here. These measurements have been performed using a spectral emissometer, operating in the wavelength range of 0.9 to 20 microns, for varying amorphous silicon film thickness in the range of 1000 to 5000 . Interpretations have been sought by detailed comparisons of the experimental data with those on polysilicon/SiO/Si structures. The effect of grain size/macroscale roughness on emissivity is investigated. A qualitative understanding of the influence of surface morphology on emissivity in these structures is inferred from these studies.
5:00 PM F1.12
TEMPERATURE ESTIMATION AND PRECISION CONTROL OF RTP SYSTEMS BY MULTI-ZONE LAMP INTERFERENCE AND WAFER EMISSIVITY COMPENSATION, Sergey Belikov, New Jersey Inst of Technology, Electronic Imaging Center, Newark, NJ; Jalil Kamali, Young Jin Lee, Mehrdad Moslehi, CVC Products Inc, Fremont, CA.
RTP temperature measurement using conventional pyrometric technique has serious limitations such as uncertainty of emissivity, lamp interference, and window/chamber heating effect. In this paper, we propose to compensate for these effects, using a real-time computational algorithm based on physical models of pyrometric detectors and wafer temperature dynamics. We consider an RTP system for processing 200 mm wafers, with five zones of heating lamps and ten pyrometric sensors, five of which measure the radiation from five optically isolated dummy lamps and the rest measure the radiation of the wafer back side at different radial positions. Thermocouple measurements are also used to identify the model parameters.
The model of detectors is based on the Plank's formula of radiation density, model of narrow optical filter and emissivity of the wafer, estimated in real time. The dynamic model of heat transfer on the wafer uses the same parameters as the detectors' model. Temperature and emissivity are estimated in real time using spatial and temporal filtering. The geometrical and physical parameters of the models are identified before the real time runs through specially designed experiments. A nonlinear adaptive algorithm is used as the temperature controller. Application of the adaptive estimation and control enables one to evaluate the best abilities of an existing RTP system and come up with optimal RTP design.
SESSION F2: RTCVD
Chair: Jimmie Wortman
Wednesday Morning, April 2, 1997
Nob Hill B
8:30 AM *F2.1
SELECTIVE Si/SiGe HETEROSTRUCTURES FOR ADVANCED CMOS AND BiCMOS TECHNOLOGIES, Jeorge L. Regolini, France Telecom, CNET, Meylan, FRANCE.
New device architectures for advanced Integrated Circuits (IC) have been studied within the frame of our GRESSI Program through the technological development of the well known but less implemented low temperature selective epitaxial Si and SiGe films. High performance IC manufacturing requirements, such as large diameter wafer uniformity, reproducibility, throughput and reliability can be fulfilled by commercial integrated processing, single wafer cluster tools.
Using an industrially available CVD single wafer reactor special care has been taken to integrate those films in advanced CMOS and BiCMOS processes with a minimum of drawbacks. In fact, the Si and SiGe growth rate dependance on filling ratio as well as full selectivity are major issues. The loading effect as a function of temperature, gas mixture, Ge and dopant incorporation has been studied and optimized for these applications. Finally, device results are compared between the conventional and developed architectures, showing real improvements with a minimum process modifications.
9:00 AM F2.2
EFFECT OF C AND Ge CONCENTRATION ON THE THERMAL STABILITY OF RTCVD-GROWN Si GeC ALLOYS, Patricia Warren, Stephane Retzmanick, Martin Gotza, Marc Ilegems, EPFL, Lausanne, SWITZERLAND.
Si/Si/Si heterostructures containing up to 20 at.Ge and1.9at. C were grown on (001) silicon by low pressure Rapid Thermal Chemical Vapor Deposition, using a mixture of silane, germane and methylsilane, diluted in hydrogen. The samples were then annealed in a Rapid Thermal Processing furnace, under an atmospheric pressure of nitrogen, at temperatures ranging from 900 to 1030C. The samples were characterized using Infrared Spectroscopy (FTIR) and x ray diffraction. SIMS profiling and TEM observation were performed on some of the samples.
Substitutional C gradually precipitated out to form cubic silicon carbide (-SiC). The in-plane lattice constant remained constant after annealing, indicating that there was no mechanical strain relaxation misfit dislocations. The perpendicular lattice constant increased due to the decreasing substitutional C concentration, as it decreased due to the germanium out-diffusion. This variation of the strain with annealing was modelized, and allowed the determination of the kinetics of the precipitation. The same behavior was observed for all samples. Indeed, the precipitation speed was always increased for samples with higher initial Ge and C concentrations.The kinetics of this precipitation was found in very good agreement with present results of the literature. This systematic study of the phenomena as a function of Ge initial concentration, moreover, explains the discrepancies observed in the literature results.
9:15 AM F2.3
B-IMPLANTATION AND ANNEALING OF SiGe ALLOYS, Ronlian Jiang, W. P. Liu, Ning Jiang, S. M. Zhu, L. Q. Hu, Youdou Zheng, Nanjing Univ, Dept of Physics, Nanjing, CHINA.
SiGe epilayers have been used widely to fabricate various devices. Consequently, it is important to understand the ion implantation and annealing behavior in SiGe epilayers. In this paper, boron ion implantation and annealing of SiGe epilayers were investigated. SiGe alloy films were grown on p-Si(100) substrates by Rapid Thermal Process/Very Low-Pressure-CVD. Ge fraction x was selected to be 0.18-0.30. The samples were implanted with 40 KeV B for a dose of 2.5 x 10 cm, and then annealed by rapid thermal annealing (RTA) at 650-900C for 10 sec and by furnace annealing at 550-650C for 30 min, respectively. Hall effect and x-ray diffraction measurements were performed. For the samples annealed in RTA at 750C for 10 sec, it has been found that the mobilities were as high as 260-320 cm/Vs (x = 0.18-0.30), and the activation was higher than 95. While for the samples annealed in the furnace at 600C for 30 min, similar mobilities and activation were obtained, but the crystallinity worsened. Moreover, the relation between Ge fraction and annealing temperature is also discussed.
9:30 AM F2.4
COMPARISON OF SiH AND SiH RTCVD KINETICS USING IN SITU SPECTROSCOPIC ELLIPSOMETRY, Yaoshi Hu, Sing Pin Tay, Yuval Wasserman, AG Associates, Dept of Process Technology, San Jose, CA; Changyi Zhao, Eugene A. Irene, Univ of North Carolina, Dept of Chemistry, Chapel Hill, NC.
A comparison of the kinetics of RTCVD polysilicon using SiH and Si was performed. Quantitative assessment of the nucleation parameters and the microstructures of the deposited polycrystalline Si (poly-Si) films on SiO have been determined using in-situ real time single wavelength and spectroscopic ellipsometry. In addition to ellipsometry, atomic force microscopy and cross-sectional transmission electron microscopy were used ex-situ to observe the nucleation stage and the microstructures of the poly-Si films. In the present study the nucleation film microstructure and surface roughness of polysilicon deposited using SiH and Si in the RTCVD system were compared. It is shown that under the same processing conditions, the saturation nuclei density for Si-based process is about 6 times higher than that for SiH, resulting in a smoother and more columnar structure than that from SiH.
A particularly important parameter for selective epitaxial depositions is the time for nuclei to form, i.e., the incubation time. Operational incubation times were determined from the real time ellipsometric measurements and confirmed by AFM. The incubation times for SiH4 and Si chemistries are different but show similar activation energies of about E = 1 eV in the 600-800C range. A formula of incubation time t was obtained and expressed as follows: where P is the partial pressure (Torr) of the reactant gas, C is constant depending on minimum detectable nucleus size, substrate, and reactant gas, C = 2.6x10 minTorr for SiH, and C = 4.4x10 minTorr for Si. The physical meaning and comparison with the previous experimental results from other publications are also discussed.
9:45 AM F2.5
ELECTRICAL PROPERTIES OF SCHOTTKY CONTACTS OF TiW ON RTCVD SiGeC FILMS, Jian Mi, Yilu Zhang, Cary Y. Yang, Santa Clara Univ, Dept of Electrical Engr, Santa Clara, CA; Patricia Warren, EPFL, Lausanne, SWITZERLAND.
The Si/Si heterosystem has received increased interest as a material for fabricating high-performance devices using Si based technology. The advantages of SiGeC/Si lie in the adjustability of strain, bandgap, and band offsets by tailoring the Si Cy composition. The main issue underlying the epitaxial growth process is to incorporate carbon into the alloy without introducing defects.
We have grown high-quality Si/Si heterostructures using rapid thermal chemical vapor deposition with silane, germane, and methylsilane as source gases . The substitutional Ge and C concentrations in the alloys were up to 30 at and 2.2 at, respectively. A model describing the mechanism of carbon incorporation was proposed. In this work, Schottky diodes of TiW and Al on SiGeC layers, with Ge content being 20 at and C contents ranging from 1.6 to 2.2 at, were fabricated using conventional Si processes including ion implantation, thermal annealing, and metal sputtering. Electrical measurements (I-V and C-V) were performed to assess the effects of structural defects in the alloy on diode electrical properties. The study led to further understanding of the precise nature of these defects. The relationship between electrical property degradation and growth conditions is also investigated.
10:00 AM F2.6
POLYCRYSTALLINE Si GROWTH ON -SiC BY RAPID THERMAL CHEMICAL VAPOR DEPOSITION, Cheewee Liu, National Taiwan Univ, Dept of Elect Engr, Taipei, TAIWAN; James C. Sturm, Princeton Univ, Dept of Electrical Engr, Princeton, NJ.
Polysilicon growth on silicon dioxide has been extensively studied with great success on device applications. Since the SiO is amorphous material, the strain effect due to the crystalline substrates cannot be observed. We, therefore, performed the polysilicon growth on single crystalline, -SiC buffers on (100) Si by RTCVD. The single crystalline SiC buffer on Si was grown at 800C using methylsilane. The poly Si films were deposited on the SiC buffers at the temperature of 625 - 1000C at 6 torr using dichlorosilane or silane. Note that the same growth conditions for bare Si substrates yield to single crystalline Si layers.
At high growth temperature (800 - 1000C), the (110), (111). and (311) textures of 0.6 m poly Si have been observed by XRD, and the relative contents of (311) and (111) decrease as the growth temperature decreases, very similar to the poly Si growth on oxide with similar thickness . The activation energy of (111) and (311) is 2.6 eV and 1.7 eV higher than that of (110) textures. For poly Si on oxide grown at low temperature (700C), the 0.6 m poly Si film was dominated by (111) textures [l]. However, the poly Si with a thickness of 0.1 m grown at 625C on SiC buffer exhibits only (110) texture without diffraction peaks from other textures such as (111) and (311) in the XRD spectrum. The enhanced growth rate of (110) texture in thin poly Si on SiC can be understood by the small misfit of 3(average of two transverse direction) between (110) Si plane and (100) SiC plane, which makes it possible to grow single crystalline Si. However, due to the (100) Si substrate interference, the single crystalline growth of the epitaxial Si cannot be confirmed. One of the authors (C.W. Liu) would like to thank the support of NSC, ROC (86 2221-E-002-089).
10:45 AM F2.7
HIGH PERFORMANCE HIGH DIELECTRIC CONSTANT FILMS DEPOSITED BY DUAL SPECTRAL SOURCE ASSISTED METALORGAINC CHEMICAL VAPOR DEPOSITION (MOCVD), Yuanning Chen, Rajendra Singh, Clemson Univ, Dept of E&CE, Clemson, SC.
Dual spectral source assisted MOCVD is an ideal technique for the deposition of high dielectric constant materials. Tungsten halogen lamps and deuterium lamp are used as the sources of optical and thermal energy. Tantalum pentoxide films were deposited at 400 degree centigrade for 15 minutes and annealed at 600 degree centigrade for 40 minutes. The low deposition and annealing temperature meets the requirement of future integrated circuit processing. Several techniques have been used to characterize the films. The leakage current density is as low as 10 A/cm. for voltage under 4V. A dielectric constant of 25 is measured at a frequency of 10K Hz. The surface roughness for the samples processed with and without VUV radiation are 24.3nm and 31.4nm respectively. Corresponding stress valuse with and without VUV radiation are 5.74x10 dynes/cm and 3.47x10 dynes/cm, respectively. The high energy photons used in the deposition and annealing process plays an important role in obtaining high performance films of tantalum pentoxide. Complete details of the electrical, structural, and mechanical characteristics of tantalum pentoxide films will be presented.
11:00 AM F2.8
PSEUDOMORPHIC CSi ALLOYS GROWN ON Si BY RTP/VLP-CVD, Ning Jiang, Han Ping, R. H. Wang, S. M. Zhu, Ronlian Jiang, Youdou Zheng, Nanjing Univ, Dept of Physics, Nanjing, CHINA.
Bandgap engineering concepts have had a significant impact on silicon technology for many devices. In lots of applications, it is desirable to have a wider bandgap than that of pure Si. C is a possible candidate for a wide bandgap Si-based material which can be integrated with Si. We have deposited pseudomorphic Si alloys on silicon substrates by Rapid Thermal Process Very Low Pressure Chemical Vapor Deposition (RTP/VLP-CVD) using SiH and C as sources for silicon and carbon at temperatures in the range of 650 700C. There are two different growth mechanisms in the growth process, one corresponding to the strained layer, the other to the strain relaxed. Raman spectra show the peak of Si-Si bond in epilayer differs with that of substrate due to the strain. A phonon mode corresponding to Si-C bond at 960 cm in Raman spectra and 282.2 eV peak appearing in XPS spectrum means that the Si-C bonds have been formed. X-ray diffraction confirms the growth of pseudomorphic, tetragonally strained alloy, and AES determine the carbon component in epilayers. It can be concluded that the pseudomorphic, strained Si epilayers with the substitutional carbon atoms and the maximum C component of 5 have been obtained by RTP/VLP-CVD.
11:15 AM F2.9
SELECTIVE RAPID THERMAL CHEMICAL VAPOR DEPOSITION OF TITANIUM DISILICIDE ON SILICON AND POLYSILICON, Lixin Nie, Chad Weintraub, Mehmet C. Ozturk, North Carolina State Univ, Dept of ECE, Raleigh, NC.
Selective rapid thermal chemical vapor deposition (RTCVD) of TiSi is a new process currently investigated as a means to form contacts to ultrashallow junctions without substrate consumption. In this paper, we present our results on RTCVD of TiSi on polycrystalline silicon using TiCl/SiH/He chemistry. Samples were prepared by depositing TiSi films selectively on oxide patterned crystalline silicon, undoped polysilicon and phosphorus doped (3 x 10 cm) silicon. TiSi deposition was studied by varying SiH to TiCl flow ratio, deposition temperature and deposition time.
On crystalline silicon a SiH:TiCl flow ratio of 75:1 at 775C results in low resistivity C54 TiSi films with complete suppression of silicon consumption. We find that under the same deposition conditions the TiSi thickness on polysilicon grows linearly with deposition time and the growth rate (160 nm/min) is comparable with that on single crystalline silicon substrates. On the other hand, silicon consumption on polysilicon is faster requiring higher SiH:TiCl flow ratios. Phosphorus doping on the other hand, shows no significant effects on TiSi growth rate or silicon consumption. The results on submicrometer thin lines on crystalline silicon show that the sheet resistance is comparable to that on large structures and a linewidth dependency is not observed down to 0.5 mm. However, on polysilicon, sheet resistance starts to increase gradually below 1 um. Our results indicate that sheet resistance decreases as the deposition is reduced from 825C to 750C. Within the experimental conditions of this study, TiSi2 sheet resistance on both silicon and polysilicon remained below 2 ohms/square down to our minimum feature size of 0.5 m. Experiments on smaller geometries down to 0.1 m are currently in progress.
Our results indicate that RTCVD of TiSi is a promising alternative to the conventional SALICIDE process in the deep submicron regime.
SESSION F3: MODELING AND MANUFACTURING ISSUES
Chair: Terrence J. Riley
Wednesday Afternoon, April 2, 1997
Nob Hill B
1:30 PM *F3.2
BENEFITS AND LIMITATIONS OF RADIATIVELY HEATED SUSZEPTORS, Alfred Kersch, Siemens AG, Munich, GERMANY.
In radiatively heated single wafer reactors, suszeptors are used to control the wafer temperature. This temperature, however, might be significantly different than the suszeptor temperature. The reason is that the conductive coupling of the suszeptor to the wafer is often small, even when the wafer is placed directly on the suszeptor, and the temperature difference is then determined by the optical properties and the spectral distribution of the illumination.
In this paper, these temperature differences are calculated with reactor scale simulation for typical geometries. The radiation is modeled with Monte Carlo and the optical properties of the surfaces are calculated from the electromagnetic theory of thin films.
A commercial system with a thick suszeptor for Si-CVD at reduced pressure serves as an example for the size of the discussed effect and the comparison of the simulation with measurements provides a model validation. Then, a typical RTP system equipped with a thin suszeptor is investigated. The configuration is identified, under which the thin suszeptor leads to a reduced temperature variation in case of a changing wafer coating.
2:00 PM F3.3
RIGOROUS VALIDATION OF A 3D RADIATION/CONDUCTION HEAT TRANSFER MODEL OF A PHOTON BOX STYLE RTP CHAMBER, Karson L. Knutson, Narasimha Acharya, AG Associates, Dept of R&D, San Jose, CA.
In this work a 3-D model of a photon box style RTP reactor is presented. The model includes view factor based radiation heat transfer among a wafer, a quartz process isolation lube, lamp filaments, and the photon box enclosure. Conduction heat transfer is solved within the wafer and quartz and gas effects are accounted for with heat transfer correlations. To approximately account for the semi-transparency of quartz, a two-band model is used which assumes quartz is transparent below 3.5 m and opaque above this wavelength. Such models have been presented previously in the literature; however, the level of model validation has not been sufficient to demonstrate the accuracy that can be achieved. Here we form empirical models of wafer temperature profiles in the RTP system being studied, around high temperature operating conditions, 1000C. These empirical models are formed from data obtained via oxidation results and thermocouple instrumented wafers. Comparison of the results from the empirical models with those from the theoretical model demonstrate that such view factor based models can accurately predict local wafer temperature sensitivities to power variations as well as absolute power temperature relationships. To use models for design of reactors which meet current semiconductor technology requirements, they must predict wafer temperatures to within around 1C. For such precision, view factor models must be augmented by experimental calibration.
2:15 PM F3.4
MODELING AND MODEL VALIDATION FOR RTP DESIGN, Mark J. Fordham, Ming-Te Pan, Ji-Dih Hu, North Carolina State Univ, Raleigh, NC; F. Yates Sorrell, North Carolina State Univ, Dept of Mechanical & Aerospace Engr, Raleigh, NC.
A ray-trace algorithm is used to predict the spatial heat flux distribution on the wafer in a RTP system. This radiant heat flux distribution is combined with a finite volume conduction model to predict the wafer temperature profile during processing. Three different RTP configurations have been designed using this methodology, and the wafer temperature profiles for all three systems were measured using both thermocouples and two different IR imaging systems. For two of the systems there was good agreement between the measured and predicted temperature profiles. In the third system, the measured temperature profile was in disagreement with model predictions. The third system used different tungsten halogen lamps and reflectors than the first two systems. The disagreement was traced to a different radiant heat flux distribution from the lamps that were employed in the third system. This was determined by direct measurement of the radiation from the lamps, and by measurement of the spatial profile of the lamp irradiation at the wafer plane. The technique for measuring the irradiation profile as well as measured profiles are given, and these results are compared with model predictions.
2:30 PM F3.5
THE INFLUENCE OF FACILITY CONDITIONS ON WAFER TEMPERATURE DURING OPEN LOOP, LAMP POWER CONTROLLED, RTP, Peter Vandenabeele, Wayne Renken, Sensarray, Mijlen, BELGIUM.
An RTP system was optimized for high repeatability under open-loop, lamp-power control (1C 3 achieved). An important aspect was the sensitivity of the wafer atmosphere to facility conditions. Experiments and simulations were executed to find the sensitivity to the cooling water and cooling air temperature and flow. The experimental system was a Heatpulse 610 reactor, with custom precision lamp control electronics. The temperature was measured using a thermocouple instrumented wafer.
The wafer temperature was highly sensitive to the cooling air flow and much less sensitive to cooling air temperature, and water inlet temperature and flow. A similar result was found from the simulations. This sensitivity to cooling air flow could be explained as a chain reaction, where the cooling air flow influences the quartz tube temperature and this, in turn, influences the wafer temperature. The first wafer of a series of heat cycles was always colder than the next wafers of a series. In one experimental setup, the quartz tube temperature was measured with a tube pyrometer and the measured value was used to correct the lamp voltage to yield a constant wafer temperature. In this fashion, the sensitivity to cooling air flow and the first wafer effect could be fully corrected (avoiding the need for a dummy first wafer or preheat).
A side effect of the high sensitivity of the wafer temperature to cooling air was that the wafer temperature distribution could be drastically modified by using a special top plate in which different injection holes were separately controlled. It is shown that this technique of local quartz cooling can be used to very locally control wafer temperature.
To minimize the sensitivity to cooling air flow, a new process was developed wherein no cooling air is used during a 30-second heat cycle and, after that, the quartz is completely cooled during 330 seconds, while the lamps are off. This process was 10 times less sensitive to the cooling air flow than the regular process.
2:45 PM F3.6
A NEW TEMPERATURE COMPENSATION METHOD FOR Si WAFERS IN RAPID THERMAL PROCESSOR USING SEPARATED Si RINGS AS SUSCEPTORS, Jenn-Gwo Hwu, Kuo-Chung Lee, National Taiwan Univ, Dept of Elec Engr, Taipei, TAIWAN; Hong-Yuan Chang, National Taiwan Univ, Taipei, Taiwan.
Temperature non-uniformity is a very important issue for rapid thermal processing (RTP). Generally, wafer's edge will be colder than the center. Suitable design of chamber reflector geometry or multiple zone lamp clusters with separated power controls could reduce the temperature non-uniformity. As an alternative, guard rings can lower the radiant losses from the wafer's edge. But guard rings also have their limits; the center of wafer still has higher temperature than the edge.
In this work, a new temperature compensation concept, heat flow through patterned susceptor, is first presented. Concentric Si rings are used as patterned susceptors to get uniform temperature distribution of Si wafers. Si rings were fabricated from 4-inch Si wafer by chemical wet etching. Each ring is 3.5 mm in width and 300 m in thickness. The distance between adjacent rings is 1 mm. Si rings were put on the quartz or on the 4-inch Si wafer as susceptor. 3-inch Si wafers were used to monitor the oxide thickness after rapid thermal oxidation processing Si wafers were front side heated. The oxidation condition is 960C, 30 sec at 500 torr without rotation. It is found that proper arrangement of Si rings on the quartz and Si susceptor can make the Si wafers have more uniform oxide thickness distributions than those without using Si rings. The mechanism of temperature compensation is described. Since the Si wafer is one side heated, the susceptor without heated is always colder than the wafer. Through the Si rings, there is energy flow conducted to the colder susceptor from the hotter spot of Si wafers. Therefore, proper arrangement of Si rings can make the Si wafers have more uniform oxide thickness distributions than those without using Si rings. Further study is under investigation.
3:30 PM F3.7
THE PERFORMANCE OF THE FAST RAMP VERTICAL FURNACE, Kenneth Torres, SEMATECH Inc, Austin, TX; Robert Weaver, Semitool, Kalispell, MT.
This paper summarizes a joint project between Semitool, SEMATECH and Sandia National Labs to develop a fast ramp vertical furnace. The achieved goal of this project was to deliver a production vertical furnace capable of heating and cooling a batch of 50 wafers at rates of 75 and 50C/min, respectively. This paper will outline the distinctive and enabling design features of the furnace, such as the use of model predictive control techniques to stabilize the wafer temperatures within 2 to 3 minutes of reaching the nominal target temperature. The test results of a ten run passive data collection for a boron S/D anneal will be discussed, showing a 3C 3-sigma variation for all points. The fast ramp vertical furnace is designed to meet 0.25 and 0.18 micron technology needs, improve cycle time, and give the customer the flexibility of using different wafer batch sizes within a 25 vertical zone (where the ramp rates are adjusted according to the wafer pitch).
3:45 PM F3.8
UNDERSTANDING THE IMPACT OF BATCH VS. SINGLE WAFER IN THERMAL PROCESSING USING COST OF OWNERSHIP ANALYSIS, S. Hossain-Pas, Texas Instruments Inc, Manufacturing Science and Technology Center, Dallas, TX.
Cost of ownership (CoO) has gone from a relatively new comparison metric to an accepted analysis technique in the semiconductor industry. This report seeks to focus on a specific type of semiconductor process, thermal processing, so that a better understanding of the relationships between technologies, film tapes, process requirements, and equipment parameters can be gained.
An important aspect of thermal processing is its long-term historical use of batch type systems and its recent and progressive foray into the world of single-wafer processing. Single-wafer processing in the case of thermal processes consists of Rapid Thermal Process (RTP). This transition from conventional batch (vertical reactors in this report) to RTP equipment provides a good basis for studying process dependence on CoO. Factors such as total test time, $/good cm, process flexibility, and others are discussed as well as more well-known metrics such as $/wafer, MTBF, etc. Preliminary analysis of Chemical Vapor Deposited (CVD) polysilicon shows that, if all other parameters are kept constant and only the diameter of the wafer is varied, the cost associated with $/good cm2 is reduced as wafer diameter is increased. Increasing wafer diameter from 150 mm to 300 mm, the reduction in $/good cm is roughly by a factor of four for CVD polysilicon. RTP systems have improved recently in performance and capability, but more advances in performance parameters such as MTBF and throughput are required in order for them to compete against batch systems in the manufacturing environment. Where enabling process capabilities are not the sole criteria, batch systems currently remain the thermal processing tool of choice.
In order to make a valid comparison where possible, SEMATECH defaults are used. Process specific inputs such as film thickness, dopant concentration, and anneal times are standardized. The level of technology is at 0.25 m while some inputs are borrowed from 0.35 m where necessary. These inputs are noted as such. One of the most important questions In thermal processing is ''should the transition from batch to RTP be made and, if so, when should it be made?'' Thus report attempts to debate this question using CoO as a foundation.
4:00 PM F3.9
RAPID VERTICAL PROCESSOR, FAST-RAMP SMALL-BATCH VERTICAL BATCH FURNACE DIFFUSION AND OXIDATION APPLICATIONS, Cole D. Porter, Silicon Valley Group Inc, Thermco Systems Div, San Jose, CA.
Fast-ramp small-batch and enhanced ramp large-batch vertical furnace technology improves batch furnace processing capabilities. A new high watt density furnace heater element is designed and implemented to accommodate the accelerated temperature ramp-up rate. By increasing temperature ramp rates, both up and down, advancements in batch furnace processing can be realized. Cycle time and thermal budget reduction, improved diffusion control, and improved film thickness uniformity will be reported and discussed. Increasing the temperature ramp rates in a batch furnace introduces a number of new challenges. Wafer warpage and slip resulting from large temperature differences across the wafer experienced during fast ramp conditions, require innovations in wafer fixturing and quartzware design. A new fast-ramp wafer fixture design is implemented which reduces within wafer temperature gradients. Wafer warpage, slip, and the demands of 0.25 and 0.18 micron processing dictate improvements in furnace and wafer temperature control which are overcome by using Model Based Temperature Control (MBTC). MBTC uses a mathematical model of the thermal characteristics of the furnace, process chamber and wafer stack to predict and control the wafer's temperature. This paper will describe the testing and results of the Silicon Valley Group Inc., Thermco Systems Division ''Rapid Vertical Processor''; the RVP-9000 which incorporates the above advancement in furnace technology and temperature control.
SESSION F3a: MODELING AND MANUFACTURING ISSUES
Chair: Terrence J. Riley
Wednesday Morning, April 2, 1997
Nob Hill B
11:30 AM *F3a.1
RAPID THERMAL PROCESSING: WHEN WILL IT REPLACE BATCH PROCESSING?, Michael F. Pas, Texas Instruments Inc, Semiconductor Process & Device Center, Dallas, TX; Sylvia D. Pas, Texas Instruments Inc, Mfg Science & Technology Ctr, Dallas, TX.
Rapid Thermal Processing (RTP) is currently well established at the sub- 0.5 m nodes for implant anneal and silicide formation/anneal in logic applications. Rapid Thermal Chemical Vapor Deposition (RTCVD) is also being evaluated to deposit thin nitride for the DRAM storage node dielectric. A combination RTP/RTCVD has been evaluated in the form of a cluster tool to evaluate 60 gate oxides. These applications of RTP are considered process enabling because of either improved temperature ramp control or ambient control which is not available in batch processing. However, even with these specialized applications, rapid thermal processing comprises less than 15 of the front end thermal processes in a typical 0.35 m fab. There remains major process and equipment issues with rapid thermal processing which must be overcome if it is to supplant batch processing at the 0 35 m node. The process issues which are especially critical for RTCVD processing require improved temperature measurement, high growth/deposition rate, and an efficient method to clean the process chamber. Major equipment issues are reliability and throughput which directly affects the tool cost of ownership. In this paper each or these issues will be addressed and compared to batch processing using a generic logic and DRAM flow. It will also look into the feasibility of rapid thermal processing replacing batch processing as 300 mm wafer processing is implemented.
SESSION F4: INTEGRATED PROCESSING
Chair: Martin L. Green
Thursday Morning, April 3, 1997
Nob Hill B
8:45 AM F4.1
INTEGRATED RAPID THERMAL PROCESSING SOLUTIONS FOR 0.25-0.18 MICRON TECHNOLOGIES, Yitzhak E. Gilboa, Haim I. Gilboa, Ziv Atzmon, Hadvi Spielberg, Etai Branski, AG Associates, San Jose, CA; Yuval Wasserman, AG Associates, Dept of Process Technology, San Jose, CA.
This review paper describes a new processing approach with an emphasis on integrated process solutions for CMOS gate stack and DRAM capacitor stack formation. Data supporting an integrated approach for RTCVD fabrication will be shown. A typical gate stack formation process for Logic or Nonvolatile Memory devices consists of three major steps: Si surface cleaning and passivation in the dry cleaning module, followed by rapid thermal gate oxidation/nitridation, and in-situ doped polysilicon deposition. The capability of an integrated process solution for gate oxide is demonstrated. The distribution of charge to breakdown (Qbd) of a 55 MOS gate dielectric formed in an RTP reactor without an integrated cleaning was compared to a gate dielectric that was processes through a dry cleaning module prior to the oxidation step. It can be seen that the Qdb value for 50 failure is higher when an integrated cleaning process is applied.
An Integrated process solution for the formation of DRAM capacitor dielectric is shown. In this case the polysilicon surface of the bottom capacitor plate is cleaned using a dry cleaning process. The wafer is transferred into the dielectric module and a thin thermal Si nitride film is grown followed by a thin LPCVD Si-nitride deposition. The wafer is then transferred to the poly deposition module in which the top capacitor plate is deposited. The integration solution results in a superior capacitor performance in comparison to the standard manufacturing process done in stand-alone batch tools. The results of such a comparison are shown.
9:00 AM F4.2
GATE STACK FORMATION USING A FULLY INTEGRATED SINGLE WAFER CLUSTER TOOL, David C. Frystak, John Kuehne, Texas Instruments Inc, Semiconductor Process & Device Ctr, Dallas, TX; Rick L. Wise, Texas Instruments Inc, Semiconductor Process & Device Center, Dallas, TX; Burt Fowler, SEMATECH Inc, Austin, TX; Phil Grothe, Joel Barnett, FSI International, Chaska, MN; Gary Miner, Applied Materials Inc, Santa Clara, CA.
A single wafer gate cluster tool has been under evaluation at Texas Instruments in an effort to quantify the effects of gate clustering on defect density, process capability and device performance The single wafer gate cluster tool consists of a hydrofluoric vapor (HF-vapor) pre gate cleanup module, a rapid thermal oxidation (RTO) module and a polysilicon rapid thermal chemical vapor deposition (RTCVD) module. All three modules are mounted onto a centralized vacuum loadlock transfer chamber. The gate dielectric charge to breakdown (Qbd) of capacitor structures formed using the single wafer gate cluster tool typically averaged 9.1 to 12.3 coulombs per square centimeter. Excellent gate oxide integrity yield values in the range of 99.8 to 100 were also routinely obtained. The films were free of low field and midfield gate dielectric breakdown events and the devices exhibited dielectric breakdown field strength in excess of 10 megavolts per centimeter. The basic process capability associated with each of the three modules operating as stand alone tools will be discussed, along with issues associated with operating these modules in cluster mode. Details of the device characterization and an evaluation of the overall impact of single wafer gate clustering will be reported.
9:15 AM F4.3
GATE STACK FORMATION IN AN INTEGRATED PROCESSING CLUSTER TOOL, Frederique Glowacki, AST Elektronik, Dornstadt, GERMANY; Barbara Froeschle, Lutz Deutschmann, Isabelle Sagnes, Francois Martin, Daniel Bensahel, AST elektronik GmbH, Dornstadt, GERMANY; Anton J. Bauer, Fraunhofer-Inst, Integrierte Schaltungen-Bauelementetechnologie, Dornstadt, GERMANY.
The purpose of this publication is to give an insight into process developments performed in two modules which belong to a cluster tool designed for the gate stack process sequence of cleaning, gate oxidation, and polysilicon chemical vapor deposition. For the first time, two suppliers integrate together complementary modules to build a cluster tool answering the demand of the IC manufacturers and following the ''best of breed'' approach. Three single-wafer rapid thermal process chambers, a Vapor Phase Cleaning (VPC), and a Rapid Thermal Oxidation/Nitridation (RTO/N) modules from AST Elektronik and a polysilicon chemical vapor deposition module from ASM International are currently connected together to test the feasibility of the single-wafer processing gate oxidation cluster tool.
Thin films of good quality and reproducibility are essential for advanced technologies to form reliable dielectrics. Such characteristics involve very precise control of the silicon surface preparation and gate oxide growth. Nitridation treatment is also required in order to improve the reliability and the electrical characteristics of the oxide. Vapor phase surface cleaning in AHF (Anhydrous HF)/methanol has been investigated and has shown promising results in terms of electrical characteristics. Preliminary results on the surface preparation under ozone to create, in gas phase, an oxide to passivate or stabilize with respect to time the silicon surface are resumed. Recently, NO nitridation has been investigated in comparison with NO nitridation in the formation of the gate oxynitride layer. Preliminary results have shown that the use of NO in a single-water cluster tool at low pressure and reduced thermal budget is well suited to the nitridation of thin oxide films with properties at least equivalent to those obtained under NO nitridation. All these results are favorable to the buildup of an integrated cluster tool for gate stack formation.
9:30 AM F4.4
A SUPPLIER'S PERSPECTIVE ON PROCESS INTEGRATION UTILIZING RAPID THERMAL PROCESSING, John K. Lowell, Applied Materials Inc, Austin, TX; Chris Gronet, Gary Miner, Kelly Truman, Applied Materials Inc, Thermal Process & Implant Div, Austin, TX.
As progress towards deep submicron devices and the introduction of 300 mm wafers continues, the role of rapid thermal processing (RTP) in semiconductor continues to expand. For semiconductor equipment suppliers, this development imposes several pathways which must be addressed simultaneously and in parallel. First there is the requirement of device performance demanded by customers. As suggested in the NTRS roadmap, RTP tools must be able to address process capability capable of meeting the issues of reduced supply voltages, leakage requirements, speed, reliability, and device design in all technologies. In addition future tools must also provide acceptable customer benefits with regard to cost of-ownership, throughput, controllability, and repeatability. However RTP is unique in its application to so many diverse areas of semiconductor fabrication such as junction anneals, contact formation, and oxide growth. This factor alone is responsible for the last area of development which is process integration. By this term we refer to the merging of several process steps within a fabrication sequence (gate stack formation for example) into an integrated whole. This integration will evolve from several stand-alone tools performing in concert to more complex cluster tools as customer needs change. For the supplier this is formidable challenge. In this task we will discuss some aspects of this task, and how RTP-based process integration efforts are meeting this challenge today and possibly in the future.
9:45 AM F4.5
CHARACTERIZATION OF OXIDE ETCHING AND WAFER CLEANING USING VAPOR-PHASE ANHYDROUS HF AND OZONE, Barbara Froeschle, Lutz Deutschmann, AST elektronik GmbH, Dornstadt, GERMANY; Anton J. Bauer, Edmund P. Burte, Fraunhofer-Inst, Integrierte Schaltungen-Bauelementetechnologie, Dornstadt, GERMANY.
As film thickness decreases, Si/SiO interface properties play a more significant role with respect to gate dielectric processing and integrity. Thus, pregate surface preparation becomes one of the most critical steps in future device technologies. The commonly wet cleaning prior to gate oxide growth is not only expensive, but also environmentally detrimental, since large quantities of ultrapure liquids are manufactured and have to be treated properly after use. Furthermore, wet cleaning is not compatible with integrated single-wafer manufacturing in cluster tools, which is expected to be important for 0.18 m technology and beyond. In our contribution, we will discuss the efficiency of vapor phase pregate silicon surface preparation processes carried out with a cleaning module integrated in a state-of-the-art cluster tool. The dependence of HF/methanol vapor phase etch rate on process parameters as etch time, AHF-flow and temperature has been studied, Using various combinations of vapor phase surface preparation chemistries, O-oxides at 1000C in the RTO-module are prepared, following immediately after the cleaning process without breaking the vacuum. Time dependent dielectric breakdown results will be presented for oxides preoxidation-cleaned in AHF, in ozone, and in AHF followed by ozone, and for a reference sample without any dry preoxidation cleaning. The results of capacitance-voltage, current voltage, and constant current injection measurements will be shown revealing the high quality and integrity of dielectric thin films grown in on precleaned silicon surfaces. From our results, we can state that vapor phase cleaning shows promising results for advanced single wafer ULSI manufacturing.
SESSION F5: SILICIDES
Chair: Tony Speranza
Thursday Morning, April 3, 1997
Nob Hill B
10:30 AM F5.1
IN-LINE AMBIENT MONITORING DURING SILICIDE RAPID THERMAL PROCESSING, E. Kondoh, IMEC, Leuven, BELGIUM; Karen Maex, IMEC vzw, Leuven, BELGIUM.
The impurity chemistry during rapid thermal processing is becoming an important topic in sub quarter micron ULSI manufacturing. The residual oxygen and moisture in the chamber ambient are key factors to improve yield of narrow silicided areas [e.g., Q.-W. Wang et al., MRS vol. 402, 221]. On the other hand, impurities desorption from the wafer itself occurs and can be a serious issue as well. In this respect, this paper reports on the real-time monitoring of gaseous impurities (mainly O) during TiSi and CoSi RTP. To monitor the O concentration, an in-line zirconia O sensor was installed on a pilot-line RTP system. The O content was monitored for processing of Ti/Si, Co/Si, oxides, and device wafers. Data taken during Ti and Co silicidation clearly revealed desorption and adsorption of O originating from the wafers. The amount of ad/desorption was estimated quantitatively relating to metallization structures and of gas management. The gas flow characteristics of the RTP system is modelled as a simple limited diffusion reactor to mathematically describe the transient response of O concentration to incoming O. The model is combined with experimental data to elucidate the behavior of O. Monitoring other gaseous impurities such as moisture and hydrocarbons is now being investigated.
10:45 AM F5.2
FORMATION OF TITANIUM-SILICIDE ON ION-IMPLANTED SILICON SUBSTRATE, Yitzhak E. Gilboa, AG Associates, San Jose, CA; Moshe Eizenberg, Technion-Israel Inst of Tech, Materials Engr, Haifa, ISRAEL.
The subject matter of this work is the formation of titanium silicide over ion implanted silicon. In order to optimize device performance, the doped Si contact characteristics after silicidation must be understood. Contact resistance depends on the dopant concentration at the silicide/Si interface. Since silicidation is known to cause a redistribution of the underlining dopants, the specific interaction of Ti silicide with As and B is of great interest. The formation of TiSi was compared over samples implanted with arsenic and BF at different doses and annealed at different temperatures and lengths of time in a rapid thermal process. Measurements were done to determine the composition, thickness and electrical characteristics of the silicide formed. The composition was determined from Auger electron spectroscopy, Rutherford backscattering, and transmission electron microscopy. The phase formation of the silicide was characterized by x-ray diffraction. The thickness of the formed silicide was calculated from profilemeter measurements, and Auger measurements. Dopant redistribution was studied using secondary ion mass spectroscopy. Contact resistance between the Ti silicide and Si was measured with a Kelvin contact probe. It was observed from comparing the results of the different implant doses that the amount of silicide formed over heavily doped Si at formation temperatures of 600C to 650 C was reduced compared to undoped Si. At formation temperatures above 750C, the implanted dose and species did not significantly affect the amount of silicide formation. Above 750C, the TiSi2 structure was found to be c54. Arsenic was found to diffuse into the Ti silicide layer in a diffusion controlled process. Boron was found to accumulate at the Ti silicide interfaces both with the substrate and with the unreacted layer. Fluorine was found at the Ti silicide/Si interface. The contact resistance measured over Arsenic implanted Si substrate increased as the silicide formation temperature was increased. The contact resistance over BF2 implanted Si remained almost constant at formation temperatures of 650C to 750C.
11:00 AM F5.3
KINETICS OF Pt AND Ir SILICIDE FORMATION STUDIED BY SPECTRAL ELLIPSOMETRY, Reinhard Schwarz, Inst Superior Tecnico, Dept of Physics, Lisboa, PORTUGAL; Lothar Ley, Armin Dittrich, Martin Hundhausen, Univ of Erlangen-Nuernberg, Dept of Technical Physics II, Erlangen, GERMANY; Liangyao Chen, Fudan Univ, Shanghai, CHINA; Dustin Woerle, Claudius Manke, Manfred Schulz, Univ of Erlangen-Nuernberg, Erlangen, GERMANY.
Silicide formation during thermal annealing can be conveniently studied by in-situ spectral ellipsometry. To monitor details of the reaction kinetics like the determination or the activation energy and the occurrence of second-order components, we have prepared Pt layers of 5 to 10 nm thickness sputtered onto (100) and (111) crystalline silicon substrates. The samples were annealed to 400C with temperature ramps of 1 to 10 degrees per minute in a UHV chamber attached to a spectral ellipsometer. The energy range extended from 1.5 to 5 eV. Earlier studies revealed a two-step silicide formation process including intermediate stages of di- and monosilicides. We found, for the example of Pt silicide, starting with a 8.5 nm thick Pt layer, that the onset of PtSi and PtSi formation shifted from 190 to 175C and from 240 to 225C, respectively, when the anneal rate was lowered from 3 to 1 K/min. One of the substrates was a 1.2 m thick microcrystalline silicon layer deposited onto glass to test whether indiffusion of metals can proceed more rapidly along grain boundaries than through bulk. Obviously, the silicide formation depends critically on the existence of oxide layers acting as diffusion barriers. Ellipsometer data was also monitored during the cooling process. At low anneal rates a small additional step was observed around 120C, possibly due to desorption of surface contaminants. The underlying model of silicide formation through a multilayer system was checked with depth profile measurements and compositional information obtained from Rutherford Backscattering.
11:15 AM F5.4
LASER ASSISTED TiSi FORMATION FOR ULSI APPLICATIONS, Nader Shamma, Hewlett Packard Co, ULSI Research Lab, Palo Alto, CA; Somit Talwar, Gaurav Verma, Karl-Josef Kramer, Ultratech Stepper, San Jose, CA; Nigel Farrar, Hewlett Packard Co, ULSI Research Lab, Palo Alto, CA; Chiu Chi, Wayne Greene, Hewlett Packard Co, ULSI Research Lab, Palo Alto, CA; Kurt Weiner, Ultratech Stepper, San Jose, CA.
Metal silicides are used in ULSI CMOS ICs as local interconnection as well as gate and source/drain contacts. In particular, disilicides of titanium have received considerable attention for device fabrication . Nonetheless, challenging issues for silicidation that arise from vertical and lateral scaling of device geometries remain to be addressed. The solid state reaction of Ti thin films and Si leads to the formation of various phases of titanium silicide of which the disilicides are of interest to device application. The nucleation of the C49-TiSi phase initiates at 550-700C, resulting in a film that has a specific resistivity of greater than 60 -cm. The transformation of the C49 phase to the low resistivity (15-20 -cm) C54-TiSi takes place at 700-850C. The C49 to C54 transition temperature scales inversely with the initial metal thickness and directly with the lateral confinement of the silicided region. This has resulted in substantial difficulty in scaling TiSi to sub-0.25 m device fabrication. In this report, we describe the results of recent work in which formation of the parent disilicide phase is achieved using XeCl pulsed excimer laser induced mixing of Ti and Si. The resulting C49 grain size is shown to be smaller than that obtained using ' 'traditional'' RTA. The parent phase is then easily converted to the C54 phase by "traditional" rapid thermal processing. Formation of continuous C54 TiSi on sub-0.1 m polysilicon lines is confirmed by sheet resistance measurements which indicate improved uniformity resulting from the diminished silicide-silicon interface roughness. It is proposed that uniform silicon melting upon laser exposure is the primary cause of the reduced interface roughness. Other processing advantages to be gained using this technique include relatively low sensitivity of silicide formation to substrate impurity concentration and to the presence of a native silicon oxide between Ti and silicon.
11:30 AM F5.5
USE OF A TIN CAP TO ATTAIN LOW SHEET RESISTANCE FOR SCALED TiSi ON SUB-HALF-MICRON POLYSILICON LINES, Pushkar P. Apte, Gordon Pollack, Texas Instruments Inc, Dallas, TX.
Achieving low resistivity and high thermal stability for ultrathin silicide films on sub-half-micron polysilicon lines represents a critical problem for CMOS technology scaling. The problem is compounded further at sub half-micron technology nodes, where film thicknesses of 20-30 nm are required due to shallow junction considerations for logic/DSPs, and where the silicide may undergo high-temperature processing (including source/drain anneal) for technologies like low resistivity word (LRW) lines for DRAMs. High-resistivity lines can cause RC delays severe enough to destroy the performance and density advantages gained by technology scaling, and hence, this problem must be addressed urgently. We present here a novel, effective and simple solution: namely, the use of a TiN capping layer during the TiSi formation and anneal. For narrow (0.25 0.35 m) lines and ultrathin (20 nm) Ti, the values of TiSi sheet resistance using the TiN-cap technology are ONE-THIRD to ONE-HALF of the corresponding values with the control (uncapped) RTP process. The thermal stability of the TiN-capped ultrathin films is excellent: even 950C causes no agglomeration, while agglomeration starts at 900C with the standard process. Also, the TiN-cap technology effectively lowers the thermal budget because it enables lower resistivity at lower temperatures: 85 of the TiSi film is transformed to the low-resistivity C54 phase at 850C for the TiN-cap technology, vs, only 75 even at 890C for the standard process. The TiN-cap technology is ideally suited for ease of integration and manufacturing for standard CMOS flows, because it introduces no lithography/masking or thermal or energetic-ion steps, thus ensuring that topographical, dopant and damage profiles are practically unchanged, and because it has low standard deviation. In summary, a new TiN-cap technology has been demonstrated that successfully achieves excellent performance and thermal stability for ultrathin TiSi films on sub-half-micron lines. The TiN-cap technology can be integrated easily in the standard CMOS flow and offers better control, thus presenting a manufacturable solution for a critical and urgent problem for logic/DSP and memory devices at sub-half-micron technology nodes.
SESSION F6: ANNEALING AND DEFECTS
Chair: Fred Roozeboom
Thursday Afternoon, April 3, 1997
Nob Hill B
1:30 PM *F6.1
PHYSICAL AND ELECTRICAL PROPERTIES OF DEFECTS FORMED IN RAPID THERMAL PROCESSING, Yukio Takano, Science Univ of Tokyo, Faculty of Ind Science & Tech, Chiba, JAPAN.
Rapid thermal processing of Si waters makes various kinds of defects in Si. It is well known that slip dislocations can be easily introduced when thermal distribution is not uniformed in a wafer at high temperatures, contamination impurities come from RTP instruments diffuse deeply in Si and point defects such as vacancies and interstitials which are generated at high temperatures interact with other impurities and are quenched to room temperature. In this paper, we focus on the contamination impurities and the point defects. This is because annealing time in RTP is too short for the slip dislocations to slide in a long distance and is not enough to getter the contamination impurities into the sink such as oxygen precipitates. We found that nitrogen diffused from ambient gas made deep levels when the specimen was annealed in N and quenched to room temperature. The deep levels generation was confirmed to be due to the formation of nitrogen vacancy complexes. We could control the deep level density by supplying the interstitial from growing SiO films. In addition to the deep level formation by nitrogen-vacancy complexes, deep levels induced by Cu in Si which is typical transient metals with large diffusion coefficient will be shown.
2:00 PM *F6.2
CREATION AND ANNEALING OUT MECHANISMS OF DEFECTS IN ION-IMPLANTED Si CRYSTALS INVESTIGATED BY POSITRON ANNIHILATION, Shoichiro Tanigawa, Univ of Tsukuba, Dept of Matls Science, Ibaraki, JAPAN.
Point defects in semiconductors introduced by ion implantation have been studied by using an energy-variable positron beam. In the present brief list of surface treatments, ion implantation deserves special attention for its importance in the modern semiconductor industry as a standard processing technique for producing structures with submicrometer geometrical definition. Unfortunately, ion implantation always introduces subsurface disorder. Characterization and control of the disorder is a problem whose importance is growing the more the design of integrated circuits is moving toward shallower devices. The present state of the art of technology of slow/monoenergetic positrons can successfully determine the nature and depth distribution of point defects in subsurface regions.
In the present paper, the general features of point defects induced by ion implantation will be clarified from the point of view of their dependence on a) implanted species, b) implanted target, c) ion dose, d) ion energy, e) temperature during implantation, f) thermal treatment after implantation, g) the presence of oxide overlayers, and so on. In particular, the physical meaning of the Rapid Thermal Annealing technique will be discussed on the basis of the recent observed properties of point defects through positron annihilation in Si crystals.
Positron technique is very sensitive not only to vacancy-type defects but also to oxygen atoms in Si crystals. The nature of oxygen in as-grown Si crystals in them after a variety of rapid thermal and integrated processes will be discussed on the basis of recent results of positron annihilation measurements.
2:30 PM F6.3
RAPID THERMAL PROCESS REQUIREMENTS FOR THE ANNEALING OF ULTRASHALLOW JUNCTIONS, Daniel F. Downey, Sonu Daryanani, Marylou Meloni, Marc DeRosa, Varian Associates Inc, Ion Implant Systems, Gloucester, MA; Susan B. Felch, Brian S. Lee, Varian Research Ctr, Palo Alto, CA; Steven Marcus, Jeff Gelpey, AST Elektronik USA Inc, Tempe, AZ.
Optimized and repeatable ultrashallow junctions not only require stringent temperature control and repeatability, but also tight control and reproducibility of the annealing ambient. In the annealing of boron and BF2 doped wafers, boron can diffuse from the surface as volatile compounds of boron, or be consumed into an oxide layer grown intentionally or unintentionally during the annealing stage. The control of this complicated surface chemistry is critical to optimize the ' 'retained'' boron dose in the Si substrate. It is this retained boron dose which directly affects the sheet resistance value of the junctions. In addition, the junction depth and its reproducibility can also be significantly affected by the ambient, e.g., the partial pressure of the residual oxygen. This paper addresses these issues by systematically investigating the effects of various ambients, such as N, N + O, N + NH, Ar, and others, on the sheet resistance, retained boron dose in Si and the junction depth of 2.2 keV, BF and 2.0 keV ion implanted wafers and 1.0 kV BF plasma doped (PLAD) wafers. RGA data was collected during the anneal stage to assist in identifying the complex surface chemistry responsible for the boron out diffusion. Subsequent to the anneals, ellipsometric, XPS, four-point probe resistance and SIMS measurements were performed to further elucidate the effects of the different ambients on the retained boron dose, the sheet resistance value, the RTP grown oxide layer and the junction depth. This study not only yields detailed knowledge of the surface chemistry involved in the boron dose loss, but also identifies optimum anneal conditions required to minimize the sheet resistance value for a desired junction depth.
2:45 PM F6.4
PROBLEMS WITH THE CONCEPT OF THERMAL BUDGET: EXPERIMENTAL DEMONSTRATIONS, Edmund Seebauer, Roderick Ditchfield, Univ of Illinois-Urbana, Chem Engr Dept, Urbana, IL.
Up to now, kinetic effects in rapid thermal processing (RTP) have been assessed using the concept of thermal budgets with the idea that thermal budget minimization should minimize dopant diffusion and interface degradation. This work highlights shortcomings with that principle. Experiments comparing directly the rate of Si chemical vapor deposition with that of dopant diffusion show how thermal budget minimization can actually worsen diffusion problems rather than mitigate them. We present a straightforward framework for improving the results through comparison of activation energies of the desired and undesired phenomena. This framework explains all the experimental results and provides strong kinetic arguments for continued development of rapid isothermal processing and small batch fast ramp methods.
3:00 PM F6.5
DEEP DIFFUSIONS AND SOI LAYERS PRODUCED BY RAPID THERMAL PROCESSING FOR SMART POWER APPLICATIONS, Jean-Marie Dilhac, Laurent Cornibert, Christian Ganibal, CNRS, LAAS, Toulouse, FRANCE.
Power devices often contain very deep boron diffusions extending through the thickness of the wafer to create junction isolation. However, these junctions are about twice as wide as their depth, and require days in furnaces at very high temperature. These annealings may therefore induce crystal defects and wafer warpage. In this paper we first report our investigations to replace this standard solid-state deep diffusion, with Temperature-Gradient Zone Melting (TGZM). During TGZM, a molten silicon/aluminium solution moves through a Si wafer in minutes, leaving a highly Al doped trail behind it. The liquid phase diffusion is driven by the vertical thermal gradient created in the wafer by a properly designed RTP. Because of an increasing demand, cost and availability of full silicon on insulator (SOI) substrates are no longer a problem for the VLSI domain. However, for the purpose of high voltage (> 400V) smart power applications, substrates with localised and thick SOI layers are needed because the power device is generally vertical and needs then to be embedded into a bulk substrate, whereas the low voltage circuitry has to be dielectrically isolated. However, the existing techniques are expensive while yield has still to be improved. Moreover, SOI wafers with local oxide layers are not commercially available. We then present a method for recrystallization of thick polysilicon films by Lateral Epitaxial Growth over Oxide (LEGO) to fabricate substrates with localised SOI layers. While similar to classical Zone Melting Recrystallisation (ZMR), this method avoids any horizontal thermal gradient in the solid phase and therefore produces less defects, while allowing the formation of much thicker films than in any other melt-based technique. The two processes, that is LEGO and TGZM, use a Rapid Thermal Processor (RTP) and are compatible. The RTP is specially designed to create a thermal gradient perpendicular to the wafer surface.
3:45 PM F6.6
NEAR AND SUB-KEV BORON IMPLANTATION AND RAPID THERMAL ANNEALING: A SIMS AND TEM STUDY, Michael I. Current, Applied Materials Inc, Implant Div, Austin, TX; Majeed A. Foad, Univ of Salford, Joule Lab, Salford, UNITED KINGDOM; Jon England, Applied Materials Inc, Horsham, UNITED KINGDOM; David Lopes, Applied Materials Inc, RTP Div, Santa Clara, CA; Clive Jones, David Hung-I Su, Philips Semiconductors, Materials Analysis Group, Sunnyvale, CA.
SIMS and cross-section TEM were used to determine the vertical and lateral junction profiles for Boron implants at a dose of 10 B/cm over an energy range of 0.2 to 10 keV. RTP anneals were done over a temperature range of 900 and 1050C for a soak time of 20 s. Among the unusual features of this study was the use of a differential lens technology to provide beam currents of a milli-amp or more, even in the deep sub-keV energy regime, providing a first look at profile and damage accumulation effects at low energies, with high beam flux densities and rapid thermal cycling. This study provides encouraging evidence that implantation and RTP techniques can be directly extended into the sub-keV ion energies and short thermal cycles required of 1Gb devices and beyond.
4:00 PM F6.7
A REVERSIBLE EFFECT OF RAPID THERMAL ANNEALING OF INDIUM IN ION IMPLANTED SILICON, Leonid Krasnobaev, Jerome. J. Cuomo, North Carolina State Univ, Dept of MS&E, Raleigh, NC.
N-type Silicon wafers were implanted with Indium ions at close to the equilibrium solubility. Following implantation, both sides of the wafer were annealed in succession using Rapid Thermal Annealing. The sheet resistance of the implanted layer was reduced by front side annealing. However, the sheet resistance of this layer was increased by subsequent annealing with the back side facing toward the halogen lamp. Furthermore, the sheet resistance decreased again following a second irradiation of the front surface. These resistance changes were reproducible over several tens of cycles of annealing. The explanation of this phenomena is discussed.
SESSION F7: DIELECTRICS - 1
Chair: John Kuehne
Thursday Afternoon, April 3, 1997
Nob Hill B
4:15 PM *F7.1
LOW TEMPERATURE Si OXIDATION WITH EXCIMER LAMP SOURCES, Ian W. Boyd, Univ College London, Dept of E&EE, London, UNITED KINGDOM.
Intense ultraviolet light can be generated using dielectric barrier discharges to form excimer mixtures of rare gases and rare gas-halides. The emission spectra of the excimers formed are typically narrow-band (5-15 nm) and centered at a fixed wavelength in the ultraviolet which, depending upon the gas mixture, can be from 126 to 354 nm. Such radiation is clearly potentially useful for thin film and surface processing. The underlying operating mechanisms of these relatively novel sources whose conversion efficiencies (from input electrical to output optical energy) can be as high as 15 under optimum conditions will be described. These systems provide a low-cost high power and large area alternative to conventional Hg arc discharge UV lamps for industrial large-scale UV processes. This paper will discuss their application toward the low temperature (C) growth of oxides on silicon where reaction rates of nearly 2 orders of magnitude over the traditional thermal rates have been obtained and the fastest light-induced solid-state Si oxidation process yet achieved is reported. The structural and electrical properties of the layers grown will also be described.
4:45 PM F7.2
ULTRA LOW THERMAL BUDGET RAPID THERMAL PROCESSING FOR THIN GATE OXIDE DIELECTRICS: REDUCTION OF SUBOXIDE TRANSISITION REGIONS IN LOW TEMPERATURE PROCESSED Si/SiO STRUCTURES BY A 900DEGC 30 S RAPIDTHERMAL ANNEAL, Gerald Lucovsky, Bruce R. Hinds, North Carolina State Univ, Dept of Physics, Raleigh, NC.
Device-quality gate oxides with nitrided interfaces have been prepared by 300degC plasma-assisted oxidation and thin film deposition followed by a low thermal budget rapid thermal anneal (RTA) (30 s at 900degC). Interfacial bonding has been studied by optical second harmonic generation (SHG) and X-ray photoelectron spectroscopy (XPS). In addition, the temperature stability of bulk silicon suboxides (SiO) has been studied by photoluminescence (PL) and infrared absorption. Si-SiO interfaces formed below 800degC by display essentially the same interfacial SHG resonance energies. Annealing for 30 s at 900degC produces significant changes including different resonances for O- or N-terminated interfaces. After the same RTA, XPS on interfaces formed by 700degC thermal oxidation show factor of 2-3 decrease in Si 2p features associated with SiO bonding. 1.4 to 2.0 eV PL from bulk SiO and ambient-oxidized Si-nanocrystals is essentially the same leading to an assignment of THIS SPECTRAL COMPONENT of Si nanocrystal PL to interfacial SiO regions. Bulk film PL is reduced below minimum detection following a 30 s 900degC RTA which produces phase separation into Si nanocrystals and SiO. The absence of PL after the RTA indicates an absence of SIGNIFICANT SiO transition regions at the nanocrystal/ SiO interfaces. Combining results from optical SHG and XPS on Si/ SiO interfaces with the PL from bulk SiO explains changes in SHG resonance energy as being brought about by reductions in suboxide bonding. The same bonding changes also explain a reduction of defects at Si/ SiO interfaces after similar RTAs. The conclusion is that device quality oxides can be prepared by low temperature (e.g., 300degC) interface oxidation/nitridation and thin film deposition, provided that these steps are followed by a low thermal budget RTA or equivalent thermal exposure (e.g., 30 s at 900degC). Supported by ONR, NSF and SRC
5:00 PM F7.3
UNIFORM ULTRA-THIN OXIDES GROWN BY RAPID THERMAL OXIDATION OF SILICON IN NO, Guangcia Xing, Applied Materials Inc, RPT Div, Santa Clara, CA; David Lopes, Applied Materials Inc, RTP Div, Santa Clara, CA; Gary Miner, Applied Materials Inc, Thermal Process & Implant Div, Santa Clara, CA.
Rapid thermal oxidation of silicon in NO ambient has the merit of improving ultra-thin oxide integrity and device reliability for sub-micron ULSI applications due to nitrogen incorporation in the oxides. However, thickness and compositional uniformities usually degrade when the oxides are grown in NO as compared to the oxides grown in O because of the more complex chemistry in NO oxidation process. Although uniform oxides have been reported in experiments by using low pressure NO oxidation or mixtures of NO and O, such processes usually suffer from lower growth rate and/or relatively low nitrogen incorporation. In this paper, we report the study of rapid thermal oxidation of silicon in NO ambient by using RTP Centura rapid thermal processor, and the NO oxide thickness and compositional uniformities with respect to gas flow rate and wafer rotation speed as well as other process parameters. We found that NO oxide uniformity is strongly dependent on gas flow rate and wafer rotation speed in addition to process pressure. With proper setting of the process parameters, excellent oxidation uniformities (one sigma <1) were obtained at atmospheric pressure NO ambient. Nitrogen concentrations of such uniform oxides grown at 1050C atmospheric pressure NO oxidation processes were 1.7 for 40 oxide and 2.5 for 60 oxide, respectively, as characterized by SIMS analysis. In addition, processes on rapid thermal oxidation in mixture of NO and O will also be discussed.
SESSION F8: DIELECTRICS - 2
Chair: Shuichi Saito
Friday Morning, April 4, 1997
Nob Hill B
8:30 AM *F8.1
ENABLING THERMAL PROCESSING OF HIGH AND LOW DIELECTRIC CONSTANT MATERIALS, Randhir P.S. Thakur, S. DeBoer, Micron Technology, Boise, ID; Rajendra Singh, Clemson Univ, Dept of E&CE, Clemson, SC.
The focus of ultralarge scale integration (ULSI) electronics is shifting rapidly towards the development and integration of various low and high dielectric constant materials. Memory manufacturers are driving the quest for integration-friendly, high dielectric constant materials, while logic makers are seeking materials with lowest dielectric constant to use as interlayer dielectric for their multilayer backend needs. Both categories of materials need the highest reliability, integratability, and manufacturability in the current and upcoming real world. Strong development emphasis in improving the structural aspects of these materials is needed now more than ever before both in university laboratories and industrial R&D. An intense focus on these materials demands immediate, improved, and innovative process solutions. One key process area is the thermal engineering/processing of these materials and hence is the focus of this paper. In this paper, we present recent results from both university and industry process development work. We compare and contrast the thermal process requirements of some enabling materials with dielectric constants ranging from 2 to 30. The examples in our study encompass materials such as teflon, boron nitride, oxynitrides, cell nitrides, and tantalum pentoxide. The enhancements in the structural and electrical performance of these materials as a function of thermal cycles used either for deposition or annealing is demonstrated through various examples.
9:00 AM F8.2
RAPID THERMAL NITRIDATION OF Si IN N, Martin L. Green, Tom W. Sorsch, Bell Labs, Lucent Technologies, Murray Hill, NJ; Leonard C. Feldman, Vanderbilt Univ, Dept of Physics & Astronomy, Nashville, TN; William Lennard, Univ of Western Ontario, Dept of Phyics, London, CANADA.
We have found that Si can react with N in a rapid thermal processing chamber, at moderate temperatures (850-1050C). This finding is inconsistent with the widely held belief that N is inert to Si in this temperature range. In fact, more N is incorporated into silicon oxynitride (SiON forms due to Si reaction not only with N, but with oxidant impurities such as HO and O as well) using N than with NO, for identical temperatures and times. For example, 6 x 10 N/cm are incorporated in a 10 nm NO-oxide grown at 950. Using N under the same conditions, to prenitridize the Si, 1.9 x 10 N/cm are incorporated. Furthermore, the amount of N is seen to increase with increasing temperature and N exposure time.
After nitridation in N, the layer can be further reoxidized to form dielectrics of useful thicknesses. When the prenitridation time at 950C is varied from zero to five minutes, final dielectric thickness (after reoxidation at 1000C) is decreased from 6 to 2.2 nm, due to retardation of the oxidation kinetics by the N. The Si/dielectric interface of these samples has been examined by AFM, and found to be identically smooth compared to the pure Si/SiO case. At the presentation, we will discuss the electrical properties of these dielectrics, as well as the effects of gas phase impurities on the reaction of Si with N.
9:15 AM F8.3
NITRIC OXIDE RAPID THERMAL NITRIDATION OF THIN GATE OXIDES, John Kuehne, Texas Instruments Inc, Semiconductor Process & Device Ctr, Dallas, TX; Sunil Hattangady, Texas Instruments Inc, Dallas, TX; Joe Piccirillo, Applied Materials Inc, Dallas, TX; Guangcia Xing, Applied Materials Inc, RPT Div, Santa Clara, CA; Gary Miner, Applied Materials Inc, Thermal Process & Implant Div, Santa Clara, CA.
Nitric oxide rapid thermal nitridation of thin gate insulators was investigated. 25 to 55 angstrom gate oxides were grown in an Applied Materials RTP chamber and subsequently nitrided using nitric oxide gas (NO) in the same chamber. A linear designed experiment was carried out to evaluate nitrogen incorporation and film thickness growth during NO nitridation. Process temperature ranged from 900 deg. C to 1100 deg. C. Process times ranged from 15 sec. to 120 sec. SIMS analysis of the samples showed nitrogen peaked at the oxide silicon interface. The variables which affected the peak nitrogen incorporation were in descending order of importance: temperature, process time, initial oxide thickness, and NO flow rate. Peak concentrations ranged from 1 atomic peak for 900 deg. C, 15 sec., 55 angstrom initial oxide thickness to 9 atomic peak for 1100 deg C, 120 sec., 25 angstrom initial oxide thickness.. Oxide growth during nitridation ranged from 2 angstroms to 11 angstroms. Oxide thickness uniformity was not degraded by nitridation. Rapid thermal reoxidation kinetics of the nitrided films were characterized as a function of nitrogen incorporation and reoxidation temperature. At 1000C, the rate decreases by a factor of 4.6 when going from 3 atomic to 9 atomic nitrogen. The process chamber was monitored for corrosion using visual inspection and MCLT and SPV iron test wafers. No degradation was observed. The controllability, uniformity and high nitrogen incorporation of rapid thermal NO nitridation make it an attractive process for deep sub-micron gate insulators.
9:30 AM F8.4
EXTENDING THE USE OF NO DIELECTRICS FOR DRAM BY ULTRATHIN SILICON NITRIDE RTCVD WITH IN SITU AMMONIA AND HYDROGEN PREDEPOSITION SURFACE CONDITIONING, Paul A. Tiner, Aditi Banerjee, Malcolm J. Bevan, Clark D. Johnston, Rajesh B. Khamankar, Michael F. Pas, Katherine E. Violette, Rick L. Wise, Texas Instruments Inc, Semiconductor Process & Device Center, Dallas, TX.
The use of thin nitride/oxide (NO) stacked dielectrics is common in DRAM storage node structures today. The cell capacitance can be increased without increasing the cell plate area by decreasing the thickness of the dielectric. Combinations of novel storage node structures, textured electrode surfaces, and very thin NO films (equivalent oxide thickness equal <30 Angstroms) are being characterized for use in 256 Mb and 1 Gb DRAM devices as an alternative to premature use of high k dielectric materials. However, the native oxide formed on the surface of the polysilicon bottom electrode prior to dielectric nitride deposition in a standard LPCVD furnace reactor causes the leakage current and reliability properties of the dielectric to degrade for very thin films. Using a vacuum load-locked RTCVD single-wafer reactor with appropriate in situ ammonia and hydrogen predeposition surface conditioning, the native oxide can be eliminated and very thin nitride films of much higher quality can be deposited. A comparison between standard batch LPCVD processing and single-wafer RTCVD for silicon nitride deposition has been done and electrical characteristics (including leakage current and time dependent dielectric breakdown) of the films have been measured. These results indicate that use of NO dielectric films may be extended 1-2 more generations of DRAM devices. This will allow more time for improving the quality of high k dielectric films.
SESSION F9: RTP OF III-V MATERIALS AND OTHER NOVEL APPLICATIONS
Chair: Paul J. Timans
Friday Morning, April 4, 1997
Nob Hill B
10:15 AM *F9.1
SURFACE PASSIVATION OF III-V SEMICONDUCTORS BY MEANS OF INTEGRATED PROCESSING, L. S. How Kee Chun, B. Lescaut, J. L. Courant, Yves I. Nissim, France Telecom, CNET Lab de Bagneux, Bagneux, FRANCE.
For a long time, the passivation of III-V semiconductor surfaces has been a limiting factor for device performances. The development of integrated processes has brought new insights to this problem. The cleaning procedure of the surface that is required for passivation has to be followed up in-situ by an encapsulation step in order to obtain stable and reproducible results. In this presentation, we will make a review, as well as present some new results, of the work that has been carried out on III-V devices including MISFET, HBT, HEMT, and photodetectors. The cleaning process is either a DECR surface treatment or a UV induced surface reduction. The chemistry used is hydrogen, ammonia, or xenon fluoride. The encapsulation is a silicon based dielectric film that is deposited by UV or RT CVD. Among all these choices a comprehensive analysis is made to offer the best passivation scheme for each of those specific devices.
10:45 AM F9.2
A GENERALIZED MODEL OF BERYLLIUM DIFFUSION IN InGaAs EPITAXIAL STRUCTURES UNDER POINT DEFECT NONEQUILIBRIUM CONDITIONS, Serge Koumetz, Sylvestre Gautier, Jerome Marcon, Kaouther Ketata, Mohamed Ketata, INSA de Rouen, LCIA, Mont Saint Aignan, FRANCE; Patrick Launay, CNET-PAB.
A high p-type base doping level is necessary in InGaAs/InP Heterojunction Bipolar Transistors (HBTs) to achieve high device performances. However, this requires to control the base dopant diffusion during the epitaxial growth and the post-growth technological processes. The subject of this work is the modeling of Be diffusion during post-growth Rapid Thermal Annealing (RTA) of InGaAs epitaxial layers grown by Chemical Beam Epitaxy (CBE) and Gas Source Molecular Beam Epitaxy (GSMBE). To characterize the Be depth profiles, Secondary Ion Mass Spectrometry (SIMS) has been used. To explain the observed concentration profiles and related diffusion mechanisms, a General Substitutional-Interstitial Diffusion model is proposed. A simultaneous diffusion by Dissociative and Kick-out mechanisms under point defect nonequilibrium is suggested. Taking into account Fermi-level and electric build-in field effects, the obtained differential equation system has been solved numerically by finite-difference explicit scheme. Good agreements have been obtained between experimental depth profiles and simulated curves.
11:00 AM F9.3
RAPID THERMAL PROCESSING OF III-NITRIDES, Jin Hong, Jewon Lee, Cathy B. Vartuli, John Devin MacKenzie, Sean M. Donovan, Cammy R. Abernathy, R. V. Crockett, Stephen J. Pearton, Univ of Florida, Dept of MS&E, Gainesville, FL; John C. Zolper, Sandia National Laboratories, Albuquerque, NM; Fan Ren, Bell Labs, Lucent Technologies, Murray Hill, NJ.
Transient thermal processing is employed for implant activation, contact alloying, implant isolation and dehydrogenation during III- nitride device fabrication. We have compared use of InN, AlN and GaN powder as methods for providing a N overpressure within a graphite susceptor for high temperature annealing of GaN, InN, AlN and InAlN. The AlN powder provides adequate surface protection to temperatures of 1100C for AlN, 1050C for GaN, 600C for InN and 800C for the ternary alloy. While the InN powder provides a higher N2 partial pressure than AlN powder, at temperatures above 750C the evaporation of In is sufficiently high to produce condensation of In droplets on the surfaces of the annealed samples. GaN powder is expected to achieve better surface protection than the other two cases.
11:15 AM F9.4
DEEP LEVEL INVESTIGATION IN Si-GaAs BY RAPID THERMAL ANNEALING, Zhou-Yin Zhao, Nanjing Electronic Devices Inst, Dept of Materials Research, Nanjing, CHINA; Feng-Mei Wu, Nanjing Univ, Ctr of Materials Analysis, Nanjing, CHINA; Ying Zhang, Nanjing Tongmei Machinery Ltd Co, Nanjing, CHINA.
Deep levels in undoped LEC semi-insulating (SI) GaAs have been investigated by rapid thermal annealing (RTA). The GaAs wafers were annealed for 10 sec in N atmosphere at temperatures ranging from 500 to 900C. Using photo-induced current transient spectroscopy (PICTS) and Hall measurement, we have investigated the behavior of various deep levels as a function of RTA temperature and the phenomenon of thermal conversion. The change and even inversion in resistivity is related not only to decrease of the EL2 and EL6 defects, but also to shallow acceptor caused by arsenic-escaping in the surface of the wafer. Choosing proper RTA temperature, the electrical properties of SI-GaAs after RTA will be improved.
11:30 AM F9.5
GROWTH AND NITRIDATION OF SILICON-DIOXIDE FILMS ON SILICON-CARBIDE, H. Barry Harrison, Sima Dimitrijev, Hui-feng Li, Dennis Sweatman, Griffith Univ, School of Microelectronic Engr, Brisbane, AUSTRALIA; Philip Tanner, Griffith Univ, School of Microelectronics Engr, Nathan Queensland, AUSTRAILIA.
Successful growth of silicon-dioxide films on silicon-carbide substrates may mark the beginning of a new era in semiconductor electronics. Metal oxide-semiconductor (MOS) devices based on a wide bandgap material such as silicon carbide have the potential to revolutionize power electronics, microwave systems, high-temperature and many other applications.
At present, high quality oxide films can be grown on N-type, but on P-type SiC. Searching for the solution to this problem, it was initially speculated that the aluminium (used as the P-type dopant in SiC) was adversely affecting the interface. Later, it was shown that boron-doped P-type SiC does not improve the quality of the interface, and that aluminium is also present in high-quality oxides grown on N-type SiC.
We have recently presented results which shift the focus from the potential problems with the P-type SiC to the beneficial role of nitrogen. used as a dopant in the N-type SiC. The very first results on nitridation of oxides grown on SiC show beneficial effects of NO nitridation but, somewhat surprisingly, detrimental effect of N0 nitridation. We found that NO nitridation significantly improved the high-frequency C-V curve of oxides grown on P-type SiC, and reduced the density of slow traps in the case of oxides grown on N-type SiC. As opposed to these effects, NO nitridation deteriorated the HF C-V curve of P-type oxides, and significantly increased the slow-trap density of N-type oxides.
11:45 AM F9.6
GRAIN ENHANCEMENT OF THIN SILICON LAYERS USING OPTICAL PROCESSING, Bhushan L. Sopori, National Renewable Energy Laboratory, Golden, CO.
Thin-film silicon solar cells (thickness < ''absorption depth'') can yield high efficiencies even when the material quality is not very high. However, a reduced cell thickness must be compensated for by an effective light-trapping to enhance the absorption of the incident solar spectrum. Although the requirements on the material quality are less stringent, the minority carrier diffusion length should be about twice the film thickness, and the typical grain size should be much greater than the film thickness. The cell design and device processing should be compatible with low-temperature processing.
These requirements put a lot of restrictions on the cell design, structure, and fabrication processes. The low-cost requirement necessitates using a substrate-like low-grade glass, which has a softening point of about 500C. In addition, low-quality substrates can have impurities that can diffuse into the silicon film and degrade its quality. Because of these restrictions, the cell processing temperatures must be significantly lower than those used in conventional silicon processing. We describe a technique that produces large-grain silicon thin films at low temperatures, in a manner that is compatible with the use of low-cost glass substrates. The grain enhancement is produced by using vacancy injection and optical illumination.
12:00 NOON F9.7
EXPLOITATION OF QUANTUM PHOTOEFFECTS IN REDUCING MICROSCOPIC DEFECTS AND PROCESSING CYCLETIME IN ADVANCED RAPID THERMAL PROCESSING, Lakshmemson, SC.
Rapid thermal processing is fast i Vedula, Veena Vedagarbha, Deepa Ratakonda, Rajendra Singh, Clemson Univ, Dept of E&CE, Clemerging as a vital low thermal budget processing technique. Use of photons of wavelengths less than 800 nm in conjunction with infrared and visible photons in RTP resulted in the reduction of microscopic defects and processing cycletime. Recently we have studied the role of quantum photoeffects in processes like metallization and diffusion.
For the first time, the role of quantum photoeffects in metallization process was studied. Screen printed ohmic contacts which are an integral part of solar cells were processed and schottky barrier diodes were made. Cycletime was reduced from 162 secs to 122 secs. The films were characterized extensively, and a significant improvement was observed in terms of contact resistance, minority carrier lifetime, diode performance, surface roughness and quality of the interface. For instance, the surface roughness varied from 562 nm to 189 nm depending upon the amount of photons reaching the interface.
Additionally the study of diffusion process has shown the effect of VUV photons on the sheet resistance, stress, concentration profiles and bulk minority carrier lifetime. All the properties have improved considerably when the photons were directly incident on the Si-PSG interface. Exploiting the quantum photoeffects, experiments were designed to do double diffusion in a single step which lead to the reduction of mask levels. Most recent experimental results and qualitaive explanation for the observed resluts will be discussed in this paper.