Meetings & Events

 

spring 1997 logo1997 MRS Spring Meeting & Exhibit

March 31 - April 4, 1997 | San Francisco
Meeting Chairs: Linda G. Griffith-Cima, David J. Eaglesham, Alexander H. King

Symposium K—Multilevel Metal Process Integration

Chairs

Girish Dixit, Texas Instruments Inc
Robert Fiordalice, Motorola Inc
Roderick Mosely, Applied Materials Inc

In sessions below "*" indicates an invited paper.

SESSION K1: BARRIERS 
Chair: Girish A. Dixit
Tuesday Morning, April 1, 1997
Salon 3

8:30 AM *K1.1 
PROCESS TECHNOLOGY AND INTEGRATION CHALLENGES FOR HIGH PERFORMANCE INTERCONNECTS, Gurtej Sandhu, Micron Technology, R&D, Boise, ID.

Interconnect metallization for 0.18 m technology presents many new challenges for the process technologies. The DRAM device architecture imposes severe requirements of shallow junctions and narrow line widths which combine to put constraints on the thermal budget while requiring low RC time constant for the interconnects. A number of new materials such as TiSi, TiN, W, WN, Pt are under consideration for interconnect and capacitor plate metallization. These materials need to provide low resistance lines, be thermally stable, have no deleterious effects on the gate oxide and capacitor dielectric, and must be compatible with the overall process flow. Deposition processes for interconnect materials as well as interlevel dielectrics with superior conformality are necessary for a complete fill without voids. A review of the requirements for a manufacturable interconnect scheme and limitations of the current technology will be presented.

9:00 AM K1.2 
PROPERTIES OF W-Si-N FILMS DEPOSITED BY LOW TEMPERATURE CHEMICAL VAPOR DEPOSITION, James G. Fleming, Paul Martin Smith, Jonathan S. Custer, Elizabeth Rotherty-Osmun, Sandia National Laboratories, Dept 1323, Albuquerque, NM; Yong-Dal Kim, California Inst of Technology, Dept of Applied Physics, Pasadena, CA; Thorsten Kacsich, California Inst of Technology, Dept of Physics, Pasadena, CA; Mark A. Nicolet, California Inst of Technology, Dept of Applied Physics, Pasadena, CA.

Current diffusion barrier technologies may not meet the challenges posed by future interconnect systems. We have previously reported on the chemical vapor deposition of W-Si-N from a gas mixture of WF, NH and SiH. The wafer temperature is less than 350C In this work we report on the properties of films with a composition of roughly WSiN. The resistivity of these films is cm. As deposited they are TEM amorphous, a highly desirable characteristic for a diffusion barrier. These films demonstrate excellent barrier properties; a 1000 thick film is an effective barrier to Cu up to a temperature of 700C The time at temperature in vacuum was 30 minutes and the tests were performed on large area diodes. In general, the properties of these materials, deposited by chemical vapor deposition, are remarkably similar to those reported for reactively sputtered films. The major advantage of the chemical vapor deposition process is 100 step coverage on test structures with an aspect ratio of 4 and an opening of 0.25 m. The excellent step coverage and barrier properties of these films make them extremely promising candidates for future diffusion barrier applications.

9:15 AM K1.3 
MATERIAL CHARACTERIZATION OF TITANIUM AND TITANIUM-NITRIDE FILMS FORMED BY ION METAL PLASMA DEPOSITION, Simon Hui, Ken Ngan, Murali Narasimhan, Sesh Ramaswami, Applied Materials Inc, PVD Division, Santa Clara, CA.

Ion Metal Plasma (IMP) deposition from ionized magnetron sputtering discharge has been reviewed in the literature. The process is based on conventional magnetron sputtering with the addition of a higher density inductively coupled RF plasma between the sputtering cathode and the substrate. Metal atoms sputtered from the cathode due to inert gas ion bombardment transit the RF plasma and become ionized. The metal ions can then be accelerated to the substrate by means of a low voltage DC bias. In addition to enhancing step coverage of metal films such as Ti and TiN, this process also has significant effects on material properties. In this paper, material properties such as resistivity, crystal orientation, surface roughness, atomic composition, and stress of the IMP Ti and TiN films have been examined and compared to conventional PVD Ti and TiN films. In addition, the effects of various process parameters such as pressure, sputter power, RF inductive power, and the bias power have been investigated. There are clear differences in resistivity, surface roughness, stress, and crystal orientation between the films deposited under various process conditions. Also, good correlation among various material properties, such as resistivity vs. crystal orientation, has been established.

9:30 AM K1.4 
MOCVD OF TiN AND/OR Ti FROM NEW PRECURSORS, Hyun-Koock Shin, H-J Shin, Ultra Pure Chemical Inc, MOCVD Dept, Suwon, SOUTH KOREA; Y.-H. Cho, Ultra Pure Chemical Inc, Suwon, SOUTH KOREA; Jae-Gab Lee, Kookmin Univ, Dept of Metallurgical Engr, Seoul, SOUTH KOREA; Jong-Tae Baek, ETRI, Semiconductor Div, Daejeon, SOUTH KOREA; H.-J. Yoo, ETRI, Taejon, SOUTH KOREA.

Possible application of Ti/TiN film in microelectronics industry includes its use as an excellent barrier material for Al planarization gap filling of contacts and vias, and as an adhesion and nucleation layer for chemical vapor deposition blanket tungsten deposition. The TiN or Ti CVD was reported from a number of different inorganic and organic titanium compounds including TiCl, TiL, and Ti(NR), where R = Me and Et, complexes. 
As a part of our studies of the synthesis of noble precursors for metal or metal nitride CVD, we recently prepared new titanium compounds TiL and TiLL. The goal of the work described here is to explore new compounds for titanium or titanium nitride CVD. These species were characterized, and CVD from these was attempted. New compounds are yellow or yellow-orange liquids at room temperature and exhibit high vapor pressures at its boiling temperature. 
CVD of titanium nitride from TiL without using ammonia reactant gas was carried out onto Si under conditions where the growth temperature was varied over the range of 230C to 300C, with the precursor temperature kept at 65C. In general, the step coverage for the films deposited over this temperature region was fairly similar 90 in 0.4 m contacts. TiN growth rate was in the range of 50 to 1550 /min, depending on the deposition temperature. Noted that the use of new precursor lowered carbon content significantly 18 at, while that of Ti(NR) yielded 30 at C in the film. CVD of Ti and TiN was also attempted from TiLL compound.

9:45 AM K1.5 
TiN PREPARED BY PLASMA SOURCE ION IMPLANTATION OF NITROGEN INTO Ti AS DIFFUSION BARRIER FOR Si/Cu METALLIZATION, Wei Wang, John Booske, Leon Shohet, Henley Liu, Steve Gearhart, Univ of Wisconsin-Madison, Engr Research Center, Madison, WI; Steve Bedell, Bill Lanford, SUNY-Albany, Dept of Physics, Albany, NY.

TiN films were prepared by using plasma source ion implantation (PSII) of nitrogen into 1000 A Ti deposited on Si substrates. The PSII processes utilized a dose of 1 x 10N/cm and peak voltages of -10, -15 and -20 kV. The properties of these TiN films as diffusion barbers between Cu and Si were investigated by annealing Cu(2000A)TiN/Si films in vacuum from 500C to 700C, and by analyzing with four-point probe sheet resistance measurements, Rutherford back scattering spectrometry (RBS), Auger electron spectroscopy (AES), scanning elecl:ron microscopy (SEM) and glancing angle x-ray diffraction. 
No diffusion of Cu into TiN was observed from RBS and AES after annealing at 550C for 30 min. indicating negligible reaction between Cu and TiN at the interface. The sheet resistances were changed for the films where the TiN were implanted at -15 and -20 kV, but it increased about 5 for the film where the TiN was implanted at -lO kV. When this latter film was annealed at 600C for 30 min, Cu diffused into the TiN films. However, the TiN films implanted at higher voltages of -15 and -20 kV showed no sign of diffusion barrier degradation. Upon annealing at 700C for 2 min and 600C for 28 min., RBS showed some Cu diffusion into the TiN film implanted at -15 kV. However, the TiN film implanted at -20 kV was stable and free of CuTiN omterdoffisopm, even for this high thermal budget anneal.

10:30 AM K1.6 
CVD TiN FOR APPLICATIONS AS BARRIER LAYER/ADHESION PROMOTER IN ULSI APPLICATIONS, Cheryl Faltermeier, Cindy Goldberg, Michael Jones, Allan Upham, Alain E. Kaloyeros, SUNY-Albany, Dept of Physics, Albany, NY.

The continuous decrease in device sizes requires barrier layers in chip metallization to provide increased reliability at decreasing thIcknesses. This paper discusses the development of a low-temperature () thermal CVD process, which employs TiI and NH to grow ultrathin TiN layers () with the performance needed for incorporation in the 0.18 m device generation and beyond. In particular, results are presented from studies of: (a) precursor decomposition pathways and associated activation energies; (b) the effects of critical process parameters on the composition, resistivity, structure, step coverage, and barrier integrity of the TiN thus grown; and (c) a systematic study which employed AFM, SEM, TEM, AES, and XRD to compare the characteristics of our CVD-grown versus PVD and MOCVD deposited TiN in 0.35 m device structures.

10:45 AM K1.7 
IONIZED PHYSICAL VAPOR DEPOSITION OF TITANIUM AND TITANIUM NITRIDE, Praburam Gopalraja, Yoichiro Tanaka, Kent Tanimoto, John Forster, Applied Materials Inc, Santa Clara, CA; Zheng Xu, Applied Materials Inc, PVD Products Business Group, Santa Clara, CA.

The trend towards smaller dimensions in microelectronic devices has sparked interest in a new type of sputter technology, commonly referred to as ionized metal plasma (IMP) deposition. This technology relies on ionizing the sputtered material with a plasma generated between the target and substrate, usually by radio frequency inductive coupling. Application of bias to the substrate allows for control of the ion bombardment energy. Introduction of this new technology into semiconductor fabrication requires an understanding of how the available process variables influence film properties. This paper will present how various process variables, including sputter power, RF inductive power, pressure, and bias voltage, influence film properties such as deposition rate, resistivity, stress, uniformity, and step coverage, for both titanium and reactively sputtered titanium nitride (TiN) films. For example, in the case of titanium and TiN, the deposition rate follows a fairly simple scaling with DC power, RF power, and pressure. Other variables, such as stress and bottom coverage are a result of more complex interactions. In the case of reactively sputtered TiN, an additional process control variable is the nitrogen partial pressure. The nitrogen partial pressure has a strong effect on resistivity, and a weaker influence upon deposition rate. The bias voltage and the RF power have a strong influence on crystal orientation of the deposited film. The above scalings, influences and effects will be discussed in context with the physical processes occurring in the plasma and at the substrate surface.

11:00 AM K1.8 
CHEMICAL BONDING AT METAL GATE - SiO INTERFACES, Bruce B. Claflin, Gerald Lucovsky, North Carolina State Univ, Dept of Physics, Raleigh, NC.

The high packing density of ULSI devices imposes demanding performance requirements on gate electrode materials to maintain proper scaling behavior. Metals and metal alloys such as titanium nitride (TiN) are promising gate electrode candidates, either as single layers or as part of a multi-layer metal gate stack [1,2]. However, several technological and material science challenges must be addressed before metallic films can replace heavily doped polycrystalline silicon (poly-Si) as the material of choice for gate electrodes. Of particular importance are interface properties such as diffusion and thermal stability against chemical reaction with the gate dielectric [3,4] during processing steps that follow the gate metal deposition. We use Auger electron spectroscopy (AES) to investigate the bonding and chemical reactivity at the interface between reactive sputtered TiN films and SiO before and after various rapid thermal annealing (RTA) cycles. We also examine the effect on the properties and performance of the interface associated with the introduction of an ultra-thin silicon nitride (SiN) top dielectric layer as a diffusion/reaction barrier.

11:15 AM K1.9 
THERMAL STABILITY OFAl/BARRIER/TiSi AND Al/BARRIER/SiO MULTILAYER STRUCTURES, Jiong-Ping Lu, Wei-Yung Hsu, Texas Instruments Inc, Semiconductor Process & Device Ctr, Dallas, TX; Qi-Zhong Hong, Texas Instruments Inc, Semiconductor Process & Device Center, Dallas, TX; Girish A. Dixit, Texas Instruments Inc, Semiconductor Process & Device Ctr, Dallas, TX; J. D. Luttmer, Texas Instruments Inc, Semiconductor Process & Device Center, Dallas, TX; Robert H. Havemann, Texas Instruments Inc, Semiconductor Process & Device Ctr, Dallas, TX; P. J. Chen, H. L. Tsai, Texas Instruments Inc, Materials Science Lab, Dallas, TX.

The application of Al-plug at contact level poses severe challenges for barrier materials due to problems with Al junction spiking. Although Al plug technology offers lower cost, lower resistivity, extendibility to smaller geometry, and better EM performance over W-plug technology, it is not used in large scale production partially due to the lack of high quality contact barrier films. In this talk, investigations of two different types of barriers are reported. These barriers are TiN films prepared by physical vapor deposition (PVD), and TiN films prepared by metal-organic chemical vapor deposition (MOCVD) and post-deposition anneal in silane. Al/barrier/TiSi and Al/barrier/SiO multilayer structures were used as physical models for the bottom and side wall of Al-plugs, respectively. PVD TiN films were prepared by reactive sputtering of Ti in nitrogen. MOCVD TiN-based films were deposited by thermal decomposition of tetrakis(dimethylamino)-titanium precursor. Since the MOCVD films are unstable in air, an in-situ silane anneal was performed to stabilize the films. Four-point probe, diode leakage current, and scanning electron microscopy cross-section analyses were used to characterize the thermal stability of the multilayer structures. Chemical and structural differences of the two barrier systems were examined by secondary ion mass spectrometry, Rutherford back scattering, and transmission electron microscopy. Experimental results show that silane-treated MOCVD films have superior thermal stability to the PVD films and serve as good contact barriers for Al metallization.

11:30 AM K1.10 
MECHANISM OF VOLCANO FORMATION AND TiN BARRIER INTEGRITY FOR THE W-PLUG PROCESS, Suketu A. Parikh, Silicon Systems Inc, Santa Cruz, CA; Lidia Akselrod, Applied Materials Inc, Santa Clara, CA; Jim Gardner, Nitin Parekh, Silicon Systems Inc, Santa Cruz, CA; Karl Armstrong, Applied Materials Inc, Santa Clara, CA.

Formation of volcanoes during the interaction of WF6 with the underlying Ti layer is a concern for W Plug process at submicron geometries. We show that the density and the size of volcanoes are strongly dependent on TiN barrier properties (such as Ti/N ratio, stress, thickness), RTP conditions, and on the W deposition conditions. Finally we characterize the volcano structure with SEM-EDX, stress, and SIMS analysis based on which a mechanism for volcano formation is proposed. The above study allows integration of a robust barrier and W plug process.

11:45 AM K1.11 
EFFECT OF ANNEALING TEMPERATURE ON BARRIER PROPERTY OF TiN FILMS, Hirotaka Hamamura, Univ of Tokyo, Dept of Chemical System Engr, Tokyo, JAPAN.

Ti layer is often employed to have low contact resistance in contact holes and TiN films are deposited on Ti layer as diffusion barriers in ULSI fabrication process. We have investigated the structural change of TiN/Ti layers as a function of annealing temperature by x-ray diffraction (XRD) using Cu-K and found that TiN/Ti layers deposited on thermal oxide changed into TiN films by annealing above 450C. TiN/Ti films were deposited on Si(100) wafers with 80 nm thermal oxide layer by conventional DC sputtering. The thickness of Ti layer was 20 nm and 40 nm TiN was reactively deposited on Ti layer by using Ti target in Ar/N atmosphere. The substrate temperature for Ti and TiN deposition was 280C and DC power was fixed at 10 kW. Annealing of TiN/Ti films was performed at 450C, 500C, 550C and 600C for 30 minutes in N atmosphere. We investigated peak position, intensity of peak, and peak width by XRD. Ti(002) peak was observed at 38.5 and TiN(200) peak was observed at 36.3 in the as-deposited sample. By annealing the sample at 450C, those peaks disappeared and TiN(111) or TiN(112) peak at 36.8 and TiN(103) peak at 37.6 were observed. When annealing temperature was above 500C, TiN(103) peak disappeared and only TiN(111) or TiN(112) peak at 36.8 was observed. Intensity of XRD peak and peak width also showed that size and orientation of TiN grain changed greatly between 450C and 500 C. These results suggest that barrier property of TiN/Ti layer on the side wall of contact hole can be improved by N annealing. The barrier performance of these annealed sample was examined by using secondary ion mass spectroscopy (SIMS) and transmission electron microscopy (TEM). The detail of these results will be discussed in the presentation.

SESSION K2: INTERCONNECTS - I 
Chair: Robert W. Fiordalice
Tuesday Afternoon, April 1, 1997
Salon 3

1:30 PM *K2.1 
CVD Al/PVD Al INTEGRATION FOR ADVANCED VIA AND INTERCONNECT TECHNOLOGY, Israel Beinglass, Applied Materials Inc, PSI, Santa Clara, CA.

As the semiconductor industry progresses to smaller and smaller geometries with more levels of interconnects, the needs for simpler via and interconnect scheme becomes evident. A metallization process that could at the same time fill the ever shrinking via size and form the interconnect at the same time is very desirable. In this report an enabling technology combining CVD Al technology with an overlayer of PVD Al deposited in the same cluster tool will be discussed. The technology that is compatible with m feature size and with low temperature processing issues. Films fill capability, films morphology and electrical performance will be discussed.

2:00 PM K2.2 
SIMULATION OF SPUTTER DEPOSITION AND REFLOW OF Cu AND Al FILMS IN INTERCONNECT TRENCHES AND VIAS, Nicholas I. Choly, Harry A. Atwater, California Inst of Technology, Dept of Applied Physics, Pasadena, CA; Imran Hashim, Applied Materials Inc, Physical Vapor Deposition Div, Santa Clara, CA.

Thin film evolution by sputter deposition and reflow has been simulated using a front-tracking model, and the results are related to fabrication of high aspect ratio submicron Cu and Al metallization structures in dielectric trenches and vias. The surfaces of thin films deposited on interconnect trenches were approximated as surfaces of constant cross section and a shadow model of Bales and Zangwill was used to describe the local sputter deposition rate. Simultaneous growth and reflow for Al and Cu was found to result in two distinct phases of film evolution: 1) film roughening (growth-dominant) at low temperatures and high deposition rates, and 2) film planarization (reflow dominant) at high temperatures and low deposition rates. The boundary between these regimes was found for both Al and Cu to follow a simple physical scaling law on the temperature-flux plane where the critical parameter is the surface self-diffusion constant. We also report the first simple three- dimensional physical model for via filling and reflow, in which films deposited in vias were approximated as surfaces of revolution. An equation was developed that describes the evolution of such a surface due to reflow, and simulations were again performed with a finite-element simulation. Importantly, a critical film aspect ratio was identified that cause the film surface to be drawn into the axis of symmetry, leading to void formation in the via and preventing fill planarization. This result for vias differs markedly from a trench of constant cross section, and may impose an important physical constraint on via filling by reflow.

2:15 PM K2.3 
INTEGRATED CVD Al PLUG PROCESSING FOR SUB-HALF MICRON FEATURES, Anthony Konecni, Texas Instruments Inc, Dallas, TX; Girish A. Dixit, Texas Instruments Inc, Semiconductor Process & Device Ctr, Dallas, TX; Noel Russell, Texas Instruments Inc, Dallas, TX; J. D. Luttmer, Robert H. Havemann, Texas Instruments Inc, Semiconductor Process & Device Ctr, Dallas, TX.

Aluminum plugs for via and contact level processing have received considerable attention in the last few years because of their advantages over tungsten plugs. Benefits include lower resistance, lower processing temperature, and reduced process flow complexity. Using CVD Al plugs, it is possible to deposit both the plug fill and interconnect in the same deposition step. Chemical vapor deposition of Al plugs using MOCVD precursors such as dimethylaluminum hydride (DMAH) offers a means of forming plugs and interconnect with high quality Al films at process temperatures below 200C. 
We have achieved void free fill of 0.3 m contacts and vias with aspect ratios >3:1 using CVD Al films grown from DMAH using two different process schemes on a cluster CVD and PVD system. In this paper, we present the results of these integrated flows: 1) blanket deposition of CVD Al films followed by PVD AlCu and 2) thin (<700 ) blanket CVD Al liner depositions followed by PVD AlCu deposition and reflow at less than 400C. Processes were optimized based on physical characterization of the films using SEM, TEM, SIMS, X-ray diffraction, and Rs measurements. A complete electrical characterization of CVD Al plug wafer processed through a 0.35 m CMOS flow using salicided devices, contacts/vias patterned using i-line lithography and etched using high density plasma oxide etch, and chemical mechanical polishing is also discussed.

2:30 PM K2.4 
AN INTEGRATED Al-PLUG PROCESS FOR .5 m CONTACT/VIA AT 420C, Suketu A. Parikh, Silicon Systems Inc, Santa Cruz, CA.

A low-temperature (T = 420C) Al planarization process is demonstrated for filling .5 m via with AR = 2, of 0.4 m BICMOS process. Thermal budget is a critical factor for the backend integration, since it dictates type of dielectric/SOG and the TiN barrier requirements. 
Al plug process was integrated by characterization of the key parameters. Specifically, via profiles tailored by sputter etch, barrier/wetting layer (Ti/TiN), degas, Al deposition conditions (temperature, deposition rate) were optimized. The above process vas integrated with improved TiN barrier properties achieved by RTP in N/O, or by plasma ash. The vias were characterized electrically (10 k via chain), and by SEM cross-section.

2:45 PM K2.5 
TEMPERATURE DEPENDENCE OF THE Al-FILL PROCESSES FOR SUBMICRON-VIA STRUCTURES, Stefan J. Weber, Siemens Components, Thin Film and CMP Dept, Hopewell Junction, NY ; Roy C. Iggulden, IBM, Thin Film & CMP Dept, Hopewell Jct, NY; Rainer F. Schnabel, Siemens Components, IGBit Integration, Hopewell Jct, NY; Peter Weigand, Siemens Components, 256MB Integration, Hopewell Junction, NY; Ebrahim A. Mehter, D. D. Restaino, IBM, Thin Film & CMP Dept, Hopewell Jct, NY; Stephen B. Brodsky, IBM, Metals Sputter Process, Hopewell Jct, NY; Larry A. Clevenger, IBM East Fishkill Facility, Microelectronics Div, Hopewell Junction, NY.

Today numerous different PVD techniques are used for the filling of submicron contacts and vias. One of the most promising approaches is the Al-fill process with respect to future applications in ULSI devices. Within this process the effect of different deposition temperatures are investigated. After the initial liner/barrier deposition an Al film is deposited as a one- or two-step process. In the two-step process the first layer is deposited at 150C with a second Al layer which is deposited between 300C and 500C. In contrast the one step process was done between 250C and 450C. Sequential deposition of cold/hot Al-alloys has shown better results in filling submicron-via structures. Cross-section SEM analysis demonstrates an evolution of different morphologies in tapered vias. The influence of via dimensions and metal deposition temperature on various electrical properties on film and contacts will be discussed. We also present the influence of the deposition temperature on the electrical data of underlying metal films.

3:30 PM K2.6 
NUCLEATION AND GROWTH OF CVD Al on DIFFERENT TYPES OF TiN, Michal Avinun, Moshe Eizenberg, Technion-Israel Inst of Tech, Materials Engr, Haifa, ISRAEL; M. Nalk, T. Guo, L. Y. Chen, Roderick C. Mosely, K. Lillao, S. Zhou, L. Y. Chen, Applied Materials Inc, Santa Clara, CA.

The reduction in device dimensions below 0.25 m imposes stringent requirements on the technology of filling gaps with a high aspect ratio. Low resistivity of the gap filling metal as well as low temperature processing are recognized as very important requirements. The deposition of Al by CVD on top of a TiN/Ti liner is a very promising approach. In this work we have studied the nucleation and growth of CVD Al and its bulk properties as a function of the type of TiN used. Three different types of TiN were used: PVD TiN, MOCVD TiN, and H/N plasma-treated MOCVD TiN. For a given type of TiN, we deposited films in a wide range of thicknesses (50-1000 Å) characteristic of both the nucleation and the bulk stages. The deposition were carried out in a cluster tool (Endura) where in some cases we deliberately allowed for a vacuum break prior to the Al deposition. 
Auger Spectroscopy was used to measure the amount of Al deposited, yielding thus the kinetics of Al growth. X-ray diffraction was used to determine the preferred orientation of the Al, which is important for electromigration resistance. This island formation, surface coverage and the evolution of the microstructure were studied as a function of the deposition time by SEM, TEM, and AFM. The results yield a good correlation between the surface roughness and the optical reflectivity of the Al films. We have found that air exposure affects the nucleation, the rate of growth at the early states, and the resultant morphology. A correlation exists between the nucleation stages of the growth and the bulk properties. A model has been developed to explain our findings.

3:45 PM K2.7 
INTEGRATED BARRIER/PLUG FILL SCHEMES FOR HIGH ASPECT RATIO GB DRAM CONTACT METALLIZATION, Yu-Pei Chen, Texas Instruments Inc, Dallas, TX; Girish A. Dixit, Jiong-Ping Lu, Wei-Yung Hsu, J. D. Luttmer, Robert H. Havemann, Texas Instruments Inc, Semiconductor Process & Device Ctr, Dallas, TX.

As circuit dimensions continue to shrink, the aspect ratios of contact and via become more aggressive. Such a high aspect ratio has posed a big challenge to the current barrier and contact/via filling processes. To achieve low contact resistance for high aspect ratio contacts, new deposition processes and contact integration schemes have to be developed. In this paper, the results of the investigation of various contact integration schemes to achieve low contact resistance for high aspect ratio contacts will be presented. Different types of Ti liners, TiN barriers, and contact plugs were investigated and evaluated. The wafers were characterized by scanning electron microscopy and transmission electron microscopy to determine the bottom and sidewall coverages and the contact filling performance for different liner and barrier deposition processes and contact filling techniques. The wafers were electrically probed and the contact parametrics were measured.

4:00 PM K2.8 
MELTING POINT DEPRESSION OF ULTRA-THIN DISCONTINUOUS Al FILMS, Shouliang Lai, Johan R.A. Carlsson, Leslie H. Allen, Univ of Illinois-Urbana, Dept of MS&E, Urbana, IL.

Recently, great progress has been made I the development of the Al reflow process for multilevel submicron VLSI applications [1]. However, the basic mechanism(s) and dynamics which govern the reflow process in confined dimensions have not been elucidated yet. This paper is intended to provide new insight into the dynamics of the reflow process. In the early stages of deposition, clustering of Al on surfaces is thermodynamically favored and the properties of Al are much different than that of the bulk. Using a novel ultrafast and sensitive differential scanning calorimeter [2,3], we have investigated the melting properties of Al films with thickness ranging from 6 to 200 deposited on a Si-N substrate. The melting points of the nanometer-scaled thin films exhibit a significant dimension-dependent depression as the deposition thickness . Melting of Al at T500C has been observed when the deposition thickness of 6 . Thermodynamic arguments will be used to discuss the origin of this phenomenon.

4:15 PM K2.9 
A 0.18m TECHNOLOGY SOLUTION FOR MULTI-LEVEL VIA PLUG AND INTERCONNECTS USING INTEGRATED CVD Al AND PVD Al-Cu, T. Guo, L. Chen, M. Naik, H. Zhang, Roderick C. Mosely, Applied Materials Inc, Santa Clara, CA; Fu-Sen Chen, Applied Materials Inc, PVD Products Business Group, Santa Clara, CA; Israel Beinglass, Applied Materials Inc, PSI, Santa Clara, CA; G. Wyborn, G. Goltz, N. Chan Tung, G. Bease, S. Louwers, CNET, Cntr Commun - SGS Thomson, Crolles, FRANCE.

The challenge of developing integrated processes for 0.25 m and smaller features with excellent electrical and reliability parameters is critical for the semiconductor industry. We have developed a novel integrated PVD/CVD Al metallization process that is capable of filling sub-0.25 m features and is integratable with low-K dielectric materials. The key to this successful technology is the in-situ sequential deposition of a thin CVD Al film and PVD Al(Cu). CVD Al is deposited at low temperatures (C), using Dimethyl-Aluminum Hydride (DMAH). The PVD Al deposition is done at temperatures less than 350C. 
This technology is developed on an integrated cluster Endura metallization tool which enables the in-situ deposition of CVD Al and PVD Al(CU) in a UHV of 10 torr without vacuum break. The PVD Al film grows epitaxially on the CVD Al, and simultaneously gives excellent Cu distribution throughout the integrated Al film, without additional ex-situ anneal. No grain boundary is observed between the two Al films. The uniform doping of Cu in the Al film is important for good electromigration reliability. Micro-Auger measurements indicate the same average Cu concentration at the bottom of the vias and in the metal lines. A repeatable and complete feature fill without voids is critical to the reliable operation of devices. In this paper, we will present TEM and SEM cross-sectional micrograghs showing completely filled 0.25 m contact with an aspect ratio (AR) greater than 4.5. SIMS analysis show the CVD Al deposited using DMAH has excellent film properties, comparable to those of PVD Al. Device wafers for the 0.35 m technology with multilayer interconnect structure have been successfully processed using this novel technology. Excellent electrical results are obtained. A better than 2 X improvement on via resistance over other plug fill technologies is achieved. Via resistance and electromigration data will be presented. This integrated process not only provides void-free, low resistance and low temperature metallization, the single-pass Al plug and interconnect solution also simplifies the manufacturing sequence, compared with other plug-fill technologies, therefore reducing the cost and increasing the overall production throughput.

4:30 PM K2.10 
Al WETTING LAYER ATTRIBUTES OF ION METAL PLASMA Ti/TiN FILMS, Simon Hui, Ken Ngan, Applied Materials Inc, PVD Division, Santa Clara, CA; Barry Hogan, Gonga Yao, Applied Materials Inc, PVD Div, Santa Clara, CA; Murali Narasimhan, Applied Materials Inc, PVD Division, Santa Clara, CA.

Aluminum planarization is a low cost alternative process to CVD W for contact and via plug formation in semiconductor fabrication. In order to planarize the contacts or vias, a wetting layer is required. PVD Ti and TiN are widely used as the wetting layer and diffusion barrier in this application. As contact/via feature size shrinks, the major difficulty for Al planarization at the contact level is diffusion barrier deposition onto high aspect ratio features; for via processing, the major difficulty is the wetting layer deposition. Ion Metal Plasma (IMP) process provides directional flux of sputtered atoms required for coating high aspect ratio features. This process is based on conventional magnetron sputtering with the addition of a higher density, inductively coupled RF plasma between the sputtering cathode and the substrate. Metal atoms sputtered from the cathode due to inert gas ion bombardment transit the RF plasma and can be ionized. The metal ions can then be accelerated to the substrate by means of a low voltage DC bias. 
In this paper, the effects of the process conditions of the IMP Ti and TiN on the material properties of the aluminum films will be presented. Parameters such as process pressure, bias, process temperature of the IMP Ti and TiN process as well as the wetting layer thickness have significant effects on the grain size, reflectivity, crystal orientation, and surface roughness of the aluminum films.

SESSION K3: SILICIDES 
Chair: Roderick C. Mosely
Wednesday Morning, April 2, 1997
Salon 3

8:30 AM *K3.1 
SELF-ALIGNED SILICIDES FOR HIGH PERFORMANCE SUB-0.18m CMOS TECHNOLOGIES, Jorge Kittl, Qi-Zhong Hong, Texas Instruments Inc, Semiconductor Process & Device Center, Dallas, TX; C. P. Chao, V. McNeil, T. Breedijk, Texas Instruments Inc, Semiconductor Process & Device Cntr, Dallas, TX.

Self-aligned silicide (SALICIDE) processes are a key factor for scaling of high performance CMOS technologies. They are used to lower sheet and contact resistances, increasing device performance and reducing RC delays to allow for higher clock speeds. As junction depths and linewidths are scaled down, achieving both low sheet resistance and low diode leakage, meeting all other integration constrains becomes a difficult challenge. The application of silicides to deep-submicron technologies is controlled by their fundamental materials properties such as kinetics of phase formation, microstructural evolution and interface characteristics. In this paper we present an overview on SALICIDE development for sub 0.18 m CMOS technologies at Texas Instruments, emphasizing the fundamental materials aspects of Ti and Co silicidation, and comparing alternative processes.

9:00 AM K3.2 
SILICIDATION KINETICS FOR CVD TiSi: THE ROLE OF MICROSTRUCTURE IN ENHANCING PERFORMANCE IN ULTRAFINE FEATURES, Cindy Goldberg, Cheryl Faltermeier, Michael Jones, Allan Upham, Alain E. Kaloyeros, SUNY-Albany, Dept of Physics, Albany, NY.

The inability to form low resistivity contacts in subquarter micron lines using conventionally grown TiSi is attributed to the low density of nucleation sites for C54 TiSi formation. Although Si pre-amorphization prior to PVD Ti has achieved low resistivity silicides down to 0.1 m, the technique is implicitly inconductive, with shallow junctions which may yield high leakage current. Alternatively, CoSi is being investigated as a promising solution. However, the higher Si consumption, along with a tendency to react with spacer materials, make such schemes susceptible to device leakage as well. Instead, the authors have developed a CVD-based Ti process which, when coupled with a subsequent RTA sequence, hields TiSi in narrow lines with the required resistivity and leakage performance. In this paper, results are presented from a systematic RTA sutdy which compared the silicidation kinetics and associated performance in ultrafine lines for CVD Ti versus PVD Ti. These results are discussed in terms of the Ti-Si interfacial characteristics, as well as grain size and texture of the resulting C49 and C54 phases.

9:15 AM K3.3 
EFFECT OF IMPLANTATION OXIDE ON THE SILICIDATION OF NARROW DIFFUSION AND POLY-LINES, Abdalla Naem, National Semiconductor Corp, Santa Clara, CA; Anne Lauwers, IMEC, Leuven, BELGIUM; Muriel do Potter, Karen Maex, IMEC vzw, Leuven, BELGIUM.

It has been shown before that impurities play a crucial role in silicidation. For reliable silicide formation, dopant and other impurity levels need to be minimized. This holds both for TiSi and CoSi in current integration processes. It is well known that knock-on oxygen is present in the Si after implantation of dopants through a thin oxide. In order to verify the effect of this knock-on oxygen, experiments were set up with and without oxide during implantation. The effect on silicide sheet resistance has been evaluated for narrow poly-Si runners and narrow diffusion areas. Both dopant types were included in the experiments.
From our results, both the mean value and the standard deviation of the sheet resistance of the narrowest lines increase. In this paper the electrical data will be presented for both silicides and discussed, together with detailed physical and chemical analysis.

9:30 AM K3.4 
REACTION OF Ti WITH WSi, Jeff Gambino, IBM East Fishkill Facility, Hopewell Junction, NY; B. Cunningham, Dominion Semiconductor, Manassas, VA; E. D. Adams, P. DeHaven, IBM Microelectronics, Essex Junction, VT.

Titanium is commonly used in contacts in integrated circuits, as an underlayer for either W studs or Al vias. Although there have been many studies on Ti contacts to Si, there have been relatively few studies on Ti contacts to silicides. In particular, there have been no studies on reactions between Ti and WSi, even though WSi polycide structures are commonly used in advanced CMOS devices. 
In this work, reactions between Ti and WSi have been studied at temperatures between 400 and 800C. These structures simulate the gate contact in a 256 M DRAM process, where W studs (with a Ti/TiN underlayer) contact a WSi polycide gate. It is observed that Ti and WSi react to form TiSi starting at 600C. The reaction temperature is higher than that for Ti on Si, because the Si supply is limited by diffusion through WSi. At 700C, localized formation of Ti silicide is observed underneath the WSi, presumably due to grain boundary diffusion of Ti through WSi. These results suggest that post-metallization anneals of Ti on WSi2 polycide structures should be kept below 700C to avoid device degradation.

9:45 AM K3.5 
INTERFACIAL SILICIDE THIN FILM CHARACTERIZATION BY XPS, Daniel F. Allgeyer, Micron Technology, Boise, ID.

The interfacial chemistry of metal silicide thin films and related materials using x-ray photoelectron spectroscopy (XPS) is discussed. Some of the materials and interfaces characterized include tungsten silicide, titanium nitride, titanium cobalt silicide, cobalt silicide, titanium silicide, and aluminum. These materials are often supported on conductive (silicon, polysilicon) and nonconductive (boron-doped phosphosilicate glass or BPSG, tetraethylorthosilicate or TEOS) substrates. Determining their interfacial chemistry is accomplished by using a dual, high-energy magnesium (1253.6 eV) zirconium anode (2042.4 eV) operating simultaneously. Simultaneous operation of the magnesium and zirconium anodes allows the analysis of both the photoelectron as well as the corresponding higher energy Auger electrons for such materials as silicon and aluminum. Using these two transitions provides both line energies necessary for determining their Auger parameters. The Auger parameter, independent of localized sample charging, provides chemical identification of metal silicide materials and thin films. Charging is common to many materials supported on insulating substrates and is especially prevalent using a monochromatized aluminum source for XPS analysis. Thus, the interfacial chemistry of metal silicide thin films and materials via the simultaneous use of the magnesium (1253.6 eV) and zirconium (2042.4 eV) anodes is discussed.

10:00 AM K3.6 
INVESTIGATION OF THE INTERFACE PROPERTIES OF DICHLOROSILANE-BASED TUNGSTEN SILICIDE FILMS INTEGRATED WITH AMORPHOUS SILICON, John Y. Adachi, Robert C. McIntosh, David E. Badt, Genus Inc, Sunnyvale, CA.

The properties of silane-based CVD tungsten silicide (Wsix) deposited on a doped polysilicon film in a gate structure are well understood [1]. Recently, significant advances have been made in the area of polycide gate structures, which have introduced new areas of concern to the process integration engineer. Specifically, in the spirit of process simplification, the wet HF clean has been eliminated as a result of the integration of the doped polysilicon film deposition with the deposition of tungsten silicide in the same cluster tool, without breaking vacuum. In addition, amorphous silicon has been proposed and is under investigation as an alternative to polysilicon in the gate structure. Finally, a new reducing chemistry, dichlorosilane, has replaced silane as a reactant gas in the CVD deposition of Wsix [2]. These changes have warranted an investigation of the interface quality of the polycide structure and its effect on CVD tungsten silicide film deposition and properties. In this study we investigate the integrated deposition of dichlorosilane based CVD WSix on in-situ doped amorphous silicon. The silicide film composition, particularly at the amorphous Si/silicide interface, is studied through the use of analytical techniques such as Rutherford Backscattering (RBS), and Secondary Ion Mass Spectrometry (SIMS). The morphology of the as-deposited and annealed integrated stack is investigated through cross-sectional Transmission Electron Microscopy (TEM) and X-Ray Diffraction (XRD). Finally, silicide film properties such as film adhesion and resistivity are discussed relative to the use of the dichlorosilane chemistry.

SESSION K4: INTERCONNECTS - II 
Chair: Roderick C. Mosely
Wednesday Morning, April 2, 1997
Salon 3

10:45 AM *K4.1 
ELECTROMIGRATION IN W-PLUG, Al FILLED AND Cu FILLED VIAS, Hisao Kawasaki, Cristiano Capasso, Martin Gall, Richard Hernandez, Dharmesh Jawarani, Motorola Inc, Advanced Products Research & Dev Lab, Austin, TX.

Electromigration experiments are performed for lifetime extrapolation of interconnects to use conditions and to set guidelines for circuit design applications. For Al-Cu alloys at tungsten (w) plug contact/via areas, a new failure model has been established. This model predicts that lifetimes of Al-Cu interconnects at use conditions are dominated by Cu drift, or incubation times [1]. For process simplification and cost reduction in multilevel metallizations, an Al filled via is a promising candidate to replace W plug vias. For performance improvement in high speed logic devices, Cu metallization schemes are being developed. This paper describes an application of the established failure model to the different metallization systems mentioned above and shows how data, obtained from accelerated tests, should be analyzed for lifetime extrapolation of VLSI interconnect to use conditions.

11:15 AM K4.2 
WHAT LIMITS APPLICATION OF TEM IN SEMICONDUCTOR INDUSTRY, Hong Zhang, PVD Technology, Applied Materials, Santa Clara, CA.

Transmission electron microscope (TEM) may be one of the most dramatic instruments made in human history. The new generation field emission TEM provide less than 2 Åpoint-to-point resolution, nanoscale chemical analysis (EDS), and electronic structure information (EELS). For a long time, TEM has been characterized as a research instrument for academic field mainly because of the difficulty of making TEM specimen from real parts, and no such high resolution requirement for most of the industrial applications. However, the rapid development of semiconductor industry really brings new life to TEM. Today's sub-half-micron technology requires multiple-layer metallization to improve contact resistance, adhesion and wetting property. Characterization of nanometer thick materials at bottom of 0.25 m structure is beyond the ability of any other instrument. 
In general, we classify the use of TEM for semiconductor device as process evaluation and failure analysis, each of which requires different sample preparation techniques. For process evaluation, a large number of features, like contacts and vias, need to be surveyed to have statistical conclusion about current processes, while for failure analysis, precision TEM technique is applied to reach specific area, such as single poly gate, contact or via, and find out the root cause of the failure. Today's sample preparation techniques is on such stage that, on one hand, it allows us to make the TEM specimen of semiconductor device with five layer metals and covering 2 mm long cross section; on the other hand, it enables us to pinpoint the smallest feature on the device. Meanwhile, the turnaround time has been shortened to less than four hours. In this paper, a large number of examples are given to explain how the TEM techniques should be utilized to solve different problems related to semiconductor manufacture and device failure. As far as we can see, the application of TEM on semiconductor industry is limited only by our imagination.

11:30 AM K4.3 
AN INTEGRATED SOLUTION FOR TEXTURE AND REFLECTIVITY IMPROVEMENT OF CVD AND PVD AlCu METALLIZATIONS, L. Y. Chen, M. Naik, T. Guo, Roderick C. Mosely, Applied Materials Inc, Santa Clara, CA; Fu-Sen Chen, Applied Materials Inc, PVD Products Business Group, Santa Clara, CA; Israel Beinglass, Applied Materials Inc, PSI, Santa Clara, CA.

Aluminum-plug and interconnect technology is considered to be a promising alternative to the Tungsten-plug/AlCu interconnect in terms of simplification of process sequence for sub-0.35 m technology. Technology issues that need to be resolved include consistent void-free via/contact fill for sub-0.35 m structures with highly [111] oriented and highly reflective Al exhibiting smooth surface morphology. Highly [111] oriented interconnect is desired for improved electromigration, and highly reflective films with smooth surface for ease in photolithography. For Al plug and interconnect, process conditions are optimized such that void-free via-fill and excellent Cu distribution are achieved by in-situ integration of CVD Al and PVD AlCu. The impact of these process conditions, including the use of different liner materials on the microstructure of the integrated Al stack is studied. Typical CVD Al films deposited in-situ on commonly used nucleation layers such as Ti, PVD TiN, CVD TiN are usually less reflective or less [111] textured, compared to PVD Al films. 
In this work, we report on the reflectivity and texture improvement of CVD/PVD AlCu deposited on CVD TiN, PVD TiN, and Ti. A novel P referential R eflectivity Improv e ment (PRIME) integration sequence for CVD/PVD AlCu is also developed. The PRIME technology involves depositing a thin self-aligned layer to preferentially change the nucleation characteristics of CVD Al films on the field without affecting the contact profile or fill performance. As an example, in the case of Ti/CVD TiN liner, the full width at half maximum of the Al [111] peak was improved from 13.5 to 2 degrees. We will present TEM and SEM micrographs showing complete quarter-micron via-fill with morphological improvement, and [111] x-ray rocking curves showing strong Al texture improvement.

11:45 AM K4.4 
HIGH-DENSITY PLASMA SPUTTER PRE-CLEANING OF SUB-HALF MICRON VIAs USING AN Ar/H2 PLASMA, Anthony Konecni, Texas Instruments Inc, Dallas, TX; Girish A. Dixit, Texas Instruments Inc, Semiconductor Process & Device Ctr, Dallas, TX; David Aldrich, Noel Russell, Texas Instruments Inc, Dallas, TX; J. D. Luttmer, Robert H. Havemann, Texas Instruments Inc, Semiconductor Process & Device Ctr, Dallas, TX.

An Ar sputter preclean of vias to remove native oxide and post-etch residue from the bottom of vias prior to metal liner deposition is commonly used in multilevel metallization. While this process aids in providing excellent electrical contact between adjacent conductive layers, topologically sharp features are also subject to preferential etching leading to unwanted shape change of these features. For high aspect ratio features, high ion energies are necessary in order to achieve sufficient cleaning at the bottom of the via. The use of a chemically assisted cleaning process would aid in improving this electrical contact. The addition of hydrogen to an argon plasma to improve the effectiveness of the sputter preclean was explored. Hydrogen was added to the plasma in order to provide a means of chemical reduction of any contamination at the bottom of the via. The addition of hydrogen to the standard preclean conditions in a commercially available inductively coupled plasma (ICP) preclean chamber has shown promise in reducing the amount of preclean required. A 300 Ar/H preclean showed comparable via resistance to a 400 Ar only preclean. A complete process window characterization of the blanket etch response to different plasma conditions was explored. A physical characterization of the differences between Ar/H vs Ar only plasmas on oxide roughness, metal texture, and via corner faceting will be presented. A full electrical characterization on a 0.35 m CMOS flow including via resistance for single vias and vias chains will be presented.

SESSION K5: INTERCONNECTS - III 
Chair: Robert W. Fiordalice
Wednesday Afternoon, April 2, 1997
Salon 3

1:30 PM *K5.1 
PRECISION CROSS SECTION TEM STUDY ON ELECTROMIGRATION OF SUBMICRON DEVICE, Hong Zhang, PVD Technology, Applied Materials, Santa Clara, CA; Roderick C. Mosely, Applied Materials Inc, Santa Clara, CA; Fu-Sen Chen, Applied Materials Inc, PVD Products Business Group, Santa Clara, CA.

Electromigration originally was found to be the cause of contact failure in electronic package. As the dimension of devices scale down to submicron regime, it has shown to be one of primary cause of chip-level failure on conducting lines, and there is evidence showing the failure mechanism . While a great deal of study has been done on the fundamental mechanism of atomic motion induced by electric current and on failure statistics, there has been relatively less amount of work linking those fundamental studies to the actual device failure, in other words, lack of experimental evidence to show the development of microstructure during failure process. In this study, we use precision cross section TEM technique to characterize the real electromigration test structure of submicron devices. The results reveal void formations, Cu redistribution, and microstructure development corresponding to different metal stacks, such as PVD Al, CVD Al, and W vias during electromigration testing. In order to have complete information, the TEM specimens have to be made to cover entire test structure. Therefore what is the best test structure from TEM characterization point of view has also been discussed.

2:00 PM K5.2 
RATE ENHANCEMENT STRATEGIES FOR COPPER CVD, Narendra S. Borgharkar, Gregory L. Griffin, Louisiana State Univ, Dept of Chem Engr, Baton Rouge, LA.

We have studied the alcohol-induced enhancement of deposition rates for copper CVD using Cu(hfac) reduction. We have measured the evaporation rates of Cu(hfac)/alcohol solutions and the deposition kinetics of gas phase Cu(hfac)/alcohol mixtures, in order to resolve the relative contribution of reactant transport effects vs. changes in the intrinsic kinetics. 
Steady-state deposition rates were measured using a hot-wall microbalance reactor. For base conditions of 2 Torr Cu(hfac), 40 Torr H, and 300C without added alcohol vapor, a growth rate of 0.5 mg/cm/hr (ca. 10 nm/min) is observed. Reaction order experiments suggest that the rate limiting step for the overall Cu(hfac) reduction process is a bimolecular surface reaction between adsorbed (hfac) ligands and H atoms. 
The evaporation behavior of Cu(hfac) dissolved in ethanol was studied using transpiration measurements. Initial results showed that the ethanol solvent evaporates cleanly, leaving all of the Cu(hfac) ehind in the evaporator. Later experiments using mass spectrometer sampling confirm that no significant Cu(hfac) is evaporated into the carrier gas. 
The effect of -PrOH on the intrinsic kinetics was studied by adding a second carrier gas stream from an alcohol evaporator. The growth rate is observed to increase linearly with -PrOH partial pressure, up to a maximum of 2.5 mg/cm/hr at 4.5 Torr. 
The combined results indicate that the presence of alcohols does not increase the evaporation rate of Cu(hfac) entering the carrier gas. Instead, the higher observed growth rates are due to an enhancement of the intrinsic kinetics. We speculate that alcohol dehydrogenation acts as an alternate H atom source for the rate limiting H(hfac) desorption step.

2:15 PM K5.3 
THE CARRIER GAS EFFECTS ON SELECTIVITY AND THE ENHANCEMENT OF SELECTIVITY BY SURFACE PASSIVATION WITH HMDS IN COPPER-CVD, Seok Kim, Jong-Man Park, Doo-Jin Choi, Yonsei Univ, Ceramic Engr, Seoul, SOUTH KOREA.

Recently, Chemical Vapor Deposition (CVD) of Cu films has been widely studied with the various metal organic precursors. One of the interesting parts of Cu-CVD is the selective deposition, which attracts more attention based on its potential as a patteming method of Cu. In this study, the selectivity of CVD-Cu for Al, TiN, and CVD-SiO substrates was investigated systematically using (hfac)Cu(VTMS) with carrier gas of H and Ar as functions of the deposition temperature (150200C), chamber pressure (0.31.0 Torr), and deposition time. The apparent incubation time on each substrate was increased as the conductivity of substrate, the deposition temperature, and the chamber pressure were decreased. H carrier gas system had shorter incubation time and higher deposition rate than Ar carrier system. However there was selectivity loss due to accidental nucleation on the SiO surface even in the period of the incubation. To enhance the selectivity, a few methods of SiO surface passivation with silylating agents (MeSiCI, MeSiCI, MeSiNH, etc) have been tried by Jain et al., Gelatos , etc. In this study, SiO surface passivation was accomplished by the predosing with HMDS (MeSiNH) using bubbler system. And this effect was investigated for both H and Ar carrier gas system. HMDS predosing process lengthened the incubation time on SiO substrate and had little influence on that of TiN and Al substrate. Moreover, other interesting properties (resistivity, morphology, crystallinity, adhesion, purity, etc) were also studied.

2:30 PM K5.4 
CHARACTERIZATION OF ELECTROPLATED COPPER SOLDER BUMPS PROCESSING FOR FLIP-CHIP APPLICATIONS, Surasit Chungpaiboonpatana, Stephen P. Beaudoin, Arizona State Univ, Dept of Chem Bio & Matls Engr, Tempe, AZ; Timothy S. Cale, Arizona State Univ, Ctr for Solid State Electronics, Tempe, AZ; Cynthia L. Pillote, Gordon Tam, Marlene J. Begay, Bill Marlin, Jaynal Molla, Bill Lytle, Motorola Inc, Tempe, AZ.

Manufacturing smaller microprocessing devices and placing these devices in smaller packages are two goals of the modern semiconductor industry. Electroplated solder bumps or solder interconnect technologies for electrical connection can help satisfy these needs by reducing die and substrate area requirements compared to conventional interconnect technologies such as wire bonding and tape automated bonding methods. The ability to electroplate uniform solder bumps on wafers is important to the subsequent integrity of interconnects made with these bumps. This paper reports on the results of experiment designed to understand the effects of five copper plating parameters on the intrawafer copper bump height variability. The parameters are: 1) anode shape (a circular plate with holes that allows solution to flow through the anode toward the wafer electrode vs. an annular-ring that allows the solution to flow toward the wafer unobstructed), 2) current level (27 or 15 m), 3) mode of wafer-electrode contact (scratching through the photoresist with the pins that make electrical contact vs. developing and exposing openings in the photoresist using standard lithographic techniques), 4) solution flow rate (20 or 10 GPM), and 5) plating additive concentration (160 or 80 mL of Enthone Sel-Rex additive per bath). This paper also reviews the experimental design, results, and characterization work that led to the recommendations to use: I) the annular-ring anode, 2) low current, 3) patterned openings for contact, 4) high solution flow rate, and 5) high plating additive concentration. All five parameters significantly affect the copper plate height uniformity.

2:45 PM K5.5 
THE ROLE OF SOLVENT AND PRECURSOR ON HIGH ASPECT RATIO GAP FILLING BEHAVIOR OF POLYIMIDES DURING CURE, John G. Pellerin, SEMATECH Inc, Austin, TX; Andrew J. McKerrow, Texas Instruments Inc, Semiconductor Process & Device Ctr, Dallas, TX; Paul S. Ho, Univ of Texas-Austin, Dept of MS&E, Austin, TX.

Successful integration of polyimide interlayer dielectrics (ILD) into subtractive metal etch, or gap fill, interconnect architectures depends in part on their ability to fill high aspect ratio, submicron dimension trenches. Because polyimides are insoluble in a majority of solvents, they are typically solution coated as poly(amic acid) or poly(amic alkyl ester) precursors and thermally treated to remove solvent and convert precursor to the final polyimide. Unlike many spin-coated polymer ILD candidates, polyimide gap filling behavior is not only dependent on solvent evaporation, but is further complicated by chemicaL and hence, thermomechanical changes owing in the polymer film. To understand the roles of solvent and precursor on gap filling behavior, we have developed a methodology that correlates physical observation of gap filling with thermomechnnical and chemical changes. 
Optical and cross-sectional scanning electron microscopy have revealed void formation in high aspect ratio trenches as a function of temperature during thermal cure. In addition, it is noted that the temperature regime and trench dimensions in which voids were detected depend on the solvent system as well as the precursor itself, i.e., poly(amic acid) or poly(amic alkyl ester). Further studies on blanket polyimide films have characterized weight loss, extent of imidization and film stress evolution during the same thermal curing cycle. Based on the results of this study, we have identified interrelationships among the thermomechanical film properties, extent of imidization and solvent loss as critical factors affecting tile gap filling ability of polyimides. The methodology and results presented can be generalized to study the behavior of other polymer ILDs.

3:00 PM K5.6 
INTERSURFACE MECHANISMS IN CMP: ROLE OF PARTICLE MATERIAL PROPERTIES I, Rajeev Bajaj, Sanjit Das, Jamie Saravia, Motorola Inc, APRDL, Austin, TX.

Chemical Mechanical Planarization (CMP) technology is based on balance of chemical and mechanical aspects of material removal from the wafer. Oxide CMP is aimed at reducing step height, due to underlying metal, in ILD (interlayer dielectrics) oxides. This is critical to submicron, multilevel interconnect schemes. Tungsten CMP is fast replacing etch back technology due to its improved ability to produce planar plugs and elimination of residual tungsten defects. 
CMP slurries have long been viewed as twin systems wherein abrasive particle provides mechanical abrasion and chemical component is provided by additive in the particle suspension or provided separately. Silica abrasives in alkaline media are used to polish interlayer dielectrics (SiO). Various models for material removal have been proposed. These revolve around stress induced deformation of the surface layer and subsequent diffusion of alkaline media to depolymerize the Si-O-Si network. Presence of alkaline media has been viewed as key to uniform oxide removal. Tungsten CMP slurries are typically comprise separate abrasive and chemical components. Alumina and silica abrasives have been used. Alumina abrasives offer higher removal rates for tungsten films. 
In this article we show that role of abrasive particles is far more complex than providing mechanical abrasion alone. Interaction between particle and polish film is a determining factor in its efficacy as an abrasive. Van der Waal forces and electrostatic interaction between particle and polish film along with particle hardness and size are important . determinants. It is shown that while relative hardness of abrasive and polish film show correlation with removal rate, softer abrasive may exhibit higher removal rate when its interaction with polish film is low. Also, strong interaction between particle and polish film can induce unique defects. Understanding of relative importance of particle characteristics in CMP processes can help in selecting abrasives for improved rate and lower abrasive induced defectivity.

3:15 PM K5.7 
EXPLORING CMP SOLUTIONS TO PLANARITY CHALLENGES WITH TUNGSTEN PLUGS, John Mendonca, Motorola Inc, Advanced Products R&D Lab, Austin, TX; Krishna Murella, Inki Kim, Jim Schlueter, SpeedFam Corp, Chandler, AZ; T. Breedijk, Texas Instruments Inc, Semiconductor Process & Device Cntr, Dallas, TX.

Tungsten plugs have been used in the recent past for local interconnects and for level-level interconnect applications. The resist etch back process has been the method of choice historically for planarization purposes. However, with the advent of chemical mechanical polishing (CMP) technology, one has an alternate path for achieving global planarity. Process in integration issues have to be worked out. In this paper we have explored the effect of various process parameters and consumable changes on planarity/nonuniformity. The across wafer and wafer-wafer nonuniformity 1-sigma was reduced from 10-20 to The optimized process was verified on a 500 wafer extended run to obtain /minute with 5.5 wafer-wafer removal variation.

SESSION K6: IN-ROOM POSTER SESSION 
Wednesday Afternoon, April 2, 1997
4:00 P.M. 
Salon 3

K6.1 
IMPROVED TIN AS A DIFFUSION BARRIER BETWEEN CU AND SI, Sa-Kyun Rha, KAIST, Dept of MS&E, Taejon, SOUTH KOREA; Won-Jun Lee, LG Semicon Co Ltd, Advanced Technology Lab, Cheongju, SOUTH KOREA; Seung-Yun Lee, Yoon-Jik Lee, Dong IL Kim, KAIST, Dept of MS&E, Taejon, SOUTH KOREA; Dong-Won Kim, Kyonggi Univ, Dept of MS&E, Suwon, SOUTH KOREA; Chong-Ook Park, KAIST, Dept of MS&E, Taejon, SOUTH KOREA.

Reactively sputtered TiN films were studied as a diffusion barrier between Cu film and Si substrate. The microstructure of TiN film were modified by the sequential processes of sputtering/vacuum breaking/sputtering and by the stuffings in various ambient gases. The diffusion barrier property of TiN was improved by vacuum breaking between sputter-depositions and stuffing. The effect of microstructure on diffusion barrier property of TiN was also investigated using various characterization methods. By double sputtering, the grain boundary length of TiN(as the diffusion length of Cu) was increased and by stuffing, the grain boundary width(as the diffusion path of Cu) became narrow. The improved had outstanding diffusion barrier property compared to the conventional single sputtered TiN.

K6.2 
STRUCTURAL AND CHEMICAL STABILITY OF TA-SI-N THIN FILMS BETWEEN SI AND CU, Yoon Jik Lee, Bong Seok Seo, KAIST, Dept of MS&E, Taejon, SOUTH KOREA; Won-Jun Lee, LG Semicon Co Ltd, Advanced Technology Lab, Cheongju, SOUTH KOREA; Sa Kyun Rha, Dong IL Kim, KAIST, Dept of MS&E, Taejon, SOUTH KOREA ; Dong-Won Kim, Kyonggi Univ, Dept of MS&E, Suwon, SOUTH KOREA; Chong Ook Park, KAIST, Dept of MS&E, Taejon, SOUTH KOREA.

Reactively RF sputtered Ta-Si-N thin films of various compositions were studied as a diffusion barrier between Si and Cu. The compositions of these thin films were controlled by varying the sputtering power of Ta and Si target and the nitrogen flow rate relative to argon during sputtering. Before and after annealing, X-ray diffraction, Auger electron spectroscopy and cross-section transmission electron microscopy were used to investigate the structural and chemical stability and the effectiveness as a diffusion barrier of Ta-Si-N thin film between Si and Cu.

K6.3 
A DEPOSITION MECHANISM OF SiO CVD USING TETRA-ISOCYANATE-SILANE AND WATER, Akira Fujimoto, Osamu Sugiura, Tokyo Inst of Technology, Dept of Physical Electronics, Tokyo, JAPAN.

We have studied a chemical vapor deposition of SiO films using tetraisocyanate-silane(Si(NCO):TICS) and water (HO) for application to interlayer dielectric films of multilevel interconnections. The deposition temperature of TICS/HO SiO CVD is as low as 100C, and the deposition rate is exponentially decreased with the increasing deposition temperature. This material system has features such as the conformal deposition at high temperature, the flow-like deposition at low temperature, and the selective deposition using resist masks. The deposition characteristic of the CVD can be explained by the adsorption of the source gases on the substrate surface. In the adsorbed layer, the deposition reactions occur as follows: i) Si-NCO + HO Si-OH + HNCO; ii) Si-NCO + HO-Si Si-O-Si + HNCO; iii) Si-OH + HO Si Si-O-Si + HO. The rate determining step is reaction i). The deposition rate of the CVD was calculated under the assumption that the source gases independently follow the BET isotherm theory. Calculated results of the dependence of the deposition rate on the deposition temperature well fitted with the experimental data by setting a reaction constant V = 400 mn/min which are defined as the deposition rate under the monolayer adsorption of source gases.

K6.4 
THE ETCHING BEHAVIOR OF TUNGSTEN (W) WITH RESPECT TO THE ORIENTATION OF THE GRAIN BOUNDARY AND MASKING LAYERS, Hean-Cheal Lee, IMEC vzw, Dept ASP/MP, Leuven, BELGIUM; Serge Vanhaelemeersch, IMEC vzw, Leuven, BELGIUM; Luc Van den hove, IMEC vzw, ASP/MP, Leuven, BELGIUM.

Blanket W deposition followed by etch back is an attractive solution for filling anisotropically etched contacts and vias. The so-called plug recess, used to indicate the height difference between the top of the Tungsten plug and the top of the contact, is a critical parameter but is difficult to control due to micro-loading effects, among others. In this paper, we present the study of the W etch rate as a function of different masking materials: Ti/TiN and SiO. In addition, the impact of the W grain boundary orientation on the etch rate is established. With the use of a SiO masking layer, the W etch rate is 5 times higher as compared to the etching with a Ti/TiN masking film. The blanket W etch rate is the average of these two values. The observed differences will be discussed in terms of different polymerization and changing plasma composition (O-atoms) when using different masking materials. The difference in etch rate between blanket Tungsten and W plugs may also be explained in terms of the change in grain boundary orientation in both cases: while for the blanket etch, the boundaries are parallel to the etch direction, in the plug, the grain boundaries are rotated over 90 and are exposed orthogonal to the etch plasma. To investigate any possible impact, contact boles were defined in W films. After removal of the oxide hardmask, the contacts were filled using a second blanket Tungsten deposition. In this way, both ways of orientation are exposed to the plasma on the same wafer without interference of other materials present. The etch rates were determined for two different etch plasma setups. In a SF6/Ar plasma with a highly anisotropic component due to the ion bombardment, no difference in etch rate was observed. In a more isotropic pure SF6 plasma there is a slight difference between the two orientations where the etch rate of the second Tungsten layer (orthogonal grain boundaries) is slightly higher.

K6.5 
ENHANCEMENT OF ELECTROMIGRATION RESISTANCE IN ALUMINUM THIN FILMS BY PACVD Al/SPUTTERED Cu BILAYER, Byung-Yoon Kim, Dong Chan Kim, Byung-ll Lee, Seung-Ki Joo, Seoul National Univ, Dept of Metallurgical Engr, Seoul, SOUTH KOREA.

Recently, we have reported that planar metallization is possible by plasma assisted chemical vapor deposition (PACVD) technique. According to this new method, the plasma of which energy density is less than 6 mW/cm makes the nonselective deposition possible, while the conformal step coverage is maintained so that the planar aluminum metal surface can be obtained with the submicron contact holes plugged perfectly. Since only pure aluminum can be obtained from the pyrolysis of the DMEAA precursor, in this case, however, electromigration immunity remains as a possible problem. In this work, a thin layer of copper (14 nm) was deposited on top of the planarized PACVD aluminum and the electromigration test was performed. PACVD Al/sputtered Cu bilayer was annealed at 450C for one hour in a vacuum ambient before the accelerated electromigration test, where the specimen was heated at 240 C during the test and j was about 3 MA/cm. The top copper layer enhanced the electromigration resistance of both PACVD aluminum and the sputtered aluminum and PACVD aluminum showed much better MTF than the sputtered aluminum at least by one order of magnitude. Enhancement of the electromigration resistance in PACVD aluminum by the formation of Al/Cu bilayer will be discussed in detail in terms of grain boundary diffusion and alloy precipitation.

K6.6 
TUNABLE COVERAGE METALLIZATION DEPOSITION USING ION METAL PLASMA, Simon Hui, Ken Ngan, Applied Materials Inc, PVD Division, Santa Clara, CA; Barry Hogan, Gonga Yao, Applied Materials Inc, PVD Div, Santa Clara, CA; Sesh Ramaswami, Applied Materials Inc, PVD Division, Santa Clara, CA.

Aluminum planarization is a low cost alternative process to CVD W for contact and via plug formation in semiconductor fabrication. In order to planarize the contacts or vias, a wetting layer is required. PVD Ti and TiN are widely used as the wetting layer and diffusion barrier in this application. As contact/via feature size shrinks, the major difficulty for Al planarization at the contact level is diffusion barrier deposition onto high aspect ratio features; for via processing, the major difficulty is the wetting layer deposition. Ion Metal Plasma (IMP) process provides directional flux of sputtered atoms required for coating high aspect ratio features. This process is based on conventional magnetron sputtering with the addition of a higher density, inductively coupled RF plasma, between the sputtering cathode and the substrate. Metal atoms sputtered from the cathode due to inert gas ion bombardment transit the RE plasma and become ionized, The metal ions can then be accelerated to the substrate by means of a low voltage DC bias. A key process parameter to measure is the bottom and sidewall coverage of the IMP Ti and TiN wetting layer. In this paper, the effects of the IMP process conditions on the coverage of the Ti and TiN wetting layer will be described. Wetting layer with the optimum coverage will be shown to give superior Al planarization for subhalf micron vias. Moreover, Al film deposited on this wetting layer will be shown to have high reflectivity and a stable crystal orientation.

K6.7 
GAS PHASE REACTION RATE CONSTANT OF CVD TUNGSTEN SILICIDE PROCESS, Yong-Kee Chae, Univ of Tokyo, Dept of Chemical System Engr, Tokyo, JAPAN.

Kinetic studies on chemical vapor deposition of tungsten silicide (WSix) were made focusing on the gas phase reaction, using reduction of tungsten hexafluoride (WF) by silane (SiH). Tubular hot wall type CVD reactor was employed and the film growth rate profile in the reactor was mainly investigated by using Rutherford Backscattering Spectrometry (RBS) and Scanning Electron Microscopy (SEM). The flow rate of WF and SiH was controlled by thermal mass flow controller and Ar was also used as inert balance gas to control the total pressure and partial pressure of the reacting species. The experiments were performed in the temperature range of 120210C. We are assuming that deposition of WSix film proceeds via gas phase radical formation. The gas phase reaction rate constant to produce radicals is the key parameter for optimal design of WSix-CVD reactor. This gas phase rate constant was estimated by correlating experimental date with numerical calculations using Fluent. The obtained gas phase reaction rate constant can be expressed as kg = 2.4x10 exp ( 3.3x 10/T). The activation energy was 23 kJ/mol. We have also examined the gas phase rate constant with different total and partial pressure or different reactor diameter, resulting to have the same rate constant. The two-dimensional CVD reactor simulation using these kinetic information are now under study and part of those results will be discussed in the presentation.

K6.8 
PHONONS SPECTRA OF Mo-Si AND THEIR STRUCTURAL CHANGES FOR VARIED ANNEALING TEMPERATURES, Guangxu Cheng, Nanjing Univ, Natl Lab of Solid State Microstructures, Nanjing, CHINA; Yu-Ping Zhou, Chun-Lie Chen, Nanjing Univ, Ctr of Materials Analysis, Nanjing, JAPAN; Jian-Nian Li, Nanjing Univ, Electrical Devices Inst, Nanjing, CHINA.

The phonons spectra of molybdenum silicides had been studied by using Raman spectroscopy and their structures have been examined by x-ray diffraction for different anneal temperatures (383 1244 K), with the resulting structure changes. It is clear that there are a sensitivity range for the microstructures varied, for 973 K, it only depends on the c-Si and Mo thickness were domained by hexagonal phase, and the Raman intensity of lower wave number is stronger than modes of higher frequency. According to the Marker model, it is a preliminary interpreted that the ''MoSi pest'' occur at the top of MoSi layer. In the case of MoSi, a mixture of hexagonal and tetragonal phase were found after annealing at 933 K. The tetragonal phase MoSi and MoSi, at higher temperature (>1113 K) results in further growth of Mo or MoSi. It can be noted that the low phonon vibration had been presented, it is good reflected that the structures of molybdenum silicides are incident, too. Data of x-ray have been given together.