National Renewable Energy Laboratory
Golden, CO 80401-3393
dpiX, A Xerox Co
Xerox Palo Alto Research Center
Palo Alto, CA 94304
Dept of Interface Physics
Utrecht, 3508 TA NETHERLANDS
Dept of Innovative & Engr Matls
Tokyo Inst of Technology
Graduate School at Nagatsuta
Yokohama, 227 JAPAN
Dept of Electrical Engr
B422 Engineering Quad
Princeton, NJ 08544
*AKZO Chemicals, Inc.
*dpiX, Xerox Company
*Electric Power Research Institute (EPRI)
*Fuji Electric Corporate Research & Development, Ltd.
*Mitsui Chemical Co., Ltd.
*Sanyo Electric Co., Ltd.
1998 Spring Exhibitor
Proceedings published as Volume 507
of the Materials Research Society
Symposium Proceedings Series.
* Invited paper
STA: AMORPHOUS SILICON MATERIALS AND DEVICES FOR LARGE-AREA ELECTRONICS
Monday, April 13, 8:30 a.m. - 4:30 p.m.
Hydrogenated amorphous silicon (a-Si:H) is an important technological material for large-area electronics, with applications to solar cells, liquid crystal displays, optical scanners, and radiation imaging. The course describes the growth, material properties, device physics and large-area- array technology of amorphous silicon. The relation between material properties and device performance of a-Si:H is emphasized.
Robert A. Street
, Xerox Palo Alto Research Center
, dpiX, A Xerox Company
8:30 AM *A1.1/B1.1
SESSION A1/B1: JOINT SESSION:
AMORPHOUS AND POLY-Si TFTs
Chair: Ruud E.I. Schropp
Tuesday Morning, April 14, 1998
HYBRID AMORPHOUS AND POLYCRYSTALLINE SILICON DEVICES FOR LARGE-AREA ELECTRONICS. Ping Mei
, James B. Boyce, David K. Fork, Greg Anderson, Xerox Palo Alto Research Center, Palo Alto, CA; Mike Hack, Rene Lujan, Xerox dpiX, Palo Alto, CA.
A natural extension of active matrix technology is the monolithic integration of peripheral drivers for the improvement of reliability, cost reduction and compactness of large-area electronics. This goal has been approached three ways, namely through large area polysilicon, amorphous silicon peripheral circuit design, and a mix of amorphous silicon pixel switches and polysilicon drivers. For some unique applications, we have developed the third approach to exploit the positive qualities of both amorphous and polysilicon in an intimate monolithic mix analogous to CMOS. Our process is a simple modification of the amorphous silicon transistor process which uses selective area laser crystallization. This approach allows us to share many of the process steps involved in making both the amorphous and polysilicon devices. The first major challenge which has arisen in this work relates to controlling the hydrogen evolution during the selective crystallization. The second major challenge was identifying a common gate insulator for both devices which would provide adequate control of the threshold voltage. Both issues will be addressed in the presentation.
9:00 AM A1.2/B1.2
a-Si:H THIN-FILM TRANSISTORS ON ROLLABLE 25-m THICK STEEL FOIL. Eugene Y. Ma
and Sigurd Wagner, Princeton University, Department of Electrical Engineering, Princeton, NJ.
Stainless steel has proven to be a substrate material that is surprisingly compatible with a-Si:H TFTs made from standard processing techniques even though the coefficient of thermal expansion for steel is 5 times that of a-Si:H. After deposition, the thin films comprising the TFT structure are forced to follow the thermal contraction of the much thicker substrate. We have observed, however, that a-Si:H TFTs fabricated on 25 m thick steel foil substrates are highly insensitive to the resulting strain. This evidence is obtained from evaluation of the electrical performance of these devices as a function of mechanical stress introduced by controlled bending.
The TFTs were made in the inverted-staggered, back-channel etch configuration with 120 nm thick Cr gate electrodes, 320/160/50 nm PECVD SiN gate dielectric, a-Si:H channel, and n+
a-Si:H contact layers, respectively, and finally 120 nm Cr source/drain contacts, all on top of spin-on-glass (SOG) planarized steel foil with an additional SiN layer. The maximum process temperature is 350ºC used for the gate nitride. The resulting TFTs-on-steel can be rolled facing-in or facing-out to radii as low as 3 mm with only small drifts in TFT performance. In fact, at smaller radii of curvature the devices fail mechanically, peeling off at the SOG/nitride interface, before failing electrically. We show that under our bending tests, the mechanical stress can be made equal to the stress from differential contraction, and we will describe and analyze the results of electrical and mechanical tests as a function of substrate bending.
Taking advantage of the flexibility and resiliency of these devices, we have fabricated TFTs using only xerographic toner masks printed directly on to the substrate. We have succeeded for the first time in overlay aligning each of the four mask levels in the laser printer, and will describe this novel process in detail.
9:15 AM A1.3/B1.3
SURFACE REACTIONS FOR LOW TEMPERATURE (110ºC) AMORPHOUS SILICON TFT FORMATION ON TRANSPARENT PLASTIC SUBSTRATES. G.N. Parsons
, C.S. Yang, C.B. Arthur, T.M. Klein, A.I. Chowdhury, and L.L. Smith, Department of Chemical Engineering, North Carolina State University, Raleigh, NC.
This paper describes initial results of chemical mechanisms for good quality low temperature amorphous silicon thin film transistor fabrication on transparent plastic substrates. Inverted-staggered TFTís formed in our lab on PET at a maximum process temperature of 110ºC have linear mobility of 0.11 cm2
/Vs, on/off ratio > 106
, off current <10-12
Amps, good quality n+ contacts, and minimal gate leakage. Silane/hydrogen mixtures were used for a-Si:H deposition. Mass spectroscopy and infrared transmission show that at temperatures between 250ºC and room temperature, H abstraction and etching reduce H content and control SiH/SiH2
ratio. Silicon nitride film quality is predominantly sensitive to Si-H/N-H bond density ratio, and materials with optimized bonding can be formed with N2
/He plasmas with H content 20 at. at 110ºC. The process is sensitive to temperature because N-H bond formation proceeds through a thermally activated surface reaction. Using ammonia, the process is less sensitive to temperature, but H contents are about a factor of 2 larger. When smooth glass substrates are used instead of PET to form TFTís at 110ºC, an improved mobility is observed (0.33 cm2
/Vs). Scanning force microscopy shows rms roughness of 4 to 5 nm on PET, compared to <1 nm for glass. Progress toward TFT formation on other plastic substrates will be presented.
9:30 AM A1.4/B1.4
STEPPED GATE POLYSILICON THIN FILM TRANSISTOR FOR LARGE AREA POWER APPLICATIONS. J. Aschenbeck
, Department of Engineering, University of Cambridge, Cambridge, UNITED KINGDOM; Y. Chen, Department of Electrical Engineering & Electronics, University of Liverpool, Liverpool, UNITED KINGDOM; F. Clough, Y.Z. Xu, E.M. Sankara Narayanan, all from Emerging Technologies Research Centre, De Montfort University; W.I. Milne, Department of Engineering, University of Cambridge, Cambridge, UNITED KINGDOM.
The standard polysilicon (poly-Si) High Voltage Thin Film Transistor (HVTFT) technologies currently available have a range of limitations. The Offset Drain (OD) HVTFT structure has a low on current . Metal Field-Plate (MFP) HVTFT structures have and excellent on/off current ratio of 6 orders but require an additional bias connection to drive the metal field plate. MFP HVTFTs also have a modest blocking capability defined by the electric field peaks which arise at the edges of the MFP due to discontinuities in the bias voltages . The magnitude of this peak field is a function of the field oxide thickness. More recently we demonstrated a HVTFT structure with a Semi-insulating field plate . The SI HVTFT has a blocking capability in excess of 250 V but a switching speed which is limited by the rate at which the SI layer can be charged and discharged. In this paper we propose a new Stepped Gate (SG) HVTFT structure with a much improved switching performance relative to the SI HVTFT. The field oxide in the offset region is stepped to define two field oxide thicknesses. A MFP is connected to the polysilicon gate and covers both levels of the stepped field gate oxide. The result is a 3 terminal TFT structure with a field oxide thickness which becomes progressively thicker from source to drain. 2-D numerical simulation has been used to model both the dc (on/off ratio, blocking voltage) and transient performance of the device. The thicker field oxide near the drain results in a reduced peak field and a good device blocking capability. The Silvaco Atlas Device Simulation tool has been used to model the transient response times. The simulated transient response times are comparable to those of 4 terminal MFP structures. The on/off ratio is as good as in the SI Device. There is still a trade-off between on-current and device blocking capability which has to be considered. This has been optimised by simulations.
9:45 AM A1.5/B1.5
TRANSISTORS WITH A PROFILED ACTIVE LAYER MADE BY HOT-WIRE CVD. H. Meiling
, A.M. Brockhoff, J.K. Rath, and R.E.I. Schropp, Debye Institute, Section Interface Physics, Utrecht University, Utrecht, THE NETHERLANDS.
We report on thin-film silicon based transistors, TFTs, in which the channel material is deposited with the hot-wire chemical vapour deposition (hot-wire CVD) technique. Recently, we showed that with hot-wire CVD deposition rates for hydrogenated amorphous silicon, -Si:H, close to 20 Å/s can be achieved while maintaining good material and TFT properties. Also, these TFTs did not show any shift of the threshold voltage upon 1.5 h of gate bias stress, in contrast to conventional, plasma-deposited -Si:H TFTs. In this study we compare the behaviour of hot-wire deposited thin-film silicon transistors, in which the structure of the material changes from purely amorphous to completely polycrystalline silicon (poly-Si:H). We present the transfer characteristics before and after prolonged gate bias stress for up to 65 h. We also show cross-sectional transmission electron microscopy images of the semiconductor/insulator interface, and correlate the observed structures with results on crystallinity from Raman spectroscopy measurements. By diluting silane with hydrogen during hot-wire CVD a wide range of (profiled) materials can be made. With silane only, -Si:H is obtained, whereas when a mixture of silane and hydrogen is used, a 50-nm amorphous incubation layer is present in a furthermore completely poly-Si:H layer. Only at a very high hydrogen dilution of the silane gas we observe a completely poly-Si:H active layer, and the occurrence of the incubation layer at the interface is avoided. The poly-Si:H transistor with the -Si:H incubation layer did not show any threshold voltage shift, even after 65 h of gate bias stress. We suspect that the incubation layer is a heterogeneous layer with nanocrystalline domains. The fully -Si:H TFT showed a minor shift of 1.5 V after 65 h. A reference plasma-CVD -Si:H TFT showed a threshold-voltage shift of 8 V in the same time-frame.
10:15 AM *A2.1/B2.1
SESSION A2/B2: JOINT SESSION:
AMORPHOUS SILICON AND PROCESSING
Chairs: Ruud E.I. Schropp and Chuang Chuang Tsai
Tuesday Morning, April 14, 1998
HIGH CONDUCTIVITY GATE METALLURGY FOR TFT/LCD*s. Peter M. Fryer
, IBM Research Division, Yorktown Heights, NY.
Amorphous silicon based thin film transistor liquid crystal displays (TFT/LCD) have become the dominant technology used for flat panel displays for notebook computers. The need for higher resolution, larger diagonal displays for both notebook and desktop applications will be discussed. Currently used materials and processes are not always extendible as resolution and display size increase, and efforts to replace them can lead to substantial increases in manufacturing cost. Calculations have shown that the use of high conductivity gate metal, together with the implementation of improved groundrules, can significantly extend today's technology. For example, high conductivity gate metal such as aluminum and copper are highly desirable, but they are difficult to implement. Aluminum suffers from problems with hillock formation during PECVD processing, and copper typically has poor adhesion to glass, reaction problems with silicon and other PECVD films, and difficulties in contacting it to other metals. Approaches to solving problems with both materials will be presented, and a typical TFT fabrication process incorporating these materials described.
10:45 AM A2.2/B2.2
TFT-LCD FABRICATION TECHNOLOGY FOR DESKTOP MONITORS. C.W. Kim
, C.O. Jeong, M.K. Hur, J.H. Souk, AMLCD Division, Samsung Electronics, Kiheung, Kyungkido, KOREA.
As the notebook PC market is saturated, the TFT-LCD panel makers are looking for the new area and the desktop monitor market is the best candidate. Compared to notebook panels, monitors require large size panel fabrication and driving technology. Longer signal lines for large size panel affect the RC time delay of the signal. Low resistance materials are reviewed for gate line and data line materials. Properties of Al-alloy thin films as well as the fabrication technology of large size TFT panels are discussed. By using the Al-alloy metallization technology, high resolution and large size TFT-LCD monitors are realized.
11:00 AM A2.3/B2.3
CONTROLLED CRYSTALLIZATION BY SHORT PULSE LASER INTERFERENCE STRUCTURING OF AMORPHOUS SI FILMS ON GLASS. Silke H. Christiansen
, Martin Albrecht, Horst P. Strunk, Uni Erlangen, GERMANY;. Christoph E. Nebel, Berit Dahlheimer, Martin Stutzmann, Walter Schottky Institut, TU Muenchen, GERMANY.
We analyze by transmission electron microscopy, scanning electron microscopy and laterally resolved Hall measurements the relation between grain boundary distribution (i.e. grain boundary type and distribution) and electronical properties (mobility) of laser crystallized amorphous Si Layers deposited on glass substrates. The amorphous layers are crystallized by a frequency doubled Nd:YAG laser using the following three approaches: (i) short-pulse laser crystallization with two-beam and three-beam interference (interference structuring); (ii) generation of seed arrays based on interference structuring and subsequent thermal annealing for 12 hrs. at 650ºC; (iii) scanning the surface within multiple pulses using interference structuring result in forced growth of grains from the rim of the melted structures where nanocrystals of all orientation reside, to the centre. These grains are single crystalline with preferential orientations (fast growth directions <110> and <112>) and show a low defect density. Evaluation of the grain boundary types from electron backscattering pattern (EBSP) investigations and electron diffraction patterns reveal (i) a high amount of twin related tilt boundaries for the seeded growth experiments; (ii) the typical leaf-like structure for the thermally annealed material; (iii) a drastically increased crystal size for the scanning experiments.
11:15 AM A2.4/B2.4
SURFACE PLANARIZATION AND TEXTURE ENGINEERING OF THIN Si FILMS PREPARED VIA SEQUENTIAL LATERAL SOLIDIFICATION. M.A. Crowder
, Robert S. Sposili, and James S. Im, Program in Materials Science, School of Engineering and Applied Science, Columbia Univ., New York, NY.
The sequential lateral solidification (SLS) is a low-temperature excimer-laser crystallization process which can create large, location-controlled single-crystal regions in as-deposited amorphous or polycrystalline silicon films on SiO2
[Appl. Phys. Lett. 70
In this paper, we report on morphological and microstructural characteristics of the resulting SLS processed material, with particular emphasis on (1) improving the surface topology of the crystallized areas and (2) inducing constrained crystallographic textures in the single-crystal regions. The surface of the crystallized areas, examined using profilometry and atomic force microscopy (AFM), is found to be smooth on a microscopic scale, with gentle undulations (e.g., approximately 50 Å amplitude with a spatial period of several microns, for 2000 Å-thick films).
It is found that these minor undulations can be further reduced by SLS of silicon films with a thick capping oxide layer. Additionally, we show that it is possible to preselect the texture of the single-crystal regions through ``seeding'' by inducing development of restricted crystallographic textures through multiple-pulse-induced-grain-growth of the film -- attained by irradiating at near-complete melting conditions -- prior to SLS.
11:30 AM *A2.5/B2.5
RECENT PROGRESS OF LOW TEMPERATURE POLY-SI TFT TECHNOLOGY. Kiyoshi Yoneda
, LCD Division, Sanyo Electric Co. Ltd., Osaka, JAPAN.
Currently, LCD manufactures pay a considerable effort toward the establishment of production technology in low temperature poly-Si TFTs because it promises to produce higher premium TFT LCD management on behalf of a conventional amorphous TFT LCD. In order to achieve a high yield in production, however, low temperature poly-Si technology must overcome a number of significant production challenges. In this article, we will submit the existing subjects of low temperature poly-Si technologies especially, CVD, ELA, and ion doping processes and discuss their recent progresses.
1:30 PM *A3.1
SESSION A3: COLOR AND X-RAY SENSORS
Chair: Rodrigo Martins
Tuesday Afternoon, April 14, 1998
ACTIVE MATRIX FLAT-PANEL IMAGERS (AMFPIs)-A POTENTIALLY DOMINANT TECHNOLOGY FOR MEDICAL X-RAY IMAGING IN THE 21ST CENTURY. Larry E. Antonuk
, Youcef El-Mohri, University of Michigan Medical Center, Department of Radiation Oncology, Ann Arbor, MI.
After approximately ten years of intensive development, the technology of active matrix, flat-panel imagers (AMFPIs) is at the threshold of routine clinical use for a wide variety of applications including general radiography, fluoroscopy, mammography, and radiotherapy imaging. the imagers are based on two-dimensional a-Si:H arrays with pixels consisting of a thin-film transistor coupled to a p-i-n photodiode. They are operated in conjunction with a scintillating material such as a phosphor screen or CsI positioned over, or deposited on the array surface, and are read out by means of gate drivers and preamplifier-multiplexer-ADC electronics. The technology allows capture of both individual images (radiographic mode) as well as real-time imaging at 30 frames per second (fluoroscopic mode). Practical, large area devices have been reported with pixel pitches extending down to 97 m. AMFPIs offer numerous advantages over existing technologies including a large field of view (up to 30x40 cm2
presently), real-time digital readout, high-quality images free of distortion, glare, and processor artifacts, compact packaging, and large dynamic range. Furthermore, the very high optical transfer efficiency of these devices facilitates excellent signal-to-noise properties leading to the definite potential of improved image quality at reduced dose for some applications. In this presentation, the present state of the technology will be summarized, and the intrinsic properties of the imagers will be reviewed. Medical imaging examples illustrating properties of the underlying a-Si:H technology and highlighting the advantages over conventional medical x-ray imaging systems will be presented. Finally, prospects for the future evolution of this potentially dominant technology will be discussed.
2:00 PM A3.2
A NOVEL ROOM TEMPERATURE INFRARED DETECTOR USING MICROCOMPENSATED AMORPHOUS SILICON. D. Caputo, G. de Cesare, A. Nascetti, F. Palma
, Department of Electronic Engineering, University of Rome ``La Sapienza'', Rome, ITALY.
In this paper we present a new a-Si:H structure, which allows detection of infrared light through capacitance measurement at room temperature. The device is a p-c-n
structure, where the internal absorber c
layer indicates a-Si:H compensated material, with very low concentrations of phosphorous and boron atoms. Infrared radiation causes transitions from extended states in the valence band to defects in the forbidden gap. This process does not give rise to a photocurrent, rather it changes defect occupancy and thus the electric field distribution. At room temperature this effect can be observed as variation of differential capacitance of the structure. We experimentally found that measured capacitance is sensitive to radiation from 900 nm up to 4 m. Capacitance measurements performed in the same condition on a p-i-n standard solar cell does not show any difference between dark condition nor under IR illumination. The different sensitivities of the p-c-n device and p-i-n structure to IR radiation, is ascribed to the different nature of defects in compensated and intrinsic materials. In particular, compensated materials are rich in defects which act as hole traps, while in intrinsic materials defects act mainly as recombination centers.
2:15 PM A3.3
STABLIZED THREE COLOR PIINIP SENSOR FOR HIGH ILLUMINATION CONDITIONS. D. Knipp
, H. Stiebig, H. Wagner, Forschungszentrum Juelich GmbH, Juelich, GERMANY.
The development of amorphous silicon based color detectors operating under high illumination conditions is of great interest for scanners, color copier and various kinds of outdoor applications. Only under high illumination fast color recognition can be realized, because the sensor peformance is limited by the transient photocurrent response, especially at low levels of intensity. The rise time of a-Si:H based detectors increases nearly linearly with decreasing illumination. On the other hand under high illumination conditions light induced degradation is more pronounced. Therefore, we have investigated the influence of light induced degradation on various two terminal devices like nipiin, piinip and piiin structures in order to develop a stabile three color detector. The best results are obtained for a piinip layer sequence. The novel detector is realized by two different i-layers in the top diode with decreasing optical bandgap from the p- to the n-layer in order to obtain a color separation of blue and green light. Red light is detected in the bottom diode. In order to achieve a high stability of the devices high optical bandgap materials using a gas mixture of silane and methane (a-SiC:H) is replaced by low temperature deposited a-Si:H (Ts =140-160ºC) using high hydrogen dilution (10-30) and low bandgap materials based on a-SiGe:H alloys is substituted by c-Si:H, respectively. These materials exhibit a reduced defect creation under light exposure. The novel two terminal device shows maxima of the spectral response at 470 nm (-0.1V), 520nm (-2.0V) and 630nm (+2.0V) and a dynamic range exceeding 85 dB. The dynamic as well as the color separation is not affected significantly after AM1.5 illumination of more than 100h. For different detector systems the influence of light induced degradation on the spectral response, the dynamic and the dark current will be discussed.
2:30 PM A3.4
MATERIAL ASPECTS OF A-SIN:H BASED 2D DIRECT X-RAY SENSOR ARRAY. I. Popov
, G. Van Doorselaer, A. Van Calster, H. De Smet, Univ. Ghent, ELIS-TFCG/IMEC, Ghent, BELGIUM; E. Boesman, F. Callens, Univ. Ghent, CSSS, Ghent, BELGIUM.
Recent developments in a cost effective 2D direct X-ray sensor array on the base of a-SiN:H Thin Film Diodes (TFDs) [1,2] lead to the necessity of careful understanding of the behavior of a-SiN:H films under X-ray irradiation. `Direct sensing' means that there is no intermediate layer to convert the incoming x-ray irradiation into a less energetic one. In other words we are using the same medium (atomic network) for the absorption of the incoming high energy x-ray photons and conversion of the signal into the electrical form. The closest example of such approach is the electroradiographic plates on the base of amorphous Se (from the point of view of the medium, not the strategy of image creation and reading out). This material exhibits higher efficiency in x-ray absorption but the major drawback is its insufficient stability which follows from its structural network. Another approach is to separate the medium responsible for the x-ray absorption and the medium responsible for the electrical signal delivery. In the latter case each medium can be optimized separately. In our case this is not working, the a-SiN:H TFD must be optimized taking into account all requirements, which, sometimes, contradict each other. This will include optimization of the a-SiN:H thin films and TFD technology processing. There are three major issues in the optimization of the sensing TFD: (i) increase of the response current; (ii) decrease of the ìoffî -state current; (iii) lifetime. Means that are employed for achieving this optimization include a-SiN:H technology processing (such as N, H concentration; doping), metals used for the top and bottom electrodes of the TFD, design of the TFD.
2:45 PM A3.5
PROCESS INTEGRATION OF a-Si:H SCHOTTKY DIODE AND THIN FILM TRANSISTOR FOR LOW ENERGY X-RAY IMAGING APPLICATIONS. Byung-kyu Park
, Koorosh Aflatooni, Murthy Rambhatla, and Arokia Nathan, Electrical and Computer Engineering Department, University of Waterloo, Waterloo, Ontario, CANADA.
Recently (IEDM 1997), we reported the design and the fabrication of a direct-conversion x-ray detector based on Mo/a-Si:H Schottky diode for large area imaging of low energy x-rays. In this diode, the interaction of x-ray photons with Mo leads to injection of high energy electrons, by virtue of the photoelectric effect, into a reverse-biased a-Si:H depletion layer, where electron (avalanche) multiplication yields a gain. The pixel operates at low bias voltage (<4V) with a sensitivity of 0.2-2.7*108
electrons over an x-ray range of 40-100 kVp.