1998 MRS Spring Meeting & Exhibit

Chairs 

Derek Houghton
SiGe Microsystems Inc
Bldg M50 Ste A06
Ottawa, ON K1A 0R6 CANADA
613-748-1334

1998 Spring Exhibitor 

* Invited paper

SESSION FF1: TECHNOLOGIES AND DEVICES 
Chairs: Derek C. Houghton and Andrew T. Hunter 
Monday Morning, April 13, 1998 
Golden Gate C3

8:30 AM *FF1.1 
SiGe RF-ELECTRONIC: DEVICES, CIRCIUTS, COMPETITORS, MARKETS. Ulf König, Daimler Benz Research, Ulm, GERMANY. 

The turnover of microeletronic devices and circuits is rapidly growing form $45 billion in 1990 to $77 in 1993 over $154 in 1995 to about $350 billion in 2000. Si dominates with 97% over III/V. This trend was on motivation to develop superior Si-based heterodevices. SiGe heterobipolar tranisistors (HBTs), SiGe heterofieldeffect transistors (HFETs or MODFETS) and SiGe heteroCMOS (HCMOS) fit best into the respetive Si markets. The accessible market share will depend on cost- and performance advantages. As SiGe needs no new fab and can use large Si wafers the high volume chip price of $0.12/mm² does not differ essentially from $0.09/mm² for Si, while respective GaAs-ICs cost more than $0.5/mm². Outstanding performances have been demonstrated for SiGe HBTs, e.g. high current gains 400-5000, ideal Gummel plots, high frequencies f_t-116 GHz, f_max=160 GHz, low noisse F_min <0.5dB at 2 GHz and <0.9dB at 10 GHz, low l/f noise f_c < 300Hz, high power added efficiency PAE=72% at class A/B, 11-20 ps for ECL-ring oscillators, 12 bit DAC at 1 GHz, AMPs capable of 9.5 dB with 18 GHz bandwidth, VCO and DRO for 4-10 GHz with low phase noise of -135 dBc/Hz 10kHz off, LNAs with F_min of 1.7 dB. A comparison with datas of III/V HBTs will be presented. Promising results already have been obtained for SiGe HFETs, e.g. high transconductances of 500 mS/mm for n-type and 300 mS/mm for p-type devices, high currents of 300-700 mA/mm, high frequencies f_t=50 or 70 GHz for p or n-type, f_max=95 GHz, inverter delays of 22 ps, AMPs with a high gain of 70 dBQ. Low cost high performance SiGe-ICs are best suitable for the high volume communictation markets at the beginning of the next century, like for mobile phones operating at 1-2 GHz, for wireless local area networks at 2.4-5.8 GHz, for 10-14 GHz broadband satellite user terminals and for cable and fibre transmission at 3-40 Gbit/s, later even for applications at higher frequencies. 

9:00 AM *FF1.2 
APPLICATION OF SiGe HBT's TO DATACOM AND WIRELESS. Robert Hadaway, Peter Schvan, Sorin Voinigescu, Yuriy Greshishchev, Nortel, Ottawa, CANADA; Piers Dawe, Nortel, Harlow, ENGLAND. 

After many years of research, development, speculation and controversy, SiGe heterojunction bipoIar transistor (HBT) technology is posed to emerge in a diverse range of products. SiGe technology is being implemented in a number of different forms, but one thing is certain; epi base technology, including SiGe, is the next stop on the bipolar / BiCMOS technology roadmap. SiGe technology promises cost and performance advantages over currently entrenched technologies in wireless and high-speed data communications. Our experience suggests that enhanced performance alone is not sufficient to unseat these incumbent technologies. However, the combination of high-speed and large wafer size, narrow linewidths, large densities, high yield and low cost provided by mainstream silicon manufacturing, leads to a high-performance, low-power capability for implementing systems-on-a-chip. The presentation will begin with a review of the performance characteristics of the availablee componentry. The essencee of good high-performance design is rooted in representing these components with accurate models, and as such, examples of passive and active modelling will be discussed. Finally a selection of data and wireless circuit blocks will be described to demonstrate the high-performance, flexible nature of SiGe HBT technology. World class performance ranging-up to 21GHz for darlington amplifiers and 20 GB/s for complex datacom circuits will be revealed in the context of highly integrated systems. 

9:30 AM *FF1.3 
TOWARD RF SYSTEM-LEVEL INTEGRATION: PROCESS INTEGRATION ISSUES IN SIGE BICMOS. G. Freeman, K. Schonenberg, D. Ahlgren, S-J. Jeng, D. Nguyen-Ngoc, K. Stein, D. Colavito, S. Subbanna, D. Harame; IBM Microelectronics Division, Hopewell Junction, NY. 

The SiGe HBT appears to be the most viable device to enable the goal of RF systems on a chip. It has been demonstrated that this device has the potential to replace the standard GaAs front-end of RF systems, but with greater potential for large-scale integration and reduced cost available from Si technologies in 200mm wafers. However, the SiGe HBT can only be part of a large-scale RF system on a chip when, in the same technology, NFETs and PFETs are provided for low power, low frequency digital logic, and a suite of resistors, capacitors, diodes, and inductor passive elements are provided for the high frequency analog circuitry. Furthermore, all these elements must be manufacturable defect-free at medium and high levels of integration. This paper covers key process integration issues confronting technologists when integrating a SiGe HBT device with the requisite CMOS and passive elements and at the same time maintaining very high GaAs-like performance. Principle among these issues is to start with a modular process design where the CMOS devices may be optimized independently of the HBT. Equally important is that the base growth technique and B and Ge base profile must be compatible with the large-scale integration yield and performance objectives. To this end, discussion of the epitaxial SiGe film integration with CMOS devices, the epitaxial growth technique, and the Ge profile are presented. In addition, crystal defect formation and propagation as a function of Ge content, device area, and isolation stress are reviewed. Integration issues and tradeoffs of passive devices for RF systems on a chip will also be addressed. Status of the IBM SiGe BiCMOS technology will be presented to illustrate the first successful integration of this set of devices into a manufacturable process. 

10:30 AM *FF1.4 
CARRIER TRANSPORT AND VELOCITY OVERSHOOT IN STRAINED SI ON SIGE HETEROSTRUCTURES. David K. Ferry, Dragica Vasileska, Arizona State University, Department of Electrical Engineering, Tempe, AZ; Gabriele Formicone, Motorola, Mesa, AZ. 

The use of strained Si, grown heteroepitaxially on a relaxed SiGe ìsubstrateî creates a heterostructure in which carriers can be confined within quantum wells of the strained Si. Many laboratories around the world have been studying this structure, and quite high mobilities are obtained at low temperatures. We have carried out ensemble Monte Carlo studies of the transport of both electrons and holes in the strained Si and have simulated devices fabricated on this heterostructure. Here, we discuss the overshoot that occurs in the strained Si, its sources, and the similarities and differences expected from the effect observed in various III-V compounds. We estimate the performance advantages that strained Si devices can accrue in the sub-0.1 micron regime. 

11:00 AM FF1.5 
CHARACTERISTICS OF SURFACE-CHANNEL, STRAINED  N-MOSFETS. K. Rim, T.O. Mitchell, J.L. Hoyt, and, J.F. Gibbons, Solid State Electronics Laboratory, Stanford University, Stanford, CA; G. Fountain, Research Triangle Institute, Research Triangle Park, NC. 

The first demonstration of n-MOSFETs fabricated using strained  surface channels is reported. Due to the biaxial tensile strain,  epitaxial layers grown pseudomorphically on Si are expected to have a conduction band edge energy splitting analogous to strained Si grown on relaxed . Because of the reduced intervalley scattering associated with this conduction band energy splitting, n-MOSFETs employing strained Si channels exhibit enhanced in-plane electron mobility. In the absence of additional scattering mechanisms, enhanced electron mobility may thus be expected for strained  alloys grown on Si. In this work, tensile-strained  layers with substitutional carbon contents up to 0.8 atomic percent were epitaxially grown on <100> Si substrates by rapid thermal chemical vapor deposition, using silane and methylsilane as the silicon and carbon precursors. n-MOSFETs were fabricated using standard MOS processing with reduced thermal exposure to minimize the possibility of strain relaxation. A remote plasma CVD oxide was employed to form the gate oxide. 
The  devices exhibit electrical characteristics that are typical for Si n-MOSFETs, with excellent turn-on and sub-threshold characteristics. MOS capacitance-voltage analysis performed at 100, 200, and 295K demonstrates comparable oxide interface qualities for the  and Si control devices, and indicates the absence of parasitic hole or electron confinement in the epitaxial layer structures. No carbon-related leakage current is observed in source and drain diode junctions. Characterization of the MOSFET electron inversion layer mobility at room temperature shows comparable mobilities, within the sensitivity of the measurement, for the  and Si control devices. This is in contrast to the mobility enhancement observed in n-MOSFETs fabricated using tensile-strained Si grown on relaxed  layers. At low temperatures, the inversion layer mobility of  devices is lower than that of the Si controls, and appears to be affected by additional Coulomb scattering. 

11:15 AM FF1.6 
GROWTH OF SIGE ESAKI DIODES BY MOLECULAR BEAM EPITAXY. P.E. Thompson, K. Hobart, F. Kub, Naval Research Laboratory, Washington, DC; J. East, G. Haddad, Solid State Electronics Laboratory, University of Michigan, Ann Arbor, MI. 

By employing our knowledge of Si and Ge molecular beam epitaxy, we have been able to grow a hyperabrupt n-p junction inside of a SiGe quantum well. These structures have been fabricated into the first SiGe Esaki diodes. During the growth of this structure, great care had to be taken to prevent strain relaxation of the SiGe quantum well and have minimal segregation of the dopants, while maintaining high quality epitaxial growth. The Si buffer layer and the p+ contact layer were grown at 650 ^oC. Reduced temperature epitaxy at 400 ^oC was used for the SiGe quantum well. In the center of the well, a growth pause was initiated for the build-up of Sb in the center of the well. After the formation of the p-n junction the temperature was further reduced to 350 ^oC for the growth of the n+ contact layer. The samples were fabricated into Esaki diodes at the University of Michigan. At room temperature the peak current was 27 mA and the valley current was 3.4 mA for a peak to valley ratio of 7.9. The peak current density of the Esaki diode was 4x10⁴ A cm^-2. The integration of the Esaki diodes with heterojunction bipolar transistors (HBTs) shows great promise for ultrafast, monolithic digital integrated circuits, with special emphasis on multivalued logic. This work was sponsored by ONR and the DARPA ULTRA Electronics Program. 

11:30 AM FF1.7 
CHARACTERIZATIONS OF Zr/Si_1-x-yGe_xC_y AFTER RAPID THERMAL ANNEALING. V. Aubry-Fortuna, M. Barthula, F. Meyer, Institut d'Electronique Fondamentale, Université Paris Sud, Orsay, FRANCE; A. Eyal, C. Cytermann, M. Eizenberg, Solid-State Institute, Technion, Haifa, ISRAEL; O. Chaix-Pluchery, LMPG, CNRS UMR, St. Martin d'Hères, FRANCE. 

Their low resistivity make Zr and Ti silicides of great interest for applicatons in very large scale integrated (VLSI) circuits. Nevertheless, the solid-state reaction of Ti with Si_1-xGe_x alloy at high temperature leads to a germanosilicide with a Ge-content lower than in the as-deposited layer. As a matter of fact, this induces a Ge segregation at the interface. A previous study has shown that the final compound of the reaction between Zr and Si_1-xGe_x relaxed layers (x = 0.17 and 0.33) is the C49 Zr(Si_1-xGe_x)₂ phase. We did not observe any Ge segregation or any formation of a Ge-rich SiGe layer, even after heat treatment at 800ºC. In this study, we have extented our investigations to pseudomorphic Si_1-x-yGe_xC_y epilayers. Annealings are realized in a RTA furnace under Ar/H₂ atmosphere. The phase formation was followed by Rutherford Backscattering Spectrometry, X-Ray diffraction and sheet resistance measurements. Four crystal X-Ray diffraction was performed to measure the residual strain and the lattice parameters of the unreacted SiGeC layer. Secondary lon Mass Spectroscopy was utilized to determine the depth distribution of Zr, Si, Ge and C. A rather small relaxation has occured in the SiGe layer after annealing at 800ºC. With the presence of C. no relaxation was detected, but the perpendicular lattice parameter increased suggesting a lost of the C onto substitutionnal sites. In addition, we have studied the electrical properties of the Schottky barrier height as a function of the annealing temperature. The Schottky barrier height on p-type is decreased by the formation of the germanosilicide. Schottky barrier height behaviour versus Ge-content and C-content will be also shown. 

11:45 AM FF1.8 
ANALYSIS OF SiGe FET DEVICE STRUCTURES ON SILICON-ON-SAPPHIRE SUBSTRATES BY X-RAY DIFFRACTION. P.M. Mooney, J.A. Ott, J.O. Chu, J.L. Jordan-Sweet, B.S Meyerson, IBM T.J. Watson Research Center, Yorktown Heights, NY; W.B. Dubbelday, I. Lagnado, Navy SPAWARSYSCOM Div. San Diego, CA; K.L. Kavanagh, ECE Dept. Univ. of CA at San Diego, La Jolla, CA. 

Silicon CMOS on sapphire is one of the oldest silicon on insulator technologies and has excellent microwave characteristics. CMOS devices, which include a strained SiGe layer as the active channel, have been sucessfully fabricated on silicon-on-sapphire substrates (1,2). These device structures, grown epitaxially by UHV/CVD on improved silicon-on-sapphire substrates, consist of an initial Si layer followed by a 10 nm-thick Si_1-xGe_x layer and then a 15 nm-thick Si cap layer. There is a relatively high density of threading defects present in the original Si layer, and therefore also in the epitaxial layers, which causes mosaic broadening of the x-ray diffraction peaks. Despite this, the alloy composition, strain and thickness of each layer could be determined from high resolution x-ray diffraction measurements performed at Beamline X20A at NSLS at Brookhaven National Lab using a triple-axis configuration. By measuring device wafers before and after device fabrication, the net effect of the device fabrication processes, e.g. wafer cleaning, oxidation, and other heat treatments, on each layer was determined. As expected, the thickness of the Si cap layer was reduced by about 7 nm by wafer cleaning and gate oxidation. Significant strain-driven out-diffusion of Ge from the SiGe layer was also found to occur during device fabrication.

SESSION FF2: DEVICES, PROCESSING AND CHARACTERIZATION 
Chairs: Patricia M. Mooney and Stefan Zollner 
Monday Afternoon, April 13, 1998 
Golden Gate C3

1:30 PM *FF2.1 CONFINED BIEXCITONS, TRIEXCITONS, TETRAEXCITONS IN SIGE GROWN ON SI(001). Kai Shum, The City College of New York, Dept of Electrical Engineering, New York, NY; P.M. Mooney, and J. O. Chu, IBM T. J. Watson Research Center, Yorktown Heights, NY. 

We report experimental evidence for the existence of three-dimensionally (3D) confined biexcitons, triexcitons, and tetraexcitons in strain-relaxed SiGe layers grown on step-wise graded buffers on Si(001) substrates by ultra-high vacuum chemical vapor deposition. The 3D potential wells for the spatial confinement of polyexcitons originate from local alloy fluctuations. The potential well profile is important to selectively accommodate each type of exciton complex and it can be varied by isochronal annealing due to strain-driven inter-diffusion of Si and Ge. Evidence in support of the identification of these exciton complexes is the value of the slope of a log-log plot of the integrated photoluminescence intensity of biexcitons, triexcitons, and tetraexcitions vs. the integrated exciton photoluminescence intensity which was measured to be 2, 3 or 4, respectively, and the dependence of the exciton density on the photoexcitation power density which was observed to be 1/2 (1/3, 1/4) for the coupled biexcition-exciton (triexciton-exciton, tetraexciton-exciton) system. A calculation of the photoluminescence line shape based on a simple model for biexcitons is found to be in good agreement with experiment. From this theoretical fit we deduce a binding energy of 1.55 meV for the 3D-confined biexcitons. This binding energy is larger than the reported value of 1.36 meV for a free biexciton in Si indicating a quantum confinement effect. The photoluminescence line shape for the triexciton and tetraexciton is also consistent with a recent theoretical calculation [A. C. Cancio and Yia-Chung Chang, Phys. Rev. B 50, 11606 (1994)]. 

2:00 PM FF2.2 
RAMAN SPECTROSCOPY OF EPITAXIAL Si/Si1-xGex HETEROSTRUCTURES. Ran Liu, Stefan Zollner, Ming Liaw, Motorola, MRST, Mesa, AZ; David O'Meara, Nigel Cave, Motorola, APRDL, Austin, TX. 

Raman scattering studies were carried out on Si/Si1-xGex (x=0.1 to 0.3) heterostructures consisting of a thin Si cap layer (100 - 400 ‰) on a top graded Si1-xGex layer, a constant Si1-xGex layer and a bottom graded Si1-xGex layer. Different Ge composition, Si1-xGex layer thicknesses and thermal treatment were used to achieve different relaxation in the Si1-xGex layers. It has been revealed that, to a very good approximation, the absolute strains in the cap Si and constant Si1-xGex layers follow a simple sum-rule that is imposed by the lattice mismatch between unstrained Si and completely relaxed Si1-xGex. Excellent agreement was found between the theoretical curve obtained with LO phonon strain coefficient b=-930cm-1 and the experimental total strain for all samples, regardless of the degree of the Si1-xGex layer relaxation. This sum rule can be used to determine the Ge composition and stresses in both cap Si and constant Si1-xGex layers. 

2:15 PM FF2.3 
GROWTH AND CHARACTERIZATION OF HIGH QUALITY OPTIMIZED RELAXED GRADED SiGe/Si FOR Si-BASED OPTOELECTRONICS APPLICATIONS. Srikanth B. Samavedam, Matthew T. Currie, Thomas A. Langdo, Eugene A. Fitzgerlad, MIT, Dept. of Materials Science and Engineering, Cambridge, MA. 

Relaxed graded SiGe/Si layers can be used in a variety of optoelectronics applications such as pseudo-substrates for III-V/Si integration, and as detectors and waveguides in optical communication. With increasing Ge content in the graded SiGe layers, some of the materials challenges that need to be addressed are- (i) a high surface roughness, (ii) the formation of dislocation pile-ups, (iii) an increase in the threading dislocation density, (iv) thermal mismatch and cracking, and (v) particulate formation from gas phase nucleation events. We have shown that deleterious interactions between gliding 60º dislocations and deep surface features result in dislocation pile-ups and an associated increase in threading dislocation density in the Ge-rich SiGe layers. A modification in the conventional growth technique frees dislocations trapped in pile-ups and leads to optimized relaxation of the graded buffers. Additional changes in growth condiitions in the higher Ge regions of the graded buffer help alleviate the thermal mismatch problem and reduce particulate formation. The threading dislocation density in the Ge layers on graded SiGe/Si determined through plan view transmission electron microscopy (TEM) and etch pit density (EPD) was found to be in the range 2.1 x 10⁶/cm², one order of magnitude less than conventional buffers graded to pure Ge and two orders of magnitude less than Ge grown directly on Si. Experiments based on patterning and regrowth suggest possible further reduction in the threading dislocation density. Ge p-i-n diodes were fabricated to assess the electronic quality of the material. Extremely low dark currents (0.4 mA/cm² at - 1 V, one to two orders of magnitude lower than previous Ge detectors on Si) were observed in these devices proving the feasibility of high quality infrared Ge photodetectors on Si substrates. 

2:30 PM FF2.4 
INVESTIGATION OF PLASTIC RELAXATION IN SI_1-XGE_X/SI DEPOSITED BY SELECTIVE EPITAXY. Susanne Wickenhäuser, Lili Vescan, Christel Dieker, Karl Schmidt, Hans Lüth, Institut für Schicht- und Ionentechnik, Forschungszentrum Jülich GmbH, Jülich, GERMANY. 

Relaxed Si_1-xGe_x buffer layers become more and more interesting for application such as virtual substrates for strained Si layers. Below a certain stress Si_1-xGe_x layers relax plastically, that is by formation of misfit dislocations. During this process usually threading dislocations are created. These degrade any device, therefore, in order to avoid the disturbing threading dislocations, it is necessary to study this relaxation mechanism in detail. Patterned wafers with square holes in the SiO₂ mask and dimensions between 10-300m were used as substrates. Si_0.84Ge_0.16/Si heterostructures with different layer thicknesses grown by selective LPCVD epitaxy at a temperature of 700ºC were investigated with regard to plastic relaxation by formation of dislocations. PL studies reflect the relaxation qualitativly by the well known D1 - D4 peaks in the spectrum and RBS measurements determine the degree of strain in the different Si_0.84Ge_0.16 layers. TEM and optical micrograph were performed to determine the dislocation density. For each layer thickness and each square mesa we observe a different degree of relaxation. While in small and thin structures only nucleation and propagation occurs, the dislocation-dislocation interaction (mainly MFR multiplication) becomes more and more important in larger and thicker structures. Therefore it was possible to separate the three different mechanisms which play a role in relaxation, i.e. nucleation, propagation, multiplication, and to study them independently . From the analysis of the misfit dislocations at the initial stage of relaxation it was possible to determine the nucleation site density and an activation energy of 2.8 eV for the heterogeneous nucleation of misfit dislocations. The relaxation mechanism of graded buffer layers will be investigated by using the idea of varying both layer thickness and mesa dimension and by that the relaxation stage. 

2:45 PM FF2.5 
MOSAIC CRYSTAL TILTS AND THEIR RELATIONSHIP TO DISLOCATION STRUCTURE, SURFACE ROUGHNESS AND GROWTH CONDITIONS IN RELAXED SiGe LAYERS. D.J. Wallis, D.J. Robbins, A.J. Pidduck, G.M. Williams, A. Churchill and J. Newey, DERA, Malvern, Worcestershire, UNITED KINGDOM. 

In recent years the growth of virtual substrates using graded SiGe buffer layers has shown great promise for the development of high performance devices. Whilst significant progress has been made in the control of growth conditions to produce low threading dislocation densities of the order suitable for commercial exploitation, several technological problems still have to be overcome. An example of such problems are cosmetic surface defects such as pits and the cross hatched surface roughness associated with mosaic crystal tilts. The work described here utilises a variety of techniques, including X-ray diffraction reciprocal space maps, TEM, AFM and SIMS to provide a comparison between several SiGe virtual substrates grown using low pressure-CVD at high (800C) and low (600C) temperatures, and at different grade rates (5-50% Ge mm-1). The growth conditions are seen to have a strong effect on the crystal tilts present in the layers with the low temperature layers showing a much larger spread of mosaic tilts. The origin of these tilts is seen to occur during the early stages of the relaxation process irrespective of growth temperature and at similar Ge fractions for all samples. TEM imaging close to the initial growth interface shows that dislocation pileups occur in this region and also suggest that the pileups have a characteristic spacing of 1-2mm. A similar characteristic length scale is also observed in the surface roughness by AFM, the form of which is seen to depend upon the growth conditions. 

3:30 PM *FF2.6 
DEVICE AND FABRICATION ISSUES OF HIGH PERFORMANCE Si/SiGe FETs. Mohamed Arafa and Ilesanmi Adesida, University of Illinois at Urbana-Champaign, Urbana, IL; Khaled Ismail, IBM T. J. Watson Research Center. Yorktown Heights, NY. 

In the last decade, advances in Si/SiGe heterostructure growth have brought to fore a silicon-compatible technology that has the potential to compete favorably with III-V devices in application-specific designs requiring low power consumption such as cellular telephone and other portable and wireless electronics. The excellent performance demonstrated by bandgap-engineered devices such as HBTs and MODFETs on GaAs and InP has provided the impetus to study them using the Si/SiGe materials. The excellent transport properties achieved for both electrons and holes have led to devices with record high performance. High performance MODFETs have been demonstrated by several groups. A record unity current gain cutoff frequency of 70 GHz was achieved for p- MODFETs, and a record maximum frequency of oscillation of 81 GHz was achieved for n-type MODFETs. The performance of the fabricated p-type SiGe MODFETs is higher than any p-type FETs achieved on Si and III-V compound semiconductors. There is still a lot of room to improve the performance by using a better quality materials and employing a more sophisticated techniques. SiGe based heterostructures add another dimension to device design. It offers several attractive features such as the possibility of forming atomically abrupt discontinuities in either the conduction- or valence-band leading to a well-controlled buried channels for electrons and holes. Also, a reduction of the supply bias can be adopted because of the enhancement of the carrier mobility. Moreover, a larger improvement in the holes transport properties compared to electrons leads to a more symmetric complementary structure.